kernel_samsung_a53x/arch/x86/kernel/cpu
Michael Kelley cda86a0cb1 x86/hyperv: Set X86_FEATURE_TSC_KNOWN_FREQ when Hyper-V provides frequency
[ Upstream commit 8fcc514809de41153b43ccbe1a0cdf7f72b78e7e ]

A Linux guest on Hyper-V gets the TSC frequency from a synthetic MSR, if
available. In this case, set X86_FEATURE_TSC_KNOWN_FREQ so that Linux
doesn't unnecessarily do refined TSC calibration when setting up the TSC
clocksource.

With this change, a message such as this is no longer output during boot
when the TSC is used as the clocksource:

[    1.115141] tsc: Refined TSC clocksource calibration: 2918.408 MHz

Furthermore, the guest and host will have exactly the same view of the
TSC frequency, which is important for features such as the TSC deadline
timer that are emulated by the Hyper-V host.

Signed-off-by: Michael Kelley <mhklinux@outlook.com>
Reviewed-by: Roman Kisel <romank@linux.microsoft.com>
Link: https://lore.kernel.org/r/20240606025559.1631-1-mhklinux@outlook.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Message-ID: <20240606025559.1631-1-mhklinux@outlook.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-11-23 23:21:15 +01:00
..
mce x86/mce: Make sure to grab mce_sysfs_mutex in set_bank() 2024-11-19 09:23:10 +01:00
microcode Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
mtrr x86/mtrr: Check if fixed MTRRs exist before saving them 2024-11-23 23:20:30 +01:00
resctrl Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
acrn.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
amd.c x86/CPU/AMD: Update the Zenbleed microcode revisions 2024-11-19 09:22:36 +01:00
aperfmperf.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
bugs.c x86/cpu: Enable STIBP on AMD if Automatic IBRS is enabled 2024-11-19 09:22:43 +01:00
cacheinfo.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
centaur.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
common.c x86/srso: Add SRSO mitigation for Hygon processors 2024-11-19 09:22:46 +01:00
cpu.h Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
cpuid-deps.c x86/cpufeatures: Fix dependencies for GFNI, VAES, and VPCLMULQDQ 2024-11-19 11:32:22 +01:00
cyrix.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
feat_ctl.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
hygon.c x86/cpu/hygon: Fix the CPU topology evaluation for real 2024-11-18 11:43:21 +01:00
hypervisor.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
intel.c x86/cpu/intel: Detect TME keyid bits before setting MTRR mask registers 2024-11-18 23:18:30 +01:00
intel_epb.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
intel_pconfig.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
Makefile Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
match.c x86/cpu: Fix x86_match_cpu() to match just X86_VENDOR_INTEL 2024-11-19 14:19:29 +01:00
mkcapflags.sh Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
mshyperv.c x86/hyperv: Set X86_FEATURE_TSC_KNOWN_FREQ when Hyper-V provides frequency 2024-11-23 23:21:15 +01:00
perfctr-watchdog.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
powerflags.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
proc.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
rdrand.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
scattered.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
topology.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
transmeta.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
tsx.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
umc.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
umwait.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
vmware.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
zhaoxin.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00