166 lines
6.1 KiB
C
Executable file
166 lines
6.1 KiB
C
Executable file
/*
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* s2mf301_top.h - Header of S2MF301 TOP Driver
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*
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* Copyright (C) 2021 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef S2MF301_TOP_H
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#define S2MF301_TOP_H
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#include <linux/mfd/samsung/s2mf301.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/power_supply.h>
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enum {
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S2MF301_TOP_REG_DC_AUTO_PPS_INT = 0x04,
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S2MF301_TOP_REG_TOP_PM_RID_INT = 0x05,
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S2MF301_TOP_REG_TOP_TC_RID_INT = 0x06,
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S2MF301_TOP_REG_DC_AUTO_PPS_INT_MASK = 0x0B,
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S2MF301_TOP_REG_TOP_PM_RID_INT_MASK = 0x0C,
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S2MF301_TOP_REG_TOP_TC_RID_INT_MASK = 0x0D,
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S2MF301_TOP_REG_AUTO_PPS_SETTING = 0x50,
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S2MF301_TOP_REG_DC_TOP_OFF_CURRENT = 0x51,
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S2MF301_TOP_REG_DC_CV_LEVEL = 0x52,
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S2MF301_TOP_REG_THERMAL_CONDITION = 0x53,
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S2MF301_TOP_REG_DC_CC_STEP_VBAT1 = 0x54,
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S2MF301_TOP_REG_DC_CC_STEP_VBAT2 = 0x55,
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S2MF301_TOP_REG_DC_CC_STEP_1 = 0x56,
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S2MF301_TOP_REG_DC_CC_STEP_2 = 0x57,
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S2MF301_TOP_REG_DC_CC_STEP_3 = 0x58,
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S2MF301_TOP_REG_THERMAL_WAIT = 0x59,
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S2MF301_TOP_REG_DC_AUTO_PPS_STATE = 0x5A,
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S2MF301_TOP_REG_TEST_SEL = 0x5B,
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S2MF301_TOP_REG_DC_RSVD = 0x5C,
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};
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/* 0x50 S2MF301_TOP_REG_AUTO_PPS_SETTING */
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#define S2MF301_TOP_REG_EN_REG_WRITE_SHIFT 7
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#define S2MF301_TOP_REG_THERMAL_EN_SHIFT 6
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#define S2MF301_TOP_REG_THERMAL_SELECTION_SHIFT 5
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#define S2MF301_TOP_REG_CC_ICHG_SEL_SHIFT 4
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#define S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_SHIFT 2
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#define S2MF301_TOP_REG_EN_STEP_CC_SHIFT 1
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#define S2MF301_TOP_REG_AUTO_PPS_START_SHIFT 0
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#define S2MF301_TOP_REG_EN_REG_WRITE_MASK (0x1 << S2MF301_TOP_REG_EN_REG_WRITE_SHIFT)
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#define S2MF301_TOP_REG_THERMAL_EN_MASK (0x1 << S2MF301_TOP_REG_THERMAL_EN_SHIFT)
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#define S2MF301_TOP_REG_THERMAL_SELECTION_MASK (0x1 << S2MF301_TOP_REG_THERMAL_SELECTION_SHIFT)
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#define S2MF301_TOP_REG_CC_ICHG_SEL_MASK (0x1 << S2MF301_TOP_REG_CC_ICHG_SEL_SHIFT)
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#define S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_MASK (0x3 << S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_SHIFT)
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#define S2MF301_TOP_REG_EN_STEP_CC_MASK (0x1 << S2MF301_TOP_REG_EN_STEP_CC_SHIFT)
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#define S2MF301_TOP_REG_AUTO_PPS_START_MASK (0x1 << S2MF301_TOP_REG_AUTO_PPS_START_SHIFT)
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/* 0x51 S2MF301_TOP_REG_DC_TOP_OFF_CURRENT */
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#define S2MF301_TOP_REG_DC_DONE_SOC_SHIFT 4
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#define S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_SHIFT 0
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#define S2MF301_TOP_REG_DC_DONE_SOC_MASK (0xF << S2MF301_TOP_REG_DC_DONE_SOC_SHIFT)
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#define S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_MASK (0xF << S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_SHIFT)
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/* 0x52 S2MF301_TOP_REG_DC_CV_LEVEL*/
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#define S2MF301_TOP_REG_DC_CV_SHIFT 0
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#define S2MF301_TOP_REG_DC_CV_MASK (0xF << S2MF301_TOP_REG_DC_CV_SHIFT)
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/* 0x53 S2MF301_TOP_REG_THERMAL_CONDITION */
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#define S2MF301_TOP_REG_THERMAL_END_SHIFT 4
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#define S2MF301_TOP_REG_THERMAL_START_SHIFT 0
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#define S2MF301_TOP_REG_THERMAL_END_MASK (0xF << S2MF301_TOP_REG_THERMAL_END_SHIFT)
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#define S2MF301_TOP_REG_THERMAL_START_MASK (0xF << S2MF301_TOP_REG_THERMAL_START_SHIFT)
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/* 0x54 S2MF301_TOP_REG_DC_CC_STEP_VBAT1 */
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#define S2MF301_TOP_REG_CC_STEP_VBAT1_SHIFT 0
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#define S2MF301_TOP_REG_CC_STEP_VBAT1_MASK (0xFF << S2MF301_TOP_REG_CC_STEP_VBAT1_SHIFT)
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/* 0x55 S2MF301_TOP_REG_DC_CC_STEP_VBAT2 */
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#define S2MF301_TOP_REG_CC_STEP_VBAT2_SHIFT 0
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#define S2MF301_TOP_REG_CC_STEP_VBAT2_MASK (0xFF << S2MF301_TOP_REG_CC_STEP_VBAT2_SHIFT)
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/* 0x56 S2MF301_TOP_REG_DC_CC_STEP1 */
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#define S2MF301_TOP_REG_DC_CC_STEP1_SHIFT 0
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#define S2MF301_TOP_REG_DC_CC_STEP1_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP1_SHIFT)
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/* 0x57 S2MF301_TOP_REG_DC_CC_STEP2 */
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#define S2MF301_TOP_REG_DC_CC_STEP2_SHIFT 0
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#define S2MF301_TOP_REG_DC_CC_STEP2_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP2_SHIFT)
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/* 0x58 S2MF301_TOP_REG_DC_CC_STEP3 */
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#define S2MF301_TOP_REG_DC_CC_STEP3_SHIFT 0
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#define S2MF301_TOP_REG_DC_CC_STEP3_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP3_SHIFT)
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/* 0x59 S2MF301_TOP_REG_THERMAL_WAIT */
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#define S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_SHIFT 4
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#define S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_SHIFT 0
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#define S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_MASK (0xF << S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_SHIFT)
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#define S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_MASK (0xF << S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_SHIFT)
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/* 0x5A S2MF301_TOP_REG_DC_AUTO_PPS_STATE */
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#define S2MF301_TOP_REG_DC_DONE_SOC_STATE_SHIFT 4
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#define S2MF301_TOP_REG_DC_TOP_OFF_SHIFT 3
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#define S2MF301_TOP_REG_THERMAL_CONTROLLING_SHIFTs 2
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#define S2MF301_TOP_REG_CHARGING_STATE_SHIFT 0
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#define S2MF301_TOP_REG_DC_DONE_SOC_STATE_MASK (0x1 << S2MF301_TOP_REG_DC_DONE_SOC_STATE_SHIFT)
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#define S2MF301_TOP_REG_DC_TOP_OFF_MASK (0x1 << S2MF301_TOP_REG_DC_TOP_OFF_SHIFT)
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#define S2MF301_TOP_REG_THERMAL_CONTROLLING_MASK (0x1 << S2MF301_TOP_REG_THERMAL_CONTROLLING_SHIFT)
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#define S2MF301_TOP_REG_CHARGING_STATE_MASK (0x3 << S2MF301_TOP_REG_CHARGING_STATE_SHIFT)
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/* 0x5B S2MF301_TOP_REG_TEST_SEL */
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#define S2MF301_TOP_REG_DC_MON_SEL_SHIFT 0
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#define S2MF301_TOP_REG_DC_MON_SEL_MASK (0xF << S2MF301_TOP_REG_DC_MON_SEL_SHIFT)
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/* 0x5B S2MF301_TOP_REG_TEST_SEL */
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#define S2MF301_TOP_REG_DC_CV_LEVEL_SEL_SHIFT 0
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#define S2MF301_TOP_REG_DC_CV_LEVEL_SEL_MASK (0x1 << S2MF301_TOP_REG_DC_CV_LEVEL_SEL_SHIFT)
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struct s2mf301_top_data {
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struct i2c_client *i2c;
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struct device *dev;
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struct s2mf301_platform_data *s2mf301_pdata;
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int irq_rampup_done;
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int irq_rampup_fail;
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int irq_thermal_control;
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int irq_charging_state_change;
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int irq_charging_done;
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struct power_supply *psy_pm;
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struct power_supply_desc psy_pm_desc;
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};
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#endif /*S2MF301_PMETER_H*/
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