/* * s2mf301_top.h - Header of S2MF301 TOP Driver * * Copyright (C) 2021 Samsung Electronics Co.Ltd * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef S2MF301_TOP_H #define S2MF301_TOP_H #include #include #include #include #include enum { S2MF301_TOP_REG_DC_AUTO_PPS_INT = 0x04, S2MF301_TOP_REG_TOP_PM_RID_INT = 0x05, S2MF301_TOP_REG_TOP_TC_RID_INT = 0x06, S2MF301_TOP_REG_DC_AUTO_PPS_INT_MASK = 0x0B, S2MF301_TOP_REG_TOP_PM_RID_INT_MASK = 0x0C, S2MF301_TOP_REG_TOP_TC_RID_INT_MASK = 0x0D, S2MF301_TOP_REG_AUTO_PPS_SETTING = 0x50, S2MF301_TOP_REG_DC_TOP_OFF_CURRENT = 0x51, S2MF301_TOP_REG_DC_CV_LEVEL = 0x52, S2MF301_TOP_REG_THERMAL_CONDITION = 0x53, S2MF301_TOP_REG_DC_CC_STEP_VBAT1 = 0x54, S2MF301_TOP_REG_DC_CC_STEP_VBAT2 = 0x55, S2MF301_TOP_REG_DC_CC_STEP_1 = 0x56, S2MF301_TOP_REG_DC_CC_STEP_2 = 0x57, S2MF301_TOP_REG_DC_CC_STEP_3 = 0x58, S2MF301_TOP_REG_THERMAL_WAIT = 0x59, S2MF301_TOP_REG_DC_AUTO_PPS_STATE = 0x5A, S2MF301_TOP_REG_TEST_SEL = 0x5B, S2MF301_TOP_REG_DC_RSVD = 0x5C, }; /* 0x50 S2MF301_TOP_REG_AUTO_PPS_SETTING */ #define S2MF301_TOP_REG_EN_REG_WRITE_SHIFT 7 #define S2MF301_TOP_REG_THERMAL_EN_SHIFT 6 #define S2MF301_TOP_REG_THERMAL_SELECTION_SHIFT 5 #define S2MF301_TOP_REG_CC_ICHG_SEL_SHIFT 4 #define S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_SHIFT 2 #define S2MF301_TOP_REG_EN_STEP_CC_SHIFT 1 #define S2MF301_TOP_REG_AUTO_PPS_START_SHIFT 0 #define S2MF301_TOP_REG_EN_REG_WRITE_MASK (0x1 << S2MF301_TOP_REG_EN_REG_WRITE_SHIFT) #define S2MF301_TOP_REG_THERMAL_EN_MASK (0x1 << S2MF301_TOP_REG_THERMAL_EN_SHIFT) #define S2MF301_TOP_REG_THERMAL_SELECTION_MASK (0x1 << S2MF301_TOP_REG_THERMAL_SELECTION_SHIFT) #define S2MF301_TOP_REG_CC_ICHG_SEL_MASK (0x1 << S2MF301_TOP_REG_CC_ICHG_SEL_SHIFT) #define S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_MASK (0x3 << S2MF301_TOP_REG_DC_PDO_MAX_CUR_SEL_SHIFT) #define S2MF301_TOP_REG_EN_STEP_CC_MASK (0x1 << S2MF301_TOP_REG_EN_STEP_CC_SHIFT) #define S2MF301_TOP_REG_AUTO_PPS_START_MASK (0x1 << S2MF301_TOP_REG_AUTO_PPS_START_SHIFT) /* 0x51 S2MF301_TOP_REG_DC_TOP_OFF_CURRENT */ #define S2MF301_TOP_REG_DC_DONE_SOC_SHIFT 4 #define S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_SHIFT 0 #define S2MF301_TOP_REG_DC_DONE_SOC_MASK (0xF << S2MF301_TOP_REG_DC_DONE_SOC_SHIFT) #define S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_MASK (0xF << S2MF301_TOP_REG_DC_TOP_OFF_CURRENT_SHIFT) /* 0x52 S2MF301_TOP_REG_DC_CV_LEVEL*/ #define S2MF301_TOP_REG_DC_CV_SHIFT 0 #define S2MF301_TOP_REG_DC_CV_MASK (0xF << S2MF301_TOP_REG_DC_CV_SHIFT) /* 0x53 S2MF301_TOP_REG_THERMAL_CONDITION */ #define S2MF301_TOP_REG_THERMAL_END_SHIFT 4 #define S2MF301_TOP_REG_THERMAL_START_SHIFT 0 #define S2MF301_TOP_REG_THERMAL_END_MASK (0xF << S2MF301_TOP_REG_THERMAL_END_SHIFT) #define S2MF301_TOP_REG_THERMAL_START_MASK (0xF << S2MF301_TOP_REG_THERMAL_START_SHIFT) /* 0x54 S2MF301_TOP_REG_DC_CC_STEP_VBAT1 */ #define S2MF301_TOP_REG_CC_STEP_VBAT1_SHIFT 0 #define S2MF301_TOP_REG_CC_STEP_VBAT1_MASK (0xFF << S2MF301_TOP_REG_CC_STEP_VBAT1_SHIFT) /* 0x55 S2MF301_TOP_REG_DC_CC_STEP_VBAT2 */ #define S2MF301_TOP_REG_CC_STEP_VBAT2_SHIFT 0 #define S2MF301_TOP_REG_CC_STEP_VBAT2_MASK (0xFF << S2MF301_TOP_REG_CC_STEP_VBAT2_SHIFT) /* 0x56 S2MF301_TOP_REG_DC_CC_STEP1 */ #define S2MF301_TOP_REG_DC_CC_STEP1_SHIFT 0 #define S2MF301_TOP_REG_DC_CC_STEP1_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP1_SHIFT) /* 0x57 S2MF301_TOP_REG_DC_CC_STEP2 */ #define S2MF301_TOP_REG_DC_CC_STEP2_SHIFT 0 #define S2MF301_TOP_REG_DC_CC_STEP2_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP2_SHIFT) /* 0x58 S2MF301_TOP_REG_DC_CC_STEP3 */ #define S2MF301_TOP_REG_DC_CC_STEP3_SHIFT 0 #define S2MF301_TOP_REG_DC_CC_STEP3_MASK (0xFF << S2MF301_TOP_REG_DC_CC_STEP3_SHIFT) /* 0x59 S2MF301_TOP_REG_THERMAL_WAIT */ #define S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_SHIFT 4 #define S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_SHIFT 0 #define S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_MASK (0xF << S2MF301_TOP_REG_THERMAL_RECOVERY_WAITING_SHIFT) #define S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_MASK (0xF << S2MF301_TOP_REG_THERMAL_CONTROL_WAITING_SHIFT) /* 0x5A S2MF301_TOP_REG_DC_AUTO_PPS_STATE */ #define S2MF301_TOP_REG_DC_DONE_SOC_STATE_SHIFT 4 #define S2MF301_TOP_REG_DC_TOP_OFF_SHIFT 3 #define S2MF301_TOP_REG_THERMAL_CONTROLLING_SHIFTs 2 #define S2MF301_TOP_REG_CHARGING_STATE_SHIFT 0 #define S2MF301_TOP_REG_DC_DONE_SOC_STATE_MASK (0x1 << S2MF301_TOP_REG_DC_DONE_SOC_STATE_SHIFT) #define S2MF301_TOP_REG_DC_TOP_OFF_MASK (0x1 << S2MF301_TOP_REG_DC_TOP_OFF_SHIFT) #define S2MF301_TOP_REG_THERMAL_CONTROLLING_MASK (0x1 << S2MF301_TOP_REG_THERMAL_CONTROLLING_SHIFT) #define S2MF301_TOP_REG_CHARGING_STATE_MASK (0x3 << S2MF301_TOP_REG_CHARGING_STATE_SHIFT) /* 0x5B S2MF301_TOP_REG_TEST_SEL */ #define S2MF301_TOP_REG_DC_MON_SEL_SHIFT 0 #define S2MF301_TOP_REG_DC_MON_SEL_MASK (0xF << S2MF301_TOP_REG_DC_MON_SEL_SHIFT) /* 0x5B S2MF301_TOP_REG_TEST_SEL */ #define S2MF301_TOP_REG_DC_CV_LEVEL_SEL_SHIFT 0 #define S2MF301_TOP_REG_DC_CV_LEVEL_SEL_MASK (0x1 << S2MF301_TOP_REG_DC_CV_LEVEL_SEL_SHIFT) struct s2mf301_top_data { struct i2c_client *i2c; struct device *dev; struct s2mf301_platform_data *s2mf301_pdata; int irq_rampup_done; int irq_rampup_fail; int irq_thermal_control; int irq_charging_state_change; int irq_charging_done; struct power_supply *psy_pm; struct power_supply_desc psy_pm_desc; }; #endif /*S2MF301_PMETER_H*/