638 lines
22 KiB
C
Executable file
638 lines
22 KiB
C
Executable file
/*
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* Copyright (c) 2019 Samsung Electronics Co., Ltd.
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*
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* Author: Hajun Sung <hajun.sung@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos2100 interrupt controller.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define INTREQ__CLKMON_MONCLK 0
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#define INTREQ__CLKMON_REFSTUCK 1
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#define INTREQ__COMB_NONSECURE_SYSREG_VGPIO2AP 2
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#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_ALIVE 3
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#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_ALIVE 4
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#define INTREQ__GPIO_ALIVE 5
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#define INTREQ__I3C_APM 6
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#define INTREQ__I3C_APM_BATCHER 7
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#define INTREQ__I3C_CPU 8
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#define INTREQ__I3C_CPU_BATCHER 9
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#define INTREQ__MAILBOX_APM2AP 10
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#define INTREQ__MAILBOX_CP2AP_0 11
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#define INTREQ__MAILBOX_CP2AP_1 12
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#define INTREQ__MAILBOX_CP2AP_2 13
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#define INTREQ__MAILBOX_CP2AP_3 14
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#define INTREQ__MAILBOX_CP2AP_4 15
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#define INTREQ__MAILBOX_DBGCORE2AP 16
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#define INTREQ__NOTIFY 17
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#define INTREQ__PEM_INTERRUPT_0 18
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#define INTREQ__PEM_INTERRUPT_1 19
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#define INTREQ__RTC_ALARM_INT 20
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#define INTREQ__RTC_TIC_INT_0 21
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#define INTREQ__S_MAILBOX_CP2AP 22
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#define INTREQ__TOP_RTC_ALARM_INT 23
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#define INTREQ__TOP_RTC_TIC_INT_0 24
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#define INTREQ__AUD_ABOX_GIC400 25
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#define INTREQ__AUD_WDT 26
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#define INTREQ__SYSMMU_AUD_S1_NS 27
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#define INTREQ__SYSMMU_AUD_S1_S 28
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#define INTREQ__SYSMMU_AUD_S2 29
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#define INTREQ__TREX_D0_BUS0_debugInterrupt 30
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#define INTREQ__TREX_D1_BUS0_debugInterrupt 31
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#define INTREQ__TREX_P_BUS0_debugInterrupt 32
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#define INTREQ__DIT_Err 33
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#define INTREQ__DIT_RxDst0 34
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#define INTREQ__DIT_RxDst1 35
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#define INTREQ__DIT_RxDst2 36
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#define INTREQ__DIT_Tx 37
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#define INTREQ__PDMA 38
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#define INTREQ__SBIC 39
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#define INTREQ__SPDMA 40
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#define INTREQ__SYSMMU_S2_ACVPS 41
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#define INTREQ__SYSMMU_S2_DIT 42
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#define INTREQ__SYSMMU_S2_SBIC 43
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#define INTREQ__TREX_D_BUS1_debugInterrupt 44
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#define INTREQ__TREX_P_BUS1_debugInterrupt 45
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#define INTREQ__TREX_RB_BUS1_debugInterrupt 46
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#define INTREQ__TREX_D_BUS2_debugInterrupt 47
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#define INTREQ__TREX_P_BUS2_debugInterrupt 48
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#define EXT_INTA0_OUT0 49
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#define EXT_INTA0_OUT1 50
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#define EXT_INTA0_OUT2 51
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#define EXT_INTA0_OUT3 52
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#define EXT_INTA0_OUT4 53
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#define EXT_INTA0_OUT5 54
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#define EXT_INTA0_OUT6 55
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#define EXT_INTA0_OUT7 56
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#define EXT_INTA1_OUT0 57
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#define EXT_INTA1_OUT1 58
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#define EXT_INTA1_OUT2 59
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#define EXT_INTA1_OUT3 60
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#define EXT_INTA1_OUT4 61
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#define EXT_INTA1_OUT5 62
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#define EXT_INTA1_OUT6 63
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#define EXT_INTA1_OUT7 64
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#define EXT_INTA2_OUT0 65
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#define EXT_INTA2_OUT1 66
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#define EXT_INTA2_OUT2 67
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#define EXT_INTA2_OUT3 68
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#define EXT_INTA2_OUT4 69
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#define EXT_INTA2_OUT5 70
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#define EXT_INTA2_OUT6 71
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#define EXT_INTA2_OUT7 72
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#define EXT_INTA3_OUT0 73
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#define EXT_INTA3_OUT1 74
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#define EXT_INTA3_OUT2 75
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#define EXT_INTA3_OUT3 76
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#define EXT_INTA3_OUT4 77
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#define EXT_INTA3_OUT5 78
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#define EXT_INTA3_OUT6 79
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#define EXT_INTA3_OUT7 80
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#define EXT_INTA4_OUT0 81
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#define EXT_INTA4_OUT1 82
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#define INTREQ__ADC_CMGP2AP 83
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#define INTREQ__ADC_CMGP2AP2 84
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#define INTREQ__EXT_INTM00 85
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#define INTREQ__EXT_INTM01 86
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#define INTREQ__EXT_INTM02 87
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#define INTREQ__EXT_INTM03 88
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#define INTREQ__EXT_INTM04 89
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#define INTREQ__EXT_INTM05 90
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#define INTREQ__EXT_INTM06 91
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#define INTREQ__EXT_INTM07 92
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#define INTREQ__EXT_INTM08 93
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#define INTREQ__EXT_INTM09 94
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#define INTREQ__EXT_INTM10 95
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#define INTREQ__EXT_INTM11 96
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#define INTREQ__EXT_INTM12 97
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#define INTREQ__EXT_INTM13 98
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#define INTREQ__EXT_INTM14 99
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#define INTREQ__EXT_INTM15 100
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#define INTREQ__EXT_INTM16 101
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#define INTREQ__EXT_INTM17 102
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#define INTREQ__EXT_INTM18 103
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#define INTREQ__EXT_INTM19 104
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#define INTREQ__EXT_INTM20 105
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#define INTREQ__EXT_INTM21 106
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#define INTREQ__EXT_INTM22 107
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#define INTREQ__EXT_INTM23 108
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#define INTREQ__EXT_INTM24 109
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#define INTREQ__EXT_INTM25 110
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#define INTREQ__EXT_INTM26 111
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#define INTREQ__EXT_INTM27 112
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#define INTREQ__EXT_INTM28 113
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#define INTREQ__EXT_INTM29 114
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#define INTREQ__EXT_INTM30 115
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#define INTREQ__EXT_INTM31 116
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#define INTREQ__EXT_INTM32 117
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#define INTREQ__EXT_INTM33 118
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#define INTREQ__I2C_CMGP0 119
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#define INTREQ__I2C_CMGP1 120
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#define INTREQ__I2C_CMGP2 121
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#define INTREQ__I2C_CMGP3 122
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#define INTREQ__I3C_CMGP 123
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#define INTREQ__USI_CMGP0 124
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#define INTREQ__USI_CMGP1 125
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#define INTREQ__USI_CMGP2 126
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#define INTREQ__USI_CMGP3 127
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#define INTREQ__CCI_ERRINT_COR 128
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#define INTREQ__CCI_ERRINT_UNCOR 129
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#define INTREQ__CCI_TZCINT 130
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#define INTREQ__PPC_DEBUG_CCI_PPC_INTR 131
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#define INTREQ__PPCFW_G3D_INT 132
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#define INTREQ__SYSMMU_G3D0_O_INTERRUPT_S2 133
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#define INTREQ__SYSMMU_G3D1_O_INTERRUPT_S2 134
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#define INTREQ__SYSMMU_G3D2_O_INTERRUPT_S2 135
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#define INTREQ__SYSMMU_G3D3_O_INTERRUPT_S2 136
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#define INTREQ__SYSMMU_MODEM_O_INTERRUPT_S2 137
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#define INTREQ__TREX_D_CORE_debugInterrupt 138
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#define INTREQ__TREX_P0_CORE_debugInterrupt 139
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#define INTREQ__TREX_P1_CORE_debugInterrupt 140
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#define INTREQ__ACE_US_D0_FATAL_ERR 141
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#define INTREQ__ACE_US_D1_FATAL_ERR 142
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#define INTREQ__CPUCL0_CLUSTERPMUIRQ 143
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#define INTREQ__CPUCL0_DPM 144
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#define INTREQ__CPUCL0_ERRIRQ_0 145
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#define INTREQ__CPUCL0_ERRIRQ_1 146
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#define INTREQ__CPUCL0_ERRIRQ_2 147
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#define INTREQ__CPUCL0_ERRIRQ_3 148
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#define INTREQ__CPUCL0_ERRIRQ_4 149
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#define INTREQ__CPUCL0_ERRIRQ_5 150
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#define INTREQ__CPUCL0_ERRIRQ_6 151
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#define INTREQ__CPUCL0_ERRIRQ_7 152
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#define INTREQ__CPUCL0_ERRIRQ_8 153
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#define INTREQ__CPUCL0_FAULTIRQ_0 154
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#define INTREQ__CPUCL0_FAULTIRQ_1 155
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#define INTREQ__CPUCL0_FAULTIRQ_2 156
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#define INTREQ__CPUCL0_FAULTIRQ_3 157
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#define INTREQ__CPUCL0_FAULTIRQ_4 158
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#define INTREQ__CPUCL0_FAULTIRQ_5 159
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#define INTREQ__CPUCL0_FAULTIRQ_6 160
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#define INTREQ__CPUCL0_FAULTIRQ_7 161
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#define INTREQ__CPUCL0_FAULTIRQ_8 162
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#define INTREQ__OCP_REATOR_CPUCL0_0 163
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#define INTREQ__OCP_REATOR_CPUCL0_1 164
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#define INTREQ__OCP_REATOR_CPUCL0_2 165
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#define INTREQ__OCP_REATOR_CPUCL0_3 166
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0 167
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1 168
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0 169
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1 170
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0 171
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1 172
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0 173
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1 174
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#define O_DD_ERR_IRQ_FAST_0_CPUCL0 175
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#define O_DD_ERR_IRQ_FAST_1_CPUCL0 176
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#define O_DD_ERR_IRQ_FAST_2_CPUCL0 177
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#define O_DD_ERR_IRQ_FAST_3_CPUCL0 178
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#define O_DD_ERR_IRQ_FAST_4_CPUCL0 179
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#define O_DD_ERR_IRQ_SLOW_0_CPUCL0 180
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#define O_DD_ERR_IRQ_SLOW_1_CPUCL0 181
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#define O_DD_ERR_IRQ_SLOW_2_CPUCL0 182
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#define O_DD_ERR_IRQ_SLOW_3_CPUCL0 183
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#define O_DD_ERR_IRQ_SLOW_4_CPUCL0 184
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#define O_HPM_IRQ_CPUCL0 185
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#define O_INTREQ__ADD_CTRL_0_CPUCL0 186
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#define O_INTREQ__ADD_CTRL_1_CPUCL0 187
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#define O_INTREQ__ADD_CTRL_2_CPUCL0 188
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#define O_STR_IRQ_0_CPUCL0 189
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#define O_STR_IRQ_1_CPUCL0 190
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#define O_STR_IRQ_2_CPUCL0 191
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#define O_STR_IRQ_3_CPUCL0 192
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#define INTREQ__CSIS0 193
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#define INTREQ__CSIS1 194
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#define INTREQ__CSIS2 195
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#define INTREQ__CSIS3 196
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#define INTREQ__CSIS4 197
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#define INTREQ__CSIS5 198
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#define INTREQ__CSIS_DMA0 199
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#define INTREQ__CSIS_DMA1 200
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#define INTREQ__CSIS_DMA2 201
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#define INTREQ__CSIS_DMA3 202
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#define INTREQ__OIS_MCU_CSIS 203
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#define INTREQ__PDP0 204
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#define INTREQ__PDP1 205
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#define INTREQ__PDP2 206
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#define INTREQ__PDP3 207
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#define INTREQ__PDP4 208
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#define INTREQ__PDP5 209
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#define INTREQ__PDP6 210
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#define INTREQ__PDP7 211
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#define INTREQ__STRP_DMA0 212
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#define INTREQ__STRP_DMA1 213
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#define INTREQ__DBGCORE_UART 214
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#define INTREQ__SYSMMU_D0_CSIS_S1_NS 215
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#define INTREQ__SYSMMU_D0_CSIS_S1_S 216
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#define INTREQ__SYSMMU_D0_CSIS_S2 217
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#define INTREQ__SYSMMU_D1_CSIS_S1_NS 218
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#define INTREQ__SYSMMU_D1_CSIS_S1_S 219
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#define INTREQ__SYSMMU_D1_CSIS_S2 220
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#define INTREQ__SYSMMU_D2_CSIS_S1_NS 221
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#define INTREQ__HDCP 222
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#define INTREQ__TBASE 223
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#define INTREQ__SECURE_LOG 224
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#define INTREQ__RPMB 225
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#define INTREQ__SYSMMU_D2_CSIS_S1_S 226
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#define INTREQ__SYSMMU_D2_CSIS_S2 227
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#define INTREQ__SYSMMU_D3_CSIS_S1_NS 228
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#define INTREQ__SYSMMU_D3_CSIS_S1_S 229
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#define INTREQ__SYSMMU_D3_CSIS_S2 230
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#define INTREQ__ZSL_DMA0 231
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#define INTREQ__ZSL_DMA1 232
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#define INTREQ__OVERFLOW_CSISX6 233
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#define INTREQ__STRP_DMA2 234
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#define INTREQ__STRP_DMA3 235
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#define INTREQ__ZSL_DMA2 236
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#define INTREQ__ZSL_DMA3 237
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#define INTREQ__DNS0_0 238
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#define INTREQ__DNS0_1 239
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#define INTREQ__SYSMMU_D0_DNS_S1_NS 240
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#define INTREQ__SYSMMU_D0_DNS_S1_S 241
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#define INTREQ__SYSMMU_D0_DNS_S2 242
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#define INTREQ__SYSMMU_D1_DNS_S1_NS 243
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#define INTREQ__SYSMMU_D1_DNS_S1_S 244
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#define INTREQ__SYSMMU_D1_DNS_S2 245
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#define INTREQ__DPUB_DECON0_DQE_DIMMING_END 246
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#define INTREQ__DPUB_DECON0_DQE_DIMMING_START 247
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#define INTREQ__DPUB_DECON0_EXTRA 248
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#define INTREQ__DPUB_DECON0_FRAME_DONE 249
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#define INTREQ__DPUB_DECON0_FRAME_START 250
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#define INTREQ__DPUB_DECON1_EXTRA 251
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#define INTREQ__DPUB_DECON1_FRAME_DONE 252
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#define INTREQ__DPUB_DECON1_FRAME_START 253
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#define INTREQ__DPUB_DECON2_EXTRA 254
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#define INTREQ__DPUB_DECON2_FRAME_DONE 255
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#define INTREQ__DPUB_DECON2_FRAME_START 256
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#define INTREQ__DPUB_DSIM0 257
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#define INTREQ__DPUB_DSIM1 258
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#define INTREQ__DPUB_DECON1_DQE_DIMMING_END 259
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#define INTREQ__DPUB_DECON1_DQE_DIMMING_START 260
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#define INTREQ__DPUB_DECON3_EXTRA 261
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#define INTREQ__DPUB_DECON3_FRAME_DONE 262
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#define INTREQ__DPUB_DECON3_FRAME_START 263
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#define INTREQ__DPUB_DSIM2 264
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#define INTREQ__DPUF0_DMA_DSIMFC0 265
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#define INTREQ__DPUF0_DMA_DSIMFC1 266
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#define INTREQ__DPUF1_DMA_DSIMFC0 267
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#define INTREQ__DPUF1_DMA_DSIMFC1 268
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#define INTREQ__MMC_CARD 269
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#define INTREQ__UFS_EMBD 270
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#define INTREQ__MCFP0_0 271
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#define INTREQ__MCFP0_1 272
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#define INTREQ__ORBMCH0_O_INT 273
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#define INTREQ__ORBMCH1_O_INT 274
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#define INTREQ__GDC_IRQ 275
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#define INTREQ__USI09_I2C 276
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#define INTREQ__USI09_USI 277
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#define INTREQ__USI10_I2C 278
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#define INTREQ__USI10_USI 279
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#define O_HPM_IRQ_VTS 280
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#define INTREQ__FRC_MC_DBL_ERR 281
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#define INTREQ__DPUF0_DMA_L0 284
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#define INTREQ__DPUF0_DMA_L1 285
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#define INTREQ__DPUF0_DMA_L2 286
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#define INTREQ__DPUF0_DMA_L3 287
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#define INTREQ__DPUF0_DMA_L4 288
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#define INTREQ__DPUF0_DMA_L5 289
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#define INTREQ__DPUF0_DMA_L6 290
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#define INTREQ__DPUF0_DMA_L7 291
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#define INTREQ__DPUF0_DMA_WB 292
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#define INTREQ__DPUF0_DPP_L0 293
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#define INTREQ__DPUF0_DPP_L1 294
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#define INTREQ__DPUF0_DPP_L2 295
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#define INTREQ__DPUF0_DPP_L3 296
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#define INTREQ__DPUF0_DPP_L4 297
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#define INTREQ__DPUF0_DPP_L5 298
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#define INTREQ__DPUF0_DPP_L6 299
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#define INTREQ__DPUF0_DPP_L7 300
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#define INTREQ__SYSMMU_DPUF0D0_S1_NS 301
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#define INTREQ__SYSMMU_DPUF0D0_S1_S 302
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#define INTREQ__SYSMMU_DPUF0D0_S2 303
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#define INTREQ__SYSMMU_DPUF0D1_S1_NS 304
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#define INTREQ__SYSMMU_DPUF0D1_S1_S 305
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#define INTREQ__SYSMMU_DPUF0D1_S2 306
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#define INTREQ__DPUF1_DMA_L0 308
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#define INTREQ__DPUF1_DMA_L1 309
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#define INTREQ__DPUF1_DMA_L2 310
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#define INTREQ__DPUF1_DMA_L3 311
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#define INTREQ__DPUF1_DMA_L4 312
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#define INTREQ__DPUF1_DMA_L5 313
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#define INTREQ__DPUF1_DMA_L6 314
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#define INTREQ__DPUF1_DMA_L7 315
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#define INTREQ__DPUF1_DMA_WB 316
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#define INTREQ__DPUF1_DPP_L0 317
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#define INTREQ__DPUF1_DPP_L1 318
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#define INTREQ__DPUF1_DPP_L2 319
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#define INTREQ__DPUF1_DPP_L3 320
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#define INTREQ__DPUF1_DPP_L4 321
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#define INTREQ__DPUF1_DPP_L5 322
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#define INTREQ__DPUF1_DPP_L6 323
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#define INTREQ__DPUF1_DPP_L7 324
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#define INTREQ__SYSMMU_DPUF1D0_S1_NS 325
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#define INTREQ__SYSMMU_DPUF1D0_S1_S 326
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#define INTREQ__SYSMMU_DPUF1D0_S2 327
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#define INTREQ__SYSMMU_DPUF1D1_S1_NS 328
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#define INTREQ__SYSMMU_DPUF1D1_S1_S 329
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#define INTREQ__SYSMMU_DPUF1D1_S2 330
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#define INTREQ__DDD_FAST_G3D 335
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#define INTREQ__DDD_SLOW_G3D 336
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#define INTREQ__G3D_IRQEVENT 337
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#define INTREQ__G3D_IRQGPU 338
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#define INTREQ__G3D_IRQJOB 339
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#define INTREQ__G3D_IRQMMU 340
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#define INTREQ__G3D_O_OCP_THROTT 341
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#define INTREQ__G3D_STR_IRQ 342
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#define O_ADD_APBIF0_G3D_FLAG_IRQ_PEND 343
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#define O_HPM_IRQ 344
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#define INTREQ__DP_LINK 345
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#define INTREQ__SYSMMU_USB 346
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#define INTREQ__USB2_REMOTE_CONNECT_GIC 347
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#define INTREQ__USB2_REMOTE_TIMER_GIC 348
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#define INTREQ__USB2_REMOTE_WAKEUP_GIC 349
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#define INTREQ__USB31DRD_FSVMINUS_GIC 350
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#define INTREQ__USB31DRD_FSVPLUS_GIC 351
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#define INTREQ__USB31DRD_GIC_0 352
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#define INTREQ__USB31DRD_GIC_1 353
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#define INTREQ__USB31DRD_REWA_WAKEUP_REQ 354
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#define INTREQ__USBDPPHY_UDBG_IRQ 355
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#define INTREQ__GPIO_HSI1 356
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#define INTREQ__PCIE_GEN2 357
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#define INTREQ__PCIE_GEN4_0 358
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#define INTREQ__PCIE_GEN4A_MSI_0 359
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#define INTREQ__PCIE_GEN4A_MSI_1 360
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#define INTREQ__PCIE_GEN4A_MSI_2 361
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#define INTREQ__PCIE_GEN4A_MSI_3 362
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#define INTREQ__PCIE_GEN4A_MSI_4 363
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#define INTREQ__PCIE_IA_GEN2 364
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#define INTREQ__PCIE_IA_GEN4_0 365
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#define INTREQ__PCIE_PCS_GEN4_0 366
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#define INTREQ__SYSMMU_HSI1_S2MPU 367
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#define INTREQ__LME_O_INT0 373
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#define INTREQ__LME_O_INT1 374
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#define INTREQ__SYSMMU_D_LME_S1_NS 377
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#define INTREQ__SYSMMU_D_LME_S1_S 378
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#define INTREQ__SYSMMU_D_LME_S2 379
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#define INTREQ__M2M__ASTC 380
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#define INTREQ__M2M__JPEG0 381
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#define INTREQ__M2M__JPEG1 382
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#define INTREQ__M2M__JSQZ 383
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#define INTREQ__M2M__M2M 384
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#define INTREQ__M2M__SYSMMU_D_S1_NS 385
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#define INTREQ__M2M__SYSMMU_D_S1_S 386
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#define INTREQ__M2M__SYSMMU_D_S2 387
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#define INTREQ__SYSMMU_D0_MCFP0_S1_NS 389
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#define INTREQ__SYSMMU_D0_MCFP0_S1_S 390
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#define INTREQ__SYSMMU_D0_MCFP0_S2 391
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#define INTREQ__SYSMMU_D1_MCFP0_S1_NS 392
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#define INTREQ__SYSMMU_D1_MCFP0_S1_S 393
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#define INTREQ__SYSMMU_D1_MCFP0_S2 394
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#define INTREQ__SYSMMU_D2_MCFP0_S1_NS 395
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#define INTREQ__SYSMMU_D2_MCFP0_S1_S 396
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#define INTREQ__SYSMMU_D2_MCFP0_S2 397
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#define INTREQ__SYSMMU_D3_MCFP0_S1_NS 398
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#define INTREQ__SYSMMU_D3_MCFP0_S1_S 399
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#define INTREQ__SYSMMU_D3_MCFP0_S2 400
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#define INTREQ__MCFP1_O_INT 401
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#define INTREQ__SYSMMU_D_MCFP1_S1_NS 403
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#define INTREQ__SYSMMU_D_MCFP1_S1_S 404
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#define INTREQ__SYSMMU_D_MCFP1_S2 405
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#define INTREQ__ADD_MCSC 406
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#define INTREQ__DDD_FAST_MCSC 413
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#define INTREQ__DDD_SLOW_MCSC 414
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#define INTREQ__MCSC_OTF0 417
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#define INTREQ__O_HPM_IRQ_MCSC 418
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#define INTREQ__SYSMMU_D0_MCSC_S1_NS 419
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#define INTREQ__SYSMMU_D0_MCSC_S1_S 420
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#define INTREQ__SYSMMU_D0_MCSC_S2 421
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#define INTREQ__SYSMMU_D1_MCSC_S1_NS 422
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#define INTREQ__SYSMMU_D1_MCSC_S1_S 423
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#define INTREQ__SYSMMU_D1_MCSC_S2 424
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#define INTREQ__SYSMMU_D2_MCSC_S1_NS 425
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#define INTREQ__SYSMMU_D2_MCSC_S1_S 426
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#define INTREQ__SYSMMU_D2_MCSC_S2 427
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#define INTREQ__MFC0 428
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#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_ns 429
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#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_s 430
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#define INTREQ__SYSMMU_MFC0D0_interrupt_s2 431
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#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_ns 432
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#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_s 433
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#define INTREQ__SYSMMU_MFC0D1_interrupt_s2 434
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#define INTREQ__WFD 435
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#define INTREQ__MFC1 436
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#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_ns 437
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#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_s 438
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#define INTREQ__SYSMMU_MFC1D0_interrupt_s2 439
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#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_ns 440
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#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_s 441
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#define INTREQ__SYSMMU_MFC1D1_interrupt_s2 442
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#define INTREQ__DMC_ECC_CORERR_MIF0 443
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#define INTREQ__DMC_ECC_UNCORERR_MIF0 444
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#define INTREQ__DMC_PPMPINT_MIF0 445
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#define INTREQ__DMC_SWZQ0_MIF0 446
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#define INTREQ__DMC_SWZQ1_MIF0 447
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#define INTREQ__DMC_TEMPERR_MIF0 448
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#define INTREQ__DMC_TEMPHOT_MIF0 449
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#define INTREQ__DMC_TZCINT_MIF0 450
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#define INTREQ__DMC_ECC_CORERR_MIF1 451
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#define INTREQ__DMC_ECC_UNCORERR_MIF1 452
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#define INTREQ__DMC_PPMPINT_MIF1 453
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#define INTREQ__DMC_SWZQ0_MIF1 454
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#define INTREQ__DMC_SWZQ1_MIF1 455
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#define INTREQ__DMC_TEMPERR_MIF1 456
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#define INTREQ__DMC_TEMPHOT_MIF1 457
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#define INTREQ__DMC_TZCINT_MIF1 458
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#define INTREQ__USB3_REMOTE_WAKEUP_GIC 459
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#define INTREQ__DMC_ECC_CORERR_MIF2 460
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#define INTREQ__DMC_ECC_UNCORERR_MIF2 461
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#define INTREQ__DMC_PPMPINT_MIF2 462
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#define INTREQ__DMC_SWZQ0_MIF2 463
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#define INTREQ__DMC_SWZQ1_MIF2 464
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#define INTREQ__DMC_TEMPERR_MIF2 465
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#define INTREQ__DMC_TEMPHOT_MIF2 466
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#define INTREQ__DMC_TZCINT_MIF2 467
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#define INTREQ__DMC_ECC_CORERR_MIF3 468
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#define INTREQ__DMC_ECC_UNCORERR_MIF3 469
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#define INTREQ__DMC_PPMPINT_MIF3 470
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#define INTREQ__DMC_SWZQ0_MIF3 471
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#define INTREQ__DMC_SWZQ1_MIF3 472
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#define INTREQ__DMC_TEMPERR_MIF3 473
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#define INTREQ__DMC_TEMPHOT_MIF3 474
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#define INTREQ__DMC_TZCINT_MIF3 475
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#define INTREQ_RESET_REQ 476
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#define SFR_BUS_RDY 477
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#define INTREQ__ADD_CTRL_NPUS 478
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#define INTREQ__DD_ERR_IRQ_FAST_NPUS 479
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#define INTREQ__DD_ERR_IRQ_SLOW_NPUS 480
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#define INTREQ__HPM_IRQ_NPUS 481
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#define INTREQ__OCP_THROTT_INTR_NPUS 482
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_NS 483
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_S 484
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2 485
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_NS 486
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_S 487
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2 488
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#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S1_NS 489
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#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S1_S 490
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#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S2 491
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#define O_INTREQ_NS_NPUS_HOST_0 492
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#define O_INTREQ_NS_NPUS_HOST_1 493
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#define O_INTREQ_NS_NPUS_HOST_2 494
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#define O_INTREQ_NS_NPUS_HOST_3 495
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#define O_INTREQ_NS_NPUS_HOST_4 496
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#define O_INTREQ_NS_NPUS_HOST_5 497
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#define O_INTREQ_NS_NPUS_HOST_6 498
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#define O_INTREQ_NS_NPUS_HOST_7 499
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#define O_INTREQ_S_NPUS_HOST_0 500
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#define O_INTREQ_S_NPUS_HOST_1 501
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#define O_INTREQ_S_NPUS_HOST_2 502
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#define O_INTREQ_S_NPUS_HOST_3 503
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#define O_INTREQ_S_NPUS_HOST_4 504
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#define O_INTREQ_S_NPUS_HOST_5 505
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#define O_INTREQ_S_NPUS_HOST_6 506
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#define O_INTREQ_S_NPUS_HOST_7 507
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#define INTREQ__DBG_UART 508
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#define INTREQ__GPIO_PERIC0 509
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#define INTREQ__PWM0 510
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#define INTREQ__PWM1 511
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#define INTREQ__PWM2 512
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#define INTREQ__PWM3 513
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#define INTREQ__PWM4 514
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#define INTREQ__USI00_I2C 515
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#define INTREQ__USI00_USI 516
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#define INTREQ__USI01_I2C 517
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#define INTREQ__USI01_USI 518
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#define INTREQ__USI02_I2C 519
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#define INTREQ__USI02_USI 520
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#define INTREQ__USI03_I2C 521
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#define INTREQ__USI03_USI 522
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#define INTREQ__USI04_I2C 523
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#define INTREQ__USI04_USI 524
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#define INTREQ__USI05_I2C 525
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#define INTREQ__USI05_USI 526
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#define INTREQ__USI13_I2C 527
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#define INTREQ__USI13_USI 528
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#define INTREQ__USI14_I2C 529
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#define INTREQ__USI14_USI 530
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#define INTREQ__USI15_I2C 531
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#define INTREQ__USI15_USI 532
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#define INTREQ__BT_UART 533
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#define INTREQ__GPIO_PERIC1 534
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#define INTREQ__USI11_I2C 539
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#define INTREQ__USI11_USI 540
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#define INTREQ__USI12_I2C 541
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#define INTREQ__USI12_USI 542
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#define INTREQ__USI16_I2C 543
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#define INTREQ__USI16_I3C 544
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#define INTREQ__USI16_USI 545
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#define INTREQ__USI17_I2C 546
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#define INTREQ__USI17_I3C 547
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#define INTREQ__USI17_USI 548
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#define INTREQ__USI18_I2C 549
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#define INTREQ__USI18_USI 550
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#define INTREQ__GPIO_PERIC2 551
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#define INTREQ__USI06_I2C 552
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#define INTREQ__USI06_USI 553
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#define INTREQ__USI07_I2C 554
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#define INTREQ__USI07_USI 555
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#define INTREQ__USI08_I2C 556
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#define INTREQ__USI08_USI 557
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#define INTREQ__PPMU_SSP_O_interrupt_upper_or_normal 558
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#define INTREQ__RTIC 559
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#define INTREQ__SSPCORE_0 560
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#define INTREQ__SSPCORE_1 561
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#define INTREQ__SSPCORE_2 562
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#define INTREQ__SSPCORE_3 563
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#define INTREQ__SSS 564
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#define INTREQ__SSS_DMA 565
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#define INTREQ__SSS_KM 566
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#define INTREQ__SSS_NS_MB 567
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#define INTREQ__SSS_S_MB 568
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#define INTREQ__SSS_SWDT1 569
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#define INTREQ__SYSMMU_SSP 570
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#define INTREQ__ADD_TAA 571
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#define INTREQ__DD_ERR_IRQ_FAST_TAA 580
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#define INTREQ__DD_ERR_IRQ_SLOW_TAA 581
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#define INTREQ__HPM_TAA 582
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#define INTREQ__SYSMMU_TAA_S1_NS 583
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#define INTREQ__SYSMMU_TAA_S1_S 584
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#define INTREQ__SYSMMU_TAA_S2 585
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#define INTREQ__TAA_CH0_0 586
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#define INTREQ__TAA_CH0_1 587
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#define INTREQ__TAA_CH1_0 588
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#define INTREQ__TAA_CH1_1 589
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#define INTREQ__TAA_CH2_0 590
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#define INTREQ__TAA_CH2_1 591
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#define INTREQ__TAA_CH3_0 592
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#define INTREQ__TAA_CH3_1 593
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#define INTREQ__ADD_CTRL_VPC 594
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#define INTREQ__DD_ERR_IRQ_FAST_VPC 595
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#define INTREQ__DD_ERR_IRQ_SLOW_VPC 596
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#define INTREQ__FROM_VPC_TO_HOST_NS_0 597
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#define INTREQ__FROM_VPC_TO_HOST_NS_1 598
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#define INTREQ__FROM_VPC_TO_HOST_NS_2 599
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#define INTREQ__FROM_VPC_TO_HOST_NS_3 600
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#define INTREQ__FROM_VPC_TO_HOST_NS_4 601
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#define INTREQ__FROM_VPC_TO_HOST_NS_5 602
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#define INTREQ__FROM_VPC_TO_HOST_NS_6 603
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#define INTREQ__FROM_VPC_TO_HOST_NS_7 604
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#define INTREQ__FROM_VPC_TO_HOST_S_0 605
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#define INTREQ__FROM_VPC_TO_HOST_S_1 606
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#define INTREQ__FROM_VPC_TO_HOST_S_2 607
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#define INTREQ__FROM_VPC_TO_HOST_S_3 608
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#define INTREQ__FROM_VPC_TO_HOST_S_4 609
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#define INTREQ__FROM_VPC_TO_HOST_S_5 610
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#define INTREQ__FROM_VPC_TO_HOST_S_6 611
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#define INTREQ__FROM_VPC_TO_HOST_S_7 612
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#define INTREQ__HPM_IRQ_VPC 613
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#define INTREQ__O_OCP_THROTT_INTR 614
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#define INTREQ__SYSMMU_VPC0_interrupt_s1_ns 615
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#define INTREQ__SYSMMU_VPC0_interrupt_s1_s 616
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#define INTREQ__SYSMMU_VPC0_interrupt_s2 617
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#define INTREQ__SYSMMU_VPC1_interrupt_s1_ns 618
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#define INTREQ__SYSMMU_VPC1_interrupt_s1_s 619
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#define INTREQ__SYSMMU_VPC1_interrupt_s2 620
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#define INTREQ__SYSMMU_VPC2_interrupt_s1_ns 621
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#define INTREQ__SYSMMU_VPC2_interrupt_s1_s 622
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#define INTREQ__SYSMMU_VPC2_interrupt_s2 623
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#define INTREQ__MAILBOX_AP_VTS 624
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#define INTREQ__WDT_VTS 625
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#define INTREQ__FRC_MC_DONE 627
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#define INTREQ__SYSMMU_YUVPP_S1_NS 628
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#define INTREQ__SYSMMU_YUVPP_S1_S 629
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#define INTREQ__SYSMMU_YUVPP_S2 630
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#define INTREQ__YUVPP 631
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#define INTREQ__LV3_TABLE_ALLOC 650
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#define INTREQ__BC_EMUL 937
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#define INTREQ__OTP_CON_TOP 938
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#define INTREQ__OTP_CON_BIRA 939
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#define INTREQ__OTP_CON_BISR 940
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#define INTREQ__WDT0 941
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#define INTREQ__WDT1 942
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#define INTREQ__MCT_G0 943
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#define INTREQ__MCT_G1 944
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#define INTREQ__MCT_G2 945
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#define INTREQ__MCT_G3 946
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#define INTREQ__MCT_L0 947
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#define INTREQ__MCT_L1 948
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#define INTREQ__MCT_L2 949
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#define INTREQ__MCT_L3 950
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#define INTREQ__MCT_L4 951
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#define INTREQ__MCT_L5 952
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#define INTREQ__MCT_L6 953
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#define INTREQ__MCT_L7 954
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#define INTREQ__TMU_TMU_TOP 955
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#define INTREQ__TMU_TMU_SUB 956
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#define INTREQ__GIC_PMU_INT 957
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#define INTREQ__GIC_ERR_INT 958
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#define INTREQ__GIC_FAULT_INT 959
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#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H */
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