/*
 * Copyright (c) 2019 Samsung Electronics Co., Ltd.
 *
 * Author: Hajun Sung <hajun.sung@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Device Tree binding constants for Exynos2100 interrupt controller.
*/

#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define INTREQ__CLKMON_MONCLK	0
#define INTREQ__CLKMON_REFSTUCK	1
#define INTREQ__COMB_NONSECURE_SYSREG_VGPIO2AP	2
#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_ALIVE	3
#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_ALIVE	4
#define INTREQ__GPIO_ALIVE	5
#define INTREQ__I3C_APM	6
#define INTREQ__I3C_APM_BATCHER	7
#define INTREQ__I3C_CPU	8
#define INTREQ__I3C_CPU_BATCHER	9
#define INTREQ__MAILBOX_APM2AP	10
#define INTREQ__MAILBOX_CP2AP_0	11
#define INTREQ__MAILBOX_CP2AP_1	12
#define INTREQ__MAILBOX_CP2AP_2	13
#define INTREQ__MAILBOX_CP2AP_3	14
#define INTREQ__MAILBOX_CP2AP_4	15
#define INTREQ__MAILBOX_DBGCORE2AP	16
#define INTREQ__NOTIFY	17
#define INTREQ__PEM_INTERRUPT_0	18
#define INTREQ__PEM_INTERRUPT_1	19
#define INTREQ__RTC_ALARM_INT	20
#define INTREQ__RTC_TIC_INT_0	21
#define INTREQ__S_MAILBOX_CP2AP	22
#define INTREQ__TOP_RTC_ALARM_INT	23
#define INTREQ__TOP_RTC_TIC_INT_0	24
#define INTREQ__AUD_ABOX_GIC400	25
#define INTREQ__AUD_WDT	26
#define INTREQ__SYSMMU_AUD_S1_NS	27
#define INTREQ__SYSMMU_AUD_S1_S	28
#define INTREQ__SYSMMU_AUD_S2	29
#define INTREQ__TREX_D0_BUS0_debugInterrupt	30
#define INTREQ__TREX_D1_BUS0_debugInterrupt	31
#define INTREQ__TREX_P_BUS0_debugInterrupt	32
#define INTREQ__DIT_Err	33
#define INTREQ__DIT_RxDst0	34
#define INTREQ__DIT_RxDst1	35
#define INTREQ__DIT_RxDst2	36
#define INTREQ__DIT_Tx	37
#define INTREQ__PDMA	38
#define INTREQ__SBIC	39
#define INTREQ__SPDMA	40
#define INTREQ__SYSMMU_S2_ACVPS	41
#define INTREQ__SYSMMU_S2_DIT	42
#define INTREQ__SYSMMU_S2_SBIC	43
#define INTREQ__TREX_D_BUS1_debugInterrupt	44
#define INTREQ__TREX_P_BUS1_debugInterrupt	45
#define INTREQ__TREX_RB_BUS1_debugInterrupt	46
#define INTREQ__TREX_D_BUS2_debugInterrupt	47
#define INTREQ__TREX_P_BUS2_debugInterrupt	48
#define EXT_INTA0_OUT0	49
#define EXT_INTA0_OUT1	50
#define EXT_INTA0_OUT2	51
#define EXT_INTA0_OUT3	52
#define EXT_INTA0_OUT4	53
#define EXT_INTA0_OUT5	54
#define EXT_INTA0_OUT6	55
#define EXT_INTA0_OUT7	56
#define EXT_INTA1_OUT0	57
#define EXT_INTA1_OUT1	58
#define EXT_INTA1_OUT2	59
#define EXT_INTA1_OUT3	60
#define EXT_INTA1_OUT4	61
#define EXT_INTA1_OUT5	62
#define EXT_INTA1_OUT6	63
#define EXT_INTA1_OUT7	64
#define EXT_INTA2_OUT0	65
#define EXT_INTA2_OUT1	66
#define EXT_INTA2_OUT2	67
#define EXT_INTA2_OUT3	68
#define EXT_INTA2_OUT4	69
#define EXT_INTA2_OUT5	70
#define EXT_INTA2_OUT6	71
#define EXT_INTA2_OUT7	72
#define EXT_INTA3_OUT0	73
#define EXT_INTA3_OUT1	74
#define EXT_INTA3_OUT2	75
#define EXT_INTA3_OUT3	76
#define EXT_INTA3_OUT4	77
#define EXT_INTA3_OUT5	78
#define EXT_INTA3_OUT6	79
#define EXT_INTA3_OUT7	80
#define EXT_INTA4_OUT0	81
#define EXT_INTA4_OUT1	82
#define INTREQ__ADC_CMGP2AP	83
#define INTREQ__ADC_CMGP2AP2	84
#define INTREQ__EXT_INTM00	85
#define INTREQ__EXT_INTM01	86
#define INTREQ__EXT_INTM02	87
#define INTREQ__EXT_INTM03	88
#define INTREQ__EXT_INTM04	89
#define INTREQ__EXT_INTM05	90
#define INTREQ__EXT_INTM06	91
#define INTREQ__EXT_INTM07	92
#define INTREQ__EXT_INTM08	93
#define INTREQ__EXT_INTM09	94
#define INTREQ__EXT_INTM10	95
#define INTREQ__EXT_INTM11	96
#define INTREQ__EXT_INTM12	97
#define INTREQ__EXT_INTM13	98
#define INTREQ__EXT_INTM14	99
#define INTREQ__EXT_INTM15	100
#define INTREQ__EXT_INTM16	101
#define INTREQ__EXT_INTM17	102
#define INTREQ__EXT_INTM18	103
#define INTREQ__EXT_INTM19	104
#define INTREQ__EXT_INTM20	105
#define INTREQ__EXT_INTM21	106
#define INTREQ__EXT_INTM22	107
#define INTREQ__EXT_INTM23	108
#define INTREQ__EXT_INTM24	109
#define INTREQ__EXT_INTM25	110
#define INTREQ__EXT_INTM26	111
#define INTREQ__EXT_INTM27	112
#define INTREQ__EXT_INTM28	113
#define INTREQ__EXT_INTM29	114
#define INTREQ__EXT_INTM30	115
#define INTREQ__EXT_INTM31	116
#define INTREQ__EXT_INTM32	117
#define INTREQ__EXT_INTM33	118
#define INTREQ__I2C_CMGP0	119
#define INTREQ__I2C_CMGP1	120
#define INTREQ__I2C_CMGP2	121
#define INTREQ__I2C_CMGP3	122
#define INTREQ__I3C_CMGP	123
#define INTREQ__USI_CMGP0	124
#define INTREQ__USI_CMGP1	125
#define INTREQ__USI_CMGP2	126
#define INTREQ__USI_CMGP3	127
#define INTREQ__CCI_ERRINT_COR	128
#define INTREQ__CCI_ERRINT_UNCOR	129
#define INTREQ__CCI_TZCINT	130
#define INTREQ__PPC_DEBUG_CCI_PPC_INTR	131
#define INTREQ__PPCFW_G3D_INT	132
#define INTREQ__SYSMMU_G3D0_O_INTERRUPT_S2	133
#define INTREQ__SYSMMU_G3D1_O_INTERRUPT_S2	134
#define INTREQ__SYSMMU_G3D2_O_INTERRUPT_S2	135
#define INTREQ__SYSMMU_G3D3_O_INTERRUPT_S2	136
#define INTREQ__SYSMMU_MODEM_O_INTERRUPT_S2	137
#define INTREQ__TREX_D_CORE_debugInterrupt	138
#define INTREQ__TREX_P0_CORE_debugInterrupt	139
#define INTREQ__TREX_P1_CORE_debugInterrupt	140
#define INTREQ__ACE_US_D0_FATAL_ERR	141
#define INTREQ__ACE_US_D1_FATAL_ERR	142
#define INTREQ__CPUCL0_CLUSTERPMUIRQ	143
#define INTREQ__CPUCL0_DPM	144
#define INTREQ__CPUCL0_ERRIRQ_0	145
#define INTREQ__CPUCL0_ERRIRQ_1	146
#define INTREQ__CPUCL0_ERRIRQ_2	147
#define INTREQ__CPUCL0_ERRIRQ_3	148
#define INTREQ__CPUCL0_ERRIRQ_4	149
#define INTREQ__CPUCL0_ERRIRQ_5	150
#define INTREQ__CPUCL0_ERRIRQ_6	151
#define INTREQ__CPUCL0_ERRIRQ_7	152
#define INTREQ__CPUCL0_ERRIRQ_8	153
#define INTREQ__CPUCL0_FAULTIRQ_0	154
#define INTREQ__CPUCL0_FAULTIRQ_1	155
#define INTREQ__CPUCL0_FAULTIRQ_2	156
#define INTREQ__CPUCL0_FAULTIRQ_3	157
#define INTREQ__CPUCL0_FAULTIRQ_4	158
#define INTREQ__CPUCL0_FAULTIRQ_5	159
#define INTREQ__CPUCL0_FAULTIRQ_6	160
#define INTREQ__CPUCL0_FAULTIRQ_7	161
#define INTREQ__CPUCL0_FAULTIRQ_8	162
#define INTREQ__OCP_REATOR_CPUCL0_0	163
#define INTREQ__OCP_REATOR_CPUCL0_1	164
#define INTREQ__OCP_REATOR_CPUCL0_2	165
#define INTREQ__OCP_REATOR_CPUCL0_3	166
#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0	167
#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1	168
#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0	169
#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1	170
#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0	171
#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1	172
#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0	173
#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1	174
#define O_DD_ERR_IRQ_FAST_0_CPUCL0	175
#define O_DD_ERR_IRQ_FAST_1_CPUCL0	176
#define O_DD_ERR_IRQ_FAST_2_CPUCL0	177
#define O_DD_ERR_IRQ_FAST_3_CPUCL0	178
#define O_DD_ERR_IRQ_FAST_4_CPUCL0	179
#define O_DD_ERR_IRQ_SLOW_0_CPUCL0	180
#define O_DD_ERR_IRQ_SLOW_1_CPUCL0	181
#define O_DD_ERR_IRQ_SLOW_2_CPUCL0	182
#define O_DD_ERR_IRQ_SLOW_3_CPUCL0	183
#define O_DD_ERR_IRQ_SLOW_4_CPUCL0	184
#define O_HPM_IRQ_CPUCL0	185
#define O_INTREQ__ADD_CTRL_0_CPUCL0	186
#define O_INTREQ__ADD_CTRL_1_CPUCL0	187
#define O_INTREQ__ADD_CTRL_2_CPUCL0	188
#define O_STR_IRQ_0_CPUCL0	189
#define O_STR_IRQ_1_CPUCL0	190
#define O_STR_IRQ_2_CPUCL0	191
#define O_STR_IRQ_3_CPUCL0	192
#define INTREQ__CSIS0	193
#define INTREQ__CSIS1	194
#define INTREQ__CSIS2	195
#define INTREQ__CSIS3	196
#define INTREQ__CSIS4	197
#define INTREQ__CSIS5	198
#define INTREQ__CSIS_DMA0	199
#define INTREQ__CSIS_DMA1	200
#define INTREQ__CSIS_DMA2	201
#define INTREQ__CSIS_DMA3	202
#define INTREQ__OIS_MCU_CSIS	203
#define INTREQ__PDP0	204
#define INTREQ__PDP1	205
#define INTREQ__PDP2	206
#define INTREQ__PDP3	207
#define INTREQ__PDP4	208
#define INTREQ__PDP5	209
#define INTREQ__PDP6	210
#define INTREQ__PDP7	211
#define INTREQ__STRP_DMA0	212
#define INTREQ__STRP_DMA1	213
#define INTREQ__DBGCORE_UART	214
#define INTREQ__SYSMMU_D0_CSIS_S1_NS	215
#define INTREQ__SYSMMU_D0_CSIS_S1_S	216
#define INTREQ__SYSMMU_D0_CSIS_S2	217
#define INTREQ__SYSMMU_D1_CSIS_S1_NS	218
#define INTREQ__SYSMMU_D1_CSIS_S1_S	219
#define INTREQ__SYSMMU_D1_CSIS_S2	220
#define INTREQ__SYSMMU_D2_CSIS_S1_NS	221
#define INTREQ__HDCP	222
#define INTREQ__TBASE	223
#define INTREQ__SECURE_LOG	224
#define INTREQ__RPMB	225
#define INTREQ__SYSMMU_D2_CSIS_S1_S	226
#define INTREQ__SYSMMU_D2_CSIS_S2	227
#define INTREQ__SYSMMU_D3_CSIS_S1_NS	228
#define INTREQ__SYSMMU_D3_CSIS_S1_S	229
#define INTREQ__SYSMMU_D3_CSIS_S2	230
#define INTREQ__ZSL_DMA0	231
#define INTREQ__ZSL_DMA1	232
#define INTREQ__OVERFLOW_CSISX6	233
#define INTREQ__STRP_DMA2	234
#define INTREQ__STRP_DMA3	235
#define INTREQ__ZSL_DMA2	236
#define INTREQ__ZSL_DMA3	237
#define INTREQ__DNS0_0	238
#define INTREQ__DNS0_1	239
#define INTREQ__SYSMMU_D0_DNS_S1_NS	240
#define INTREQ__SYSMMU_D0_DNS_S1_S	241
#define INTREQ__SYSMMU_D0_DNS_S2	242
#define INTREQ__SYSMMU_D1_DNS_S1_NS	243
#define INTREQ__SYSMMU_D1_DNS_S1_S	244
#define INTREQ__SYSMMU_D1_DNS_S2	245
#define INTREQ__DPUB_DECON0_DQE_DIMMING_END	246
#define INTREQ__DPUB_DECON0_DQE_DIMMING_START	247
#define INTREQ__DPUB_DECON0_EXTRA	248
#define INTREQ__DPUB_DECON0_FRAME_DONE	249
#define INTREQ__DPUB_DECON0_FRAME_START	250
#define INTREQ__DPUB_DECON1_EXTRA	251
#define INTREQ__DPUB_DECON1_FRAME_DONE	252
#define INTREQ__DPUB_DECON1_FRAME_START	253
#define INTREQ__DPUB_DECON2_EXTRA	254
#define INTREQ__DPUB_DECON2_FRAME_DONE	255
#define INTREQ__DPUB_DECON2_FRAME_START	256
#define INTREQ__DPUB_DSIM0	257
#define INTREQ__DPUB_DSIM1	258
#define INTREQ__DPUB_DECON1_DQE_DIMMING_END	259
#define INTREQ__DPUB_DECON1_DQE_DIMMING_START	260
#define INTREQ__DPUB_DECON3_EXTRA	261
#define INTREQ__DPUB_DECON3_FRAME_DONE	262
#define INTREQ__DPUB_DECON3_FRAME_START	263
#define INTREQ__DPUB_DSIM2	264
#define INTREQ__DPUF0_DMA_DSIMFC0	265
#define INTREQ__DPUF0_DMA_DSIMFC1	266
#define INTREQ__DPUF1_DMA_DSIMFC0	267
#define INTREQ__DPUF1_DMA_DSIMFC1	268
#define INTREQ__MMC_CARD	269
#define INTREQ__UFS_EMBD	270
#define INTREQ__MCFP0_0	271
#define INTREQ__MCFP0_1	272
#define INTREQ__ORBMCH0_O_INT	273
#define INTREQ__ORBMCH1_O_INT	274
#define INTREQ__GDC_IRQ	275
#define INTREQ__USI09_I2C	276
#define INTREQ__USI09_USI	277
#define INTREQ__USI10_I2C	278
#define INTREQ__USI10_USI	279
#define O_HPM_IRQ_VTS	280
#define INTREQ__FRC_MC_DBL_ERR	281
#define INTREQ__DPUF0_DMA_L0	284
#define INTREQ__DPUF0_DMA_L1	285
#define INTREQ__DPUF0_DMA_L2	286
#define INTREQ__DPUF0_DMA_L3	287
#define INTREQ__DPUF0_DMA_L4	288
#define INTREQ__DPUF0_DMA_L5	289
#define INTREQ__DPUF0_DMA_L6	290
#define INTREQ__DPUF0_DMA_L7	291
#define INTREQ__DPUF0_DMA_WB	292
#define INTREQ__DPUF0_DPP_L0	293
#define INTREQ__DPUF0_DPP_L1	294
#define INTREQ__DPUF0_DPP_L2	295
#define INTREQ__DPUF0_DPP_L3	296
#define INTREQ__DPUF0_DPP_L4	297
#define INTREQ__DPUF0_DPP_L5	298
#define INTREQ__DPUF0_DPP_L6	299
#define INTREQ__DPUF0_DPP_L7	300
#define INTREQ__SYSMMU_DPUF0D0_S1_NS	301
#define INTREQ__SYSMMU_DPUF0D0_S1_S	302
#define INTREQ__SYSMMU_DPUF0D0_S2	303
#define INTREQ__SYSMMU_DPUF0D1_S1_NS	304
#define INTREQ__SYSMMU_DPUF0D1_S1_S	305
#define INTREQ__SYSMMU_DPUF0D1_S2	306
#define INTREQ__DPUF1_DMA_L0	308
#define INTREQ__DPUF1_DMA_L1	309
#define INTREQ__DPUF1_DMA_L2	310
#define INTREQ__DPUF1_DMA_L3	311
#define INTREQ__DPUF1_DMA_L4	312
#define INTREQ__DPUF1_DMA_L5	313
#define INTREQ__DPUF1_DMA_L6	314
#define INTREQ__DPUF1_DMA_L7	315
#define INTREQ__DPUF1_DMA_WB	316
#define INTREQ__DPUF1_DPP_L0	317
#define INTREQ__DPUF1_DPP_L1	318
#define INTREQ__DPUF1_DPP_L2	319
#define INTREQ__DPUF1_DPP_L3	320
#define INTREQ__DPUF1_DPP_L4	321
#define INTREQ__DPUF1_DPP_L5	322
#define INTREQ__DPUF1_DPP_L6	323
#define INTREQ__DPUF1_DPP_L7	324
#define INTREQ__SYSMMU_DPUF1D0_S1_NS	325
#define INTREQ__SYSMMU_DPUF1D0_S1_S	326
#define INTREQ__SYSMMU_DPUF1D0_S2	327
#define INTREQ__SYSMMU_DPUF1D1_S1_NS	328
#define INTREQ__SYSMMU_DPUF1D1_S1_S	329
#define INTREQ__SYSMMU_DPUF1D1_S2	330
#define INTREQ__DDD_FAST_G3D	335
#define INTREQ__DDD_SLOW_G3D	336
#define INTREQ__G3D_IRQEVENT	337
#define INTREQ__G3D_IRQGPU	338
#define INTREQ__G3D_IRQJOB	339
#define INTREQ__G3D_IRQMMU	340
#define INTREQ__G3D_O_OCP_THROTT	341
#define INTREQ__G3D_STR_IRQ	342
#define O_ADD_APBIF0_G3D_FLAG_IRQ_PEND	343
#define O_HPM_IRQ	344
#define INTREQ__DP_LINK	345
#define INTREQ__SYSMMU_USB	346
#define INTREQ__USB2_REMOTE_CONNECT_GIC	347
#define INTREQ__USB2_REMOTE_TIMER_GIC	348
#define INTREQ__USB2_REMOTE_WAKEUP_GIC	349
#define INTREQ__USB31DRD_FSVMINUS_GIC	350
#define INTREQ__USB31DRD_FSVPLUS_GIC	351
#define INTREQ__USB31DRD_GIC_0	352
#define INTREQ__USB31DRD_GIC_1	353
#define INTREQ__USB31DRD_REWA_WAKEUP_REQ	354
#define INTREQ__USBDPPHY_UDBG_IRQ	355
#define INTREQ__GPIO_HSI1	356
#define INTREQ__PCIE_GEN2	357
#define INTREQ__PCIE_GEN4_0	358
#define INTREQ__PCIE_GEN4A_MSI_0	359
#define INTREQ__PCIE_GEN4A_MSI_1	360
#define INTREQ__PCIE_GEN4A_MSI_2	361
#define INTREQ__PCIE_GEN4A_MSI_3	362
#define INTREQ__PCIE_GEN4A_MSI_4	363
#define INTREQ__PCIE_IA_GEN2	364
#define INTREQ__PCIE_IA_GEN4_0	365
#define INTREQ__PCIE_PCS_GEN4_0	366
#define INTREQ__SYSMMU_HSI1_S2MPU	367
#define INTREQ__LME_O_INT0	373
#define INTREQ__LME_O_INT1	374
#define INTREQ__SYSMMU_D_LME_S1_NS	377
#define INTREQ__SYSMMU_D_LME_S1_S	378
#define INTREQ__SYSMMU_D_LME_S2	379
#define INTREQ__M2M__ASTC	380
#define INTREQ__M2M__JPEG0	381
#define INTREQ__M2M__JPEG1	382
#define INTREQ__M2M__JSQZ	383
#define INTREQ__M2M__M2M	384
#define INTREQ__M2M__SYSMMU_D_S1_NS	385
#define INTREQ__M2M__SYSMMU_D_S1_S	386
#define INTREQ__M2M__SYSMMU_D_S2	387
#define INTREQ__SYSMMU_D0_MCFP0_S1_NS	389
#define INTREQ__SYSMMU_D0_MCFP0_S1_S	390
#define INTREQ__SYSMMU_D0_MCFP0_S2	391
#define INTREQ__SYSMMU_D1_MCFP0_S1_NS	392
#define INTREQ__SYSMMU_D1_MCFP0_S1_S	393
#define INTREQ__SYSMMU_D1_MCFP0_S2	394
#define INTREQ__SYSMMU_D2_MCFP0_S1_NS	395
#define INTREQ__SYSMMU_D2_MCFP0_S1_S	396
#define INTREQ__SYSMMU_D2_MCFP0_S2	397
#define INTREQ__SYSMMU_D3_MCFP0_S1_NS	398
#define INTREQ__SYSMMU_D3_MCFP0_S1_S	399
#define INTREQ__SYSMMU_D3_MCFP0_S2	400
#define INTREQ__MCFP1_O_INT	401
#define INTREQ__SYSMMU_D_MCFP1_S1_NS	403
#define INTREQ__SYSMMU_D_MCFP1_S1_S	404
#define INTREQ__SYSMMU_D_MCFP1_S2	405
#define INTREQ__ADD_MCSC	406
#define INTREQ__DDD_FAST_MCSC	413
#define INTREQ__DDD_SLOW_MCSC	414
#define INTREQ__MCSC_OTF0	417
#define INTREQ__O_HPM_IRQ_MCSC	418
#define INTREQ__SYSMMU_D0_MCSC_S1_NS	419
#define INTREQ__SYSMMU_D0_MCSC_S1_S	420
#define INTREQ__SYSMMU_D0_MCSC_S2	421
#define INTREQ__SYSMMU_D1_MCSC_S1_NS	422
#define INTREQ__SYSMMU_D1_MCSC_S1_S	423
#define INTREQ__SYSMMU_D1_MCSC_S2	424
#define INTREQ__SYSMMU_D2_MCSC_S1_NS	425
#define INTREQ__SYSMMU_D2_MCSC_S1_S	426
#define INTREQ__SYSMMU_D2_MCSC_S2	427
#define INTREQ__MFC0	428
#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_ns	429
#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_s	430
#define INTREQ__SYSMMU_MFC0D0_interrupt_s2	431
#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_ns	432
#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_s	433
#define INTREQ__SYSMMU_MFC0D1_interrupt_s2	434
#define INTREQ__WFD	435
#define INTREQ__MFC1	436
#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_ns	437
#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_s	438
#define INTREQ__SYSMMU_MFC1D0_interrupt_s2	439
#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_ns	440
#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_s	441
#define INTREQ__SYSMMU_MFC1D1_interrupt_s2	442
#define INTREQ__DMC_ECC_CORERR_MIF0	443
#define INTREQ__DMC_ECC_UNCORERR_MIF0	444
#define INTREQ__DMC_PPMPINT_MIF0	445
#define INTREQ__DMC_SWZQ0_MIF0	446
#define INTREQ__DMC_SWZQ1_MIF0	447
#define INTREQ__DMC_TEMPERR_MIF0	448
#define INTREQ__DMC_TEMPHOT_MIF0	449
#define INTREQ__DMC_TZCINT_MIF0	450
#define INTREQ__DMC_ECC_CORERR_MIF1	451
#define INTREQ__DMC_ECC_UNCORERR_MIF1	452
#define INTREQ__DMC_PPMPINT_MIF1	453
#define INTREQ__DMC_SWZQ0_MIF1	454
#define INTREQ__DMC_SWZQ1_MIF1	455
#define INTREQ__DMC_TEMPERR_MIF1	456
#define INTREQ__DMC_TEMPHOT_MIF1	457
#define INTREQ__DMC_TZCINT_MIF1	458
#define INTREQ__USB3_REMOTE_WAKEUP_GIC	459
#define INTREQ__DMC_ECC_CORERR_MIF2	460
#define INTREQ__DMC_ECC_UNCORERR_MIF2	461
#define INTREQ__DMC_PPMPINT_MIF2	462
#define INTREQ__DMC_SWZQ0_MIF2	463
#define INTREQ__DMC_SWZQ1_MIF2	464
#define INTREQ__DMC_TEMPERR_MIF2	465
#define INTREQ__DMC_TEMPHOT_MIF2	466
#define INTREQ__DMC_TZCINT_MIF2	467
#define INTREQ__DMC_ECC_CORERR_MIF3	468
#define INTREQ__DMC_ECC_UNCORERR_MIF3	469
#define INTREQ__DMC_PPMPINT_MIF3	470
#define INTREQ__DMC_SWZQ0_MIF3	471
#define INTREQ__DMC_SWZQ1_MIF3	472
#define INTREQ__DMC_TEMPERR_MIF3	473
#define INTREQ__DMC_TEMPHOT_MIF3	474
#define INTREQ__DMC_TZCINT_MIF3	475
#define INTREQ_RESET_REQ	476
#define SFR_BUS_RDY	477
#define INTREQ__ADD_CTRL_NPUS	478
#define INTREQ__DD_ERR_IRQ_FAST_NPUS	479
#define INTREQ__DD_ERR_IRQ_SLOW_NPUS	480
#define INTREQ__HPM_IRQ_NPUS	481
#define INTREQ__OCP_THROTT_INTR_NPUS	482
#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_NS	483
#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_S	484
#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2	485
#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_NS	486
#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_S	487
#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2	488
#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S1_NS	489
#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S1_S	490
#define INTREQ__SYSMMU_D2_NPUS_INTERRUPT_S2	491
#define O_INTREQ_NS_NPUS_HOST_0	492
#define O_INTREQ_NS_NPUS_HOST_1	493
#define O_INTREQ_NS_NPUS_HOST_2	494
#define O_INTREQ_NS_NPUS_HOST_3	495
#define O_INTREQ_NS_NPUS_HOST_4	496
#define O_INTREQ_NS_NPUS_HOST_5	497
#define O_INTREQ_NS_NPUS_HOST_6	498
#define O_INTREQ_NS_NPUS_HOST_7	499
#define O_INTREQ_S_NPUS_HOST_0	500
#define O_INTREQ_S_NPUS_HOST_1	501
#define O_INTREQ_S_NPUS_HOST_2	502
#define O_INTREQ_S_NPUS_HOST_3	503
#define O_INTREQ_S_NPUS_HOST_4	504
#define O_INTREQ_S_NPUS_HOST_5	505
#define O_INTREQ_S_NPUS_HOST_6	506
#define O_INTREQ_S_NPUS_HOST_7	507
#define INTREQ__DBG_UART	508
#define INTREQ__GPIO_PERIC0	509
#define INTREQ__PWM0	510
#define INTREQ__PWM1	511
#define INTREQ__PWM2	512
#define INTREQ__PWM3	513
#define INTREQ__PWM4	514
#define INTREQ__USI00_I2C	515
#define INTREQ__USI00_USI	516
#define INTREQ__USI01_I2C	517
#define INTREQ__USI01_USI	518
#define INTREQ__USI02_I2C	519
#define INTREQ__USI02_USI	520
#define INTREQ__USI03_I2C	521
#define INTREQ__USI03_USI	522
#define INTREQ__USI04_I2C	523
#define INTREQ__USI04_USI	524
#define INTREQ__USI05_I2C	525
#define INTREQ__USI05_USI	526
#define INTREQ__USI13_I2C	527
#define INTREQ__USI13_USI	528
#define INTREQ__USI14_I2C	529
#define INTREQ__USI14_USI	530
#define INTREQ__USI15_I2C	531
#define INTREQ__USI15_USI	532
#define INTREQ__BT_UART	533
#define INTREQ__GPIO_PERIC1	534
#define INTREQ__USI11_I2C	539
#define INTREQ__USI11_USI	540
#define INTREQ__USI12_I2C	541
#define INTREQ__USI12_USI	542
#define INTREQ__USI16_I2C	543
#define INTREQ__USI16_I3C	544
#define INTREQ__USI16_USI	545
#define INTREQ__USI17_I2C	546
#define INTREQ__USI17_I3C	547
#define INTREQ__USI17_USI	548
#define INTREQ__USI18_I2C	549
#define INTREQ__USI18_USI	550
#define INTREQ__GPIO_PERIC2	551
#define INTREQ__USI06_I2C	552
#define INTREQ__USI06_USI	553
#define INTREQ__USI07_I2C	554
#define INTREQ__USI07_USI	555
#define INTREQ__USI08_I2C	556
#define INTREQ__USI08_USI	557
#define INTREQ__PPMU_SSP_O_interrupt_upper_or_normal	558
#define INTREQ__RTIC	559
#define INTREQ__SSPCORE_0	560
#define INTREQ__SSPCORE_1	561
#define INTREQ__SSPCORE_2	562
#define INTREQ__SSPCORE_3	563
#define INTREQ__SSS	564
#define INTREQ__SSS_DMA	565
#define INTREQ__SSS_KM	566
#define INTREQ__SSS_NS_MB	567
#define INTREQ__SSS_S_MB	568
#define INTREQ__SSS_SWDT1	569
#define INTREQ__SYSMMU_SSP	570
#define INTREQ__ADD_TAA	571
#define INTREQ__DD_ERR_IRQ_FAST_TAA	580
#define INTREQ__DD_ERR_IRQ_SLOW_TAA	581
#define INTREQ__HPM_TAA	582
#define INTREQ__SYSMMU_TAA_S1_NS	583
#define INTREQ__SYSMMU_TAA_S1_S	584
#define INTREQ__SYSMMU_TAA_S2	585
#define INTREQ__TAA_CH0_0	586
#define INTREQ__TAA_CH0_1	587
#define INTREQ__TAA_CH1_0	588
#define INTREQ__TAA_CH1_1	589
#define INTREQ__TAA_CH2_0	590
#define INTREQ__TAA_CH2_1	591
#define INTREQ__TAA_CH3_0	592
#define INTREQ__TAA_CH3_1	593
#define INTREQ__ADD_CTRL_VPC	594
#define INTREQ__DD_ERR_IRQ_FAST_VPC	595
#define INTREQ__DD_ERR_IRQ_SLOW_VPC	596
#define INTREQ__FROM_VPC_TO_HOST_NS_0	597
#define INTREQ__FROM_VPC_TO_HOST_NS_1	598
#define INTREQ__FROM_VPC_TO_HOST_NS_2	599
#define INTREQ__FROM_VPC_TO_HOST_NS_3	600
#define INTREQ__FROM_VPC_TO_HOST_NS_4	601
#define INTREQ__FROM_VPC_TO_HOST_NS_5	602
#define INTREQ__FROM_VPC_TO_HOST_NS_6	603
#define INTREQ__FROM_VPC_TO_HOST_NS_7	604
#define INTREQ__FROM_VPC_TO_HOST_S_0	605
#define INTREQ__FROM_VPC_TO_HOST_S_1	606
#define INTREQ__FROM_VPC_TO_HOST_S_2	607
#define INTREQ__FROM_VPC_TO_HOST_S_3	608
#define INTREQ__FROM_VPC_TO_HOST_S_4	609
#define INTREQ__FROM_VPC_TO_HOST_S_5	610
#define INTREQ__FROM_VPC_TO_HOST_S_6	611
#define INTREQ__FROM_VPC_TO_HOST_S_7	612
#define INTREQ__HPM_IRQ_VPC	613
#define INTREQ__O_OCP_THROTT_INTR	614
#define INTREQ__SYSMMU_VPC0_interrupt_s1_ns	615
#define INTREQ__SYSMMU_VPC0_interrupt_s1_s	616
#define INTREQ__SYSMMU_VPC0_interrupt_s2	617
#define INTREQ__SYSMMU_VPC1_interrupt_s1_ns	618
#define INTREQ__SYSMMU_VPC1_interrupt_s1_s	619
#define INTREQ__SYSMMU_VPC1_interrupt_s2	620
#define INTREQ__SYSMMU_VPC2_interrupt_s1_ns	621
#define INTREQ__SYSMMU_VPC2_interrupt_s1_s	622
#define INTREQ__SYSMMU_VPC2_interrupt_s2	623
#define INTREQ__MAILBOX_AP_VTS	624
#define INTREQ__WDT_VTS	625
#define INTREQ__FRC_MC_DONE	627
#define INTREQ__SYSMMU_YUVPP_S1_NS	628
#define INTREQ__SYSMMU_YUVPP_S1_S	629
#define INTREQ__SYSMMU_YUVPP_S2	630
#define INTREQ__YUVPP	631
#define INTREQ__LV3_TABLE_ALLOC	650
#define INTREQ__BC_EMUL	937
#define INTREQ__OTP_CON_TOP	938
#define INTREQ__OTP_CON_BIRA	939
#define INTREQ__OTP_CON_BISR	940
#define INTREQ__WDT0	941
#define INTREQ__WDT1	942
#define INTREQ__MCT_G0	943
#define INTREQ__MCT_G1	944
#define INTREQ__MCT_G2	945
#define INTREQ__MCT_G3	946
#define INTREQ__MCT_L0	947
#define INTREQ__MCT_L1	948
#define INTREQ__MCT_L2	949
#define INTREQ__MCT_L3	950
#define INTREQ__MCT_L4	951
#define INTREQ__MCT_L5	952
#define INTREQ__MCT_L6	953
#define INTREQ__MCT_L7	954
#define INTREQ__TMU_TMU_TOP	955
#define INTREQ__TMU_TMU_SUB	956
#define INTREQ__GIC_PMU_INT	957
#define INTREQ__GIC_ERR_INT	958
#define INTREQ__GIC_FAULT_INT	959

#endif	/* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H */