2a3b8254f9
[ Upstream commit a30f9f65b5ac82d4390548c32ed9c7f05de7ddf5 ]
There is another cause for soft lock-up of GPU in empty ring-buffer:
race between GPU executing last commands and CPU checking ring for
emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS
event and RPTR shadow (which is used to check ring emptiness) is updated
a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its
last commands slow enough or we check that ring too fast we will miss a
chance to trigger switch to lower priority ring because current ring isn't
empty just yet. This can escalate to lock-up situation described in
previous patch.
To work-around this issue we keep track of last submit sequence number
for each ring and compare it with one written to memptrs from GPU during
execution of CACHE_FLUSH_TS event.
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612047/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
176 lines
5.3 KiB
C
Executable file
176 lines
5.3 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*/
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#ifndef __A5XX_GPU_H__
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#define __A5XX_GPU_H__
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#include "adreno_gpu.h"
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/* Bringing over the hack from the previous targets */
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#undef ROP_COPY
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#undef ROP_XOR
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#include "a5xx.xml.h"
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struct a5xx_gpu {
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struct adreno_gpu base;
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struct drm_gem_object *pm4_bo;
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uint64_t pm4_iova;
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struct drm_gem_object *pfp_bo;
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uint64_t pfp_iova;
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struct drm_gem_object *gpmu_bo;
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uint64_t gpmu_iova;
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uint32_t gpmu_dwords;
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uint32_t lm_leakage;
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struct msm_ringbuffer *cur_ring;
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struct msm_ringbuffer *next_ring;
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struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];
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struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS];
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struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS];
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uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
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uint32_t last_seqno[MSM_GPU_MAX_RINGS];
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atomic_t preempt_state;
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spinlock_t preempt_start_lock;
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struct timer_list preempt_timer;
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struct drm_gem_object *shadow_bo;
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uint64_t shadow_iova;
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uint32_t *shadow;
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/* True if the microcode supports the WHERE_AM_I opcode */
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bool has_whereami;
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};
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#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
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#ifdef CONFIG_DEBUG_FS
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void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
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#endif
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/*
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* In order to do lockless preemption we use a simple state machine to progress
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* through the process.
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*
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* PREEMPT_NONE - no preemption in progress. Next state START.
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* PREEMPT_START - The trigger is evaulating if preemption is possible. Next
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* states: TRIGGERED, NONE
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* PREEMPT_ABORT - An intermediate state before moving back to NONE. Next
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* state: NONE.
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* PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next
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* states: FAULTED, PENDING
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* PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger
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* recovery. Next state: N/A
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* PREEMPT_PENDING: Preemption complete interrupt fired - the callback is
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* checking the success of the operation. Next state: FAULTED, NONE.
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*/
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enum preempt_state {
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PREEMPT_NONE = 0,
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PREEMPT_START,
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PREEMPT_ABORT,
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PREEMPT_TRIGGERED,
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PREEMPT_FAULTED,
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PREEMPT_PENDING,
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};
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/*
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* struct a5xx_preempt_record is a shared buffer between the microcode and the
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* CPU to store the state for preemption. The record itself is much larger
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* (64k) but most of that is used by the CP for storage.
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*
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* There is a preemption record assigned per ringbuffer. When the CPU triggers a
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* preemption, it fills out the record with the useful information (wptr, ring
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* base, etc) and the microcode uses that information to set up the CP following
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* the preemption. When a ring is switched out, the CP will save the ringbuffer
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* state back to the record. In this way, once the records are properly set up
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* the CPU can quickly switch back and forth between ringbuffers by only
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* updating a few registers (often only the wptr).
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*
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* These are the CPU aware registers in the record:
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* @magic: Must always be 0x27C4BAFC
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* @info: Type of the record - written 0 by the CPU, updated by the CP
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* @data: Data field from SET_RENDER_MODE or a checkpoint. Written and used by
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* the CP
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* @cntl: Value of RB_CNTL written by CPU, save/restored by CP
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* @rptr: Value of RB_RPTR written by CPU, save/restored by CP
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* @wptr: Value of RB_WPTR written by CPU, save/restored by CP
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* @rptr_addr: Value of RB_RPTR_ADDR written by CPU, save/restored by CP
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* @rbase: Value of RB_BASE written by CPU, save/restored by CP
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* @counter: GPU address of the storage area for the performance counters
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*/
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struct a5xx_preempt_record {
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uint32_t magic;
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uint32_t info;
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uint32_t data;
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uint32_t cntl;
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uint32_t rptr;
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uint32_t wptr;
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uint64_t rptr_addr;
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uint64_t rbase;
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uint64_t counter;
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};
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/* Magic identifier for the preemption record */
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#define A5XX_PREEMPT_RECORD_MAGIC 0x27C4BAFCUL
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/*
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* Even though the structure above is only a few bytes, we need a full 64k to
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* store the entire preemption record from the CP
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*/
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#define A5XX_PREEMPT_RECORD_SIZE (64 * 1024)
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/*
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* The preemption counter block is a storage area for the value of the
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* preemption counters that are saved immediately before context switch. We
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* append it on to the end of the allocation for the preemption record.
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*/
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#define A5XX_PREEMPT_COUNTER_SIZE (16 * 4)
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int a5xx_power_init(struct msm_gpu *gpu);
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void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
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static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
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uint32_t reg, uint32_t mask, uint32_t value)
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{
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while (usecs--) {
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udelay(1);
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if ((gpu_read(gpu, reg) & mask) == value)
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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#define shadowptr(a5xx_gpu, ring) ((a5xx_gpu)->shadow_iova + \
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((ring)->id * sizeof(uint32_t)))
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bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
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void a5xx_preempt_init(struct msm_gpu *gpu);
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void a5xx_preempt_hw_init(struct msm_gpu *gpu);
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void a5xx_preempt_trigger(struct msm_gpu *gpu);
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void a5xx_preempt_irq(struct msm_gpu *gpu);
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void a5xx_preempt_fini(struct msm_gpu *gpu);
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void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, bool sync);
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/* Return true if we are in a preempt state */
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static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu)
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{
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int preempt_state = atomic_read(&a5xx_gpu->preempt_state);
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return !(preempt_state == PREEMPT_NONE ||
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preempt_state == PREEMPT_ABORT);
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}
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#endif /* __A5XX_GPU_H__ */
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