kernel_samsung_a53x/drivers/pci
Damien Le Moal 0f475924d6 PCI: rockchip-ep: Fix address translation unit programming
commit 64f093c4d99d797b68b407a9d8767aadc3e3ea7a upstream.

The Rockchip PCIe endpoint controller handles PCIe transfers addresses
by masking the lower bits of the programmed PCI address and using the
same number of lower bits masked from the CPU address space used for the
mapping. For a PCI mapping of <size> bytes starting from <pci_addr>,
the number of bits masked is the number of address bits changing in the
address range [pci_addr..pci_addr + size - 1].

However, rockchip_pcie_prog_ep_ob_atu() calculates num_pass_bits only
using the size of the mapping, resulting in an incorrect number of mask
bits depending on the value of the PCI address to map.

Fix this by introducing the helper function
rockchip_pcie_ep_ob_atu_num_bits() to correctly calculate the number of
mask bits to use to program the address translation unit. The number of
mask bits is calculated depending on both the PCI address and size of
the mapping, and clamped between 8 and 20 using the macros
ROCKCHIP_PCIE_AT_MIN_NUM_BITS and ROCKCHIP_PCIE_AT_MAX_NUM_BITS. As
defined in the Rockchip RK3399 TRM V1.3 Part2, Sections 17.5.5.1.1 and
17.6.8.2.1, this clamping is necessary because:

  1) The lower 8 bits of the PCI address to be mapped by the outbound
     region are ignored. So a minimum of 8 address bits are needed and
     imply that the PCI address must be aligned to 256.

  2) The outbound memory regions are 1MB in size. So while we can specify
     up to 63-bits for the PCI address (num_bits filed uses bits 0 to 5 of
     the outbound address region 0 register), we must limit the number of
     valid address bits to 20 to match the memory window maximum size (1
     << 20 = 1MB).

Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Link: https://lore.kernel.org/r/20241017015849.190271-2-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-17 13:24:35 +01:00
..
controller PCI: rockchip-ep: Fix address translation unit programming 2024-12-17 13:24:35 +01:00
endpoint
hotplug PCI: cpqphp: Fix PCIBIOS_* return value confusion 2024-12-17 13:24:11 +01:00
pcie
switch
access.c
ats.c
bus.c
ecam.c
host-bridge.c
iov.c
irq.c
Kconfig
Makefile
mmap.c
msi.c
of.c
p2pdma.c
pci-acpi.c
pci-bridge-emul.c
pci-bridge-emul.h
pci-driver.c
pci-label.c
pci-mid.c
pci-pf-stub.c
pci-stub.c
pci-sysfs.c PCI: Add 'reset_subordinate' to reset hierarchy below bridge 2024-12-17 13:24:32 +01:00
pci.c PCI: Add 'reset_subordinate' to reset hierarchy below bridge 2024-12-17 13:24:32 +01:00
pci.h PCI: Add 'reset_subordinate' to reset hierarchy below bridge 2024-12-17 13:24:32 +01:00
probe.c
proc.c
quirks.c PCI: Add ACS quirk for Wangxun FF5xxx NICs 2024-12-17 13:24:32 +01:00
remove.c
rom.c
search.c
setup-bus.c PCI: Fix resource double counting on remove & rescan 2024-11-23 23:20:10 +01:00
setup-irq.c
setup-res.c
slot.c PCI: Fix use-after-free of slot->bus on hot remove 2024-12-17 13:24:18 +01:00
syscall.c
vc.c
vpd.c
xen-pcifront.c