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PCI: Add ACS quirk for Wangxun FF5xxx NICs

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[ Upstream commit aa46a3736afcb7b0793766d22479b8b99fc1b322 ]

Wangxun FF5xxx NICs are similar to SFxxx, RP1000 and RP2000 NICs.  They may
be multi-function devices, but they do not advertise an ACS capability.

But the hardware does isolate FF5xxx functions as though it had an ACS
capability and PCI_ACS_RR and PCI_ACS_CR were set in the ACS Control
register, i.e., all peer-to-peer traffic is directed upstream instead of
being routed internally.

Add ACS quirk for FF5xxx NICs in pci_quirk_wangxun_nic_acs() so the
functions can be in independent IOMMU groups.

Link: https://lore.kernel.org/r/E16053DB2B80E9A5+20241115024604.30493-1-mengyuanlou@net-swift.com
Signed-off-by: Mengyuan Lou <mengyuanlou@net-swift.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Mengyuan Lou 2024-11-15 10:46:04 +08:00 • committed by Ksawlii
parent e2418b9a54
commit 2ca1cd586c
1 changed files with 9 additions and 6 deletions
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15
drivers/pci/quirks.c
View file

@ -4822,18 +4822,21 @@ static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
}
/*
* Wangxun 10G/1G NICs have no ACS capability, and on multi-function
* devices, peer-to-peer transactions are not be used between the functions.
* So add an ACS quirk for below devices to isolate functions.
* Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on
* multi-function devices, the hardware isolates the functions by
* directing all peer-to-peer traffic upstream as though PCI_ACS_RR and
* PCI_ACS_CR were set.
* SFxxx 1G NICs(em).
* RP1000/RP2000 10G NICs(sp).
* FF5xxx 40G/25G/10G NICs(aml).
*/
static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
{
switch (dev->device) {
case 0x0100 ... 0x010F:
case 0x1001:
case 0x2001:
case 0x0100 ... 0x010F: /* EM */
case 0x1001: case 0x2001: /* SP */
case 0x5010: case 0x5025: case 0x5040: /* AML */
case 0x5110: case 0x5125: case 0x5140: /* AML */
return pci_acs_ctrl_enabled(acs_flags,
PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
}