813 lines
28 KiB
C
Executable file
813 lines
28 KiB
C
Executable file
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/*
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* Copyright (c) 2019 Samsung Electronics Co., Ltd.
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*
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* Author: Hajun Sung <hajun.sung@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos2100 interrupt controller.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_S5E_9925_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_S5E_9925_H
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define EXT_INTA0_OUT0 0
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#define EXT_INTA0_OUT1 1
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#define EXT_INTA0_OUT2 2
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#define EXT_INTA0_OUT3 3
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#define EXT_INTA0_OUT4 4
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#define EXT_INTA0_OUT5 5
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#define EXT_INTA0_OUT6 6
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#define EXT_INTA0_OUT7 7
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#define EXT_INTA1_OUT0 8
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#define EXT_INTA1_OUT1 9
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#define EXT_INTA1_OUT2 10
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#define EXT_INTA1_OUT3 11
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#define EXT_INTA1_OUT4 12
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#define EXT_INTA1_OUT5 13
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#define EXT_INTA1_OUT6 14
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#define EXT_INTA1_OUT7 15
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#define EXT_INTA2_OUT0 16
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#define EXT_INTA2_OUT1 17
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#define EXT_INTA2_OUT2 18
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#define EXT_INTA2_OUT3 19
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#define EXT_INTA2_OUT4 20
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#define EXT_INTA2_OUT5 21
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#define EXT_INTA2_OUT6 22
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#define EXT_INTA2_OUT7 23
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#define EXT_INTA3_OUT0 24
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#define EXT_INTA3_OUT1 25
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#define EXT_INTA3_OUT2 26
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#define EXT_INTA3_OUT3 27
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#define EXT_INTA3_OUT4 28
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#define EXT_INTA3_OUT5 29
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#define EXT_INTA3_OUT6 30
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#define EXT_INTA3_OUT7 31
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#define EXT_INTA4_OUT0 32
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#define EXT_INTA4_OUT1 33
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#define INTREQ__ALIVE_GNSS_ACTIVE 34
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#define INTREQ__CLKMON_MONCLK 35
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#define INTREQ__CLKMON_REFSTUCK 36
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#define INTREQ__COMB_NONSECURE_INTCOMB_VGPIO2AP 37
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#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_ALIVE 38
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#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_ALIVE 39
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#define INTREQ__DBGCORE_UART 40
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#define INTREQ__MAILBOX_APM2AP 41
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#define INTREQ__MAILBOX_CHUB2AP 42
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#define INTREQ__MAILBOX_CP2AP_0 43
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#define INTREQ__MAILBOX_CP2AP_1 44
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#define INTREQ__MAILBOX_CP2AP_2 45
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#define INTREQ__MAILBOX_CP2AP_3 46
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#define INTREQ__MAILBOX_CP2AP_4 47
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#define INTREQ__MAILBOX_DBGCORE2AP 48
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#define INTREQ__MAILBOX_GNSS2AP 49
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#define INTREQ__MCT_ALIVE_IRQ_0 50
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#define INTREQ__MCT_ALIVE_IRQ_1 51
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#define INTREQ__MCT_ALIVE_IRQ_2 52
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#define INTREQ__MCT_ALIVE_IRQ_3 53
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#define INTREQ__MCT_ALIVE_IRQ_4 54
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#define INTREQ__MCT_ALIVE_IRQ_5 55
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#define INTREQ__MCT_ALIVE_IRQ_6 56
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#define INTREQ__MCT_ALIVE_IRQ_7 57
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#define INTREQ__MCT_ALIVE_IRQ_8 58
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#define INTREQ__MCT_ALIVE_IRQ_9 59
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#define INTREQ__MCT_ALIVE_IRQ_10 60
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#define INTREQ__MCT_ALIVE_IRQ_11 61
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#define INTREQ__MCT_ALIVE_S_IRQ_0 62
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#define INTREQ__MCT_ALIVE_S_IRQ_1 63
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#define INTREQ__MCT_ALIVE_S_IRQ_2 64
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#define INTREQ__MCT_ALIVE_S_IRQ_3 65
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#define INTREQ__NOTIFY 66
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#define INTREQ__RTC_ALARM_INT 67
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#define INTREQ__RTC_TIC_INT_0 68
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#define INTREQ__S_MAILBOX_CP2AP 69
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#define INTREQ__SPMI_MASTER_PMIC_0 70
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#define INTREQ__SPMI_MASTER_PMIC_1 71
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#define INTREQ__TOP_RTC_ALARM_INT 72
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#define INTREQ__TOP_RTC_TIC_INT_0 73
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#define INTREQ__AUD_ABOX_GIC400 74
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#define INTREQ__AUD_WDT 75
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#define INTREQ__PPMU_AUD 76
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#define INTREQ__SYSMMU_AUD_S1_NS 77
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#define INTREQ__SYSMMU_AUD_S1_S 78
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#define INTREQ__SYSMMU_AUD_S2_NS 79
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#define INTREQ__SYSMMU_AUD_S2_S 80
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#define INTREQ__BYRP_0 81
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#define INTREQ__BYRP_1 82
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#define INTREQ__PPMU_BYRP 83
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#define INTREQ__SYSMMU_D_BYRP_S1_NS 84
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#define INTREQ__SYSMMU_D_BYRP_S1_S 85
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#define INTREQ__SYSMMU_D_BYRP_S2_NS 86
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#define INTREQ__SYSMMU_D_BYRP_S2_S 87
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#define INTREQ__EXT_INTH0_0 88
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#define INTREQ__EXT_INTH0_1 89
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#define INTREQ__EXT_INTH0_2 90
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#define INTREQ__EXT_INTH0_3 91
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#define INTREQ__EXT_INTH1_0 92
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#define INTREQ__EXT_INTH1_1 93
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#define INTREQ__EXT_INTH1_2 94
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#define INTREQ__EXT_INTH1_3 95
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#define INTREQ__EXT_INTH2_0 96
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#define INTREQ__EXT_INTH2_1 97
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#define INTREQ__EXT_INTH2_2 98
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#define INTREQ__EXT_INTH2_3 99
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#define INTREQ__EXT_INTH3_0 100
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#define INTREQ__EXT_INTH3_1 101
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#define INTREQ__EXT_INTH3_2 102
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#define INTREQ__EXT_INTH3_3 103
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#define INTREQ__EXT_INTH4_0 104
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#define INTREQ__EXT_INTH4_1 105
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#define INTREQ__EXT_INTH4_2 106
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#define INTREQ__EXT_INTH4_3 107
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#define INTREQ__EXT_INTH5_0 108
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#define INTREQ__EXT_INTH5_1 109
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#define INTREQ__EXT_INTH5_2 110
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#define INTREQ__EXT_INTH5_3 111
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#define INTREQ__EXT_INTH5_4 112
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#define INTREQ__I2C_CHUB 113
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#define INTREQ__I3C_CHUB 114
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#define INTREQ__SPI_I2C_CHUB0 115
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#define INTREQ__SPI_I2C_CHUB1 116
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#define INTREQ__TIMER_CHUB 117
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#define INTREQ__USI_CHUB0 118
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#define INTREQ__USI_CHUB1 119
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#define INTREQ__USI_CHUB2 120
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#define INTREQ__USI_CHUB3 121
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#define INTREQ__WDT_CHUB 122
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#define INTRQ_PWM_CHUB_0 123
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#define INTRQ_PWM_CHUB_1 124
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#define INTRQ_PWM_CHUB_2 125
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#define INTRQ_PWM_CHUB_3 126
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#define INTREQ__CMGP_I2C 127
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#define INTREQ__EXT_INTM00 128
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#define INTREQ__EXT_INTM01 129
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#define INTREQ__EXT_INTM02 130
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#define INTREQ__EXT_INTM03 131
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#define INTREQ__EXT_INTM04 132
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#define INTREQ__EXT_INTM05 133
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#define INTREQ__EXT_INTM06 134
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#define INTREQ__EXT_INTM07 135
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#define INTREQ__EXT_INTM08 136
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#define INTREQ__EXT_INTM09 137
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#define INTREQ__EXT_INTM10 138
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#define INTREQ__EXT_INTM11 139
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#define INTREQ__EXT_INTM12 140
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#define INTREQ__EXT_INTM13 141
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#define INTREQ__EXT_INTM14 142
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#define INTREQ__EXT_INTM15 143
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#define INTREQ__EXT_INTM16 144
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#define INTREQ__EXT_INTM17 145
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#define INTREQ__EXT_INTM18 146
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#define INTREQ__EXT_INTM19 147
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#define INTREQ__EXT_INTM20 148
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#define INTREQ__EXT_INTM21 149
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#define INTREQ__EXT_INTM22 150
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#define INTREQ__EXT_INTM23 151
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#define INTREQ__EXT_INTM24 152
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#define INTREQ__EXT_INTM25 153
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#define INTREQ__EXT_INTM26 154
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#define INTREQ__EXT_INTM27 155
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#define INTREQ__EXT_INTM28 156
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#define INTREQ__EXT_INTM29 157
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#define INTREQ__EXT_INTM30 158
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#define INTREQ__EXT_INTM31 159
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#define INTREQ__EXT_INTM32 160
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#define INTREQ__EXT_INTM33 161
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#define INTREQ__EXT_INTM34 162
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#define INTREQ__EXT_INTM35 163
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#define INTREQ__EXT_INTM36 164
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#define INTREQ__EXT_INTM37 165
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#define INTREQ__EXT_INTM38 166
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#define INTREQ__I2C_CMGP2 167
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#define INTREQ__I2C_CMGP3 168
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#define INTREQ__I2C_CMGP4 169
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#define INTREQ__I2C_CMGP5 170
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#define INTREQ__I2C_CMGP6 171
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#define INTREQ__I3C_CMGP 172
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#define INTREQ__SPI_I2C_CMGP0 173
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#define INTREQ__SPI_I2C_CMGP1 174
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#define INTREQ__USI_CMGP0 175
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#define INTREQ__USI_CMGP1 176
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#define INTREQ__USI_CMGP2 177
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#define INTREQ__USI_CMGP3 178
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#define INTREQ__USI_CMGP4 179
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#define INTREQ__USI_CMGP5 180
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#define INTREQ__USI_CMGP6 181
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#define CMU_CPUCL0_PLL_CTRL_USER_IRQ 182
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#define CMU_CPUCL1_PLL_CTRL_USER_IRQ 183
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#define CMU_CPUCL2_PLL_CTRL_USER_IRQ 184
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#define CMU_DSU_PLL_CTRL_USER_IRQ 185
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#define INTREQ__CPUCL0_CLUSTERCRITIRQ 186
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#define INTREQ__CPUCL0_CLUSTERERRIRQ 187
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#define INTREQ__CPUCL0_CLUSTERFAULTIRQ 188
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#define INTREQ__CPUCL0_CLUSTERPMUIRQ 189
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#define INTREQ__CPUCL0_CTIIRQ_8 190
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#define INTREQ__CPUCL0_COMPLEXERRIRQ_0 191
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#define INTREQ__CPUCL0_COMPLEXERRIRQ_1 192
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#define INTREQ__CPUCL0_COMPLEXFAULTIRQ_0 193
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#define INTREQ__CPUCL0_COMPLEXFAULTIRQ_1 194
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#define INTREQ__CPUCL0_COREERRIRQ_0 195
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#define INTREQ__CPUCL0_COREERRIRQ_1 196
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#define INTREQ__CPUCL0_COREERRIRQ_2 197
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#define INTREQ__CPUCL0_COREERRIRQ_3 198
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#define INTREQ__CPUCL0_COREERRIRQ_4 199
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#define INTREQ__CPUCL0_COREERRIRQ_5 200
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#define INTREQ__CPUCL0_COREERRIRQ_6 201
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#define INTREQ__CPUCL0_COREERRIRQ_7 202
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#define INTREQ__CPUCL0_COREFAULTIRQ_0 203
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#define INTREQ__CPUCL0_COREFAULTIRQ_1 204
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#define INTREQ__CPUCL0_COREFAULTIRQ_2 205
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#define INTREQ__CPUCL0_COREFAULTIRQ_3 206
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#define INTREQ__CPUCL0_COREFAULTIRQ_4 207
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#define INTREQ__CPUCL0_COREFAULTIRQ_5 208
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#define INTREQ__CPUCL0_COREFAULTIRQ_6 209
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#define INTREQ__CPUCL0_COREFAULTIRQ_7 210
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#define INTREQ__CPUCL0_DPM 211
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#define INTREQ__CPUCL0_MPAMNSIRQ 212
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#define INTREQ__CPUCL0_MPAMSIRQ 213
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#define INTREQ__OCP_REATOR_CPUCL0_0 214
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#define INTREQ__OCP_REATOR_CPUCL0_1 215
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#define INTREQ__OCP_REATOR_CPUCL0_2 216
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#define INTREQ__OCP_REATOR_CPUCL0_3 217
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0 218
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1 219
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0 220
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1 221
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#define INTREQ__HDCP 222
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#define INTREQ__TBASE 223
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#define INTREQ__SECURE_LOG 224
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#define INTREQ__RPMB 225
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#define INTREQ__S2_LV3_TABLE_ALLOC 226
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#define INTREQ__DUMMY_S2MPU 227
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0 230
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1 231
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0 232
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1 233
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#define O_DDD_IRQ_FAST_0_CPUCL0 234
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#define O_DDD_IRQ_FAST_1_CPUCL0 235
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#define O_DDD_IRQ_FAST_2_CPUCL0 236
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#define O_DDD_IRQ_FAST_3_CPUCL0 237
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#define O_DDD_IRQ_FAST_4_CPUCL0 238
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#define O_DDD_IRQ_FAST_5_CPUCL0 239
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#define O_DDD_IRQ_SLOW_0_CPUCL0 240
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#define O_DDD_IRQ_SLOW_1_CPUCL0 241
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#define O_DDD_IRQ_SLOW_2_CPUCL0 242
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#define O_DDD_IRQ_SLOW_3_CPUCL0 243
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#define O_DDD_IRQ_SLOW_4_CPUCL0 244
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#define O_DDD_IRQ_SLOW_5_CPUCL0 245
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#define O_HPM_IRQ_CPUCL0 246
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#define O_INTREQ__ADD_CTRL_0_CPUCL0 247
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#define O_INTREQ__ADD_CTRL_1_CPUCL0 248
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#define O_INTREQ__ADD_CTRL_2_CPUCL0 249
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#define O_STR_IRQ_0_CPUCL0 250
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#define O_STR_IRQ_1_CPUCL0 251
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#define O_STR_IRQ_2_CPUCL0 252
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#define O_STR_IRQ_3_CPUCL0 253
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#define O_VOL_ERROR_DDD_HIGH_0_CPUCL0 254
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#define O_VOL_ERROR_DDD_HIGH_1_CPUCL0 255
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#define O_VOL_ERROR_DDD_HIGH_2_CPUCL0 256
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#define O_VOL_ERROR_DDD_HIGH_3_CPUCL0 257
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#define O_VOL_ERROR_DDD_HIGH_4_CPUCL0 258
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#define O_VOL_ERROR_DDD_HIGH_5_CPUCL0 259
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#define O_VOL_ERROR_DDD_LOW_0_CPUCL0 260
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#define O_VOL_ERROR_DDD_LOW_1_CPUCL0 261
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#define O_VOL_ERROR_DDD_LOW_2_CPUCL0 262
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#define O_VOL_ERROR_DDD_LOW_3_CPUCL0 263
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#define O_VOL_ERROR_DDD_LOW_4_CPUCL0 264
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#define O_VOL_ERROR_DDD_LOW_5_CPUCL0 265
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#define INTREQ__CSIS0 266
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#define INTREQ__CSIS1 267
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#define INTREQ__CSIS2 268
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#define INTREQ__CSIS3 269
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#define INTREQ__CSIS4 270
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#define INTREQ__CSIS5 271
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#define INTREQ__CSIS6 272
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#define INTREQ__CSIS_DMA0 273
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#define INTREQ__CSIS_DMA1 274
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#define INTREQ__CSIS_DMA2 275
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#define INTREQ__CSIS_DMA3 276
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#define INTREQ__CSIS_DMA4 277
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#define INTREQ__OIS_MCU_CSIS 278
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#define INTREQ__OVERFLOW_CSIS_PDP 279
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#define INTREQ__PDP0 280
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#define INTREQ__PDP1 281
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#define INTREQ__PDP2 282
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#define INTREQ__PDP3 283
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#define INTREQ__PDP4 284
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#define INTREQ__PDP5 285
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#define INTREQ__PDP6 286
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#define INTREQ__PDP7 287
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#define INTREQ__PPMU_CSIS 288
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#define INTREQ__SYSMMU_D0_CSIS_S1_NS 289
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#define INTREQ__SYSMMU_D0_CSIS_S1_S 290
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#define INTREQ__SYSMMU_D0_CSIS_S2_NS 291
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#define INTREQ__SYSMMU_D0_CSIS_S2_S 292
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#define INTREQ__SYSMMU_D1_CSIS_S1_NS 293
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#define INTREQ__SYSMMU_D1_CSIS_S1_S 294
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#define INTREQ__SYSMMU_D1_CSIS_S2_NS 295
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#define INTREQ__SYSMMU_D1_CSIS_S2_S 296
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#define INTREQ__SYSMMU_D2_CSIS_S1_NS 297
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#define INTREQ__SYSMMU_D2_CSIS_S1_S 298
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#define INTREQ__SYSMMU_D2_CSIS_S2_NS 299
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#define INTREQ__SYSMMU_D2_CSIS_S2_S 300
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#define INTREQ__SYSMMU_D3_CSIS_S1_NS 301
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#define INTREQ__SYSMMU_D3_CSIS_S1_S 302
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#define INTREQ__SYSMMU_D3_CSIS_S2_NS 303
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#define INTREQ__SYSMMU_D3_CSIS_S2_S 304
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#define INTREQ__SYSMMU_D4_CSIS_S1_NS 305
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#define INTREQ__SYSMMU_D4_CSIS_S1_S 306
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#define INTREQ__SYSMMU_D4_CSIS_S2_NS 307
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#define INTREQ__SYSMMU_D4_CSIS_S2_S 308
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#define INTREQ__WDTRESET_OIS_MCU 309
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#define INTREQ__CSTAT_CH0_0 310
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#define INTREQ__CSTAT_CH0_1 311
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#define INTREQ__CSTAT_CH1_0 312
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#define INTREQ__CSTAT_CH1_1 313
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#define INTREQ__CSTAT_CH2_0 314
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#define INTREQ__CSTAT_CH2_1 315
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#define INTREQ__CSTAT_CH3_0 316
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#define INTREQ__CSTAT_CH3_1 317
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#define INTREQ__PPMU_CSTAT 318
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#define INTREQ__SYSMMU_D_CSTAT_S1_NS 319
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#define INTREQ__SYSMMU_D_CSTAT_S1_S 320
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#define INTREQ__SYSMMU_D_CSTAT_S2_NS 321
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#define INTREQ__SYSMMU_D_CSTAT_S2_S 322
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#define INTREQ__ADD_CTRL_DNC 323
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#define INTREQ__DD_ERR_IRQ_FAST_DNC 324
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#define INTREQ__DD_ERR_IRQ_SLOW_DNC 325
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#define INTREQ__DD_SZ_HIGH_DNC 326
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#define INTREQ__DD_SZ_LOW_DNC 327
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#define INTREQ__FROM_DNC_TO_HOST_NS_0 328
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#define INTREQ__FROM_DNC_TO_HOST_NS_1 329
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#define INTREQ__FROM_DNC_TO_HOST_NS_2 330
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#define INTREQ__FROM_DNC_TO_HOST_NS_3 331
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#define INTREQ__FROM_DNC_TO_HOST_NS_4 332
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#define INTREQ__FROM_DNC_TO_HOST_NS_5 333
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#define INTREQ__FROM_DNC_TO_HOST_NS_6 334
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#define INTREQ__FROM_DNC_TO_HOST_NS_7 335
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#define INTREQ__FROM_DNC_TO_HOST_S_0 336
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#define INTREQ__FROM_DNC_TO_HOST_S_1 337
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#define INTREQ__FROM_DNC_TO_HOST_S_2 338
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#define INTREQ__FROM_DNC_TO_HOST_S_3 339
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#define INTREQ__FROM_DNC_TO_HOST_S_4 340
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#define INTREQ__FROM_DNC_TO_HOST_S_5 341
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#define INTREQ__FROM_DNC_TO_HOST_S_6 342
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#define INTREQ__FROM_DNC_TO_HOST_S_7 343
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#define INTREQ__HPM_IRQ_DNC 344
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#define INTREQ__O_OCP_THROTT_INTR_DNC 345
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#define INTREQ__PPMU_DNC 346
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#define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S1_NS 347
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#define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S1_S 348
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#define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S2_NS 349
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#define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S2_S 350
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#define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S1_NS 351
|
|
#define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S1_S 352
|
|
#define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S2_NS 353
|
|
#define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S2_S 354
|
|
#define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S1_NS 355
|
|
#define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S1_S 356
|
|
#define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S2_NS 357
|
|
#define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S2_S 358
|
|
#define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S1_NS 359
|
|
#define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S1_S 360
|
|
#define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S2_NS 361
|
|
#define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S2_S 362
|
|
#define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S1_NS 363
|
|
#define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S1_S 364
|
|
#define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S2_NS 365
|
|
#define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S2_S 366
|
|
#define INTREQ__DPUB_DECON0_DQE_DIMMING_END 367
|
|
#define INTREQ__DPUB_DECON0_DQE_DIMMING_START 368
|
|
#define INTREQ__DPUB_DECON0_EXTRA 369
|
|
#define INTREQ__DPUB_DECON0_FRAME_DONE 370
|
|
#define INTREQ__DPUB_DECON0_FRAME_START 371
|
|
#define INTREQ__DPUB_DECON1_DQE_DIMMING_END 372
|
|
#define INTREQ__DPUB_DECON1_DQE_DIMMING_START 373
|
|
#define INTREQ__DPUB_DECON1_EXTRA 374
|
|
#define INTREQ__DPUB_DECON1_FRAME_DONE 375
|
|
#define INTREQ__DPUB_DECON1_FRAME_START 376
|
|
#define INTREQ__DPUB_DECON2_EXTRA 377
|
|
#define INTREQ__DPUB_DECON2_FRAME_DONE 378
|
|
#define INTREQ__DPUB_DECON2_FRAME_START 379
|
|
#define INTREQ__DPUB_DECON3_EXTRA 380
|
|
#define INTREQ__DPUB_DECON3_FRAME_DONE 381
|
|
#define INTREQ__DPUB_DECON3_FRAME_START 382
|
|
#define INTREQ__DPUB_DSIM0 383
|
|
#define INTREQ__DPUB_DSIM1 384
|
|
#define INTREQ__DPUB_DSIM2 385
|
|
#define INTREQ__DPUF0_DMA_C2A_MST 386
|
|
#define INTREQ__DPUF0_DMA_C2A_SLV 387
|
|
#define INTREQ__DPUF0_DMA_CGC 388
|
|
#define INTREQ__DPUF0_DMA_DSIMFC0 389
|
|
#define INTREQ__DPUF0_DMA_DSIMFC1 390
|
|
#define INTREQ__DPUF0_DMA_L0 391
|
|
#define INTREQ__DPUF0_DMA_L1 392
|
|
#define INTREQ__DPUF0_DMA_L2 393
|
|
#define INTREQ__DPUF0_DMA_L3 394
|
|
#define INTREQ__DPUF0_DMA_L4 395
|
|
#define INTREQ__DPUF0_DMA_L5 396
|
|
#define INTREQ__DPUF0_DMA_L6 397
|
|
#define INTREQ__DPUF0_DMA_L7 398
|
|
#define INTREQ__DPUF0_DMA_WB 399
|
|
#define INTREQ__DPUF0_DPP_L0 400
|
|
#define INTREQ__DPUF0_DPP_L1 401
|
|
#define INTREQ__DPUF0_DPP_L2 402
|
|
#define INTREQ__DPUF0_DPP_L3 403
|
|
#define INTREQ__DPUF0_DPP_L4 404
|
|
#define INTREQ__DPUF0_DPP_L5 405
|
|
#define INTREQ__DPUF0_DPP_L6 406
|
|
#define INTREQ__DPUF0_DPP_L7 407
|
|
#define INTREQ__DPUF0_DPP_WB 408
|
|
#define INTREQ__DPUF0_SRAMCON_D0 409
|
|
#define INTREQ__DPUF0_SRAMCON_D1 410
|
|
#define INTREQ__DPUF0_SRAMCON_D2 411
|
|
#define INTREQ__DPUF0_SRAMCON_D3 412
|
|
#define INTREQ__PPMU_DPUF0 413
|
|
#define INTREQ__SYSMMU_DPUF0D0_S1_NS 414
|
|
#define INTREQ__SYSMMU_DPUF0D0_S1_S 415
|
|
#define INTREQ__SYSMMU_DPUF0D0_S2_NS 416
|
|
#define INTREQ__SYSMMU_DPUF0D0_S2_S 417
|
|
#define INTREQ__SYSMMU_DPUF0D1_S1_NS 418
|
|
#define INTREQ__SYSMMU_DPUF0D1_S1_S 419
|
|
#define INTREQ__SYSMMU_DPUF0D1_S2_NS 420
|
|
#define INTREQ__SYSMMU_DPUF0D1_S2_S 421
|
|
#define INTREQ__DPUF1_DMA_C2A_MST 422
|
|
#define INTREQ__DPUF1_DMA_C2A_SLV 423
|
|
#define INTREQ__DPUF1_DMA_CGC 424
|
|
#define INTREQ__DPUF1_DMA_DSIMFC0 425
|
|
#define INTREQ__DPUF1_DMA_DSIMFC1 426
|
|
#define INTREQ__DPUF1_DMA_L0 427
|
|
#define INTREQ__DPUF1_DMA_L1 428
|
|
#define INTREQ__DPUF1_DMA_L2 429
|
|
#define INTREQ__DPUF1_DMA_L3 430
|
|
#define INTREQ__DPUF1_DMA_L4 431
|
|
#define INTREQ__DPUF1_DMA_L5 432
|
|
#define INTREQ__DPUF1_DMA_L6 433
|
|
#define INTREQ__DPUF1_DMA_L7 434
|
|
#define INTREQ__DPUF1_DMA_WB 435
|
|
#define INTREQ__DPUF1_DPP_L0 436
|
|
#define INTREQ__DPUF1_DPP_L1 437
|
|
#define INTREQ__DPUF1_DPP_L2 438
|
|
#define INTREQ__DPUF1_DPP_L3 439
|
|
#define INTREQ__DPUF1_DPP_L4 440
|
|
#define INTREQ__DPUF1_DPP_L5 441
|
|
#define INTREQ__DPUF1_DPP_L6 442
|
|
#define INTREQ__DPUF1_DPP_L7 443
|
|
#define INTREQ__DPUF1_DPP_WB 444
|
|
#define INTREQ__DPUF1_SRAMCON_D0 445
|
|
#define INTREQ__DPUF1_SRAMCON_D1 446
|
|
#define INTREQ__DPUF1_SRAMCON_D2 447
|
|
#define INTREQ__DPUF1_SRAMCON_D3 448
|
|
#define INTREQ__PPMU_DPUF1 449
|
|
#define INTREQ__SYSMMU_DPUF1D0_S1_NS 450
|
|
#define INTREQ__SYSMMU_DPUF1D0_S1_S 451
|
|
#define INTREQ__SYSMMU_DPUF1D0_S2_NS 452
|
|
#define INTREQ__SYSMMU_DPUF1D0_S2_S 453
|
|
#define INTREQ__SYSMMU_DPUF1D1_S1_NS 454
|
|
#define INTREQ__SYSMMU_DPUF1D1_S1_S 455
|
|
#define INTREQ__SYSMMU_DPUF1D1_S2_NS 456
|
|
#define INTREQ__SYSMMU_DPUF1D1_S2_S 457
|
|
#define INTREQ__DRCP_0 458
|
|
#define INTREQ__DRCP_1 459
|
|
#define INTREQ__PPMU_DRCP 460
|
|
#define INTREQ__SYSMMU_D_DRCP_S1_NS 461
|
|
#define INTREQ__SYSMMU_D_DRCP_S1_S 462
|
|
#define INTREQ__SYSMMU_D_DRCP_S2_NS 463
|
|
#define INTREQ__SYSMMU_D_DRCP_S2_S 464
|
|
#define CMU_G3DCORE_PLL_CTRL_USER_IRQ 465
|
|
#define INTREQ__ADD_CTRL_G3D 466
|
|
#define INTREQ__GPU_INT 467
|
|
#define INTREQ__HTU_G3D_INT 468
|
|
#define O_DDD_IRQ_FAST_G3D 469
|
|
#define O_DDD_IRQ_SLOW_G3D 470
|
|
#define O_HPM_IRQ_G3D 471
|
|
#define O_STR_IRQ_G3D 472
|
|
#define O_VOL_ERROR_DDD_HIGH_G3D 473
|
|
#define O_VOL_ERROR_DDD_LOW_G3D 474
|
|
#define INTREQ__GNSS_PPMU_IRQ 475
|
|
#define INTREQ__GNSS_SW_INT 476
|
|
#define INTREQ__GNSS_WAKEUP_INT 477
|
|
#define INTREQ__GNSS_WDOG_RESET 478
|
|
#define INTREQ__DP_LINK 479
|
|
#define INTREQ__PPMU_HSI0 480
|
|
#define INTREQ__USB2_REMOTE_CONNECT_GIC 481
|
|
#define INTREQ__USB2_REMOTE_TIMER_GIC 482
|
|
#define INTREQ__USB2_REMOTE_WAKEUP_GIC 483
|
|
#define INTREQ__USB20_PHY_FSVPLUS_MINUS_GIC 484
|
|
#define INTREQ__USB32DRD_GIC0 485
|
|
#define INTREQ__USB32DRD_GIC1 486
|
|
#define INTREQ__USB32DRD_REWA_WAKEUP_REQ 487
|
|
#define INTREQ__USBDPPHY_TCA 488
|
|
#define O_INTERRUPT_S2_NS 489
|
|
#define O_INTERRUPT_S2_S 490
|
|
#define INTREQ__GPIO_HSI1 491
|
|
#define INTREQ__GPIO_HSI1UFS 492
|
|
#define INTREQ__MMC_CARD 493
|
|
#define INTREQ__PCIE_GEN2 494
|
|
#define INTREQ__PCIE_GEN2A_MSI_0 495
|
|
#define INTREQ__PCIE_GEN2A_MSI_1 496
|
|
#define INTREQ__PCIE_GEN2A_MSI_2 497
|
|
#define INTREQ__PCIE_GEN2A_MSI_3 498
|
|
#define INTREQ__PCIE_GEN2A_MSI_4 499
|
|
#define INTREQ__PCIE_GEN3 500
|
|
#define INTREQ__PCIE_GEN3A_MSI_0 501
|
|
#define INTREQ__PCIE_GEN3A_MSI_1 502
|
|
#define INTREQ__PCIE_GEN3A_MSI_2 503
|
|
#define INTREQ__PCIE_GEN3A_MSI_3 504
|
|
#define INTREQ__PCIE_GEN3A_MSI_4 505
|
|
#define INTREQ__PCIE_IA_GEN2 506
|
|
#define INTREQ__PCIE_IA_GEN3 507
|
|
#define INTREQ__PCIE_PCS_GEN2 508
|
|
#define INTREQ__PCIE_PCS_GEN3 509
|
|
#define INTREQ__PPMU_HSI1 510
|
|
#define INTREQ__SYSMMU_HSI1_S1_NONSECURE 511
|
|
#define INTREQ__SYSMMU_HSI1_S1_SECURE 512
|
|
#define INTREQ__SYSMMU_HSI1_S2_NONSECURE 513
|
|
#define INTREQ__SYSMMU_HSI1_S2_SECURE 514
|
|
#define INTREQ__UFS_EMBD 515
|
|
#define INTREQ__FRC_MC_DBL_ERR 516
|
|
#define INTREQ__FRC_MC_DONE 517
|
|
#define INTREQ__LME_O_INT0 518
|
|
#define INTREQ__PPMU_LME 519
|
|
#define INTREQ__SYSMMU_D_LME_S1_NONSECURE 520
|
|
#define INTREQ__SYSMMU_D_LME_S1_SECURE 521
|
|
#define INTREQ__SYSMMU_D_LME_S2_NONSECURE 522
|
|
#define INTREQ__SYSMMU_D_LME_S2_SECURE 523
|
|
#define INTREQ__M2M__ASTC 524
|
|
#define INTREQ__M2M__JPEG0 525
|
|
#define INTREQ__M2M__JPEG1 526
|
|
#define INTREQ__M2M__JSQZ 527
|
|
#define INTREQ__M2M__M2M 528
|
|
#define INTREQ__M2M__SYSMMU_D_M2M_PM_S1_NS 529
|
|
#define INTREQ__M2M__SYSMMU_D_M2M_PM_S1_S 530
|
|
#define INTREQ__M2M__SYSMMU_D_M2M_PM_S2_NS 531
|
|
#define INTREQ__M2M__SYSMMU_D_M2M_PM_S2_S 532
|
|
#define INTREQ__PPMU_M2M 533
|
|
#define INTREQ__MCFP_0 534
|
|
#define INTREQ__MCFP_1 535
|
|
#define INTREQ__PPMU_MCFP 536
|
|
#define INTREQ__SYSMMU_D0_MCFP_S1_NONSECURE 537
|
|
#define INTREQ__SYSMMU_D0_MCFP_S1_SECURE 538
|
|
#define INTREQ__SYSMMU_D0_MCFP_S2_NONSECURE 539
|
|
#define INTREQ__SYSMMU_D0_MCFP_S2_SECURE 540
|
|
#define INTREQ__SYSMMU_D1_MCFP_S1_NONSECURE 541
|
|
#define INTREQ__SYSMMU_D1_MCFP_S1_SECURE 542
|
|
#define INTREQ__SYSMMU_D1_MCFP_S2_NONSECURE 543
|
|
#define INTREQ__SYSMMU_D1_MCFP_S2_SECURE 544
|
|
#define INTREQ__SYSMMU_D2_MCFP_S1_NONSECURE 545
|
|
#define INTREQ__SYSMMU_D2_MCFP_S1_SECURE 546
|
|
#define INTREQ__SYSMMU_D2_MCFP_S2_NONSECURE 547
|
|
#define INTREQ__SYSMMU_D2_MCFP_S2_SECURE 548
|
|
#define INTREQ__SYSMMU_D3_MCFP_S1_NONSECURE 549
|
|
#define INTREQ__SYSMMU_D3_MCFP_S1_SECURE 550
|
|
#define INTREQ__SYSMMU_D3_MCFP_S2_NONSECURE 551
|
|
#define INTREQ__SYSMMU_D3_MCFP_S2_SECURE 552
|
|
#define INTREQ__SYSMMU_D4_MCFP_S1_NONSECURE 553
|
|
#define INTREQ__SYSMMU_D4_MCFP_S1_SECURE 554
|
|
#define INTREQ__SYSMMU_D4_MCFP_S2_NONSECURE 555
|
|
#define INTREQ__SYSMMU_D4_MCFP_S2_SECURE 556
|
|
#define INTREQ__SYSMMU_D5_MCFP_S1_NONSECURE 557
|
|
#define INTREQ__SYSMMU_D5_MCFP_S1_SECURE 558
|
|
#define INTREQ__SYSMMU_D5_MCFP_S2_NONSECURE 559
|
|
#define INTREQ__SYSMMU_D5_MCFP_S2_SECURE 560
|
|
#define INTREQ__GDC_IRQ_0 561
|
|
#define INTREQ__GDC_IRQ_1 562
|
|
#define INTREQ__MCSC_INTREQ_0 563
|
|
#define INTREQ__MCSC_INTREQ_1 564
|
|
#define INTREQ__PPMU_MCSC 565
|
|
#define INTREQ__SYSMMU_D0_MCSC_S1_NS 566
|
|
#define INTREQ__SYSMMU_D0_MCSC_S1_S 567
|
|
#define INTREQ__SYSMMU_D0_MCSC_S2_NS 568
|
|
#define INTREQ__SYSMMU_D0_MCSC_S2_S 569
|
|
#define INTREQ__SYSMMU_D1_MCSC_S1_NS 570
|
|
#define INTREQ__SYSMMU_D1_MCSC_S1_S 571
|
|
#define INTREQ__SYSMMU_D1_MCSC_S2_NS 572
|
|
#define INTREQ__SYSMMU_D1_MCSC_S2_S 573
|
|
#define INTREQ__SYSMMU_D2_MCSC_S1_NS 574
|
|
#define INTREQ__SYSMMU_D2_MCSC_S1_S 575
|
|
#define INTREQ__SYSMMU_D2_MCSC_S2_NS 576
|
|
#define INTREQ__SYSMMU_D2_MCSC_S2_S 577
|
|
#define INTREQ__MFC0 578
|
|
#define INTREQ__PPMU_MFC0 579
|
|
#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_ns 580
|
|
#define INTREQ__SYSMMU_MFC0D0_interrupt_s1_s 581
|
|
#define INTREQ__SYSMMU_MFC0D0_interrupt_s2_ns 582
|
|
#define INTREQ__SYSMMU_MFC0D0_interrupt_s2_s 583
|
|
#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_ns 584
|
|
#define INTREQ__SYSMMU_MFC0D1_interrupt_s1_s 585
|
|
#define INTREQ__SYSMMU_MFC0D1_interrupt_s2_ns 586
|
|
#define INTREQ__SYSMMU_MFC0D1_interrupt_s2_s 587
|
|
#define INTREQ__WFD 588
|
|
#define INTREQ__MFC1 589
|
|
#define INTREQ__PPMU_MFC1 590
|
|
#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_ns 591
|
|
#define INTREQ__SYSMMU_MFC1D0_interrupt_s1_s 592
|
|
#define INTREQ__SYSMMU_MFC1D0_interrupt_s2_ns 593
|
|
#define INTREQ__SYSMMU_MFC1D0_interrupt_s2_s 594
|
|
#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_ns 595
|
|
#define INTREQ__SYSMMU_MFC1D1_interrupt_s1_s 596
|
|
#define INTREQ__SYSMMU_MFC1D1_interrupt_s2_ns 597
|
|
#define INTREQ__SYSMMU_MFC1D1_interrupt_s2_s 598
|
|
#define INTREQ__DMC_ECC_CORERR_MIF0 599
|
|
#define INTREQ__DMC_ECC_UNCORERR_MIF0 600
|
|
#define INTREQ__DMC_PPMPINT_MIF0 601
|
|
#define INTREQ__DMC_TEMPERR_MIF0 602
|
|
#define INTREQ__DMC_TEMPHOT_MIF0 603
|
|
#define INTREQ__DMC_TZCINT_MIF0 604
|
|
#define INTREQ__PPMU_MIF_MIF0 605
|
|
#define INTREQ__DMC_ECC_CORERR_MIF1 606
|
|
#define INTREQ__DMC_ECC_UNCORERR_MIF1 607
|
|
#define INTREQ__DMC_PPMPINT_MIF1 608
|
|
#define INTREQ__DMC_TEMPERR_MIF1 609
|
|
#define INTREQ__DMC_TEMPHOT_MIF1 610
|
|
#define INTREQ__DMC_TZCINT_MIF1 611
|
|
#define INTREQ__PPMU_MIF_MIF1 612
|
|
#define INTREQ__DMC_ECC_CORERR_MIF2 613
|
|
#define INTREQ__DMC_ECC_UNCORERR_MIF2 614
|
|
#define INTREQ__DMC_PPMPINT_MIF2 615
|
|
#define INTREQ__DMC_TEMPERR_MIF2 616
|
|
#define INTREQ__DMC_TEMPHOT_MIF2 617
|
|
#define INTREQ__DMC_TZCINT_MIF2 618
|
|
#define INTREQ__PPMU_MIF_MIF2 619
|
|
#define INTREQ__DMC_ECC_CORERR_MIF3 620
|
|
#define INTREQ__DMC_ECC_UNCORERR_MIF3 621
|
|
#define INTREQ__DMC_PPMPINT_MIF3 622
|
|
#define INTREQ__DMC_TEMPERR_MIF3 623
|
|
#define INTREQ__DMC_TEMPHOT_MIF3 624
|
|
#define INTREQ__DMC_TZCINT_MIF3 625
|
|
#define INTREQ__PPMU_MIF_MIF3 626
|
|
#define INTREQ_CPALV_GPIO 627
|
|
#define INTREQ_MODEM_PPMU 628
|
|
#define INTREQ_RESET_REQ 629
|
|
#define INTREQ__CCI_ERRINT_COR 630
|
|
#define INTREQ__CCI_ERRINT_UNCOR 631
|
|
#define INTREQ__CCI_TZCINT 632
|
|
#define INTREQ__PPC_DEBUG_CCI_PPC_INTR 633
|
|
#define INTREQ__PPMU_WOW_GLUE_O_INTREQ__WOW_DVFS_SCI_GIC 634
|
|
#define INTREQ__PPMU_WOW_GLUE_O_INTREQ__WOW_DVFS_SMC_GIC 635
|
|
#define INTREQ__PPMU_WOW_GLUE_O_PPMU_INTC 636
|
|
#define INTREQ__SYSMMU_APM_S2_NONSECURE 637
|
|
#define INTREQ__SYSMMU_APM_S2_SECURE 638
|
|
#define INTREQ__SYSMMU_G3D_S2_NONSECURE 639
|
|
#define INTREQ__SYSMMU_G3D_S2_SECURE 640
|
|
#define INTREQ__SYSMMU_MODEM_S1_NONSECURE 641
|
|
#define INTREQ__SYSMMU_MODEM_S1_SECURE 642
|
|
#define INTREQ__SYSMMU_MODEM_S2_NONSECURE 643
|
|
#define INTREQ__SYSMMU_MODEM_S2_SECURE 644
|
|
#define INTREQ__TREX_D_NOCL0_debugInterrupt 645
|
|
#define INTREQ__TREX_P_NOCL0_debugInterrupt 646
|
|
#define INTREQ__DIT_RxDst00 647
|
|
#define INTREQ__DIT_RxDst01 648
|
|
#define INTREQ__DIT_RxDst1 649
|
|
#define INTREQ__DIT_RxDst02 650
|
|
#define INTREQ__DIT_RxDst2 651
|
|
#define INTREQ__DIT_RxDst03 652
|
|
#define INTREQ__DIT_RxSrc0 653
|
|
#define INTREQ__DIT_RxSrc1 654
|
|
#define INTREQ__DIT_RxSrc2 655
|
|
#define INTREQ__DIT_TxDst0 656
|
|
#define INTREQ__DIT_TxDst1 657
|
|
#define INTREQ__DIT_TxDst2 658
|
|
#define INTREQ__DIT_TxSrc0 659
|
|
#define INTREQ__DIT_TxSrc1 660
|
|
#define INTREQ__DIT_TxSrc2 661
|
|
#define INTREQ__PDMA 662
|
|
#define INTREQ__PPMU 663
|
|
#define INTREQ__SPDMA 664
|
|
#define INTREQ__SYSMMU_DIT_S2_NS 665
|
|
#define INTREQ__SYSMMU_DIT_S2_S 666
|
|
#define INTREQ__SYSMMU_TT_S1_NS 667
|
|
#define INTREQ__SYSMMU_TT_S1_S 668
|
|
#define INTREQ__SYSMMU_TT_S2_NS 669
|
|
#define INTREQ__SYSMMU_TT_S2_S 670
|
|
#define INTREQ__GPIO_PERIC0 671
|
|
#define INTREQ__USI04_I2C 672
|
|
#define INTREQ__USI04_USI 673
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#define INTREQ__BT_UART 674
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#define INTREQ__GPIO_PERIC1 675
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#define INTREQ__I3C00 676
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#define INTREQ__I3C01 677
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#define INTREQ__I3C02 678
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#define INTREQ__USI07_SPI_I2C 679
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#define INTREQ__USI07_USI 680
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#define INTREQ__USI08_SPI_I2C 681
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#define INTREQ__USI08_USI 682
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#define INTREQ__USI09_I2C 683
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#define INTREQ__USI09_USI 684
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#define INTREQ__USI10_I2C 685
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#define INTREQ__USI10_USI 686
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#define INTREQ__DBG_UART 687
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#define INTREQ__GPIO_PERIC2 688
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#define INTREQ__I3C03 689
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#define INTREQ__I3C04 690
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#define INTREQ__I3C05 691
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#define INTREQ__I3C06 692
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#define INTREQ__I3C07 693
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#define INTREQ__I3C08 694
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#define INTREQ__I3C09 695
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#define INTREQ__I3C10 696
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#define INTREQ__I3C11 697
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#define INTREQ__PWM0 698
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#define INTREQ__PWM1 699
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#define INTREQ__PWM2 700
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#define INTREQ__PWM3 701
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#define INTREQ__PWM4 702
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#define INTREQ__USI00_SPI_I2C 703
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#define INTREQ__USI00_USI 704
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#define INTREQ__USI01_SPI_I2C 705
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#define INTREQ__USI01_USI 706
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#define INTREQ__USI02_I2C 707
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#define INTREQ__USI02_USI 708
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#define INTREQ__USI03_I2C 709
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#define INTREQ__USI03_USI 710
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#define INTREQ__USI05_I2C 711
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#define INTREQ__USI05_USI 712
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#define INTREQ__USI06_I2C 713
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#define INTREQ__USI06_USI 714
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#define INTREQ__USI11_I2C 715
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#define INTREQ__USI11_USI 716
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#define INTREQ__PPMU_RGBP 717
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#define INTREQ__RGBP_0 718
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#define INTREQ__RGBP_1 719
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#define INTREQ__SYSMMU_D0_RGBP_S1_NS 720
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#define INTREQ__SYSMMU_D0_RGBP_S1_S 721
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#define INTREQ__SYSMMU_D0_RGBP_S2_NS 722
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#define INTREQ__SYSMMU_D0_RGBP_S2_S 723
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#define INTREQ__SYSMMU_D1_RGBP_S1_NS 724
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#define INTREQ__SYSMMU_D1_RGBP_S1_S 725
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#define INTREQ__SYSMMU_D1_RGBP_S2_NS 726
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#define INTREQ__SYSMMU_D1_RGBP_S2_S 727
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#define INTREQ__PPMU_SSP_O_interrupt_upper_or_normal 728
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#define INTREQ__RTIC 729
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#define INTREQ__SSS 730
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#define INTREQ__SSS_CTIIRQ_0 731
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#define INTREQ__SSS_CTIIRQ_1 732
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#define INTREQ__SSS_DMA 733
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#define INTREQ__SSS_KM 734
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#define INTREQ__SSS_NS_MB 735
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#define INTREQ__SSS_S_MB 736
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#define INTREQ__SSS_SWDT1 737
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#define INTREQ__STRONG_0 738
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#define INTREQ__STRONG_1 739
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#define INTREQ__STRONG_2 740
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#define INTREQ__STRONG_3 741
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#define INTREQ__STRONG_CPU_WDTRESET 742
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#define INTREQ__SYSMMU_NONSECURE 743
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#define INTREQ__SYSMMU_SECURE 744
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#define INTREQ__I3C_INTREQ 745
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#define INTREQ__PDMA_INTREQ 746
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#define INTREQ__SPI_INTREQ 747
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#define INTREQ__UFD_0_INTREQ 748
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#define INTREQ__UFD_1_INTREQ 749
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#define INTREQ__UFD_2_INTREQ 750
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#define INTREQ__UFD_3_INTREQ 751
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#define INTREQ__UFD_4_INTREQ 752
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#define INTREQ__UFD_5_INTREQ 753
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#define INTREQ__UFD_6_INTREQ 754
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#define INTREQ__UFD_7_INTREQ 755
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#define INTREQ__MAILBOX_AP_VTS 756
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#define INTREQ__WDT_VTS 757
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#define INTREQ__ADD_YUVP 758
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#define INTREQ__DD_ERR_IRQ_FAST_YUVP 759
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#define INTREQ__DD_ERR_IRQ_SLOW_YUVP 760
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#define INTREQ__DD_SZ_HIGH_YUVP 761
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#define INTREQ__DD_SZ_LOW_YUVP 762
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#define INTREQ__HPM_YUVP 763
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#define INTREQ__PPMU_YUVP 764
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#define INTREQ__SYSMMU_D_YUVP_S1_NS 765
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#define INTREQ__SYSMMU_D_YUVP_S1_S 766
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#define INTREQ__SYSMMU_D_YUVP_S2_NS 767
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#define INTREQ__SYSMMU_D_YUVP_S2_S 768
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#define INTREQ__YUVP_0 769
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#define INTREQ__YUVP_1 770
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#define INTREQ__TEEGRIS_EVENT 868
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#define INTREQ__TEEGRIS_PANIC 869
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#define INTREQ__OTP_CON_BIRA 938
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#define INTREQ__TREX_DEBUG 939
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#define INTREQ__OTP_CON_TOP 940
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#define INTREQ__WDT0 941
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#define INTREQ__WDT1 942
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#define INTREQ__MCT_G0 943
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#define INTREQ__MCT_G1 944
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#define INTREQ__MCT_G2 945
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#define INTREQ__MCT_G3 946
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#define INTREQ__MCT_L0 947
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#define INTREQ__MCT_L1 948
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#define INTREQ__MCT_L2 949
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#define INTREQ__MCT_L3 950
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#define INTREQ__MCT_L4 951
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#define INTREQ__MCT_L5 952
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#define INTREQ__MCT_L6 953
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#define INTREQ__MCT_L7 954
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#define INTREQ__TMU_TMU_TOP 955
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#define INTREQ__TMU_TMU_SUB 956
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#define INTREQ__GIC_PMU_INT 957
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#define INTREQ__GIC_ERR_INT 958
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#define INTREQ__GIC_FAULT_INT 959
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#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H */
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