7f2e7dede7
[ Upstream commit 5f491356b7149564ab22323ccce79c8d595bfd0c ]
Binutils 2.38 complains about the use of mfpmr when building
ppc6xx_defconfig:
CC arch/powerpc/kernel/pmc.o
{standard input}: Assembler messages:
{standard input}:45: Error: unrecognized opcode: `mfpmr'
{standard input}:56: Error: unrecognized opcode: `mtpmr'
This is because by default the kernel is built with -mcpu=powerpc, and
the mt/mfpmr instructions are not defined.
It can be avoided by enabling CONFIG_E300C3_CPU, but just adding that to
the defconfig will leave open the possibility of randconfig failures.
So add machine directives around the mt/mfpmr instructions to tell
binutils how to assemble them.
Cc: stable@vger.kernel.org
Reported-by: Jan-Benedict Glaw <jbglaw@lug-owl.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240229122521.762431-3-mpe@ellerman.id.au
Signed-off-by: Sasha Levin <sashal@kernel.org>
96 lines
3.9 KiB
C
Executable file
96 lines
3.9 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Contains register definitions for the Freescale Embedded Performance
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* Monitor.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
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#define __ASM_POWERPC_REG_FSL_EMB_H__
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#include <linux/stringify.h>
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#ifndef __ASSEMBLY__
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile(".machine push; " \
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".machine e300; " \
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"mfpmr %0," __stringify(rn) ";" \
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".machine pop; " \
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: "=r" (rval)); rval;})
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#define mtpmr(rn, v) asm volatile(".machine push; " \
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".machine e300; " \
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"mtpmr " __stringify(rn) ",%0; " \
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".machine pop; " \
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: : "r" (v))
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#endif /* __ASSEMBLY__ */
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/* Freescale Book E Performance Monitor APU Registers */
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#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
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#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
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#define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
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#define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
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#define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
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#define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
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#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
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#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
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#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
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#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
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#define PMRN_PMLCA4 0x094 /* PM Local Control A4 */
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#define PMRN_PMLCA5 0x095 /* PM Local Control A5 */
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#define PMLCA_FC 0x80000000 /* Freeze Counter */
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#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
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#define PMLCA_FCU 0x20000000 /* Freeze in User */
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#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
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#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
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#define PMLCA_CE 0x04000000 /* Condition Enable */
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#define PMLCA_FGCS1 0x00000002 /* Freeze in guest state */
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#define PMLCA_FGCS0 0x00000001 /* Freeze in hypervisor state */
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#define PMLCA_EVENT_MASK 0x01ff0000 /* Event field */
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#define PMLCA_EVENT_SHIFT 16
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#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
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#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
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#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
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#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
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#define PMRN_PMLCB4 0x114 /* PM Local Control B4 */
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#define PMRN_PMLCB5 0x115 /* PM Local Control B5 */
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#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
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#define PMLCB_THRESHMUL_SHIFT 8
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#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
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#define PMLCB_THRESHOLD_SHIFT 0
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#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
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#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
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#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
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#define PMGC0_FCECE 0x20000000 /* Freeze countes on
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Enabled Condition or
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Event */
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#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
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#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */
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#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */
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#define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */
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#define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */
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#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
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#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
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#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
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#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
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#define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */
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#define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */
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#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
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#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
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#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
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#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
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#define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */
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#define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */
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#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
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#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
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#endif /* __KERNEL__ */
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