kernel_samsung_a53x/drivers/pci/pcie
Mika Westerberg f3dac80502 PCI/DPC: Quirk PIO log size for certain Intel Root Ports
[ Upstream commit 5459c0b7046752e519a646e1c2404852bb628459 ]

Some Root Ports on Intel Tiger Lake and Alder Lake systems support the RP
Extensions for DPC and the RP PIO Log registers but incorrectly advertise
an RP PIO Log Size of zero.  This means the kernel complains that:

  DPC: RP PIO log size 0 is invalid

and if DPC is triggered, the DPC driver will not dump the RP PIO Log
registers when it should.

This is caused by a BIOS bug and should be fixed the BIOS for future CPUs.

Add a quirk to set the correct RP PIO Log size for the affected Root Ports.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
Link: https://lore.kernel.org/r/20220816102042.69125-1-mika.westerberg@linux.intel.com
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Stable-dep-of: 627c6db20703 ("PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports")
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-11-19 09:22:33 +01:00
..
aer.c PCI/AER: Decode Requester ID when no error info found 2024-11-18 12:13:20 +01:00
aer_inject.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
aspm.c PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common() 2024-11-18 11:43:22 +01:00
dpc.c PCI/DPC: Quirk PIO log size for certain Intel Root Ports 2024-11-19 09:22:33 +01:00
edr.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
err.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
Kconfig Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
Makefile PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities() 2024-11-19 09:22:18 +01:00
pme.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
portdrv.h Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
portdrv_core.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
portdrv_pci.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
ptm.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
rcec.c PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities() 2024-11-19 09:22:18 +01:00