693 lines
25 KiB
C
Executable file
693 lines
25 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/**
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _USB_USBPHY_CAL_PHY_EXYNOS_USBCON_LINK_SFR_H_
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#define _USB_USBPHY_CAL_PHY_EXYNOS_USBCON_LINK_SFR_H_
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#define USBCON_REG_VERSION 0x0000
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/*
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* Description: USB Sub-CTRL version register
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* [31:24] - Major version,
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* [23:16] - Minor version
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* [15:8] - USB3 PHY
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* 8'h00 : None
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* 8'h01 : SEC SS Combo PHY
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* 8'h02 : SEC SSP Combo PHY
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* 8'h41 : Synopsys 30 PHY (SS+HS)
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* 8'h42 : Synopsys SS PHY
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* 8'h43 : Synopsys SSP PHY
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* [7:0] - USB2 PHY
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* 8'h00 : None
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* 8'h41 : Synopsys 20 PHY
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* 8'h42 : Synopsys eUSB PHY
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*/
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typedef union {
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u32 data;
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struct {
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// bit[7:0] : USB2 PHY
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unsigned USB2PHY : 8;
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// bit[15:8] : USB3 PHY
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unsigned USB3PHY : 8;
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// bit[23:16] :
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unsigned MINOR_VER : 8;
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// bit[31:24] :
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unsigned MAJOR_VER : 8;
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} b;
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} USBCON_REG_VERSION_o, *USBCON_REG_VERSION_p;
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#define USBCON_REG_LINKCTRL 0x0004
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typedef union {
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u32 data;
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struct {
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/* bit[0]
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* Function: This signal is used to generate the PME# (Power Management Event).
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* When the Run/Stop bit of the USB Command Register is cleared during USB suspend mode,
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* the core cannot generate event and cannot assert regular interrupt.
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* In this case, the core asserts pme_generation signal to report any wakeup condition
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* if pme_en is high. If the system does not support PCI-like PME interface,
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* then it should not clear the Run/Stop bit during USB suspend mode.
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* In this case, the core generates event and asserts interrupt when there is
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* any wakeup event. If the pme interface is not used, connect pme_en to zero and
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* keep pme_generation unconnected. This is a level signal that gets cleared when the
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* software clears CSC, OCC and PLC bits in all the PORTSC registers.
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* In device mode connect pme_en to zero and keep pme_generation unconnected. */
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unsigned pme_generation:1;
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/* bit[1] Enable Signal for the pme_generation.
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* Function: Enable the core to assert pme_generation. Refer to the
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* description of pme_generation signal for details. */
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unsigned pme_en:1;
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/* Bit[2] Indicates that a Host System Error has occurred as
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* reflected in the USBSTS.HSE field.
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* It can occur when the host controller encounters an 'Error'
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* response in the AHB, the AXI, or the Native Master Bus. */
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unsigned host_system_err:1;
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// Bit[7:4]
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unsigned polarity_inversion:1;
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/* This signal disables the internal bus filters that are enabled by DWC_USB31_EN_BUS_FILTERS
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* coreConsultant parameter. This static signal is present only when DWC_USB31_EN_BUS_FILTERS
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* is 1. It is expected that this signal is set or reset at power-on reset and is not changed
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* during the normal operation of the controller.
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* The function of each bit is:
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* ■ bus_filter_bypass[2]: Bypass the filter for utmisrp_bvalid
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* ■ bus_filter_bypass[1]: Bypass the filter for pipe_PowerPresent all U3 ports
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* ■ bus_filter_bypass[0]: Bypass the filter for utmiotg_vbusvalid all U2 ports
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* In Host mode, internal bus filters are not needed.
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* Therefore, bus_filter_bypass[2:0] must be connected to logic high value (3'b111). */
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unsigned bus_filter_bypass:4;
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// Bit[8] disable HWACG
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unsigned force_qact:1;
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// Bit[9] Masking bvaild signal for HWACG
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unsigned dis_bvalid_qact:1;
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// Bit[10] Masking bvaild signal for HWACG
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unsigned dis_vbusvalid_qact:1;
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// Bit[11] Masking bvaild signal for HWACG
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unsigned dis_id0_qact:1;
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// Bit[12] Masking bvaild signal for HWACG
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unsigned dis_linkgate_qact:1;
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// Bit[13] Masking bvaild signal for HWACG
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unsigned dis_buspend_qact:1;
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// Bit[15:14] Reserved
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unsigned RSVD15_14:2;
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// Bit[16]
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unsigned force_pipe_en:1;
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// Bit[17]
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unsigned force_phystatus:1;
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// Bit[18]
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unsigned force_rxelecidle:1;
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// Bit[19] Reserved
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unsigned RSVD19:1;
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// Bit[21:20] Selection for SoF Out signal
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unsigned sel_sof:2;
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// Bit[22]
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unsigned pmgt_ref_clk_ok:1;
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// Bit[23]
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unsigned pmgt_ref_clk_off:1;
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// Bit[24]
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unsigned pmgt_ext_bus_clk_gated:1;
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// Bit[25]
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unsigned pmgt_ext_bus_clk_ok:1;
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// Bit[26]
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unsigned pmgt_ext_bus_clk_off:1;
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// Bit[27]
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unsigned _20phy_ref_clk_req:1;
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/* Bit[31:28] Option to Over-ride the device speed
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* [3] : Enable/Disable
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* [2:0]: set speed */
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unsigned devspd_ovrd:4;
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} b;
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} USBCON_REG_LINKCTRL_o, *USBCON_REG_LINKCTRL_p;
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#define USBCON_REG_LINKPORT 0x0008
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typedef union {
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u32 data;
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struct {
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/* bit[0] : Indicates if the device attached to a downstream usb2 port is permanently attached or not.
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* ■ 0: Not permanently attached
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* ■ 1: Permanently attached */
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unsigned hub_perm_attach_u2:1;
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/* bit[1] : Indicates if the device attached to a downstream usb3 port is permanently attached or not.
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* ■ 0: Not permanently attached
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* ■ 1: Permanently attached */
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unsigned hub_perm_attach_u3:1;
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/* bit[2] Select over-current receiving for usb2
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* ■ 0 :
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* ■ 1 :
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*/
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unsigned hub_port_overcurrent_sel_u2:1;
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/* bit[3] Select over-current receiving for usb3
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* ■ 0 :
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* ■ 1 :
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*/
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unsigned hub_port_overcurrent_sel_u3:1;
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/* bit[4] Value of Over-current of usb2 port
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* ■ 0 : Over-current status occured
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* ■ 1 : Normal status
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*/
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unsigned hub_port_overcurrent_u2:1;
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/* bit[5] Value of Over-current of usb3 port
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* ■ 0 : Over-current status occured
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* ■ 1 : Normal status
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*/
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unsigned hub_port_overcurrent_u3:1;
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/* bit[6] : This port defines the bit [3] of Capability Parameters (HCCPARAMS).
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* Change the PPC value through the pin Port Power Control (PPC).
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* This indicates whether the host controller implementation
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* includes port power control.
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* ■ 0: Indicates that the port does not have port power switches.
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* ■ 1: Indicates that the port has port power switches.
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*/
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unsigned host_port_power_con_present:1;
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// bit[7] :
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unsigned RSVD7:1;
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/* bit[8] : USB 2.0 Port Disable control
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* ■ 0: Port Enabled
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* ■ 1: Port Disabled
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* This signal, when '1', stops reporting connect/disconnect events on the port.
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* This could be used for security reasons where hardware can disable a port
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* irrespective of whether xHCI driver enables a port or not.
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* The 'Number of Ports' field of the HCSPARAMS1 register is not affected by this signal.
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* This signal should be static after vcc_reset_n is de-asserted (should not change during operation).
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* Note: This signal should not be asserted to disable USB2 Port0.
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*/
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unsigned host_u2_port_disable:1;
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/* bit[9] : USB 3.1 ESS Port Disable control
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* ■ 0: Port Enabled
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* ■ 1: Port Disabled
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* This signal, when '1', stops reporting connect/disconnect events on the port.
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* This could be used for security reasons where hardware can disable a port
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* irrespective of whether xHCI driver enables a port or not.
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* The 'Number of Ports' field of the HCSPARAMS1 register is not affected by this signal.
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* This signal should be static after vcc_reset_n is de-asserted (should not change during operation).
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* Note: This signal should not be asserted to disable eSS Port0.
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*/
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unsigned host_u3_port_disable:1;
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/* bit[10] Indicator of Port Power control usb2 port */
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unsigned hub_vbus_ctrl_u2:1;
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/* bit[11] Indicator of Port Power control eSS usb3 port */
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unsigned hub_vbus_ctrl_u3:1;
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/* bit[12] */
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unsigned host_num_u2:1;
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/* bit[13] */
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unsigned host_num_u3:1;
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// Bit[31:20] Reserved
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unsigned RSVD131_20:12;
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} b;
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} USBCON_REG_LINKPORT_o, *USBCON_REG_LINKPORT_p;
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#define USBCON_REG_LINK_CLKRST 0x000C
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typedef union {
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u32 data;
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struct {
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/* bit[0] : link reset overriding (to Link) with preset_n */
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unsigned link_sw_rst:1;
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/* bit[1] : Link pclk selection signal- 0:suspend_clk, 1:pipe3_clock */
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unsigned link_pclk_sel:1;
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/* Reserved 3:2 */
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unsigned RSVD3_2:2;
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/* bit[4] Clock selection for USB Audio (0: ref_clk, 1: utmi_clk) */
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unsigned usbaudio_clk_sel:1;
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/* bit[5] Enable or disable clock gate out for usb audio */
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unsigned usbaudio_clk_gate_en:1;
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/* bit[6] Glitch Free Mux reset for USB Audio clock */
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unsigned usbaudioclk_gfmux_rst:1;
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// bit[31:7] :
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unsigned RSVD31_7:25;
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} b;
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} USBCON_REG_LINK_CLKRST_o, *USBCON_REG_LINK_CLKRST_p;
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#define USBCON_REG_UTMI_CTRL 0x0010
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typedef union {
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u32 data;
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struct {
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/* bit[0] : force b-valid signal to high */
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unsigned force_bvalid:1;
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/* bit[1] : force vbus-valid signal to high */
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unsigned force_vbusvalid:1;
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/* bit[2] : force tx bit stuffen */
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unsigned force_utmi_txbitstuffen:1;
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/* bit[3] */
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unsigned RSVD3:1;
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/* bit[4] Enable forcing opmode over-ride */
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unsigned force_utmi_opmode_en:1;
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/* bit[6:5] force opmode signal */
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unsigned force_utmi_opmode:2;
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// bit[7] :
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unsigned RSVD7:1;
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/* bit[8] forcing DM-Pull down enable signal to high */
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unsigned force_DMPULLDOWN:1;
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/* bit[9] forcing DP-Pull down enable signal to high */
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unsigned force_DPPULLDOWN:1;
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// bit[11:10] :
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unsigned RSVD11_10:2;
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/* bit[12] Forcing sleep_n signal */
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unsigned force_utmi_sleep:1;
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/* bit[13] Forcing suspend_n signal */
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unsigned force_utmi_suspend:1;
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// bit[31:14] :
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unsigned RSVD2:18;
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} b;
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} USBCON_REG_UTMI_CTRL_o, *USBCON_REG_UTMI_CTRL_p;
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#define USBCON_REG_ESS_CTRL 0x0014
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typedef union {
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u32 data;
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struct {
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/* bit[0] : Force Host Speed gen1 */
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unsigned host_force_gen1_speed:1;
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/* bit[3:1] */
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unsigned RSVD3_1:3;
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/* bit[4] : PTM time adjustment valid
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* Indicates the ptm_time specified is valid for capture With ptm_time_vld
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* tied to zero ptm_time doesn't update host PTM clock You must set this
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* signal high when ptm_time indicates the wall clock in the system and
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* ready to be loaded into Host ptm_time_vld loads ptm_time in to host
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* SOF/ITP counters If your system doesn't support PTM, it is recommended
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* to tie this input to 0. */
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unsigned ptm_time_vld:1;
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/* bit[7:5] */
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unsigned RSVD7_5:3;
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/* bit[8] Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet)
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* If DisRxDetU3RxDet is set and the link is in either U3 or Rx.Detect
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* state, the controller starts receiver detection on the rising edge of this
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* bit. This signal can only be used for downstream ports. It must be set
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* to '0' for upstream ports.
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* Note: This signal is for debug purpose only, it should be tied to 0 in normal operation.
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*/
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unsigned StartRxDetU3RxDet:1;
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/* bit[9] DisRxDetU3RxDet_ack of USB 3.1 SS Ports
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* This input signal requests the controller to stop issuing more PHY commands and release
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* the PIPE ownership. The controller acknowledges this request by asserting the
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* DisRxDetU3RxDet_ack signal.
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* This signal is for Type-C support.
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*/
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unsigned DisRxDetU3RxDet:1;
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/* bit[10] Indicator DisRxDetU3RxDet_ack of USB 3.1 SS Ports
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* This signal is an acknowledgment of DisRxDetU3RxDet. When this signal is 1'b1,
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* the controller releases the ownership of the PIPE interface and does not issue PHY
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* commands to the PIPE interface.
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*/
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unsigned DisRxDetU3RxDet_ack:1;
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// RSVD[31:11]
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unsigned RSVD31_11:21;
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} b;
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} USBCON_REG_ESS_CTRL_o, *USBCON_REG_ESS_CTRL_p;
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#define USBCON_REG_PTM_TIME 0x0018
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typedef union {
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u32 data;
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struct {
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/* bit[31:0] : PTM time adjustment value
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* This signal indicates the ptm_time in terms of milliseconds and nanoseconds.
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* With ptm_time_vld tied to zero ptm_time does not update the host PTM clock.
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* You must set this signal valid when ptm_time_vld is asserted.
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* ■ ptm_time[31:20] indicates wall clock in milliseconds
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* ■ ptm_time[19:0] indicates wall clock in nanoseconds
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* ■ ptm_time_vld loads ptm_time in to host SOF/ITP counters initial
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* values when the Host controller exits halted state.
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* If your system does not support PTM, tie this input to 0. */
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unsigned ptm_time:32;
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} b;
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} USBCON_REG_ESS_PTM_TIME_o, *USBCON_REG_ESS_PTM_TIME_p;
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#define USBCON_REG_LINK_SOCBW 0x001C
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typedef union {
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u32 data;
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struct {
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/* bit[14:0] :
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* This signal is used to indicate maximum write bandwidth on SoC
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* available in terms of kilo bytes per micro-frame.
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* For example, if the AXI write bandwidth is 150MBps, then the value
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* for this signal is 150/8 = 19. */
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unsigned soc_wr_uF_kB_bandwidth:15;
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// Bit[15]
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unsigned RSVD15:1;
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/* bit[14:0] :
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* This signal is used to indicate maximum read bandwidth on SoC
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* available in terms of kilo bytes per micro-frame.
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* For example, if the AXI read bandwidth is 150MBps, then the value
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* for this signal is 150/8 = 19. */
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unsigned soc_rd_uF_kB_bandwidth:15;
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// Bit[31]
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unsigned RSVD31:1;
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} b;
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} USBCON_REG_LINK_SOCBW_o, *USBCON_REG_LINK_SOCBW_p;
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#define USBCON_REG_REWA_CTL 0x0050
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typedef union {
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u32 data;
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struct {
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/* bit[0] HS ReWA Enable */
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unsigned hsrewa_en:1;
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/* bit[31:1] */
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unsigned RSVD31_1:31;
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} b;
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} USBCON_REG_REWA_CTL_o, *USBCON_REG_REWA_CTL_p;
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#define USBCON_REG_HSREWA_INTR 0x0054
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typedef union {
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u32 data;
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struct {
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/* bit[0] Remote wake-up interrupt mask (to GIC)
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* If this bit set to 1, than usb2_wakeup_int0 interrupt is not generated.
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* 0: Enable Interrupt.
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* 1: Mask interrupt. */
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unsigned wakeup_intr_mask:1;
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/* bit[3:1] */
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unsigned RSVD3_1:3;
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/* bit[4] Status change and exception interrupt mask (to GIC)
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* If this bit set to 1, than usb2_wakeup_int1 interrupt is not generated.
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* 0: Enable Interrupt.
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* 1: Mask interrupt. */
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unsigned event_intr_mask:1;
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/* bit[7:5] */
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unsigned RSVD7_5:3;
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/* bit[8] Host K timeout interrupt mask (to GIC)
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* If this bit set to 1, than usb2_wakeup_int2 interrupt is not generated.
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* 0: Enable Interrupt.
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* 1: Mask interrupt. */
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unsigned timeout_intr_mask:1;
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/* bit[11:9] */
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unsigned RSVD11_9:3;
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/* bit[12] Wakeup interrupt mask (to PMU)
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* If this bit set to 1, than usb2_wakeup interrupt is not generated.
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* ??This interrupt asserted by usb2_wakeup_int0 and usb2_wakeup_int1.
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* 0: Enable Interrupt.
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* 1: Mask interrupt. */
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unsigned wakeup_req_mask:1;
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/* bit[31:13] */
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unsigned RSVD31_13:19;
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} b;
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} USBCON_REG_HSREWA_INTR_o, *USBCON_REG_HSREWA_INTR_p;
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#define USBCON_REG_HSREWA_CTL 0x0058
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typedef union {
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u32 data;
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struct {
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/* bit[0] Done indicator bit for system S/W
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* This bit value means that finish for ReWA operation.
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* 0: Not done
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* 1: Done */
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unsigned hs_rewa_done:1;
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/* bit[3:1] */
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unsigned RSVD3_1:3;
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/* bit[4] Error indicator bit for system S/W.
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* This bit value means that error detected during a ReWA is enabled.
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* If this bit value is 1, than S/W shuld check the HSREWA_INT1_EVNT register to get the error status.
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* 0: No errors
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* 1: Error detected */
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unsigned hs_rewa_error:1;
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/* bit[15:5] */
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unsigned RSVD15_5:11;
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/* bit[16] System valid flag for ReWA.
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* System S/W should set this bit when finished wake-up sequence from sleep mode.
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* 0: System clock is invalid
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* 1: System clock is valid */
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unsigned hs_sys_valid:1;
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/* bit[19:17] */
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unsigned RSVD19_17:3;
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/* bit[20] USB Link ready flag for ReWA.
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* System S/W should set this bit when finished USB link event handling that port status change and host K drive command.
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* 0: Link is not ready
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* 1: Link is ready */
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unsigned hs_link_ready:1;
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/* bit[23:21] */
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unsigned RSVD23_21:3;
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/* bit[24] DP/DM monitoring method selector.
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* HS-ReWA provide two DP/DM monitoring method for detect DP/DM status changes when ReWA is enabled.
|
|
* ??This bit value is should be stable before Enable the ReWA.
|
|
* 0: FSVPLUS/FSVMINUS
|
|
* 1: LINESTATE[1:0] */
|
|
unsigned dpdm_mon_sel:1;
|
|
/* bit[27:25] */
|
|
unsigned RSVD27_25:3;
|
|
/* bit[28] Digital bypass controller enable.
|
|
* HS-ReWA use to PHY's digital bypass feature for host k generation.
|
|
* ??This bit value is should be stable before Enable the ReWA.
|
|
* 0: Disable digital bypass controller.
|
|
* 1: Enable digital bypass controller. */
|
|
unsigned dig_bypass_con_en:1;
|
|
/* bit[31:29] */
|
|
unsigned RSVD31_29:3;
|
|
} b;
|
|
} USBCON_REG_HSREWA_CTL_o, *USBCON_REG_HSREWA_CTL_p;
|
|
|
|
#define USBCON_REG_HSREWA_REFTO 0x005c
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Reference value to determine host K timeout from host K drive.
|
|
* The unit of this value is i_clk tick, In other word value 1 means 30.5us.
|
|
*
|
|
* According to USB specification, Nominal host K drive time is 20ms.
|
|
* ReWA provide host K timeout interrupt and this value is expire time reference value of internal counter.
|
|
*
|
|
* Default value of this register means about 20ms.
|
|
*
|
|
* If this register value is 0 then ReWA override this value to default value (0x28d). So the minimum value of this register is 1.
|
|
*
|
|
* The original value of this register is 0x290, but the initial value is include a minus offset that 3. Because of the ReWA has an internal delay time about 3 tick of i_clk for dp/dm linestate detection. */
|
|
unsigned host_k_timeout:32;
|
|
} b;
|
|
} USBCON_REG_HSREWA_REFTO_o, *USBCON_REG_HSREWA_REFTO_p;
|
|
|
|
#define USBCON_REG_HSREWA_HSTK 0x0060
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Reference value to determine host K delay from device K event.
|
|
* The unit of this value is i_clk tick, In other word value 1 means 30.5us.
|
|
* According to USB specification, Host should respond for remote wakeup request from device at least 900us.
|
|
*
|
|
* Default value of this register means about 854us.
|
|
*
|
|
* If this register value is 0 then ReWA override this value to default value (0x19). So the minimum value of this register is 1.
|
|
*
|
|
* The original value of this register is 0x1c, but the initial value is include a minus offset that 3. Because of the ReWA has an internal delay time about 3 tick of i_clk for dp/dm linestate detection. */
|
|
unsigned host_k_delay:32;
|
|
} b;
|
|
} USBCON_REG_HSREWA_HSTK_o, *USBCON_REG_HSREWA_HSTK_p;
|
|
|
|
#define USBCON_REG_HSREWA_CNT 0x0064
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Current timer value that accumulated from device K event. */
|
|
unsigned wakeup_cnt:32;
|
|
} b;
|
|
} USBCON_REG_HSREWA_CNT_o, *USBCON_REG_HSREWA_CNT_p;
|
|
|
|
#define USBCON_REG_HSREWA_INT1_EVNT 0x0068
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[0] UTMI signal retention enabled event flag
|
|
* This bit value means that all of UTMI signals will be retained.
|
|
* 0: UTMI retention is not enabled
|
|
* 1: UTMI retention is enabled */
|
|
unsigned ret_en:1;
|
|
/* bit[1] UTMI signal retention disabled event flag
|
|
* This bit value means that retention disabled (bypass) for all of UTMI signals.
|
|
* 0: UTMI retention is not disabled
|
|
* 1: UTMI retention is disabled */
|
|
unsigned ret_dis:1;
|
|
/* bit[2] Digital BYPASS disabled event flag
|
|
* This bit value means that Digital BYPASS control signals is disabled, and the ownership of DP/DM is return to UTMI signals.
|
|
* 0: Digital BYPASS is not disabled
|
|
* 1: Digital BYPASS is disabled */
|
|
unsigned bypass_dis:1;
|
|
/* bit[15:3] */
|
|
unsigned RSVD15_3:13;
|
|
/* bit[16] Disconnect detected error event flag
|
|
* This bit value means that disconnect error detected during a ReWA is enabled.
|
|
* 0: Disconnect event is not detected
|
|
* 1: Disconnect event is detected */
|
|
unsigned discon:1;
|
|
/* bit[17] Invalid device K error event flag
|
|
* This bit value means that invalid device K detected during a waiting for host K drive after device K event.
|
|
* 0: Device K error is not detected
|
|
* 1: Device K error is detected */
|
|
unsigned err_dev_k:1;
|
|
/* bit[18] Suspend state error event flag
|
|
* This bit value means that USB PHY is not suspend state when the ReWA is enabled.
|
|
* 0: Suspend error is not detected
|
|
* 1: Suspend error is detected */
|
|
unsigned err_sus:1;
|
|
/* bit[31:19] */
|
|
unsigned RSVD31_19:13;
|
|
} b;
|
|
} USBCON_REG_HSREWA_INT1_EVNT_o, *USBCON_REG_HSREWA_INT1_EVNT_p;
|
|
|
|
#define USBCON_REG_HSREWA_INT1_EVNT_MSK 0x006c
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[0] Status event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned ret_en_mask:1;
|
|
/* bit[1] Status event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned ret_dis_mask:1;
|
|
/* bit[2] Status event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned bypass_dis_mask:1;
|
|
/* bit[15:3] Reserved */
|
|
unsigned reserve_mask0:13;
|
|
/* bit[16] Exception event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned discon_mask:1;
|
|
/* bit[17] Exception event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned err_dev_k_mask:1;
|
|
/* bit[18] Exception event mask for interrupt generation.
|
|
* 0: Enable Interrupt.
|
|
* 1: Mask interrupt. */
|
|
unsigned err_sus_mask:1;
|
|
/* bit[31:19] Reserved */
|
|
unsigned reserve_mask1:13;
|
|
} b;
|
|
} USBCON_REG_HSREWA_INT1_EVNT_MSK_o, *USBCON_REG_HSREWA_INT1_EVNT_MSK_p;
|
|
|
|
#define USBCON_REG_U3REWA_CTRL 0x0070
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[0] U3 rewa operation enable. Actullay, when this bit is enabled, RxElecIdle signal is masked to Link.
|
|
* Before Link enter the U3 state, this bit is set. And, If the system is enabled, it should be released. */
|
|
unsigned u3rewa_blk_en:1;
|
|
/* bit[1] when this bit is set, it generates tx LFPS which can overlap absolutely with Rx LFPS. */
|
|
unsigned overlap_lfps:1;
|
|
/* bit[2] check in U3 when the U3Rewa works */
|
|
unsigned check_u3:1;
|
|
/* bit[3] */
|
|
unsigned RSVD3:1;
|
|
/* bit[7:4] The number of skipped LFPS burst due to U3Rewa masking */
|
|
unsigned skip_wakeuplfps_cnt:4;
|
|
/* bit[23:8] */
|
|
unsigned RSVD23_8:16;
|
|
/* bit[24] System wakeup Interrupt masking */
|
|
unsigned sys_wakeup_intr_mask:1;
|
|
/* bit[27:25] */
|
|
unsigned RSVD27_25:3;
|
|
/* bit[28] System wakeup Interrupt */
|
|
unsigned sys_wakeup_intr:1;
|
|
/* bit[31:29] */
|
|
unsigned RSVD31_29:3;
|
|
} b;
|
|
} USBCON_REG_U3REWA_CTRL_o, *USBCON_REG_U3REWA_CTRL_p;
|
|
|
|
#define USBCON_REG_U3REWA_LMT_CNT 0x0074
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Link needs some time to generate LFPS from receiving Rx LFPS. So, when Link receives the end of Rx LFPS by ReWa Masking, LFPS overlapping may not be achived. At this time, it shoud ignore this Rx LFPS. i_lfpsresp_limit_cnt is limitation counter value for release RxElecIdle mask with i_suspend_clk. This value can be set as following.
|
|
* ( (Expected RxLFPS Burst period(10ms) - margin(1ms) ) / i_suspend_clk period(38.26ns) */
|
|
unsigned lfpsresp_limit_cnt:32;
|
|
} b;
|
|
} USBCON_REG_U3REWA_LMT_CNT_o, *USBCON_REG_U3REWA_LMT_CNT_p;
|
|
|
|
#define USBCON_REG_LTSTATE_HIS 0x0080
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[3:0] LTSSM State history buffer 0 */
|
|
unsigned ltstate_his0:4;
|
|
/* bit[7:4] LTSSM State history buffer 1 */
|
|
unsigned ltstate_his1:4;
|
|
/* bit[11:8] LTSSM State history buffer 2 */
|
|
unsigned ltstate_his2:4;
|
|
/* bit[15:12] LTSSM State history buffer 3 */
|
|
unsigned ltstate_his3:4;
|
|
/* bit[19:16] LTSSM State history buffer 4 */
|
|
unsigned ltstate_his4:4;
|
|
/* bit[30:20] */
|
|
unsigned RSVD30_20:11;
|
|
/* bit[31] Flag for the successful link training sequence (POLL=>U0) */
|
|
unsigned linktrn_done:1;
|
|
} b;
|
|
} USBCON_REG_LTSTATE_HIS_o, *USBCON_REG_LTSTATE_HIS_p;
|
|
|
|
#define USBCON_REG_LINK_DEBUG_L 0x0084
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Link internal design signal value for debugging
|
|
* Refer to the logic_analyzer_trace signal description in link databook */
|
|
unsigned debug_l:32;
|
|
} b;
|
|
} USBCON_REG_LINK_DEBUG_L_o, *USBCON_REG_LINK_DEBUG_L_p;
|
|
|
|
#define USBCON_REG_LINK_DEBUG_H 0x0088
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[31:0] Link internal design signal value for debugging
|
|
* Refer to the logic_analyzer_trace signal description in link databook */
|
|
unsigned debug_h:32;
|
|
} b;
|
|
} USBCON_REG_LINK_DEBUG_H_o, *USBCON_REG_LINK_DEBUG_H_p;
|
|
|
|
#define USBCON_REG_HSP_MISC 0x0114
|
|
typedef union {
|
|
u32 data;
|
|
struct {
|
|
/* bit[1:0] selection of resistance tune chain
|
|
* 0: Phy2 -> Phy1
|
|
* 1: Phy1 -> Phy2
|
|
* 2: Phy1 only
|
|
* 3: Phy2 only */
|
|
unsigned sel_res_tune_mux:2;
|
|
/* bit[3:2] */
|
|
unsigned RSVD3_2:2;
|
|
/* bit[4] set value for req_in port of phy2 */
|
|
unsigned set_req_in2:1;
|
|
/* bit[5] set value for ack_in port of phy2 */
|
|
unsigned set_ack_in2:1;
|
|
/* bit[6] set value for req_in port of phy1 */
|
|
unsigned set_req_in1:1;
|
|
/* bit[7] set value for ack_in port of phy1 */
|
|
unsigned set_ack_in1:1;
|
|
/* bit[9:8] host_disconnect filtering mode
|
|
* 0: Disable Filtering
|
|
* 1: host_disconnect from phy is blocked
|
|
* 2: Normal Filtering - host_disconnect siganl from phy can be transferred to link, if host_disconnect drive high more than valid_hsdiscon_count during mon_sof_count frames
|
|
* 3:: No limit of monitoring sof counter. Only if host_disconnect drive high more than valid_hsdiscon_count, then host_disconnect siganl from phy can be transferred to link. */
|
|
unsigned hsdiscon_filter_mode:2;
|
|
/* bit[11:10] */
|
|
unsigned RSVD11_10:2;
|
|
/* bit[12] */
|
|
unsigned fsvplus:1;
|
|
/* bit[13] */
|
|
unsigned fsvminus:1;
|
|
/* bit[14] */
|
|
unsigned fsvp_out_en:1;
|
|
/* bit[15] */
|
|
unsigned fsvm_out_en:1;
|
|
/* bit[23:16] host_disconnect monitoring period by number sof count */
|
|
unsigned mon_sof_count:8;
|
|
/* bit[31:24] count of asserted host_disconnect in monitoring frames */
|
|
unsigned valid_hsdiscon_count:8;
|
|
} b;
|
|
} USBCON_REG_HSP_MISC_o, *USBCON_REG_HSP_MISC_p;
|
|
|
|
|
|
#endif
|