83 lines
2.8 KiB
ArmAsm
Executable file
83 lines
2.8 KiB
ArmAsm
Executable file
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-uaccess.h>
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/*
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* flush_cache_all()
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* Corrupted registers: x0-x7, x9-x11
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*
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* Flush the entire cache system. The data cache flush is now achieved
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* using atomic clean / invalidates working outwards from L1 cache. This
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* is done using Set/Way based cache maintainance instructions. The
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* instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*/
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SYM_FUNC_START(flush_cache_all)
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mov x12, lr
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dmb sy // ensure ordering with previous memory accesses
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mrs x0, clidr_el1 // read clidr
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and x3, x0, #0x7000000 // extract loc from clidr
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lsr x3, x3, #23 // left align loc bit field
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cbz x3, finished // if loc is 0, then no need to clean
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mov x10, #0 // start clean at cache level 0
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask of the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt skip // skip if no cache, or just i-cache
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save_and_disable_irq x9 // make CSSELR and CCSIDR access atomic
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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restore_irq x9
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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mrs x14, id_aa64mmfr2_el1 // check architecture version
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mov x15, #0xf
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and x15, x15, x14, lsr #20
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cbz x15, format_32bit
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mov x4, #0x1fffff
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and x4, x4, x1, lsr #3 // find maximum number on the way size
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clz w5, w4 // find bit position of way size increment
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mov x7, #0xffffff
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and x7, x7, x1, lsr #32 // extract max number of the index size
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b loop2
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format_32bit:
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mov x4, #0x3ff
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and x4, x4, x1, lsr #3 // find maximum number on the way size
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clz w5, w4 // find bit position of way size increment
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mov x7, #0x7fff
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and x7, x7, x1, lsr #13 // extract max number of the index size
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loop2:
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mov x9, x4 // create working copy of max way size
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loop3:
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lsl x6, x9, x5
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orr x11, x10, x6 // factor way and cache number into x11
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lsl x6, x7, x2
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orr x11, x11, x6 // factor index number into x11
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dc cisw, x11 // clean & invalidate by set/way
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subs x9, x9, #1 // decrement the way
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b.ge loop3
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subs x7, x7, #1 // decrement the index
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b.ge loop2
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skip:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt loop1
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finished:
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mov x10, #0 // swith back to cache level 0
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msr csselr_el1, x10 // select current cache level in csselr
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dsb sy
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isb
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mov x0, #0
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ic ialluis // I+BTB cache invalidate
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mov lr, x12
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ret
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