1237 lines
232 KiB
C
Executable file
1237 lines
232 KiB
C
Executable file
#include "../cmucal.h"
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#include "cmucal-sfr.h"
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#include "cmucal-qch.h"
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unsigned int cmucal_qch_size = 1178;
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struct cmucal_qch cmucal_qch_list[] = {
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CLK_QCH(ALIVE_CMU_ALIVE_QCH, QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2AP_QCH, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2APM_QCH, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2PMU_QCH, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_TOP_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLKMON_QCH, QCH_CON_CLKMON_QCH_ENABLE, QCH_CON_CLKMON_QCH_CLOCK_REQ, QCH_CON_CLKMON_QCH_EXPIRE_VAL, QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DBGCORE_UART_QCH, QCH_CON_DBGCORE_UART_QCH_ENABLE, QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL, QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DOUBLE_IP_BATCHER_QCH_APM, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_ENABLE, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_CLOCK_REQ, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_EXPIRE_VAL, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_IGNORE_FORCE_PM_EN),
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CLK_QCH(DOUBLE_IP_BATCHER_QCH_CPU, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_ENABLE, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_CLOCK_REQ, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_EXPIRE_VAL, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DOUBLE_IP_BATCHER_QCH_SEMA, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_ENABLE, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_CLOCK_REQ, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_EXPIRE_VAL, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DTZPC_ALIVE_QCH, QCH_CON_DTZPC_ALIVE_QCH_ENABLE, QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ, QCH_CON_DTZPC_ALIVE_QCH_EXPIRE_VAL, QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_ALIVE_QCH, QCH_CON_GPIO_ALIVE_QCH_ENABLE, QCH_CON_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(HW_SCANDUMP_CLKSTOP_CTRL_QCH, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_PMIC_QCH_P, QCH_CON_I3C_PMIC_QCH_P_ENABLE, QCH_CON_I3C_PMIC_QCH_P_CLOCK_REQ, QCH_CON_I3C_PMIC_QCH_P_EXPIRE_VAL, QCH_CON_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_PMIC_QCH_S, DMYQCH_CON_I3C_PMIC_QCH_S_ENABLE, DMYQCH_CON_I3C_PMIC_QCH_S_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_C_MODEM_QCH, QCH_CON_LHM_AXI_C_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_C_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_C_VTS_QCH, QCH_CON_LHM_AXI_C_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_C_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_QCH, QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_C_CMGP_QCH, QCH_CON_LHS_AXI_C_CMGP_QCH_ENABLE, QCH_CON_LHS_AXI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_APM_QCH, QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_DBGCORE_QCH, QCH_CON_LHS_AXI_G_DBGCORE_QCH_ENABLE, QCH_CON_LHS_AXI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_SCAN2DRAM_QCH, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_LP_VTS_QCH, QCH_CON_LHS_AXI_LP_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_LP_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LP_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CP_QCH, QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_QCH, QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_S_QCH, QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PEM_QCH, QCH_CON_PEM_QCH_ENABLE, QCH_CON_PEM_QCH_CLOCK_REQ, QCH_CON_PEM_QCH_EXPIRE_VAL, QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ROM_CRC32_HOST_QCH, QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_ALIVE_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_DBGCORE_QCH_GREBE, QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_DBGCORE_QCH_DBG, QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_P_ALIVE_QCH, QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE, QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_SWEEPER_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ALIVE_QCH, QCH_CON_SYSREG_ALIVE_QCH_ENABLE, QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_ALIVE_QCH, QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_ALIVE_QCH, QCH_CON_WDT_ALIVE_QCH_ENABLE, QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL, QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CPU, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK4, QCH_CON_ABOX_QCH_BCLK4_ENABLE, QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CNT, QCH_CON_ABOX_QCH_CNT_ENABLE, QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK5, QCH_CON_ABOX_QCH_BCLK5_ENABLE, QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_SCLK, QCH_CON_ABOX_QCH_SCLK_ENABLE, QCH_CON_ABOX_QCH_SCLK_CLOCK_REQ, QCH_CON_ABOX_QCH_SCLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_SCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK6, QCH_CON_ABOX_QCH_BCLK6_ENABLE, QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_XCLK, QCH_CON_ABOX_QCH_XCLK_ENABLE, QCH_CON_ABOX_QCH_XCLK_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_PCMC_CLK, QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_C2A0, QCH_CON_ABOX_QCH_C2A0_ENABLE, QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_C2A1, QCH_CON_ABOX_QCH_C2A1_ENABLE, QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN),
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CLK_QCH(AUD_CMU_AUD_QCH, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_D_AUDVTS_QCH, QCH_CON_BAAW_D_AUDVTS_QCH_ENABLE, QCH_CON_BAAW_D_AUDVTS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_AUDVTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_AUD_QCH, QCH_CON_D_TZPC_AUD_QCH_ENABLE, QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_HSI0AUD_QCH, QCH_CON_LHM_AXI_D_HSI0AUD_QCH_ENABLE, QCH_CON_LHM_AXI_D_HSI0AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_HSI0AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_AUD_QCH, QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_AUD_QCH, QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_AUDHSI0_QCH, QCH_CON_LHS_AXI_D_AUDHSI0_QCH_ENABLE, QCH_CON_LHS_AXI_D_AUDHSI0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_AUDHSI0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_AUDVTS_QCH, QCH_CON_LHS_AXI_D_AUDVTS_QCH_ENABLE, QCH_CON_LHS_AXI_D_AUDVTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_AUDVTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD0_QCH, QCH_CON_MAILBOX_AUD0_QCH_ENABLE, QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD1_QCH, QCH_CON_MAILBOX_AUD1_QCH_ENABLE, QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD2_QCH, QCH_CON_MAILBOX_AUD2_QCH_ENABLE, QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD2_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD3_QCH, QCH_CON_MAILBOX_AUD3_QCH_ENABLE, QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD3_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_AUD_QCH, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_AUD_QCH_S1, QCH_CON_SMMU_AUD_QCH_S1_ENABLE, QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ, QCH_CON_SMMU_AUD_QCH_S1_EXPIRE_VAL, QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_AUD_QCH_S2, QCH_CON_SMMU_AUD_QCH_S2_ENABLE, QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ, QCH_CON_SMMU_AUD_QCH_S2_EXPIRE_VAL, QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_AUD_QCH, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_AUD_QCH, QCH_CON_TREX_AUD_QCH_ENABLE, QCH_CON_TREX_AUD_QCH_CLOCK_REQ, QCH_CON_TREX_AUD_QCH_EXPIRE_VAL, QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_AUD_QCH, QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASYNCSFR_WR_SMC_QCH, QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE, QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ, QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL, QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_VPC_QCH, QCH_CON_BAAW_P_VPC_QCH_ENABLE, QCH_CON_BAAW_P_VPC_QCH_CLOCK_REQ, QCH_CON_BAAW_P_VPC_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUS0_CMU_BUS0_QCH, QCH_CON_BUS0_CMU_BUS0_QCH_ENABLE, QCH_CON_BUS0_CMU_BUS0_QCH_CLOCK_REQ, QCH_CON_BUS0_CMU_BUS0_QCH_EXPIRE_VAL, QCH_CON_BUS0_CMU_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_CMUTOPC_QCH, QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CACHEAID_BUS0_QCH, QCH_CON_CACHEAID_BUS0_QCH_ENABLE, QCH_CON_CACHEAID_BUS0_QCH_CLOCK_REQ, QCH_CON_CACHEAID_BUS0_QCH_EXPIRE_VAL, QCH_CON_CACHEAID_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_BUS0_CMUREF_QCH, DMYQCH_CON_CMU_BUS0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUS0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_BUS0_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_BUS0_QCH, QCH_CON_D_TZPC_BUS0_QCH_ENABLE, QCH_CON_D_TZPC_BUS0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUS0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_VPC_QCH, QCH_CON_LHM_ACEL_D0_VPC_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_VPC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_VPC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D1_VPC_QCH, QCH_CON_LHM_ACEL_D1_VPC_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_VPC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_VPC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D2_VPC_QCH, QCH_CON_LHM_ACEL_D2_VPC_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_VPC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_VPC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_NPUS_QCH, QCH_CON_LHM_AXI_D0_NPUS_QCH_ENABLE, QCH_CON_LHM_AXI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_NPUS_QCH, QCH_CON_LHM_AXI_D1_NPUS_QCH_ENABLE, QCH_CON_LHM_AXI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D2_NPUS_QCH, QCH_CON_LHM_AXI_D2_NPUS_QCH_ENABLE, QCH_CON_LHM_AXI_D2_NPUS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF2_QCH, QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF3_QCH, QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_NPU00_QCH, QCH_CON_LHS_AXI_P_NPU00_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPU00_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_NPU01_QCH, QCH_CON_LHS_AXI_P_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_NPU10_QCH, QCH_CON_LHS_AXI_P_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_NPUS_QCH, QCH_CON_LHS_AXI_P_NPUS_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIC0_QCH, QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIC2_QCH, QCH_CON_LHS_AXI_P_PERIC2_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERISGIC_QCH, QCH_CON_LHS_AXI_P_PERISGIC_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERISGIC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERISGIC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VPC_QCH, QCH_CON_LHS_AXI_P_VPC_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUS0_QCH, QCH_CON_SYSREG_BUS0_QCH_ENABLE, QCH_CON_SYSREG_BUS0_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D0_BUS0_QCH, QCH_CON_TREX_D0_BUS0_QCH_ENABLE, QCH_CON_TREX_D0_BUS0_QCH_CLOCK_REQ, QCH_CON_TREX_D0_BUS0_QCH_EXPIRE_VAL, QCH_CON_TREX_D0_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D1_BUS0_QCH, QCH_CON_TREX_D1_BUS0_QCH_ENABLE, QCH_CON_TREX_D1_BUS0_QCH_CLOCK_REQ, QCH_CON_TREX_D1_BUS0_QCH_EXPIRE_VAL, QCH_CON_TREX_D1_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_BUS0_QCH, QCH_CON_TREX_P_BUS0_QCH_ENABLE, QCH_CON_TREX_P_BUS0_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS0_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_VTS_QCH, QCH_CON_BAAW_P_VTS_QCH_ENABLE, QCH_CON_BAAW_P_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUS1_CMU_BUS1_QCH, QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_BUS1_CMUREF_QCH, DMYQCH_CON_CMU_BUS1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUS1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_BUS1_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_BUS1_QCH, QCH_CON_D_TZPC_BUS1_QCH_ENABLE, QCH_CON_D_TZPC_BUS1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUS1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_HSI0_QCH, QCH_CON_LHM_ACEL_D_HSI0_QCH_ENABLE, QCH_CON_LHM_ACEL_D_HSI0_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_HSI0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_DPUF0_QCH, QCH_CON_LHM_AXI_D0_DPUF0_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_DPUF1_QCH, QCH_CON_LHM_AXI_D0_DPUF1_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_DPUF0_QCH, QCH_CON_LHM_AXI_D1_DPUF0_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_DPUF1_QCH, QCH_CON_LHM_AXI_D1_DPUF1_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_APM_QCH, QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_SBIC_QCH, QCH_CON_LHM_AXI_D_SBIC_QCH_ENABLE, QCH_CON_LHM_AXI_D_SBIC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SBIC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VTS_QCH, QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_SBIC_QCH, QCH_CON_LHS_AXI_D_SBIC_QCH_ENABLE, QCH_CON_LHS_AXI_D_SBIC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_SBIC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DPUB_QCH, QCH_CON_LHS_AXI_P_DPUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_DPUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DPUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DPUF0_QCH, QCH_CON_LHS_AXI_P_DPUF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DPUF1_QCH, QCH_CON_LHS_AXI_P_DPUF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_HSI0_QCH, QCH_CON_LHS_AXI_P_HSI0_QCH_ENABLE, QCH_CON_LHS_AXI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_HSI0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VTS_QCH, QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_QCH, QCH_CON_PDMA_QCH_ENABLE, QCH_CON_PDMA_QCH_CLOCK_REQ, QCH_CON_PDMA_QCH_EXPIRE_VAL, QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDMA_QCH, QCH_CON_QE_PDMA_QCH_ENABLE, QCH_CON_QE_PDMA_QCH_CLOCK_REQ, QCH_CON_QE_PDMA_QCH_EXPIRE_VAL, QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_SPDMA_QCH, QCH_CON_QE_SPDMA_QCH_ENABLE, QCH_CON_QE_SPDMA_QCH_CLOCK_REQ, QCH_CON_QE_SPDMA_QCH_EXPIRE_VAL, QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SBIC_QCH, QCH_CON_SBIC_QCH_ENABLE, QCH_CON_SBIC_QCH_CLOCK_REQ, QCH_CON_SBIC_QCH_EXPIRE_VAL, QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPDMA_QCH, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_EXPIRE_VAL, QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_S2_ACVPS_QCH, QCH_CON_SYSMMU_S2_ACVPS_QCH_ENABLE, QCH_CON_SYSMMU_S2_ACVPS_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_ACVPS_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_S2_ACVPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_S2_DIT_QCH, QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE, QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_DIT_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_S2_SBIC_QCH, QCH_CON_SYSMMU_S2_SBIC_QCH_ENABLE, QCH_CON_SYSMMU_S2_SBIC_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_SBIC_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_S2_SBIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUS1_QCH, QCH_CON_SYSREG_BUS1_QCH_ENABLE, QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_BUS1_QCH, QCH_CON_TREX_D_BUS1_QCH_ENABLE, QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_BUS1_QCH, QCH_CON_TREX_P_BUS1_QCH_ENABLE, QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_RB_BUS1_QCH, QCH_CON_TREX_RB_BUS1_QCH_ENABLE, QCH_CON_TREX_RB_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_RB_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_RB_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_BUS1_QCH, QCH_CON_VGEN_LITE_BUS1_QCH_ENABLE, QCH_CON_VGEN_LITE_BUS1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_BUS1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_PDMA_QCH, QCH_CON_VGEN_PDMA_QCH_ENABLE, QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL, QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUS2_CMU_BUS2_QCH, QCH_CON_BUS2_CMU_BUS2_QCH_ENABLE, QCH_CON_BUS2_CMU_BUS2_QCH_CLOCK_REQ, QCH_CON_BUS2_CMU_BUS2_QCH_EXPIRE_VAL, QCH_CON_BUS2_CMU_BUS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_BUS2_CMUREF_QCH, DMYQCH_CON_CMU_BUS2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUS2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_BUS2_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_BUS2_QCH, QCH_CON_D_TZPC_BUS2_QCH_ENABLE, QCH_CON_D_TZPC_BUS2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUS2_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_MCSC_QCH, QCH_CON_LHM_ACEL_D0_MCSC_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_HSI1_QCH, QCH_CON_LHM_ACEL_D_HSI1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_HSI1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_M2M_QCH, QCH_CON_LHM_ACEL_D_M2M_QCH_ENABLE, QCH_CON_LHM_ACEL_D_M2M_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_SSP_QCH, QCH_CON_LHM_ACEL_D_SSP_QCH_ENABLE, QCH_CON_LHM_ACEL_D_SSP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_SSP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_CSIS_QCH, QCH_CON_LHM_AXI_D0_CSIS_QCH_ENABLE, QCH_CON_LHM_AXI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_DNS_QCH, QCH_CON_LHM_AXI_D0_DNS_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DNS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MCFP0_QCH, QCH_CON_LHM_AXI_D0_MCFP0_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MFC0_QCH, QCH_CON_LHM_AXI_D0_MFC0_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MFC1_QCH, QCH_CON_LHM_AXI_D0_MFC1_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_CSIS_QCH, QCH_CON_LHM_AXI_D1_CSIS_QCH_ENABLE, QCH_CON_LHM_AXI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_DNS_QCH, QCH_CON_LHM_AXI_D1_DNS_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DNS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MCFP0_QCH, QCH_CON_LHM_AXI_D1_MCFP0_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MCSC_QCH, QCH_CON_LHM_AXI_D1_MCSC_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MFC0_QCH, QCH_CON_LHM_AXI_D1_MFC0_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MFC1_QCH, QCH_CON_LHM_AXI_D1_MFC1_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D2_CSIS_QCH, QCH_CON_LHM_AXI_D2_CSIS_QCH_ENABLE, QCH_CON_LHM_AXI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D2_MCFP0_QCH, QCH_CON_LHM_AXI_D2_MCFP0_QCH_ENABLE, QCH_CON_LHM_AXI_D2_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D2_MCSC_QCH, QCH_CON_LHM_AXI_D2_MCSC_QCH_ENABLE, QCH_CON_LHM_AXI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D3_CSIS_QCH, QCH_CON_LHM_AXI_D3_CSIS_QCH_ENABLE, QCH_CON_LHM_AXI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D3_MCFP0_QCH, QCH_CON_LHM_AXI_D3_MCFP0_QCH_ENABLE, QCH_CON_LHM_AXI_D3_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D3_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_LME_QCH, QCH_CON_LHM_AXI_D_LME_QCH_ENABLE, QCH_CON_LHM_AXI_D_LME_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_LME_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MCFP1_QCH, QCH_CON_LHM_AXI_D_MCFP1_QCH_ENABLE, QCH_CON_LHM_AXI_D_MCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_TAA_QCH, QCH_CON_LHM_AXI_D_TAA_QCH_ENABLE, QCH_CON_LHM_AXI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_YUVPP_QCH, QCH_CON_LHM_AXI_D_YUVPP_QCH_ENABLE, QCH_CON_LHM_AXI_D_YUVPP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_YUVPP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CSIS_QCH, QCH_CON_LHS_AXI_P_CSIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_HSI1_QCH, QCH_CON_LHS_AXI_P_HSI1_QCH_ENABLE, QCH_CON_LHS_AXI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_HSI1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ITP_QCH, QCH_CON_LHS_AXI_P_ITP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ITP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_LME_QCH, QCH_CON_LHS_AXI_P_LME_QCH_ENABLE, QCH_CON_LHS_AXI_P_LME_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_LME_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_M2M_QCH, QCH_CON_LHS_AXI_P_M2M_QCH_ENABLE, QCH_CON_LHS_AXI_P_M2M_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MCFP0_QCH, QCH_CON_LHS_AXI_P_MCFP0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MCSC_QCH, QCH_CON_LHS_AXI_P_MCSC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MFC0_QCH, QCH_CON_LHS_AXI_P_MFC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MFC1_QCH, QCH_CON_LHS_AXI_P_MFC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIC1_QCH, QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_SSP_QCH, QCH_CON_LHS_AXI_P_SSP_QCH_ENABLE, QCH_CON_LHS_AXI_P_SSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SSP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_TAA_QCH, QCH_CON_LHS_AXI_P_TAA_QCH_ENABLE, QCH_CON_LHS_AXI_P_TAA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_YUVPP_QCH, QCH_CON_LHS_AXI_P_YUVPP_QCH_ENABLE, QCH_CON_LHS_AXI_P_YUVPP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_YUVPP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUS2_QCH, QCH_CON_SYSREG_BUS2_QCH_ENABLE, QCH_CON_SYSREG_BUS2_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_BUS2_QCH, QCH_CON_TREX_D_BUS2_QCH_ENABLE, QCH_CON_TREX_D_BUS2_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUS2_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_BUS2_QCH, QCH_CON_TREX_P_BUS2_QCH_ENABLE, QCH_CON_TREX_P_BUS2_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS2_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S0, QCH_CON_ADC_CMGP_QCH_S0_ENABLE, QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S1, QCH_CON_ADC_CMGP_QCH_S1_ENABLE, QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_OSC, DMYQCH_CON_ADC_CMGP_QCH_OSC_ENABLE, DMYQCH_CON_ADC_CMGP_QCH_OSC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADC_CMGP_QCH_OSC_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_GPIO_CMGP_QCH, QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE, QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CMGP_QCH, QCH_CON_D_TZPC_CMGP_QCH_ENABLE, QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP0_QCH, QCH_CON_I2C_CMGP0_QCH_ENABLE, QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP1_QCH, QCH_CON_I2C_CMGP1_QCH_ENABLE, QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP2_QCH, QCH_CON_I2C_CMGP2_QCH_ENABLE, QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP3_QCH, QCH_CON_I2C_CMGP3_QCH_ENABLE, QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_CMGP_QCH_P, QCH_CON_I3C_CMGP_QCH_P_ENABLE, QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ, QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL, QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_CMGP_QCH_S, DMYQCH_CON_I3C_CMGP_QCH_S_ENABLE, DMYQCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_C_CMGP_QCH, QCH_CON_LHM_AXI_C_CMGP_QCH_ENABLE, QCH_CON_LHM_AXI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2APM_QCH, QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP0_QCH, QCH_CON_USI_CMGP0_QCH_ENABLE, QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP1_QCH, QCH_CON_USI_CMGP1_QCH_ENABLE, QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP2_QCH, QCH_CON_USI_CMGP2_QCH_ENABLE, QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP3_QCH, QCH_CON_USI_CMGP3_QCH_ENABLE, QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_TOP_CMUREF_QCH, DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK5, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D0_QCH, QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D1_QCH, QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D2_QCH, QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D3_QCH, QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_CP_QCH, QCH_CON_BAAW_CP_QCH_ENABLE, QCH_CON_BAAW_CP_QCH_CLOCK_REQ, QCH_CON_BAAW_CP_QCH_EXPIRE_VAL, QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CCI_QCH, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CORE_CMUREF_QCH, DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CORE_QCH, QCH_CON_D_TZPC_CORE_QCH_ENABLE, QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D2_MODEM_QCH, QCH_CON_LHM_ACEL_D2_MODEM_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D0_CLUSTER0_QCH, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D0_G3D_QCH, QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D1_CLUSTER0_QCH, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D1_G3D_QCH, QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D2_G3D_QCH, QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D3_G3D_QCH, QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MODEM_QCH, QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MODEM_QCH, QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_AUD_QCH, QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_CSSYS_QCH, QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T_BDU_QCH, QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM_QCH, QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_AUD_QCH, QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MODEM_QCH, QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE, QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIS_QCH, QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPCFW_G3D_QCH, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_CPUCL0_0_QCH, QCH_CON_PPC_CPUCL0_0_QCH_ENABLE, QCH_CON_PPC_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_CPUCL0_1_QCH, QCH_CON_PPC_CPUCL0_1_QCH_ENABLE, QCH_CON_PPC_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_G3D0_QCH, QCH_CON_PPC_G3D0_QCH_ENABLE, QCH_CON_PPC_G3D0_QCH_CLOCK_REQ, QCH_CON_PPC_G3D0_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_G3D1_QCH, QCH_CON_PPC_G3D1_QCH_ENABLE, QCH_CON_PPC_G3D1_QCH_CLOCK_REQ, QCH_CON_PPC_G3D1_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_G3D2_QCH, QCH_CON_PPC_G3D2_QCH_ENABLE, QCH_CON_PPC_G3D2_QCH_CLOCK_REQ, QCH_CON_PPC_G3D2_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_G3D3_QCH, QCH_CON_PPC_G3D3_QCH_ENABLE, QCH_CON_PPC_G3D3_QCH_CLOCK_REQ, QCH_CON_PPC_G3D3_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_IRPS0_QCH, QCH_CON_PPC_IRPS0_QCH_ENABLE, QCH_CON_PPC_IRPS0_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS0_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_IRPS1_QCH, QCH_CON_PPC_IRPS1_QCH_ENABLE, QCH_CON_PPC_IRPS1_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS1_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_IRPS2_QCH, QCH_CON_PPC_IRPS2_QCH_ENABLE, QCH_CON_PPC_IRPS2_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS2_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_IRPS3_QCH, QCH_CON_PPC_IRPS3_QCH_ENABLE, QCH_CON_PPC_IRPS3_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS3_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL0_0_QCH, QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL0_1_QCH, QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D0_QCH, QCH_CON_PPMU_G3D0_QCH_ENABLE, QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D1_QCH, QCH_CON_PPMU_G3D1_QCH_ENABLE, QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D2_QCH, QCH_CON_PPMU_G3D2_QCH_ENABLE, QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D3_QCH, QCH_CON_PPMU_G3D3_QCH_ENABLE, QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G3D0_QCH, QCH_CON_SYSMMU_G3D0_QCH_ENABLE, QCH_CON_SYSMMU_G3D0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G3D0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G3D1_QCH, QCH_CON_SYSMMU_G3D1_QCH_ENABLE, QCH_CON_SYSMMU_G3D1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G3D1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G3D2_QCH, QCH_CON_SYSMMU_G3D2_QCH_ENABLE, QCH_CON_SYSMMU_G3D2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G3D2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G3D3_QCH, QCH_CON_SYSMMU_G3D3_QCH_ENABLE, QCH_CON_SYSMMU_G3D3_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G3D3_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MODEM_QCH, QCH_CON_SYSMMU_MODEM_QCH_ENABLE, QCH_CON_SYSMMU_MODEM_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MODEM_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P0_CORE_QCH, QCH_CON_TREX_P0_CORE_QCH_ENABLE, QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P1_CORE_QCH, QCH_CON_TREX_P1_CORE_QCH_ENABLE, QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_MODEM_QCH, QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE, QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MODEM_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_CPUCL0_0_QCH, DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_CPUCL0_0_QCH, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_0_QCH, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_0_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_QCH, DMYQCH_CON_CPUCL0_QCH_ENABLE, DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DDD_CPUCL0_0_QCH, DMYQCH_CON_DDD_CPUCL0_0_QCH_ENABLE, DMYQCH_CON_DDD_CPUCL0_0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL0_QCH, QCH_CON_HTU_CPUCL0_QCH_ENABLE, QCH_CON_HTU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_HTU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_BUSIF_DDD_CPUCL0_0_QCH, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_ENABLE, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BPS_CPUCL0_QCH, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_CPUCL0_QCH, QCH_CON_BUSIF_HPM_CPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPM_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL, QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CPUCL0_QCH, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T0_CLUSTER0_QCH, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T1_CLUSTER0_QCH, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T2_CLUSTER0_QCH, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T3_CLUSTER0_QCH, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T4_CLUSTER0_QCH, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T5_CLUSTER0_QCH, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T6_CLUSTER0_QCH, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T7_CLUSTER0_QCH, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T_BDU_QCH, QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_DBGCORE_QCH, QCH_CON_LHM_AXI_G_DBGCORE_QCH_ENABLE, QCH_CON_LHM_AXI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_INT_CSSYS_QCH, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_INT_DBGCORE_QCH, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_INT_ETR_QCH, QCH_CON_LHM_AXI_G_INT_ETR_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_ETR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_ETR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_INT_STM_QCH, QCH_CON_LHM_AXI_G_INT_STM_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_STM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_STM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_INT_CSSYS_QCH, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_INT_DBGCORE_QCH, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_INT_ETR_QCH, QCH_CON_LHS_AXI_G_INT_ETR_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_ETR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_ETR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_INT_STM_QCH, QCH_CON_LHS_AXI_G_INT_STM_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_STM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_STM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_CPUCL0_QCH, QCH_CON_TREX_CPUCL0_QCH_ENABLE, QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ, QCH_CON_TREX_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_CPUCL0_1_QCH, DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_CPUCL0_1_QCH, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_1_QCH, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_1_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH, DMYQCH_CON_CPUCL1_QCH_ENABLE, DMYQCH_CON_CPUCL1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_DDD_HC0, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_DDD_HC1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_DDD_HC2, DMYQCH_CON_CPUCL1_QCH_DDD_HC2_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_DDD_HC2_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL1_QCH_PCLK, QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL1_QCH_CLK, QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_BUSIF_DDD_CPUCL0_2_QCH, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_ENABLE, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_CLOCK_REQ, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_EXPIRE_VAL, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_BUSIF_DDD_CPUCL0_3_QCH, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_ENABLE, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_CLOCK_REQ, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_EXPIRE_VAL, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_BUSIF_DDD_CPUCL0_4_QCH, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_ENABLE, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_CLOCK_REQ, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_EXPIRE_VAL, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_CPUCL0_2_QCH, DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_CPUCL0_2_QCH, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_2_QCH, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_2_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL2_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL2_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL2_QCH, DMYQCH_CON_CPUCL2_QCH_ENABLE, DMYQCH_CON_CPUCL2_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL2_CMU_CPUCL2_QCH, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DDD_CPUCL0_1_QCH, DMYQCH_CON_DDD_CPUCL0_1_QCH_ENABLE, DMYQCH_CON_DDD_CPUCL0_1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL2_QCH_PCLK, QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL2_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL2_QCH_CLK, QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL2_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_BUSIF_DDD_CPUCL0_1_QCH, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_ENABLE, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSISX6_QCH_VOTF0, QCH_CON_CSISX6_QCH_VOTF0_ENABLE, QCH_CON_CSISX6_QCH_VOTF0_CLOCK_REQ, QCH_CON_CSISX6_QCH_VOTF0_EXPIRE_VAL, QCH_CON_CSISX6_QCH_VOTF0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSISX6_QCH_DMA, QCH_CON_CSISX6_QCH_DMA_ENABLE, QCH_CON_CSISX6_QCH_DMA_CLOCK_REQ, QCH_CON_CSISX6_QCH_DMA_EXPIRE_VAL, QCH_CON_CSISX6_QCH_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSISX6_QCH_MCB, QCH_CON_CSISX6_QCH_MCB_ENABLE, QCH_CON_CSISX6_QCH_MCB_CLOCK_REQ, QCH_CON_CSISX6_QCH_MCB_EXPIRE_VAL, QCH_CON_CSISX6_QCH_MCB_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSISX6_QCH_VOTF1, QCH_CON_CSISX6_QCH_VOTF1_ENABLE, QCH_CON_CSISX6_QCH_VOTF1_CLOCK_REQ, QCH_CON_CSISX6_QCH_VOTF1_EXPIRE_VAL, QCH_CON_CSISX6_QCH_VOTF1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_CMU_CSIS_QCH, QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CSIS_QCH, QCH_CON_D_TZPC_CSIS_QCH_ENABLE, QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF0_CSISPDP_QCH, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF0_PDPCSIS_QCH, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF1_CSISPDP_QCH, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF1_PDPCSIS_QCH, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF2_CSISPDP_QCH, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF2_PDPCSIS_QCH, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF3_CSISPDP_QCH, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_OTF3_PDPCSIS_QCH, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_ENABLE, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_VO_CSISPDP_QCH, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_ENABLE, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_INT_VO_PDPCSIS_QCH, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_ENABLE, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_SOTF0_TAACSIS_QCH, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_SOTF1_TAACSIS_QCH, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_SOTF2_TAACSIS_QCH, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_SOTF3_TAACSIS_QCH, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_ZOTF0_TAACSIS_QCH, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_ZOTF1_TAACSIS_QCH, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_ZOTF2_TAACSIS_QCH, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_ZOTF3_TAACSIS_QCH, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_ENABLE, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CSIS_QCH, QCH_CON_LHM_AXI_P_CSIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF0_CSISPDP_QCH, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF0_PDPCSIS_QCH, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF1_CSISPDP_QCH, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF1_PDPCSIS_QCH, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF2_CSISPDP_QCH, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF2_PDPCSIS_QCH, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF3_CSISPDP_QCH, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_OTF3_PDPCSIS_QCH, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_ENABLE, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_VO_CSISPDP_QCH, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_ENABLE, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_INT_VO_PDPCSIS_QCH, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_ENABLE, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_CSISTAA_QCH, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_CSISTAA_QCH, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_CSISTAA_QCH, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_CSISTAA_QCH, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_CSIS_QCH, QCH_CON_LHS_AXI_D0_CSIS_QCH_ENABLE, QCH_CON_LHS_AXI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_CSIS_QCH, QCH_CON_LHS_AXI_D1_CSIS_QCH_ENABLE, QCH_CON_LHS_AXI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D2_CSIS_QCH, QCH_CON_LHS_AXI_D2_CSIS_QCH_ENABLE, QCH_CON_LHS_AXI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D3_CSIS_QCH, QCH_CON_LHS_AXI_D3_CSIS_QCH_ENABLE, QCH_CON_LHS_AXI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CSISPERIC1_QCH, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS0, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS2, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS3, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS4, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS5, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN),
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CLK_QCH(OIS_MCU_TOP_QCH, QCH_CON_OIS_MCU_TOP_QCH_ENABLE, QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ, QCH_CON_OIS_MCU_TOP_QCH_EXPIRE_VAL, QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDP_TOP_QCH_PDP_TOP, QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE, QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ, QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL, QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDP_TOP_QCH_C2_PDP, QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE, QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ, QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL, QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_QCH, QCH_CON_PPMU_D0_QCH_ENABLE, QCH_CON_PPMU_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_QCH, QCH_CON_PPMU_D1_QCH_ENABLE, QCH_CON_PPMU_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D2_QCH, QCH_CON_PPMU_D2_QCH_ENABLE, QCH_CON_PPMU_D2_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D3_QCH, QCH_CON_PPMU_D3_QCH_ENABLE, QCH_CON_PPMU_D3_QCH_CLOCK_REQ, QCH_CON_PPMU_D3_QCH_EXPIRE_VAL, QCH_CON_PPMU_D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA0_QCH, QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA1_QCH, QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA2_QCH, QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA3_QCH, QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_AF1_QCH, QCH_CON_QE_PDP_AF1_QCH_ENABLE, QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_AF2_QCH, QCH_CON_QE_PDP_AF2_QCH_ENABLE, QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_AF0_QCH, QCH_CON_QE_PDP_STAT_AF0_QCH_ENABLE, QCH_CON_QE_PDP_STAT_AF0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_AF0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_AF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG0_QCH, QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG1_QCH, QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG2_QCH, QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP0_QCH, QCH_CON_QE_STRP0_QCH_ENABLE, QCH_CON_QE_STRP0_QCH_CLOCK_REQ, QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP1_QCH, QCH_CON_QE_STRP1_QCH_ENABLE, QCH_CON_QE_STRP1_QCH_CLOCK_REQ, QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP2_QCH, QCH_CON_QE_STRP2_QCH_ENABLE, QCH_CON_QE_STRP2_QCH_CLOCK_REQ, QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP3_QCH, QCH_CON_QE_STRP3_QCH_ENABLE, QCH_CON_QE_STRP3_QCH_CLOCK_REQ, QCH_CON_QE_STRP3_QCH_EXPIRE_VAL, QCH_CON_QE_STRP3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL0_QCH, QCH_CON_QE_ZSL0_QCH_ENABLE, QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL1_QCH, QCH_CON_QE_ZSL1_QCH_ENABLE, QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL2_QCH, QCH_CON_QE_ZSL2_QCH_ENABLE, QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL3_QCH, QCH_CON_QE_ZSL3_QCH_ENABLE, QCH_CON_QE_ZSL3_QCH_CLOCK_REQ, QCH_CON_QE_ZSL3_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_CSIS_QCH_S1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_CSIS_QCH_S2, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_CSIS_QCH_S1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_CSIS_QCH_S2, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_CSIS_QCH_S1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_CSIS_QCH_S2, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_CSIS_QCH_S1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_CSIS_QCH_S2, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CSIS_QCH, QCH_CON_SYSREG_CSIS_QCH_ENABLE, QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D0_QCH, QCH_CON_VGEN_LITE_D0_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D1_QCH, QCH_CON_VGEN_LITE_D1_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D2_QCH, QCH_CON_VGEN_LITE_D2_QCH_ENABLE, QCH_CON_VGEN_LITE_D2_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D2_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DNS_QCH, QCH_CON_DNS_QCH_ENABLE, QCH_CON_DNS_QCH_CLOCK_REQ, QCH_CON_DNS_QCH_EXPIRE_VAL, QCH_CON_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DNS_QCH_VOTF0, QCH_CON_DNS_QCH_VOTF0_ENABLE, QCH_CON_DNS_QCH_VOTF0_CLOCK_REQ, QCH_CON_DNS_QCH_VOTF0_EXPIRE_VAL, QCH_CON_DNS_QCH_VOTF0_IGNORE_FORCE_PM_EN),
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CLK_QCH(DNS_QCH_VOTF1, QCH_CON_DNS_QCH_VOTF1_ENABLE, QCH_CON_DNS_QCH_VOTF1_CLOCK_REQ, QCH_CON_DNS_QCH_VOTF1_EXPIRE_VAL, QCH_CON_DNS_QCH_VOTF1_IGNORE_FORCE_PM_EN),
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CLK_QCH(DNS_QCH_VOTF2, QCH_CON_DNS_QCH_VOTF2_ENABLE, QCH_CON_DNS_QCH_VOTF2_CLOCK_REQ, QCH_CON_DNS_QCH_VOTF2_EXPIRE_VAL, QCH_CON_DNS_QCH_VOTF2_IGNORE_FORCE_PM_EN),
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CLK_QCH(DNS_CMU_DNS_QCH, QCH_CON_DNS_CMU_DNS_QCH_ENABLE, QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ, QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL, QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_DNS_QCH, QCH_CON_D_TZPC_DNS_QCH_ENABLE, QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_CTL_ITPDNS_QCH, QCH_CON_LHM_AST_CTL_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_CTL_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_CTL_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_ITPDNS_QCH, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_ITPDNS_QCH, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_ITPDNS_QCH, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_ITPDNS_QCH, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF4_ITPDNS_QCH, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF_MCFP1DNS_QCH, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF_TAADNS_QCH, QCH_CON_LHM_AST_OTF_TAADNS_QCH_ENABLE, QCH_CON_LHM_AST_OTF_TAADNS_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF_TAADNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ITPDNS_QCH, QCH_CON_LHM_AXI_P_ITPDNS_QCH_ENABLE, QCH_CON_LHM_AXI_P_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_CTL_DNSITP_QCH, QCH_CON_LHS_AST_CTL_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_CTL_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_CTL_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_DNSITP_QCH, QCH_CON_LHS_AST_OTF0_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_DNSITP_QCH, QCH_CON_LHS_AST_OTF1_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_DNSITP_QCH, QCH_CON_LHS_AST_OTF2_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_DNSITP_QCH, QCH_CON_LHS_AST_OTF3_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF4_DNSITP_QCH, QCH_CON_LHS_AST_OTF4_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF4_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF4_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF5_DNSITP_QCH, QCH_CON_LHS_AST_OTF5_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF5_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF5_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF6_DNSITP_QCH, QCH_CON_LHS_AST_OTF6_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF6_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF6_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF7_DNSITP_QCH, QCH_CON_LHS_AST_OTF7_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF7_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF7_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF8_DNSITP_QCH, QCH_CON_LHS_AST_OTF8_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF8_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF8_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF9_DNSITP_QCH, QCH_CON_LHS_AST_OTF9_DNSITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF9_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF9_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_DNS_QCH, QCH_CON_LHS_AXI_D0_DNS_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DNS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_DNS_QCH, QCH_CON_LHS_AXI_D1_DNS_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DNS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_DNS_QCH, QCH_CON_PPMU_D0_DNS_QCH_ENABLE, QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_DNS_QCH, QCH_CON_PPMU_D1_DNS_QCH_ENABLE, QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_DNS_QCH_S2, QCH_CON_SYSMMU_D0_DNS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_DNS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_DNS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_DNS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_DNS_QCH_S1, QCH_CON_SYSMMU_D0_DNS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_DNS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_DNS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_DNS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_DNS_QCH_S2, QCH_CON_SYSMMU_D1_DNS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_DNS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_DNS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_DNS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_DNS_QCH_S1, QCH_CON_SYSMMU_D1_DNS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_DNS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_DNS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_DNS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DNS_QCH, QCH_CON_SYSREG_DNS_QCH_ENABLE, QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ, QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D0_DNS_QCH, QCH_CON_VGEN_LITE_D0_DNS_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_DNS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D0_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D1_DNS_QCH, QCH_CON_VGEN_LITE_D1_DNS_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_DNS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D1_DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUB_QCH, QCH_CON_DPUB_QCH_ENABLE, QCH_CON_DPUB_QCH_CLOCK_REQ, QCH_CON_DPUB_QCH_EXPIRE_VAL, QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUB_CMU_DPUB_QCH, QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE, QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ, QCH_CON_DPUB_CMU_DPUB_QCH_EXPIRE_VAL, QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_DPUB_QCH, QCH_CON_D_TZPC_DPUB_QCH_ENABLE, QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUB_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DPUB_QCH, QCH_CON_LHM_AXI_P_DPUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DPUB_QCH, QCH_CON_SYSREG_DPUB_QCH_ENABLE, QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF0_QCH_DMA, QCH_CON_DPUF0_QCH_DMA_ENABLE, QCH_CON_DPUF0_QCH_DMA_CLOCK_REQ, QCH_CON_DPUF0_QCH_DMA_EXPIRE_VAL, QCH_CON_DPUF0_QCH_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF0_QCH_DPP, QCH_CON_DPUF0_QCH_DPP_ENABLE, QCH_CON_DPUF0_QCH_DPP_CLOCK_REQ, QCH_CON_DPUF0_QCH_DPP_EXPIRE_VAL, QCH_CON_DPUF0_QCH_DPP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF0_QCH_C2SERV, QCH_CON_DPUF0_QCH_C2SERV_ENABLE, QCH_CON_DPUF0_QCH_C2SERV_CLOCK_REQ, QCH_CON_DPUF0_QCH_C2SERV_EXPIRE_VAL, QCH_CON_DPUF0_QCH_C2SERV_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF0_CMU_DPUF0_QCH, QCH_CON_DPUF0_CMU_DPUF0_QCH_ENABLE, QCH_CON_DPUF0_CMU_DPUF0_QCH_CLOCK_REQ, QCH_CON_DPUF0_CMU_DPUF0_QCH_EXPIRE_VAL, QCH_CON_DPUF0_CMU_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_DPUF0_QCH, QCH_CON_D_TZPC_DPUF0_QCH_ENABLE, QCH_CON_D_TZPC_DPUF0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUF0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_DPUF1DPUF0_QCH, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_ENABLE, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DPUF0_QCH, QCH_CON_LHM_AXI_P_DPUF0_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_DPUF0_QCH, QCH_CON_LHS_AXI_D0_DPUF0_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_DPUF0_QCH, QCH_CON_LHS_AXI_D1_DPUF0_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPUF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUF0D0_QCH, QCH_CON_PPMU_DPUF0D0_QCH_ENABLE, QCH_CON_PPMU_DPUF0D0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF0D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUF0D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUF0D1_QCH, QCH_CON_PPMU_DPUF0D1_QCH_ENABLE, QCH_CON_PPMU_DPUF0D1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF0D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUF0D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF0D0_QCH_S1, QCH_CON_SYSMMU_DPUF0D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF0D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF0D0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF0D0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF0D0_QCH_S2, QCH_CON_SYSMMU_DPUF0D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF0D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF0D0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF0D0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF0D1_QCH_S1, QCH_CON_SYSMMU_DPUF0D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF0D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF0D1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF0D1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF0D1_QCH_S2, QCH_CON_SYSMMU_DPUF0D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF0D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF0D1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF0D1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DPUF0_QCH, QCH_CON_SYSREG_DPUF0_QCH_ENABLE, QCH_CON_SYSREG_DPUF0_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUF0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF1_QCH_DMA, QCH_CON_DPUF1_QCH_DMA_ENABLE, QCH_CON_DPUF1_QCH_DMA_CLOCK_REQ, QCH_CON_DPUF1_QCH_DMA_EXPIRE_VAL, QCH_CON_DPUF1_QCH_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF1_QCH_DPP, QCH_CON_DPUF1_QCH_DPP_ENABLE, QCH_CON_DPUF1_QCH_DPP_CLOCK_REQ, QCH_CON_DPUF1_QCH_DPP_EXPIRE_VAL, QCH_CON_DPUF1_QCH_DPP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF1_QCH_C2SERV, QCH_CON_DPUF1_QCH_C2SERV_ENABLE, QCH_CON_DPUF1_QCH_C2SERV_CLOCK_REQ, QCH_CON_DPUF1_QCH_C2SERV_EXPIRE_VAL, QCH_CON_DPUF1_QCH_C2SERV_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPUF1_CMU_DPUF1_QCH, QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE, QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ, QCH_CON_DPUF1_CMU_DPUF1_QCH_EXPIRE_VAL, QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_DPUF1_QCH, QCH_CON_D_TZPC_DPUF1_QCH_ENABLE, QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUF1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DPUF1_QCH, QCH_CON_LHM_AXI_P_DPUF1_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_DPUF1_QCH, QCH_CON_LHS_AXI_D0_DPUF1_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_DPUF1_QCH, QCH_CON_LHS_AXI_D1_DPUF1_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPUF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPUF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_DPUF1DPUF0_QCH, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_ENABLE, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUF1D0_QCH, QCH_CON_PPMU_DPUF1D0_QCH_ENABLE, QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF1D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUF1D1_QCH, QCH_CON_PPMU_DPUF1D1_QCH_ENABLE, QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF1D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF1D0_QCH_S2, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF1D0_QCH_S1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF1D1_QCH_S2, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUF1D1_QCH_S1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DPUF1_QCH, QCH_CON_SYSREG_DPUF1_QCH_ENABLE, QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUF1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_US_128TO256_D0_CLUSTER0_QCH, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_ENABLE, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_US_128TO256_D1_CLUSTER0_QCH, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_ENABLE, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_3_QCH, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_CPUCL0_3_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_EXPIRE_VAL, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PDBGCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_GICCLK, QCH_CON_CLUSTER0_QCH_GICCLK_ENABLE, QCH_CON_CLUSTER0_QCH_GICCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GICCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_GICCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_DBG_PD, QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PCLK, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PERIPHCLK, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_DSU_CMUREF_QCH, DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_DSU_SHORTSTOP_QCH, QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DSU_CMU_DSU_QCH, QCH_CON_DSU_CMU_DSU_QCH_ENABLE, QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL, QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_DSU_QCH, QCH_CON_HTU_DSU_QCH_ENABLE, QCH_CON_HTU_DSU_QCH_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_EXPIRE_VAL, QCH_CON_HTU_DSU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_IRI_GICCPU_CLUSTER0_QCH, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D0_CLUSTER0_QCH, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D1_CLUSTER0_QCH, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_ICC_CPUGIC_CLUSTER0_QCH, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T0_CLUSTER0_QCH, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T1_CLUSTER0_QCH, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T2_CLUSTER0_QCH, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T3_CLUSTER0_QCH, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T4_CLUSTER0_QCH, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T5_CLUSTER0_QCH, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T6_CLUSTER0_QCH, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T7_CLUSTER0_QCH, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRET_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRET_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRUN_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRUN_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_APBIF_G3D_QCH, QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL, QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_G3D_QCH, DMYQCH_CON_ADD_G3D_QCH_ENABLE, DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASB_G3D_QCH_LH_D0_G3D, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASB_G3D_QCH_LH_D1_G3D, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASB_G3D_QCH_LH_D2_G3D, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASB_G3D_QCH_LH_D3_G3D, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_G3D_QCH, QCH_CON_BUSIF_STR_G3D_QCH_ENABLE, QCH_CON_BUSIF_STR_G3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_G3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_STR_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_STR_G3D_QCH_CORE, QCH_CON_BUSIF_STR_G3D_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_G3D_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_G3D_QCH_CORE_EXPIRE_VAL, QCH_CON_BUSIF_STR_G3D_QCH_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_G3D_QCH, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPU_QCH, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_G3D_QCH_PCLK, QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_G3D_QCH_CLK, QCH_CON_HTU_G3D_QCH_CLK_ENABLE, QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_INT_G3D_QCH, QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_INT_G3D_QCH, QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_G3D_QCH, QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH_PCLK, QCH_CON_DP_LINK_QCH_PCLK_ENABLE, QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH_GTC_CLK, QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_HSI0_QCH, QCH_CON_D_TZPC_HSI0_QCH_ENABLE, QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HSI0_CMU_HSI0_QCH, QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL, QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_AUDHSI0_QCH, QCH_CON_LHM_AXI_D_AUDHSI0_QCH_ENABLE, QCH_CON_LHM_AXI_D_AUDHSI0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_AUDHSI0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_HSI0_QCH, QCH_CON_LHM_AXI_P_HSI0_QCH_ENABLE, QCH_CON_LHM_AXI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_HSI0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_HSI0_QCH, QCH_CON_LHS_ACEL_D_HSI0_QCH_ENABLE, QCH_CON_LHS_ACEL_D_HSI0_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_HSI0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_HSI0AUD_QCH, QCH_CON_LHS_AXI_D_HSI0AUD_QCH_ENABLE, QCH_CON_LHS_AXI_D_HSI0AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_HSI0AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_HSI0_BUS1_QCH, QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE, QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI0_BUS1_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_USB_QCH, QCH_CON_SYSMMU_USB_QCH_ENABLE, QCH_CON_SYSMMU_USB_QCH_CLOCK_REQ, QCH_CON_SYSMMU_USB_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_HSI0_QCH, QCH_CON_SYSREG_HSI0_QCH_ENABLE, QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_REF, DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_SLV_CTRL, QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_SLV_LINK, QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_APB, QCH_CON_USB31DRD_QCH_APB_ENABLE, QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_PCS, QCH_CON_USB31DRD_QCH_PCS_ENABLE, QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB31DRD_QCH_DBG, QCH_CON_USB31DRD_QCH_DBG_ENABLE, QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ, QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_HSI0_QCH, QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_HSI1_QCH, QCH_CON_D_TZPC_HSI1_QCH_ENABLE, QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_HSI1_QCH, QCH_CON_GPIO_HSI1_QCH_ENABLE, QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HSI1_CMU_HSI1_QCH, QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL, QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_HSI1_QCH, QCH_CON_LHM_AXI_P_HSI1_QCH_ENABLE, QCH_CON_LHM_AXI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_HSI1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_HSI1_QCH, QCH_CON_LHS_ACEL_D_HSI1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_HSI1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_MSTR, QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE, QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_PCS, QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE, QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_PHY, QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE, QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_DBI, QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_APB, QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_REF, DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE, DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_APB, QCH_CON_PCIE_GEN4_0_QCH_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_DBI, QCH_CON_PCIE_GEN4_0_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_DBI_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_DBI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_AXI, QCH_CON_PCIE_GEN4_0_QCH_AXI_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_AXI_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_AXI_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_AXI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_PCS_APB, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_REF, DMYQCH_CON_PCIE_GEN4_0_QCH_REF_ENABLE, DMYQCH_CON_PCIE_GEN4_0_QCH_REF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN4_0_QCH_REF_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_PMA_APB, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN4_0_QCH_UDBG_APB, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_IA_GEN2_QCH, QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_IA_GEN4_0_QCH, QCH_CON_PCIE_IA_GEN4_0_QCH_ENABLE, QCH_CON_PCIE_IA_GEN4_0_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN4_0_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN4_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_HSI1_QCH, QCH_CON_PPMU_HSI1_QCH_ENABLE, QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_HSI1_QCH, QCH_CON_SYSMMU_HSI1_QCH_ENABLE, QCH_CON_SYSMMU_HSI1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_HSI1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_HSI1_QCH, QCH_CON_SYSREG_HSI1_QCH_ENABLE, QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_HSI1_QCH, QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_ITP_QCH, QCH_CON_D_TZPC_ITP_QCH_ENABLE, QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ITP_QCH, QCH_CON_ITP_QCH_ENABLE, QCH_CON_ITP_QCH_CLOCK_REQ, QCH_CON_ITP_QCH_EXPIRE_VAL, QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ITP_CMU_ITP_QCH, QCH_CON_ITP_CMU_ITP_QCH_ENABLE, QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ, QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL, QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_CTL_DNSITP_QCH, QCH_CON_LHM_AST_CTL_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_CTL_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_CTL_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_DNSITP_QCH, QCH_CON_LHM_AST_OTF0_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_DNSITP_QCH, QCH_CON_LHM_AST_OTF1_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_DNSITP_QCH, QCH_CON_LHM_AST_OTF2_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_DNSITP_QCH, QCH_CON_LHM_AST_OTF3_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF4_DNSITP_QCH, QCH_CON_LHM_AST_OTF4_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF4_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF4_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF5_DNSITP_QCH, QCH_CON_LHM_AST_OTF5_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF5_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF5_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF6_DNSITP_QCH, QCH_CON_LHM_AST_OTF6_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF6_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF6_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF7_DNSITP_QCH, QCH_CON_LHM_AST_OTF7_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF7_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF7_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF8_DNSITP_QCH, QCH_CON_LHM_AST_OTF8_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF8_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF8_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF9_DNSITP_QCH, QCH_CON_LHM_AST_OTF9_DNSITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF9_DNSITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF9_DNSITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF_MCFP1ITP_QCH, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_ENABLE, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ITP_QCH, QCH_CON_LHM_AXI_P_ITP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ITP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ITP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_CTL_ITPDNS_QCH, QCH_CON_LHS_AST_CTL_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_CTL_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_CTL_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_ITPDNS_QCH, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_ITPDNS_QCH, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_ITPDNS_QCH, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_ITPDNS_QCH, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF4_ITPDNS_QCH, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF_ITPMCSC_QCH, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_ENABLE, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ITPDNS_QCH, QCH_CON_LHS_AXI_P_ITPDNS_QCH_ENABLE, QCH_CON_LHS_AXI_P_ITPDNS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ITPDNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ITP_QCH, QCH_CON_SYSREG_ITP_QCH_ENABLE, QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_LME_QCH, QCH_CON_D_TZPC_LME_QCH_ENABLE, QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ, QCH_CON_D_TZPC_LME_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_LME_QCH, QCH_CON_LHM_AXI_P_LME_QCH_ENABLE, QCH_CON_LHM_AXI_P_LME_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_LME_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_LME_QCH, QCH_CON_LHS_AXI_D_LME_QCH_ENABLE, QCH_CON_LHS_AXI_D_LME_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_LME_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LME_QCH, QCH_CON_LME_QCH_ENABLE, QCH_CON_LME_QCH_CLOCK_REQ, QCH_CON_LME_QCH_EXPIRE_VAL, QCH_CON_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LME_QCH_C2, QCH_CON_LME_QCH_C2_ENABLE, QCH_CON_LME_QCH_C2_CLOCK_REQ, QCH_CON_LME_QCH_C2_EXPIRE_VAL, QCH_CON_LME_QCH_C2_IGNORE_FORCE_PM_EN),
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CLK_QCH(LME_CMU_LME_QCH, QCH_CON_LME_CMU_LME_QCH_ENABLE, QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ, QCH_CON_LME_CMU_LME_QCH_EXPIRE_VAL, QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_LME_QCH, QCH_CON_PPMU_LME_QCH_ENABLE, QCH_CON_PPMU_LME_QCH_CLOCK_REQ, QCH_CON_PPMU_LME_QCH_EXPIRE_VAL, QCH_CON_PPMU_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_LME_QCH_S2, QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_LME_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_LME_QCH_S1, QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_LME_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_LME_QCH, QCH_CON_SYSREG_LME_QCH_ENABLE, QCH_CON_SYSREG_LME_QCH_CLOCK_REQ, QCH_CON_SYSREG_LME_QCH_EXPIRE_VAL, QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_LME_QCH, QCH_CON_VGEN_LITE_LME_QCH_ENABLE, QCH_CON_VGEN_LITE_LME_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_LME_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_LME_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASTC_QCH, QCH_CON_ASTC_QCH_ENABLE, QCH_CON_ASTC_QCH_CLOCK_REQ, QCH_CON_ASTC_QCH_EXPIRE_VAL, QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_M2M_QCH, QCH_CON_D_TZPC_M2M_QCH_ENABLE, QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JPEG0_QCH, QCH_CON_JPEG0_QCH_ENABLE, QCH_CON_JPEG0_QCH_CLOCK_REQ, QCH_CON_JPEG0_QCH_EXPIRE_VAL, QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JPEG1_QCH, QCH_CON_JPEG1_QCH_ENABLE, QCH_CON_JPEG1_QCH_CLOCK_REQ, QCH_CON_JPEG1_QCH_EXPIRE_VAL, QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JSQZ_QCH, QCH_CON_JSQZ_QCH_ENABLE, QCH_CON_JSQZ_QCH_CLOCK_REQ, QCH_CON_JSQZ_QCH_EXPIRE_VAL, QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_M2M_QCH, QCH_CON_LHM_AXI_P_M2M_QCH_ENABLE, QCH_CON_LHM_AXI_P_M2M_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_M2M_QCH, QCH_CON_LHS_ACEL_D_M2M_QCH_ENABLE, QCH_CON_LHS_ACEL_D_M2M_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_QCH, QCH_CON_M2M_QCH_ENABLE, QCH_CON_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_QCH_EXPIRE_VAL, QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_QCH_VOTF, QCH_CON_M2M_QCH_VOTF_ENABLE, QCH_CON_M2M_QCH_VOTF_CLOCK_REQ, QCH_CON_M2M_QCH_VOTF_EXPIRE_VAL, QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_CMU_M2M_QCH, QCH_CON_M2M_CMU_M2M_QCH_ENABLE, QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL, QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D_M2M_QCH, QCH_CON_PPMU_D_M2M_QCH_ENABLE, QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ASTC_QCH, QCH_CON_QE_ASTC_QCH_ENABLE, QCH_CON_QE_ASTC_QCH_CLOCK_REQ, QCH_CON_QE_ASTC_QCH_EXPIRE_VAL, QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_JPEG0_QCH, QCH_CON_QE_JPEG0_QCH_ENABLE, QCH_CON_QE_JPEG0_QCH_CLOCK_REQ, QCH_CON_QE_JPEG0_QCH_EXPIRE_VAL, QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_JPEG1_QCH, QCH_CON_QE_JPEG1_QCH_ENABLE, QCH_CON_QE_JPEG1_QCH_CLOCK_REQ, QCH_CON_QE_JPEG1_QCH_EXPIRE_VAL, QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_JSQZ_QCH, QCH_CON_QE_JSQZ_QCH_ENABLE, QCH_CON_QE_JSQZ_QCH_CLOCK_REQ, QCH_CON_QE_JSQZ_QCH_EXPIRE_VAL, QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_M2M_QCH, QCH_CON_QE_M2M_QCH_ENABLE, QCH_CON_QE_M2M_QCH_CLOCK_REQ, QCH_CON_QE_M2M_QCH_EXPIRE_VAL, QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_M2M_QCH_S2, QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_M2M_QCH_S1, QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_M2M_QCH, QCH_CON_SYSREG_M2M_QCH_ENABLE, QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL, QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_M2M_QCH, QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MCFP0_QCH, QCH_CON_D_TZPC_MCFP0_QCH_ENABLE, QCH_CON_D_TZPC_MCFP0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCFP0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_CTL_MCFP1MCFP0_QCH, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_MCFP1MCFP0_QCH, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_MCFP1MCFP0_QCH, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_MCFP1MCFP0_QCH, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_MCFP1MCFP0_QCH, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MCFP0_QCH, QCH_CON_LHM_AXI_P_MCFP0_QCH_ENABLE, QCH_CON_LHM_AXI_P_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_CTL_MCFP0MCFP1_QCH, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_MCFP0MCFP1_QCH, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_MCFP0MCFP1_QCH, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MCFP0_QCH, QCH_CON_LHS_AXI_D0_MCFP0_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MCFP0_QCH, QCH_CON_LHS_AXI_D1_MCFP0_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D2_MCFP0_QCH, QCH_CON_LHS_AXI_D2_MCFP0_QCH_ENABLE, QCH_CON_LHS_AXI_D2_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D3_MCFP0_QCH, QCH_CON_LHS_AXI_D3_MCFP0_QCH_ENABLE, QCH_CON_LHS_AXI_D3_MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D3_MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MCFP0MCFP1_QCH, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCFP0_QCH, QCH_CON_MCFP0_QCH_ENABLE, QCH_CON_MCFP0_QCH_CLOCK_REQ, QCH_CON_MCFP0_QCH_EXPIRE_VAL, QCH_CON_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCFP0_CMU_MCFP0_QCH, QCH_CON_MCFP0_CMU_MCFP0_QCH_ENABLE, QCH_CON_MCFP0_CMU_MCFP0_QCH_CLOCK_REQ, QCH_CON_MCFP0_CMU_MCFP0_QCH_EXPIRE_VAL, QCH_CON_MCFP0_CMU_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_MCFP0_QCH, QCH_CON_PPMU_D0_MCFP0_QCH_ENABLE, QCH_CON_PPMU_D0_MCFP0_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_MCFP0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_MCFP0_QCH, QCH_CON_PPMU_D1_MCFP0_QCH_ENABLE, QCH_CON_PPMU_D1_MCFP0_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_MCFP0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D2_MCFP0_QCH, QCH_CON_PPMU_D2_MCFP0_QCH_ENABLE, QCH_CON_PPMU_D2_MCFP0_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_MCFP0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D3_MCFP0_QCH, QCH_CON_PPMU_D3_MCFP0_QCH_ENABLE, QCH_CON_PPMU_D3_MCFP0_QCH_CLOCK_REQ, QCH_CON_PPMU_D3_MCFP0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D0_MCFP0_QCH, QCH_CON_QE_D0_MCFP0_QCH_ENABLE, QCH_CON_QE_D0_MCFP0_QCH_CLOCK_REQ, QCH_CON_QE_D0_MCFP0_QCH_EXPIRE_VAL, QCH_CON_QE_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D1_MCFP0_QCH, QCH_CON_QE_D1_MCFP0_QCH_ENABLE, QCH_CON_QE_D1_MCFP0_QCH_CLOCK_REQ, QCH_CON_QE_D1_MCFP0_QCH_EXPIRE_VAL, QCH_CON_QE_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D2_MCFP0_QCH, QCH_CON_QE_D2_MCFP0_QCH_ENABLE, QCH_CON_QE_D2_MCFP0_QCH_CLOCK_REQ, QCH_CON_QE_D2_MCFP0_QCH_EXPIRE_VAL, QCH_CON_QE_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D3_MCFP0_QCH, QCH_CON_QE_D3_MCFP0_QCH_ENABLE, QCH_CON_QE_D3_MCFP0_QCH_CLOCK_REQ, QCH_CON_QE_D3_MCFP0_QCH_EXPIRE_VAL, QCH_CON_QE_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCFP0_QCH_S1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCFP0_QCH_S2, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCFP0_QCH_S1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCFP0_QCH_S2, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_MCFP0_QCH_S1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_MCFP0_QCH_S2, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_MCFP0_QCH_S1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_MCFP0_QCH_S2, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MCFP0_QCH, QCH_CON_SYSREG_MCFP0_QCH_ENABLE, QCH_CON_SYSREG_MCFP0_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCFP0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_MCFP0_QCH, QCH_CON_VGEN_LITE_MCFP0_QCH_ENABLE, QCH_CON_VGEN_LITE_MCFP0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MCFP0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MCFP1_QCH, QCH_CON_D_TZPC_MCFP1_QCH_ENABLE, QCH_CON_D_TZPC_MCFP1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCFP1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_CTL_MCFP0MCFP1_QCH, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_MCFP0MCFP1_QCH, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_MCFP0MCFP1_QCH, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_VO_TAAMCFP1_QCH, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_ENABLE, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MCFP0MCFP1_QCH, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_ENABLE, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_CTL_MCFP1MCFP0_QCH, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_MCFP1MCFP0_QCH, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_MCFP1MCFP0_QCH, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_MCFP1MCFP0_QCH, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_MCFP1MCFP0_QCH, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF_MCFP1DNS_QCH, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF_MCFP1ITP_QCH, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_ENABLE, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_VO_MCFP1TAA_QCH, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_ENABLE, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_CLOCK_REQ, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_MCFP1_QCH, QCH_CON_LHS_AXI_D_MCFP1_QCH_ENABLE, QCH_CON_LHS_AXI_D_MCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_MCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCFP1_QCH, QCH_CON_MCFP1_QCH_ENABLE, QCH_CON_MCFP1_QCH_CLOCK_REQ, QCH_CON_MCFP1_QCH_EXPIRE_VAL, QCH_CON_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCFP1_CMU_MCFP1_QCH, QCH_CON_MCFP1_CMU_MCFP1_QCH_ENABLE, QCH_CON_MCFP1_CMU_MCFP1_QCH_CLOCK_REQ, QCH_CON_MCFP1_CMU_MCFP1_QCH_EXPIRE_VAL, QCH_CON_MCFP1_CMU_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH0_QCH_C2, QCH_CON_ORBMCH0_QCH_C2_ENABLE, QCH_CON_ORBMCH0_QCH_C2_CLOCK_REQ, QCH_CON_ORBMCH0_QCH_C2_EXPIRE_VAL, QCH_CON_ORBMCH0_QCH_C2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH0_QCH, QCH_CON_ORBMCH0_QCH_ENABLE, QCH_CON_ORBMCH0_QCH_CLOCK_REQ, QCH_CON_ORBMCH0_QCH_EXPIRE_VAL, QCH_CON_ORBMCH0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH1_QCH, QCH_CON_ORBMCH1_QCH_ENABLE, QCH_CON_ORBMCH1_QCH_CLOCK_REQ, QCH_CON_ORBMCH1_QCH_EXPIRE_VAL, QCH_CON_ORBMCH1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH1_QCH_C2, QCH_CON_ORBMCH1_QCH_C2_ENABLE, QCH_CON_ORBMCH1_QCH_C2_CLOCK_REQ, QCH_CON_ORBMCH1_QCH_C2_EXPIRE_VAL, QCH_CON_ORBMCH1_QCH_C2_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_ORBMCH_QCH, QCH_CON_PPMU_ORBMCH_QCH_ENABLE, QCH_CON_PPMU_ORBMCH_QCH_CLOCK_REQ, QCH_CON_PPMU_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_PPMU_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D0_ORBMCH_QCH, QCH_CON_QE_D0_ORBMCH_QCH_ENABLE, QCH_CON_QE_D0_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D0_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D0_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D1_ORBMCH_QCH, QCH_CON_QE_D1_ORBMCH_QCH_ENABLE, QCH_CON_QE_D1_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D1_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D1_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D2_ORBMCH_QCH, QCH_CON_QE_D2_ORBMCH_QCH_ENABLE, QCH_CON_QE_D2_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D2_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D2_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D3_ORBMCH_QCH, QCH_CON_QE_D3_ORBMCH_QCH_ENABLE, QCH_CON_QE_D3_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D3_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D3_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D4_ORBMCH_QCH, QCH_CON_QE_D4_ORBMCH_QCH_ENABLE, QCH_CON_QE_D4_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D4_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D4_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D5_ORBMCH_QCH, QCH_CON_QE_D5_ORBMCH_QCH_ENABLE, QCH_CON_QE_D5_ORBMCH_QCH_CLOCK_REQ, QCH_CON_QE_D5_ORBMCH_QCH_EXPIRE_VAL, QCH_CON_QE_D5_ORBMCH_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_MCFP1_QCH_S2, QCH_CON_SYSMMU_D_MCFP1_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_MCFP1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_MCFP1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_MCFP1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_MCFP1_QCH_S1, QCH_CON_SYSMMU_D_MCFP1_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_MCFP1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_MCFP1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_MCFP1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MCFP1_QCH, QCH_CON_SYSREG_MCFP1_QCH_ENABLE, QCH_CON_SYSREG_MCFP1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCFP1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D0_MCFP1_QCH, QCH_CON_VGEN_LITE_D0_MCFP1_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_MCFP1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_MCFP1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D0_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D1_MCFP1_QCH, QCH_CON_VGEN_LITE_D1_MCFP1_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_MCFP1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_MCFP1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D1_MCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_MCSC_QCH, DMYQCH_CON_ADD_MCSC_QCH_ENABLE, DMYQCH_CON_ADD_MCSC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_MCSC_QCH, QCH_CON_BUSIF_ADD_MCSC_QCH_ENABLE, QCH_CON_BUSIF_ADD_MCSC_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_MCSC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_MCSC_QCH, QCH_CON_BUSIF_HPM_MCSC_QCH_ENABLE, QCH_CON_BUSIF_HPM_MCSC_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_MCSC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MCSC_QCH, QCH_CON_D_TZPC_MCSC_QCH_ENABLE, QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GDC_QCH, QCH_CON_GDC_QCH_ENABLE, QCH_CON_GDC_QCH_CLOCK_REQ, QCH_CON_GDC_QCH_EXPIRE_VAL, QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GDC_QCH_C2_M, QCH_CON_GDC_QCH_C2_M_ENABLE, QCH_CON_GDC_QCH_C2_M_CLOCK_REQ, QCH_CON_GDC_QCH_C2_M_EXPIRE_VAL, QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN),
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CLK_QCH(GDC_QCH_C2_S, QCH_CON_GDC_QCH_C2_S_ENABLE, QCH_CON_GDC_QCH_C2_S_CLOCK_REQ, QCH_CON_GDC_QCH_C2_S_EXPIRE_VAL, QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF_ITPMCSC_QCH, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_ENABLE, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF_YUVPPMCSC_QCH, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_ENABLE, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_YUVPPMCSC_QCH, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_ENABLE, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MCSC_QCH, QCH_CON_LHM_AXI_P_MCSC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_MCSC_QCH, QCH_CON_LHS_ACEL_D0_MCSC_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MCSC_QCH, QCH_CON_LHS_AXI_D1_MCSC_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D2_MCSC_QCH, QCH_CON_LHS_AXI_D2_MCSC_QCH_ENABLE, QCH_CON_LHS_AXI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_QCH, QCH_CON_MCSC_QCH_ENABLE, QCH_CON_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_QCH_C2_W, QCH_CON_MCSC_QCH_C2_W_ENABLE, QCH_CON_MCSC_QCH_C2_W_CLOCK_REQ, QCH_CON_MCSC_QCH_C2_W_EXPIRE_VAL, QCH_CON_MCSC_QCH_C2_W_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_QCH_C2_R, QCH_CON_MCSC_QCH_C2_R_ENABLE, QCH_CON_MCSC_QCH_C2_R_CLOCK_REQ, QCH_CON_MCSC_QCH_C2_R_EXPIRE_VAL, QCH_CON_MCSC_QCH_C2_R_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_CMU_MCSC_QCH, QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_MCSC_QCH, QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_MCSC_QCH, QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D2_MCSC_QCH, QCH_CON_PPMU_D2_MCSC_QCH_ENABLE, QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCSC_QCH_S1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCSC_QCH_S2, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCSC_QCH_S1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCSC_QCH_S2, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_MCSC_QCH_S1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_MCSC_QCH_S2, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MCSC_QCH, QCH_CON_SYSREG_MCSC_QCH_ENABLE, QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D0_MCSC_QCH, QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D1_MCSC_QCH, QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MFC0_QCH, QCH_CON_D_TZPC_MFC0_QCH_ENABLE, QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_MFC1MFC0_QCH, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_MFC1MFC0_QCH, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_MFC1MFC0_QCH, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_MFC1MFC0_QCH, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MFC0_QCH, QCH_CON_LHM_AXI_P_MFC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_MFC0MFC1_QCH, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_MFC0MFC1_QCH, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_MFC0MFC1_QCH, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_MFC0MFC1_QCH, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MFC0_QCH, QCH_CON_LHS_AXI_D0_MFC0_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MFC0_QCH, QCH_CON_LHS_AXI_D1_MFC0_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_MFC0_QCH_MI, QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE, QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ, QCH_CON_LH_ATB_MFC0_QCH_MI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_MFC0_QCH_SI, QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE, QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ, QCH_CON_LH_ATB_MFC0_QCH_SI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC0_QCH, QCH_CON_MFC0_QCH_ENABLE, QCH_CON_MFC0_QCH_CLOCK_REQ, QCH_CON_MFC0_QCH_EXPIRE_VAL, QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC0_QCH_VOTF, QCH_CON_MFC0_QCH_VOTF_ENABLE, QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ, QCH_CON_MFC0_QCH_VOTF_EXPIRE_VAL, QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC0_CMU_MFC0_QCH, QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE, QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ, QCH_CON_MFC0_CMU_MFC0_QCH_EXPIRE_VAL, QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFC0D0_QCH, QCH_CON_PPMU_MFC0D0_QCH_ENABLE, QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC0D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFC0D1_QCH, QCH_CON_PPMU_MFC0D1_QCH_ENABLE, QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC0D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_WFD_QCH, QCH_CON_PPMU_WFD_QCH_ENABLE, QCH_CON_PPMU_WFD_QCH_CLOCK_REQ, QCH_CON_PPMU_WFD_QCH_EXPIRE_VAL, QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC0D0_QCH_S1, QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC0D0_QCH_S2, QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC0D1_QCH_S1, QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC0D1_QCH_S2, QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MFC0_QCH, QCH_CON_SYSREG_MFC0_QCH_ENABLE, QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_MFC0_QCH, QCH_CON_VGEN_MFC0_QCH_ENABLE, QCH_CON_VGEN_MFC0_QCH_CLOCK_REQ, QCH_CON_VGEN_MFC0_QCH_EXPIRE_VAL, QCH_CON_VGEN_MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WFD_QCH, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_EXPIRE_VAL, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_APB_MFC0MFC1_QCH, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MFC1_QCH, QCH_CON_D_TZPC_MFC1_QCH_ENABLE, QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_MFC0MFC1_QCH, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_MFC0MFC1_QCH, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_MFC0MFC1_QCH, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_MFC0MFC1_QCH, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MFC1_QCH, QCH_CON_LHM_AXI_P_MFC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF0_MFC1MFC0_QCH, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_ENABLE, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF1_MFC1MFC0_QCH, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_ENABLE, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF2_MFC1MFC0_QCH, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_ENABLE, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF3_MFC1MFC0_QCH, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_ENABLE, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MFC1_QCH, QCH_CON_LHS_AXI_D0_MFC1_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MFC1_QCH, QCH_CON_LHS_AXI_D1_MFC1_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC1_QCH, QCH_CON_MFC1_QCH_ENABLE, QCH_CON_MFC1_QCH_CLOCK_REQ, QCH_CON_MFC1_QCH_EXPIRE_VAL, QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC1_CMU_MFC1_QCH, QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE, QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ, QCH_CON_MFC1_CMU_MFC1_QCH_EXPIRE_VAL, QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFC1D0_QCH, QCH_CON_PPMU_MFC1D0_QCH_ENABLE, QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC1D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFC1D1_QCH, QCH_CON_PPMU_MFC1D1_QCH_ENABLE, QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC1D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC1D0_QCH_S2, QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC1D0_QCH_S1, QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC1D1_QCH_S2, QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC1D1_QCH_S1, QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MFC1_QCH, QCH_CON_SYSREG_MFC1_QCH_ENABLE, QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_MFC1_QCH, QCH_CON_VGEN_MFC1_QCH_ENABLE, QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ, QCH_CON_VGEN_MFC1_QCH_EXPIRE_VAL, QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBBR_DDRPHY_QCH, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBBR_DMC_QCH, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MIF_QCH, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MIF_QCH, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QCH_ADAPTER_PPC_DEBUG_QCH, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPU_QCH, QCH_CON_D_TZPC_NPU_QCH_ENABLE, QCH_CON_D_TZPC_NPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUCORE_QCH_PCLK, QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUCORE_QCH_ACLK, QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_NPU_QCH, QCH_CON_LHM_AXI_D0_NPU_QCH_ENABLE, QCH_CON_LHM_AXI_D0_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_NPU_QCH, QCH_CON_LHM_AXI_D1_NPU_QCH_ENABLE, QCH_CON_LHM_AXI_D1_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CTRL_NPU_QCH, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_ENABLE, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_NPU_QCH, QCH_CON_LHM_AXI_P_NPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CMDQ_NPU_QCH, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_ENABLE, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_RQ_NPU_QCH, QCH_CON_LHS_AXI_D_RQ_NPU_QCH_ENABLE, QCH_CON_LHS_AXI_D_RQ_NPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_RQ_NPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_RQ_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPU_CMU_NPU_QCH, QCH_CON_NPU_CMU_NPU_QCH_ENABLE, QCH_CON_NPU_CMU_NPU_QCH_CLOCK_REQ, QCH_CON_NPU_CMU_NPU_QCH_EXPIRE_VAL, QCH_CON_NPU_CMU_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPU_QCH, QCH_CON_SYSREG_NPU_QCH_ENABLE, QCH_CON_SYSREG_NPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPU01_QCH, QCH_CON_D_TZPC_NPU01_QCH_ENABLE, QCH_CON_D_TZPC_NPU01_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU01_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPU01CORE_QCH_PCLK, QCH_CON_IP_NPU01CORE_QCH_PCLK_ENABLE, QCH_CON_IP_NPU01CORE_QCH_PCLK_CLOCK_REQ, QCH_CON_IP_NPU01CORE_QCH_PCLK_EXPIRE_VAL, QCH_CON_IP_NPU01CORE_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPU01CORE_QCH_ACLK, QCH_CON_IP_NPU01CORE_QCH_ACLK_ENABLE, QCH_CON_IP_NPU01CORE_QCH_ACLK_CLOCK_REQ, QCH_CON_IP_NPU01CORE_QCH_ACLK_EXPIRE_VAL, QCH_CON_IP_NPU01CORE_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_NPU01_QCH, QCH_CON_LHM_AXI_D0_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_D0_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_NPU01_QCH, QCH_CON_LHM_AXI_D1_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_D1_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CTRL_NPU01_QCH, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_NPU01_QCH, QCH_CON_LHM_AXI_P_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CMDQ_NPU01_QCH, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_RQ_NPU01_QCH, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPU01_CMU_NPU_QCH, QCH_CON_NPU01_CMU_NPU_QCH_ENABLE, QCH_CON_NPU01_CMU_NPU_QCH_CLOCK_REQ, QCH_CON_NPU01_CMU_NPU_QCH_EXPIRE_VAL, QCH_CON_NPU01_CMU_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPU01_QCH, QCH_CON_SYSREG_NPU01_QCH_ENABLE, QCH_CON_SYSREG_NPU01_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU01_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPU10_QCH, QCH_CON_D_TZPC_NPU10_QCH_ENABLE, QCH_CON_D_TZPC_NPU10_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU10_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPU10CORE_QCH_PCLK, QCH_CON_IP_NPU10CORE_QCH_PCLK_ENABLE, QCH_CON_IP_NPU10CORE_QCH_PCLK_CLOCK_REQ, QCH_CON_IP_NPU10CORE_QCH_PCLK_EXPIRE_VAL, QCH_CON_IP_NPU10CORE_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPU10CORE_QCH_ACLK, QCH_CON_IP_NPU10CORE_QCH_ACLK_ENABLE, QCH_CON_IP_NPU10CORE_QCH_ACLK_CLOCK_REQ, QCH_CON_IP_NPU10CORE_QCH_ACLK_EXPIRE_VAL, QCH_CON_IP_NPU10CORE_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_NPU10_QCH, QCH_CON_LHM_AXI_D0_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_D0_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_NPU10_QCH, QCH_CON_LHM_AXI_D1_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_D1_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CTRL_NPU10_QCH, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_NPU10_QCH, QCH_CON_LHM_AXI_P_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CMDQ_NPU10_QCH, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_RQ_NPU10_QCH, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPU10_CMU_NPU_QCH, QCH_CON_NPU10_CMU_NPU_QCH_ENABLE, QCH_CON_NPU10_CMU_NPU_QCH_CLOCK_REQ, QCH_CON_NPU10_CMU_NPU_QCH_EXPIRE_VAL, QCH_CON_NPU10_CMU_NPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPU10_QCH, QCH_CON_SYSREG_NPU10_QCH_ENABLE, QCH_CON_SYSREG_NPU10_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU10_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_NPUS_QCH, DMYQCH_CON_ADD_NPUS_QCH_ENABLE, DMYQCH_CON_ADD_NPUS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_DAP_NPUS_QCH, DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE, DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_NPUS_QCH, QCH_CON_BUSIF_ADD_NPUS_QCH_ENABLE, QCH_CON_BUSIF_ADD_NPUS_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_NPUS_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_NPUS_QCH, QCH_CON_BUSIF_HPM_NPUS_QCH_ENABLE, QCH_CON_BUSIF_HPM_NPUS_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_NPUS_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPUS_QCH, QCH_CON_D_TZPC_NPUS_QCH_ENABLE, QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_NPUS_QCH_PCLK, QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE, QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_NPUS_QCH_CLK, QCH_CON_HTU_NPUS_QCH_CLK_ENABLE, QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH, QCH_CON_IP_NPUS_QCH_ENABLE, QCH_CON_IP_NPUS_QCH_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_C2A0, QCH_CON_IP_NPUS_QCH_C2A0_ENABLE, QCH_CON_IP_NPUS_QCH_C2A0_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A0_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_C2A1, QCH_CON_IP_NPUS_QCH_C2A1_ENABLE, QCH_CON_IP_NPUS_QCH_C2A1_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A1_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_CPU, QCH_CON_IP_NPUS_QCH_CPU_ENABLE, QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_NEON, QCH_CON_IP_NPUS_QCH_NEON_ENABLE, QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CMDQ_NPU00_QCH, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_ENABLE, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CMDQ_NPU01_QCH, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CMDQ_NPU10_QCH, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_RQ_NPU00_QCH, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_ENABLE, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_RQ_NPU01_QCH, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_ENABLE, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_RQ_NPU10_QCH, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_ENABLE, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_INT_NPUS_QCH, QCH_CON_LHM_AXI_P_INT_NPUS_QCH_ENABLE, QCH_CON_LHM_AXI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_NPUS_QCH, QCH_CON_LHM_AXI_P_NPUS_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_NPU00_QCH, QCH_CON_LHS_AXI_D0_NPU00_QCH_ENABLE, QCH_CON_LHS_AXI_D0_NPU00_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_NPU01_QCH, QCH_CON_LHS_AXI_D0_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_D0_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_NPU10_QCH, QCH_CON_LHS_AXI_D0_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_D0_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_NPUS_QCH, QCH_CON_LHS_AXI_D0_NPUS_QCH_ENABLE, QCH_CON_LHS_AXI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_NPU00_QCH, QCH_CON_LHS_AXI_D1_NPU00_QCH_ENABLE, QCH_CON_LHS_AXI_D1_NPU00_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_NPU01_QCH, QCH_CON_LHS_AXI_D1_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_D1_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_NPU10_QCH, QCH_CON_LHS_AXI_D1_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_D1_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_NPUS_QCH, QCH_CON_LHS_AXI_D1_NPUS_QCH_ENABLE, QCH_CON_LHS_AXI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D2_NPUS_QCH, QCH_CON_LHS_AXI_D2_NPUS_QCH_ENABLE, QCH_CON_LHS_AXI_D2_NPUS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CTRL_NPU00_QCH, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_ENABLE, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CTRL_NPU01_QCH, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_ENABLE, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CTRL_NPU10_QCH, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_ENABLE, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_INT_NPUS_QCH, QCH_CON_LHS_AXI_P_INT_NPUS_QCH_ENABLE, QCH_CON_LHS_AXI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPUS_CMU_NPUS_QCH, QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE, QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ, QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL, QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_NPUS_0_QCH, QCH_CON_PPMU_NPUS_0_QCH_ENABLE, QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_NPUS_1_QCH, QCH_CON_PPMU_NPUS_1_QCH_ENABLE, QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_NPUS_2_QCH, QCH_CON_PPMU_NPUS_2_QCH_ENABLE, QCH_CON_PPMU_NPUS_2_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_2_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_NPUS_QCH_S2, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_NPUS_QCH_S1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_NPUS_QCH_S2, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_NPUS_QCH_S1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_NPUS_QCH_S2, QCH_CON_SYSMMU_D2_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_NPUS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_NPUS_QCH_S1, QCH_CON_SYSMMU_D2_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_NPUS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPUS_QCH, QCH_CON_SYSREG_NPUS_QCH_ENABLE, QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_NPUS_QCH, QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE, QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_PERIC0_QCH, QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_PERIC0_QCH, QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_UART_DBG, QCH_CON_PERIC0_TOP0_QCH_UART_DBG_ENABLE, QCH_CON_PERIC0_TOP0_QCH_UART_DBG_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_UART_DBG_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_UART_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI00_USI, QCH_CON_PERIC0_TOP0_QCH_USI00_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI00_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI00_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI00_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI00_I2C, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI01_USI, QCH_CON_PERIC0_TOP0_QCH_USI01_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI01_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI01_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI01_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI01_I2C, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI02_USI, QCH_CON_PERIC0_TOP0_QCH_USI02_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI02_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI02_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI02_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI02_I2C, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI03_USI, QCH_CON_PERIC0_TOP0_QCH_USI03_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI03_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI03_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI03_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI03_I2C, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI04_USI, QCH_CON_PERIC0_TOP0_QCH_USI04_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI04_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI04_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI04_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI04_I2C, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP0_QCH_USI05_USI, QCH_CON_PERIC0_TOP0_QCH_USI05_USI_ENABLE, QCH_CON_PERIC0_TOP0_QCH_USI05_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP0_QCH_USI05_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP0_QCH_USI05_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI05_I2C, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI13_USI, QCH_CON_PERIC0_TOP1_QCH_USI13_USI_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI13_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI13_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI13_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI13_I2C, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI14_USI, QCH_CON_PERIC0_TOP1_QCH_USI14_USI_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI14_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI14_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI14_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI14_I2C, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI15_USI, QCH_CON_PERIC0_TOP1_QCH_USI15_USI_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI15_USI_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI15_USI_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI15_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_USI15_I2C, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_ENABLE, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC0_TOP1_QCH_PWM, QCH_CON_PERIC0_TOP1_QCH_PWM_ENABLE, QCH_CON_PERIC0_TOP1_QCH_PWM_CLOCK_REQ, QCH_CON_PERIC0_TOP1_QCH_PWM_EXPIRE_VAL, QCH_CON_PERIC0_TOP1_QCH_PWM_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_PERIC1_QCH, QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CSISPERIC1_QCH, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_PERIC1_QCH, QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP0_QCH_UART_BT, QCH_CON_PERIC1_TOP0_QCH_UART_BT_ENABLE, QCH_CON_PERIC1_TOP0_QCH_UART_BT_CLOCK_REQ, QCH_CON_PERIC1_TOP0_QCH_UART_BT_EXPIRE_VAL, QCH_CON_PERIC1_TOP0_QCH_UART_BT_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI11_USI, QCH_CON_PERIC1_TOP1_QCH_USI11_USI_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI11_USI_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI11_USI_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI11_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI11_I2C, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI16_USI, QCH_CON_PERIC1_TOP1_QCH_USI16_USI_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI16_USI_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI16_USI_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI16_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI16_I2C, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI17_USI, QCH_CON_PERIC1_TOP1_QCH_USI17_USI_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI17_USI_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI17_USI_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI17_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI17_I2C, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI12_USI, QCH_CON_PERIC1_TOP1_QCH_USI12_USI_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI12_USI_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI12_USI_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI12_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI12_I2C, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI18_USI, QCH_CON_PERIC1_TOP1_QCH_USI18_USI_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI18_USI_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI18_USI_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI18_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC1_TOP1_QCH_USI18_I2C, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_ENABLE, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_CLOCK_REQ, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_EXPIRE_VAL, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI16_I3C_QCH_P, QCH_CON_USI16_I3C_QCH_P_ENABLE, QCH_CON_USI16_I3C_QCH_P_CLOCK_REQ, QCH_CON_USI16_I3C_QCH_P_EXPIRE_VAL, QCH_CON_USI16_I3C_QCH_P_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI16_I3C_QCH_S, DMYQCH_CON_USI16_I3C_QCH_S_ENABLE, DMYQCH_CON_USI16_I3C_QCH_S_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USI16_I3C_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI17_I3C_QCH_P, QCH_CON_USI17_I3C_QCH_P_ENABLE, QCH_CON_USI17_I3C_QCH_P_CLOCK_REQ, QCH_CON_USI17_I3C_QCH_P_EXPIRE_VAL, QCH_CON_USI17_I3C_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI17_I3C_QCH_S, DMYQCH_CON_USI17_I3C_QCH_S_ENABLE, DMYQCH_CON_USI17_I3C_QCH_S_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USI17_I3C_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_PERIC2_QCH, QCH_CON_D_TZPC_PERIC2_QCH_ENABLE, QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC2_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERIC2_QCH, QCH_CON_GPIO_PERIC2_QCH_ENABLE, QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC2_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(LHM_AXI_P_PERIC2_QCH, QCH_CON_LHM_AXI_P_PERIC2_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC2_CMU_PERIC2_QCH, QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE, QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ, QCH_CON_PERIC2_CMU_PERIC2_QCH_EXPIRE_VAL, QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC2_TOP0_QCH_USI06_USI, QCH_CON_PERIC2_TOP0_QCH_USI06_USI_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI06_USI_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI06_USI_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI06_USI_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC2_TOP0_QCH_USI07_USI, QCH_CON_PERIC2_TOP0_QCH_USI07_USI_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI07_USI_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI07_USI_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI07_USI_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC2_TOP0_QCH_USI08_USI, QCH_CON_PERIC2_TOP0_QCH_USI08_USI_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI08_USI_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI08_USI_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI08_USI_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC2_TOP0_QCH_USI08_I2C, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP0_QCH_USI06_I2C, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP0_QCH_USI07_I2C, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_ENABLE, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_CLOCK_REQ, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_EXPIRE_VAL, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP1_QCH_USI09_USI, QCH_CON_PERIC2_TOP1_QCH_USI09_USI_ENABLE, QCH_CON_PERIC2_TOP1_QCH_USI09_USI_CLOCK_REQ, QCH_CON_PERIC2_TOP1_QCH_USI09_USI_EXPIRE_VAL, QCH_CON_PERIC2_TOP1_QCH_USI09_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP1_QCH_USI09_I2C, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_ENABLE, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_CLOCK_REQ, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_EXPIRE_VAL, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP1_QCH_USI10_USI, QCH_CON_PERIC2_TOP1_QCH_USI10_USI_ENABLE, QCH_CON_PERIC2_TOP1_QCH_USI10_USI_CLOCK_REQ, QCH_CON_PERIC2_TOP1_QCH_USI10_USI_EXPIRE_VAL, QCH_CON_PERIC2_TOP1_QCH_USI10_USI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIC2_TOP1_QCH_USI10_I2C, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_ENABLE, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_CLOCK_REQ, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_EXPIRE_VAL, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERIC2_QCH, QCH_CON_SYSREG_PERIC2_QCH_ENABLE, QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BC_EMUL_QCH, QCH_CON_BC_EMUL_QCH_ENABLE, QCH_CON_BC_EMUL_QCH_CLOCK_REQ, QCH_CON_BC_EMUL_QCH_EXPIRE_VAL, QCH_CON_BC_EMUL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_PERIS_QCH, QCH_CON_D_TZPC_PERIS_QCH_ENABLE, QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_ICC_CPUGIC_CLUSTER0_QCH, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_PERIS_QCH, QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_PERISGIC_QCH, QCH_CON_LHM_AXI_P_PERISGIC_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERISGIC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERISGIC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_IRI_GICCPU_CLUSTER0_QCH, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_BISR_QCH, QCH_CON_OTP_CON_BISR_QCH_ENABLE, QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERIS_CMU_PERIS_QCH, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TMU_SUB_QCH, QCH_CON_TMU_SUB_QCH_ENABLE, QCH_CON_TMU_SUB_QCH_CLOCK_REQ, QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TMU_TOP_QCH, QCH_CON_TMU_TOP_QCH_ENABLE, QCH_CON_TMU_TOP_QCH_CLOCK_REQ, QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT0_QCH, QCH_CON_WDT0_QCH_ENABLE, QCH_CON_WDT0_QCH_CLOCK_REQ, QCH_CON_WDT0_QCH_EXPIRE_VAL, QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT1_QCH, QCH_CON_WDT1_QCH_ENABLE, QCH_CON_WDT1_QCH_CLOCK_REQ, QCH_CON_WDT1_QCH_EXPIRE_VAL, QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BIS_S2D_QCH, DMYQCH_CON_BIS_S2D_QCH_ENABLE, DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_SCAN2DRAM_QCH, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_DAP_SSS_QCH, DMYQCH_CON_ADM_DAP_SSS_QCH_ENABLE, DMYQCH_CON_ADM_DAP_SSS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_SSS_QCH, QCH_CON_BAAW_SSS_QCH_ENABLE, QCH_CON_BAAW_SSS_QCH_CLOCK_REQ, QCH_CON_BAAW_SSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_SSP_QCH, QCH_CON_D_TZPC_SSP_QCH_ENABLE, QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_SSP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_SSPCORE_QCH, QCH_CON_LHM_AXI_D_SSPCORE_QCH_ENABLE, QCH_CON_LHM_AXI_D_SSPCORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SSPCORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_SSPCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_SSP_QCH, QCH_CON_LHM_AXI_P_SSP_QCH_ENABLE, QCH_CON_LHM_AXI_P_SSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SSP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_SSP_QCH, QCH_CON_LHS_ACEL_D_SSP_QCH_ENABLE, QCH_CON_LHS_ACEL_D_SSP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_SSP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_SSP_QCH, QCH_CON_PPMU_SSP_QCH_ENABLE, QCH_CON_PPMU_SSP_QCH_CLOCK_REQ, QCH_CON_PPMU_SSP_QCH_EXPIRE_VAL, QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_RTIC_QCH, QCH_CON_QE_RTIC_QCH_ENABLE, QCH_CON_QE_RTIC_QCH_CLOCK_REQ, QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_SSPCORE_QCH, QCH_CON_QE_SSPCORE_QCH_ENABLE, QCH_CON_QE_SSPCORE_QCH_CLOCK_REQ, QCH_CON_QE_SSPCORE_QCH_EXPIRE_VAL, QCH_CON_QE_SSPCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_SSS_QCH, QCH_CON_QE_SSS_QCH_ENABLE, QCH_CON_QE_SSS_QCH_CLOCK_REQ, QCH_CON_QE_SSS_QCH_EXPIRE_VAL, QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SSP_CMU_SSP_QCH, QCH_CON_SSP_CMU_SSP_QCH_ENABLE, QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ, QCH_CON_SSP_CMU_SSP_QCH_EXPIRE_VAL, QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_D_SSP_QCH, QCH_CON_SWEEPER_D_SSP_QCH_ENABLE, QCH_CON_SWEEPER_D_SSP_QCH_CLOCK_REQ, QCH_CON_SWEEPER_D_SSP_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_D_SSP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_RTIC_QCH, QCH_CON_SYSMMU_RTIC_QCH_ENABLE, QCH_CON_SYSMMU_RTIC_QCH_CLOCK_REQ, QCH_CON_SYSMMU_RTIC_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_SSPCTRL_QCH, QCH_CON_SYSREG_SSPCTRL_QCH_ENABLE, QCH_CON_SYSREG_SSPCTRL_QCH_CLOCK_REQ, QCH_CON_SYSREG_SSPCTRL_QCH_EXPIRE_VAL, QCH_CON_SYSREG_SSPCTRL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_RTIC_QCH, QCH_CON_VGEN_LITE_RTIC_QCH_ENABLE, QCH_CON_VGEN_LITE_RTIC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_RTIC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USS_SSPCORE_QCH, QCH_CON_USS_SSPCORE_QCH_ENABLE, QCH_CON_USS_SSPCORE_QCH_CLOCK_REQ, QCH_CON_USS_SSPCORE_QCH_EXPIRE_VAL, QCH_CON_USS_SSPCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_TAA_QCH, DMYQCH_CON_ADD_TAA_QCH_ENABLE, DMYQCH_CON_ADD_TAA_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_TAA_QCH, QCH_CON_BUSIF_ADD_TAA_QCH_ENABLE, QCH_CON_BUSIF_ADD_TAA_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_TAA_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_TAA_QCH, QCH_CON_BUSIF_HPM_TAA_QCH_ENABLE, QCH_CON_BUSIF_HPM_TAA_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_TAA_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_TAA_QCH, QCH_CON_D_TZPC_TAA_QCH_ENABLE, QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF0_CSISTAA_QCH, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF1_CSISTAA_QCH, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF2_CSISTAA_QCH, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_OTF3_CSISTAA_QCH, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_ENABLE, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AST_VO_MCFP1TAA_QCH, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_ENABLE, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_CLOCK_REQ, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_TAA_QCH, QCH_CON_LHM_AXI_P_TAA_QCH_ENABLE, QCH_CON_LHM_AXI_P_TAA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF_TAADNS_QCH, QCH_CON_LHS_AST_OTF_TAADNS_QCH_ENABLE, QCH_CON_LHS_AST_OTF_TAADNS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF_TAADNS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_SOTF0_TAACSIS_QCH, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_SOTF1_TAACSIS_QCH, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_SOTF2_TAACSIS_QCH, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_SOTF3_TAACSIS_QCH, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_VO_TAAMCFP1_QCH, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_ENABLE, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_ZOTF0_TAACSIS_QCH, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_ZOTF1_TAACSIS_QCH, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_ZOTF2_TAACSIS_QCH, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_ZOTF3_TAACSIS_QCH, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_ENABLE, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_TAA_QCH, QCH_CON_LHS_AXI_D_TAA_QCH_ENABLE, QCH_CON_LHS_AXI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_TAA_QCH, QCH_CON_PPMU_TAA_QCH_ENABLE, QCH_CON_PPMU_TAA_QCH_CLOCK_REQ, QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL, QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH, QCH_CON_SIPU_TAA_QCH_ENABLE, QCH_CON_SIPU_TAA_QCH_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH_C2_STAT, QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH_C2_YDS, QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_TAA_QCH_S1, QCH_CON_SYSMMU_D_TAA_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_TAA_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_TAA_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_TAA_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_TAA_QCH_S2, QCH_CON_SYSMMU_D_TAA_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_TAA_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_TAA_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_TAA_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_TAA_QCH, QCH_CON_SYSREG_TAA_QCH_ENABLE, QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ, QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TAA_CMU_TAA_QCH, QCH_CON_TAA_CMU_TAA_QCH_ENABLE, QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ, QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL, QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_TAA0_QCH, QCH_CON_VGEN_LITE_TAA0_QCH_ENABLE, QCH_CON_VGEN_LITE_TAA0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_TAA0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_TAA0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_TAA1_QCH, QCH_CON_VGEN_LITE_TAA1_QCH_ENABLE, QCH_CON_VGEN_LITE_TAA1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_TAA1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_TAA1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADD_VPC_QCH, DMYQCH_CON_ADD_VPC_QCH_ENABLE, DMYQCH_CON_ADD_VPC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_DAP_VPC_QCH, DMYQCH_CON_ADM_DAP_VPC_QCH_ENABLE, DMYQCH_CON_ADM_DAP_VPC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_ADD_VPC_QCH, QCH_CON_BUSIF_ADD_VPC_QCH_ENABLE, QCH_CON_BUSIF_ADD_VPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_VPC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_ADD_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_VPC_QCH, QCH_CON_BUSIF_HPM_VPC_QCH_ENABLE, QCH_CON_BUSIF_HPM_VPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_VPC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_VPC_QCH, QCH_CON_D_TZPC_VPC_QCH_ENABLE, QCH_CON_D_TZPC_VPC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_VPC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_VPC_QCH_PCLK, QCH_CON_HTU_VPC_QCH_PCLK_ENABLE, QCH_CON_HTU_VPC_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_VPC_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_VPC_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_VPC_QCH_CLK, QCH_CON_HTU_VPC_QCH_CLK_ENABLE, QCH_CON_HTU_VPC_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_VPC_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_VPC_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_VPC_QCH, QCH_CON_IP_VPC_QCH_ENABLE, QCH_CON_IP_VPC_QCH_CLOCK_REQ, QCH_CON_IP_VPC_QCH_EXPIRE_VAL, QCH_CON_IP_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPD0VPC_CACHE_QCH, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPD0VPC_SFR_QCH, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPD1VPC_CACHE_QCH, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPD1VPC_SFR_QCH, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VPC_QCH, QCH_CON_LHM_AXI_P_VPC_QCH_ENABLE, QCH_CON_LHM_AXI_P_VPC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VPC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VPC_800_QCH, QCH_CON_LHM_AXI_P_VPC_800_QCH_ENABLE, QCH_CON_LHM_AXI_P_VPC_800_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VPC_800_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VPC_800_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_VPC_QCH, QCH_CON_LHS_ACEL_D0_VPC_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_VPC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_VPC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D1_VPC_QCH, QCH_CON_LHS_ACEL_D1_VPC_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_VPC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_VPC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D2_VPC_QCH, QCH_CON_LHS_ACEL_D2_VPC_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_VPC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_VPC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPCVPD0_DMA_QCH, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPCVPD0_SFR_QCH, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPCVPD1_DMA_QCH, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPCVPD1_SFR_QCH, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VPCVPD0_QCH, QCH_CON_LHS_AXI_P_VPCVPD0_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPCVPD0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPCVPD0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VPCVPD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VPCVPD1_QCH, QCH_CON_LHS_AXI_P_VPCVPD1_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPCVPD1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPCVPD1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VPCVPD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VPC_200_QCH, QCH_CON_LHS_AXI_P_VPC_200_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPC_200_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPC_200_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VPC_200_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_VPC0_QCH, QCH_CON_PPMU_VPC0_QCH_ENABLE, QCH_CON_PPMU_VPC0_QCH_CLOCK_REQ, QCH_CON_PPMU_VPC0_QCH_EXPIRE_VAL, QCH_CON_PPMU_VPC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_VPC1_QCH, QCH_CON_PPMU_VPC1_QCH_ENABLE, QCH_CON_PPMU_VPC1_QCH_CLOCK_REQ, QCH_CON_PPMU_VPC1_QCH_EXPIRE_VAL, QCH_CON_PPMU_VPC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_VPC2_QCH, QCH_CON_PPMU_VPC2_QCH_ENABLE, QCH_CON_PPMU_VPC2_QCH_CLOCK_REQ, QCH_CON_PPMU_VPC2_QCH_EXPIRE_VAL, QCH_CON_PPMU_VPC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC0_QCH_S1, QCH_CON_SYSMMU_VPC0_QCH_S1_ENABLE, QCH_CON_SYSMMU_VPC0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_VPC0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_VPC0_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC0_QCH_S2, QCH_CON_SYSMMU_VPC0_QCH_S2_ENABLE, QCH_CON_SYSMMU_VPC0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_VPC0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_VPC0_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC1_QCH_S1, QCH_CON_SYSMMU_VPC1_QCH_S1_ENABLE, QCH_CON_SYSMMU_VPC1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_VPC1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_VPC1_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC1_QCH_S2, QCH_CON_SYSMMU_VPC1_QCH_S2_ENABLE, QCH_CON_SYSMMU_VPC1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_VPC1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_VPC1_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC2_QCH_S1, QCH_CON_SYSMMU_VPC2_QCH_S1_ENABLE, QCH_CON_SYSMMU_VPC2_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_VPC2_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_VPC2_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_VPC2_QCH_S2, QCH_CON_SYSMMU_VPC2_QCH_S2_ENABLE, QCH_CON_SYSMMU_VPC2_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_VPC2_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_VPC2_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VPC_QCH, QCH_CON_SYSREG_VPC_QCH_ENABLE, QCH_CON_SYSREG_VPC_QCH_CLOCK_REQ, QCH_CON_SYSREG_VPC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_VPC_QCH, QCH_CON_VGEN_LITE_VPC_QCH_ENABLE, QCH_CON_VGEN_LITE_VPC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_VPC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VPC_CMU_VPC_QCH, QCH_CON_VPC_CMU_VPC_QCH_ENABLE, QCH_CON_VPC_CMU_VPC_QCH_CLOCK_REQ, QCH_CON_VPC_CMU_VPC_QCH_EXPIRE_VAL, QCH_CON_VPC_CMU_VPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_VPD_QCH, QCH_CON_D_TZPC_VPD_QCH_ENABLE, QCH_CON_D_TZPC_VPD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_VPD_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_VPD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_VPD_QCH, QCH_CON_IP_VPD_QCH_ENABLE, QCH_CON_IP_VPD_QCH_CLOCK_REQ, QCH_CON_IP_VPD_QCH_EXPIRE_VAL, QCH_CON_IP_VPD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPCVPD_DMA_QCH, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_VPCVPD_SFR_QCH, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VPCVPD_QCH, QCH_CON_LHM_AXI_P_VPCVPD_QCH_ENABLE, QCH_CON_LHM_AXI_P_VPCVPD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VPCVPD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VPCVPD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPDVPC_CACHE_QCH, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VPDVPC_SFR_QCH, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VPD_QCH, QCH_CON_SYSREG_VPD_QCH_ENABLE, QCH_CON_SYSREG_VPD_QCH_CLOCK_REQ, QCH_CON_SYSREG_VPD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VPD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VPD_CMU_VPD_QCH, QCH_CON_VPD_CMU_VPD_QCH_ENABLE, QCH_CON_VPD_CMU_VPD_QCH_CLOCK_REQ, QCH_CON_VPD_CMU_VPD_QCH_EXPIRE_VAL, QCH_CON_VPD_CMU_VPD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_C_VTS_QCH, QCH_CON_BAAW_C_VTS_QCH_ENABLE, QCH_CON_BAAW_C_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_C_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_C_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_D_VTS_QCH, QCH_CON_BAAW_D_VTS_QCH_ENABLE, QCH_CON_BAAW_D_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPM_VTS_QCH, QCH_CON_BUSIF_HPM_VTS_QCH_ENABLE, QCH_CON_BUSIF_HPM_VTS_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPM_VTS_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPM_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CORTEXM4INTEGRATION_QCH_CPU, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMAILBOX_TEST_QCH_ACLK, QCH_CON_DMAILBOX_TEST_QCH_ACLK_ENABLE, QCH_CON_DMAILBOX_TEST_QCH_ACLK_CLOCK_REQ, QCH_CON_DMAILBOX_TEST_QCH_ACLK_EXPIRE_VAL, QCH_CON_DMAILBOX_TEST_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMAILBOX_TEST_QCH_PCLK, QCH_CON_DMAILBOX_TEST_QCH_PCLK_ENABLE, QCH_CON_DMAILBOX_TEST_QCH_PCLK_CLOCK_REQ, QCH_CON_DMAILBOX_TEST_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMAILBOX_TEST_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMAILBOX_TEST_QCH_LIF, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_ENABLE, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB0_QCH_PCLK, QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB1_QCH_PCLK, QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB2_QCH_PCLK, QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB3_QCH_PCLK, QCH_CON_DMIC_AHB3_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB3_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB3_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB3_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB4_QCH_PCLK, QCH_CON_DMIC_AHB4_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB4_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB4_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB4_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB5_QCH_PCLK, QCH_CON_DMIC_AHB5_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB5_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB5_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB5_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD0_QCH_PCLK, QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD0_QCH_DMIC, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD1_QCH_PCLK, QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD1_QCH_DMIC, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD2_QCH_PCLK, QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD2_QCH_DMIC, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF0_QCH_PCLK, QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF0_QCH_DMIC, DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF1_QCH_PCLK, QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF1_QCH_DMIC, DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF2_QCH_PCLK, QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF2_QCH_DMIC, DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_VTS_QCH, QCH_CON_D_TZPC_VTS_QCH_ENABLE, QCH_CON_D_TZPC_VTS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_VTS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC0_QCH, QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC1_QCH, QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC2_QCH, QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC3_QCH, QCH_CON_HWACG_SYS_DMIC3_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC3_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC3_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC4_QCH, QCH_CON_HWACG_SYS_DMIC4_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC4_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC4_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC4_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC5_QCH, QCH_CON_HWACG_SYS_DMIC5_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC5_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC5_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC5_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_SERIAL_LIF_QCH, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_AUDVTS_QCH, QCH_CON_LHM_AXI_D_AUDVTS_QCH_ENABLE, QCH_CON_LHM_AXI_D_AUDVTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_AUDVTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_LP_VTS_QCH, QCH_CON_LHM_AXI_LP_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_LP_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LP_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VTS_QCH, QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_C_VTS_QCH, QCH_CON_LHS_AXI_C_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_C_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_C_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_VTS_QCH, QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_ABOX_VTS_QCH, QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_VTS1_QCH, QCH_CON_MAILBOX_APM_VTS1_QCH_ENABLE, QCH_CON_MAILBOX_APM_VTS1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_VTS1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_VTS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_VTS_QCH, QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_VTS_QCH, QCH_CON_PDMA_VTS_QCH_ENABLE, QCH_CON_PDMA_VTS_QCH_CLOCK_REQ, QCH_CON_PDMA_VTS_QCH_EXPIRE_VAL, QCH_CON_PDMA_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_QCH_PCLK, QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_QCH_PCLK_EXPIRE_VAL, QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_QCH_LIF, DMYQCH_CON_SERIAL_LIF_QCH_LIF_ENABLE, DMYQCH_CON_SERIAL_LIF_QCH_LIF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_QCH_LIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_QCH_HCLK, DMYQCH_CON_SERIAL_LIF_QCH_HCLK_ENABLE, DMYQCH_CON_SERIAL_LIF_QCH_HCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_QCH_HCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_DEBUG_US_QCH_PCLK, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_EXPIRE_VAL, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_DEBUG_US_QCH_LIF, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_ENABLE, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_DEBUG_VT_QCH_PCLK, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_EXPIRE_VAL, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_DEBUG_VT_QCH_LIF, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_ENABLE, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_PAD2, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD2, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_D_VTS_QCH, QCH_CON_SWEEPER_D_VTS_QCH_ENABLE, QCH_CON_SWEEPER_D_VTS_QCH_CLOCK_REQ, QCH_CON_SWEEPER_D_VTS_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_D_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER_QCH, QCH_CON_TIMER_QCH_ENABLE, QCH_CON_TIMER_QCH_CLOCK_REQ, QCH_CON_TIMER_QCH_EXPIRE_VAL, QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER1_QCH, QCH_CON_TIMER1_QCH_ENABLE, QCH_CON_TIMER1_QCH_CLOCK_REQ, QCH_CON_TIMER1_QCH_EXPIRE_VAL, QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER2_QCH, QCH_CON_TIMER2_QCH_ENABLE, QCH_CON_TIMER2_QCH_CLOCK_REQ, QCH_CON_TIMER2_QCH_EXPIRE_VAL, QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_QCH, QCH_CON_VGEN_LITE_QCH_ENABLE, QCH_CON_VGEN_LITE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_YUVPP_QCH, QCH_CON_D_TZPC_YUVPP_QCH_ENABLE, QCH_CON_D_TZPC_YUVPP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_YUVPP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(FRC_MC_QCH, QCH_CON_FRC_MC_QCH_ENABLE, QCH_CON_FRC_MC_QCH_CLOCK_REQ, QCH_CON_FRC_MC_QCH_EXPIRE_VAL, QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_YUVPP_QCH, QCH_CON_LHM_AXI_P_YUVPP_QCH_ENABLE, QCH_CON_LHM_AXI_P_YUVPP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_YUVPP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AST_OTF_YUVPPMCSC_QCH, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_ENABLE, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_YUVPP_QCH, QCH_CON_LHS_AXI_D_YUVPP_QCH_ENABLE, QCH_CON_LHS_AXI_D_YUVPP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_YUVPP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_YUVPPMCSC_QCH, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_ENABLE, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_YUVPP_QCH, QCH_CON_PPMU_YUVPP_QCH_ENABLE, QCH_CON_PPMU_YUVPP_QCH_CLOCK_REQ, QCH_CON_PPMU_YUVPP_QCH_EXPIRE_VAL, QCH_CON_PPMU_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D0_YUVPP_QCH, QCH_CON_QE_D0_YUVPP_QCH_ENABLE, QCH_CON_QE_D0_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D0_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D0_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D10_YUVPP_QCH, QCH_CON_QE_D10_YUVPP_QCH_ENABLE, QCH_CON_QE_D10_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D10_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D10_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D11_YUVPP_QCH, QCH_CON_QE_D11_YUVPP_QCH_ENABLE, QCH_CON_QE_D11_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D11_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D11_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D1_YUVPP_QCH, QCH_CON_QE_D1_YUVPP_QCH_ENABLE, QCH_CON_QE_D1_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D1_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D1_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D2_YUVPP_QCH, QCH_CON_QE_D2_YUVPP_QCH_ENABLE, QCH_CON_QE_D2_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D2_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D2_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D3_YUVPP_QCH, QCH_CON_QE_D3_YUVPP_QCH_ENABLE, QCH_CON_QE_D3_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D3_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D3_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D4_YUVPP_QCH, QCH_CON_QE_D4_YUVPP_QCH_ENABLE, QCH_CON_QE_D4_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D4_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D4_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D5_YUVPP_QCH, QCH_CON_QE_D5_YUVPP_QCH_ENABLE, QCH_CON_QE_D5_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D5_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D5_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D6_YUVPP_QCH, QCH_CON_QE_D6_YUVPP_QCH_ENABLE, QCH_CON_QE_D6_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D6_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D6_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D7_YUVPP_QCH, QCH_CON_QE_D7_YUVPP_QCH_ENABLE, QCH_CON_QE_D7_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D7_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D7_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D8_YUVPP_QCH, QCH_CON_QE_D8_YUVPP_QCH_ENABLE, QCH_CON_QE_D8_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D8_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D8_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_D9_YUVPP_QCH, QCH_CON_QE_D9_YUVPP_QCH_ENABLE, QCH_CON_QE_D9_YUVPP_QCH_CLOCK_REQ, QCH_CON_QE_D9_YUVPP_QCH_EXPIRE_VAL, QCH_CON_QE_D9_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_YUVPP_QCH_S1, QCH_CON_SYSMMU_D_YUVPP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_YUVPP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_YUVPP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_YUVPP_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_YUVPP_QCH_S2, QCH_CON_SYSMMU_D_YUVPP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_YUVPP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_YUVPP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_YUVPP_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_YUVPP_QCH, QCH_CON_SYSREG_YUVPP_QCH_ENABLE, QCH_CON_SYSREG_YUVPP_QCH_CLOCK_REQ, QCH_CON_SYSREG_YUVPP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_YUVPP0_QCH, QCH_CON_VGEN_LITE_YUVPP0_QCH_ENABLE, QCH_CON_VGEN_LITE_YUVPP0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_YUVPP0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_YUVPP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_YUVPP1_QCH, QCH_CON_VGEN_LITE_YUVPP1_QCH_ENABLE, QCH_CON_VGEN_LITE_YUVPP1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_YUVPP1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_YUVPP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_YUVPP2_QCH, QCH_CON_VGEN_LITE_YUVPP2_QCH_ENABLE, QCH_CON_VGEN_LITE_YUVPP2_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_YUVPP2_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_YUVPP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(YUVPP_CMU_YUVPP_QCH, QCH_CON_YUVPP_CMU_YUVPP_QCH_ENABLE, QCH_CON_YUVPP_CMU_YUVPP_QCH_CLOCK_REQ, QCH_CON_YUVPP_CMU_YUVPP_QCH_EXPIRE_VAL, QCH_CON_YUVPP_CMU_YUVPP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(YUVPP_TOP_QCH, QCH_CON_YUVPP_TOP_QCH_ENABLE, QCH_CON_YUVPP_TOP_QCH_CLOCK_REQ, QCH_CON_YUVPP_TOP_QCH_EXPIRE_VAL, QCH_CON_YUVPP_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(YUVPP_TOP_QCH_C2COM, QCH_CON_YUVPP_TOP_QCH_C2COM_ENABLE, QCH_CON_YUVPP_TOP_QCH_C2COM_CLOCK_REQ, QCH_CON_YUVPP_TOP_QCH_C2COM_EXPIRE_VAL, QCH_CON_YUVPP_TOP_QCH_C2COM_IGNORE_FORCE_PM_EN),
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};
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unsigned int cmucal_option_size = 47;
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struct cmucal_option cmucal_option_list[] = {
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CLK_OPTION(CTRL_OPTION_CMU_ALIVE, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_AUD, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_BUS0, BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_BUS1, BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_BUS2, BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CMGP, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TOP, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CORE, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL0_GLB, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL2, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CSIS, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DNS, DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DPUB, DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DPUF0, DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DPUF1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DSU, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_G3D, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_HSI0, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_HSI1, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_ITP, ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_LME, LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_M2M, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MCFP0, MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MCFP1, MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MCSC, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MFC0, MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MFC1, MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPU, NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPU01, NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPU10, NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPUS, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERIC0, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERIC1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERIC2, PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERIS, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_S2D, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_SSP, SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_SSP, SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TAA, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VPC, VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VPD, VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VTS, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_YUVPP, YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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};
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