2482 lines
104 KiB
C
Executable file
2482 lines
104 KiB
C
Executable file
#ifndef __CMUCAL_NODE_H__
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#define __CMUCAL_NODE_H__
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#include "../cmucal.h"
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enum clk_id {
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OSCCLK_RCO_ALIVE = FIXED_RATE_TYPE,
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CLK_RCO_400,
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OSCCLK_ALIVE,
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CLK_RCO_ALIVE,
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CLK_RCO_I3C_PMIC,
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RTCCLK_ALIVE,
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OSCCLK_AUD,
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IOCLK_AUDIOCDCLK0,
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IOCLK_AUDIOCDCLK1,
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IOCLK_AUDIOCDCLK2,
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IOCLK_AUDIOCDCLK3,
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CLKIO_AUD_DSIF,
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IOCLK_AUDIOCDCLK4,
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IOCLK_AUDIOCDCLK5,
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AUDIO_LIF_BCLKI,
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OSCCLK_BUS0,
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OSCCLK_BUS1,
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OSCCLK_BUS2,
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OSCCLK_CMGP,
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OSCCLK_RCO_CMGP,
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OSCCLK_CMU,
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OSCCLK_CORE,
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OSCCLK_CPUCL0,
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STRETCHER_CLK_CPUCL0,
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OSCCLK_CPUCL0_GLB,
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OSCCLK_CPUCL1,
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STRETCHER_CLK_CPUCL1,
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OSCCLK_CPUCL2,
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STRETCHER_CLK_CPUCL2,
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OSCCLK_CSIS,
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OSCCLK_DNS,
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OSCCLK_DPUB,
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OSCCLK_DPUF0,
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OSCCLK_DPUF1,
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OSCCLK_DSU,
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STRETCHER_CLK_DSU,
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OSCCLK_G3D,
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STRETCHER_CLK_G3D,
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OSCCLK_HSI0,
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CLK_USB20PHY,
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OSCCLK_HSI1,
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OSCCLK_ITP,
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OSCCLK_LME,
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OSCCLK_M2M,
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OSCCLK_MCFP0,
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OSCCLK_MCFP1,
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OSCCLK_MCSC,
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OSCCLK_MFC0,
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OSCCLK_MFC1,
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OSCCLK_MIF,
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OSCCLK_NPU,
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OSCCLK_NPUS,
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OSCCLK_PERIC0,
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OSCCLK_PERIC1,
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OSCCLK_PERIC2,
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OSCCLK_PERIS,
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OSCCLK_S2D,
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I_SCLK_S2D,
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OSCCLK_SSP,
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OSCCLK_TAA,
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OSCCLK_VPC,
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OSCCLK_VPD,
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OSCCLK_RCO_VTS,
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CLK_RCO_VTS,
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OSCCLK_YUVPP,
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CP_PCMC_CLK,
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end_of_fixed_rate,
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num_of_fixed_rate = (end_of_fixed_rate - FIXED_RATE_TYPE) & MASK_OF_ID,
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CLKCMU_HSI1_PCIE = FIXED_FACTOR_TYPE,
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CLKCMU_HSI0_USBDP_DEBUG,
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CLK_CPUCL0_ADD_CH_CLK,
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CLK_G3D_ADD_CH_CLK,
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DIV_CLK_HSI0_USB31DRD,
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CLK_MCSC_ADD_CH_CLK,
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DIV_CLK_MIF_BUSD,
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CLK_NPUS_ADD_CH_CLK,
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CLKCMU_OTP,
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CLK_MIF_BUSD_S2D,
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CLK_TAA_ADD_CH_CLK,
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CLK_VPC_ADD_CH_CLK,
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PLL_SHARED0_D2,
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PLL_SHARED1_D2,
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PLL_SHARED2_D2,
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PLL_SHARED3_D2,
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PLL_SHARED4_D2,
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PLL_SHARED_MIF_D2,
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end_of_fixed_factor,
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num_of_fixed_factor = (end_of_fixed_factor - FIXED_FACTOR_TYPE) & MASK_OF_ID,
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PLL_AUD0 = PLL_TYPE,
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PLL_AUD1,
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PLL_G3D,
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PLL_MMC,
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PLL_SHARED0,
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PLL_SHARED1,
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PLL_SHARED2,
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PLL_SHARED3,
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PLL_SHARED4,
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PLL_SHARED_MIF,
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PLL_CPUCL0,
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PLL_CPUCL1,
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PLL_CPUCL2,
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PLL_DSU,
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PLL_MIF_MAIN,
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PLL_MIF_SUB,
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PLL_MIF_S2D,
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end_of_pll,
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num_of_pll = (end_of_pll - PLL_TYPE) & MASK_OF_ID,
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MUX_CLKCMU_CMGP_BUS = MUX_TYPE,
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MUX_CLK_ALIVE_BUS,
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MUX_CLKCMU_VTS_BUS,
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MUX_CLK_ALIVE_I3C_PMIC,
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MUX_CLKCMU_CMGP_PERI,
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MUX_CLKCMU_CMGP_ADC,
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MUX_CLK_AUD_UAIF3,
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MUX_CLK_AUD_UAIF2,
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MUX_CLK_AUD_UAIF1,
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MUX_CLK_AUD_UAIF0,
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MUX_CLK_AUD_CPU,
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MUX_CLK_AUD_DSIF,
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MUX_CLK_AUD_UAIF4,
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MUX_CLK_AUD_UAIF5,
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MUX_CLK_AUD_UAIF6,
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MUX_CLK_AUD_CNT,
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MUX_CLK_AUD_BUS,
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MUX_CLK_AUD_PCMC,
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MUX_BUS0_CMUREF,
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MUX_BUS1_CMUREF,
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MUX_BUS2_CMUREF,
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MUX_CLK_CMGP_I2C0,
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MUX_CLK_CMGP_USI0,
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MUX_CLK_CMGP_USI1,
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MUX_CLK_CMGP_USI2,
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MUX_CLK_CMGP_USI3,
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CLK_CMGP_ADC,
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MUX_CLK_CMGP_I2C1,
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MUX_CLK_CMGP_I2C2,
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MUX_CLK_CMGP_I2C3,
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MUX_CLK_CMGP_I3C,
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MUX_CLKCMU_MFC0_MFC0,
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MUX_CLKCMU_VPD_BUS,
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MUX_CLKCMU_CPUCL0_SWITCH,
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MUX_CLKCMU_CORE_BUS,
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MUX_CLKCMU_MIF_SWITCH,
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MUX_CLKCMU_TAA_BUS,
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MUX_CLKCMU_ITP_BUS,
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MUX_CLKCMU_AUD_CPU,
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MUX_CLKCMU_HPM,
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MUX_CLKCMU_CPUCL0_DBG_BUS,
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MUX_CLKCMU_CIS_CLK0,
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MUX_CLKCMU_CIS_CLK1,
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MUX_CLKCMU_CIS_CLK2,
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MUX_CLKCMU_CIS_CLK3,
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MUX_CMU_CMUREF,
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MUX_CLKCMU_PERIC0_BUS,
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MUX_CLKCMU_PERIC1_BUS,
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MUX_CLKCMU_PERIS_BUS,
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MUX_CLKCMU_HSI1_PCIE,
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MUX_CLKCMU_NPU_BUS,
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MUX_CLKCMU_ALIVE_BUS,
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MUX_CLKCMU_HSI1_BUS,
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MUX_CLKCMU_CPUCL2_SWITCH,
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MUX_CLKCMU_MFC0_WFD,
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MUX_CLKCMU_MIF_BUSP,
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MUX_CLKCMU_PERIC0_IP0,
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MUX_CLKCMU_PERIC1_IP0,
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CLKCMU_DPUF0_BUS,
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MUX_CLKCMU_DPUF0_ALT,
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MUX_CLKCMU_CPUCL1_SWITCH,
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MUX_CLKCMU_HSI0_BUS,
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MUX_CLKCMU_CMU_BOOST_MIF,
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MUX_CLKCMU_YUVPP_BUS,
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MUX_CLKCMU_CIS_CLK4,
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MUX_CLKCMU_DPUF0,
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MUX_CLKCMU_CMU_BOOST,
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MUX_CLKCMU_BUS1_BUS,
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MUX_CLKCMU_CSIS_CSIS,
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MUX_CLKCMU_MCFP0_BUS,
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MUX_CLKCMU_MCSC_BUS,
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MUX_CLKCMU_DNS_BUS,
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MUX_CLKCMU_NPUS_BUS,
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MUX_CLKCMU_MCSC_GDC,
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MUX_CLKCMU_CSIS_OIS_MCU,
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MUX_CLKCMU_SSP_SSPCORE,
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MUX_CLKCMU_CIS_CLK5,
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MUX_CLKCMU_CMU_BOOST_CPU,
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MUX_CLKCMU_M2M_BUS,
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MUX_CLKCMU_DPUB_ALT,
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CLKCMU_DPUB_BUS,
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MUX_CLKCMU_DPUB,
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MUX_CLKCMU_MFC1_MFC1,
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MUX_CLKCMU_BUS1_SBIC,
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MUX_CLKCMU_LME_BUS,
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MUX_CLKCMU_MCFP1_MCFP1,
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MUX_CLKCMU_VPC_BUS,
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MUX_CLKCMU_BUS0_BUS,
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MUX_CLKCMU_BUS2_BUS,
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MUX_CLKCMU_HSI0_USB31DRD,
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MUX_CLKCMU_HSI0_USBDP_DEBUG,
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MUX_CLKCMU_HSI0_DPGTC,
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MUX_CLKCMU_AUD_BUS,
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MUX_CLKCMU_MCFP1_ORBMCH,
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MUX_CLKCMU_CSIS_PDP,
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MUX_CP_UCPU_CLK,
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MUX_CP_LCPU_CLK,
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MUX_CP_HISPEEDY_CLK,
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MUX_CLKCMU_PERIC0_IP1,
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MUX_CLKCMU_PERIC1_IP1,
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MUX_CLKCMU_SSP_BUS,
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MUX_CLKCMU_YUVPP_FRC,
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MUX_CLKCMU_G3D_BUS,
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CLKCMU_G3D_SHADER,
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MUX_CLKCMU_PERIC2_IP0,
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MUX_CLKCMU_PERIC2_BUS,
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MUX_CLKCMU_PERIC2_IP1,
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MUX_CLKCMU_DPUF1,
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MUX_CLKCMU_DPUF1_ALT,
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CLKCMU_DPUF1_BUS,
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MUX_CLKCMU_CPUCL0_BUSP,
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MUX_CLKCMU_DSU_SWITCH,
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MUX_CLKCMU_G3D_SWITCH,
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MUX_CLKCMU_HSI1_MMC_CARD,
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MUX_CLKCMU_HSI1_UFS_EMBD,
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MUX_CORE_CMUREF,
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MUX_CPUCL0_CMUREF,
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MUX_CLK_CPUCL0_CORE,
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MUX_CLK_CPUCL0_CORE_DELAY,
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MUX_PLL_CPUCL0_DELAY,
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MUX_CLK_CPUCL1_CORE,
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MUX_CPUCL1_CMUREF,
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MUX_CPUCL2_CMUREF,
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MUX_CLK_CPUCL2_CORE,
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MUX_CLK_DSU_CLUSTER,
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MUX_DSU_CMUREF,
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MUX_PLL_DSU_DELAY,
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MUX_CLK_DSU_CLUSTER_DELAY,
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MUX_CLK_G3D_BUS,
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MUX_CLK_HSI0_BUS,
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MUX_CLK_HSI0_USB31DRD,
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MUX_MIF_CMUREF,
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MUX_CLK_PERIC0_USI00_USI,
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MUX_CLK_PERIC0_USI04_USI,
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MUX_CLK_PERIC0_USI_I2C,
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MUX_CLK_PERIC0_USI14_USI,
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MUX_CLK_PERIC0_USI01_USI,
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MUX_CLK_PERIC0_USI15_USI,
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MUX_CLK_PERIC0_USI05_USI,
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MUX_CLK_PERIC0_USI03_USI,
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MUX_CLK_PERIC0_UART_DBG,
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MUX_CLK_PERIC0_USI02_USI,
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MUX_CLK_PERIC0_USI13_USI,
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MUX_CLK_PERIC1_UART_BT,
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MUX_CLK_PERIC1_USI_I2C,
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MUX_CLK_PERIC1_USI11_USI,
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MUX_CLK_PERIC1_USI12_USI,
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MUX_CLK_PERIC1_USI16_USI,
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MUX_CLK_PERIC1_USI17_USI,
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MUX_CLK_PERIC1_USI18_USI,
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MUX_CLK_PERIC2_USI07_USI,
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MUX_CLK_PERIC2_USI_I2C,
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MUX_CLK_PERIC2_USI06_USI,
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MUX_CLK_PERIC2_USI08_USI,
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MUX_CLK_PERIC2_USI09_USI,
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MUX_CLK_PERIC2_USI10_USI,
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MUX_CLK_S2D_CORE,
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MUX_CLK_VTS_DMIC_IF,
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MUX_CLK_VTS_DMIC_AUD,
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MUX_CLK_VTS_SERIAL_LIF,
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MUX_CLK_VTS_DMIC_AHB,
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MUX_CLK_VTS_SERIAL_LIF_CORE,
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ALIVE_CMU_ALIVE_CLKOUT0,
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ALIVE_CMU_ALIVE_CLKOUT1,
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AUD_CMU_AUD_CLKOUT0,
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AUD_CMU_AUD_CLKOUT1,
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BUS0_CMU_BUS0_CLKOUT0,
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BUS0_CMU_BUS0_CLKOUT1,
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BUS1_CMU_BUS1_CLKOUT0,
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BUS1_CMU_BUS1_CLKOUT1,
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BUS2_CMU_BUS2_CLKOUT0,
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BUS2_CMU_BUS2_CLKOUT1,
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CMGP_CMU_CMGP_CLKOUT0,
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CMGP_CMU_CMGP_CLKOUT1,
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CMU_CMU_TOP_CLKOUT0,
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CMU_CMU_TOP_CLKOUT1,
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CORE_CMU_CORE_CLKOUT0,
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CORE_CMU_CORE_CLKOUT1,
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CPUCL0_CMU_CPUCL0_CLKOUT0,
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CPUCL0_CMU_CPUCL0_CLKOUT1,
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CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT0,
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CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT1,
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CPUCL1_CMU_CPUCL1_CLKOUT0,
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CPUCL1_CMU_CPUCL1_CLKOUT1,
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CPUCL2_CMU_CPUCL2_CLKOUT0,
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CPUCL2_CMU_CPUCL2_CLKOUT1,
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CSIS_CMU_CSIS_CLKOUT0,
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CSIS_CMU_CSIS_CLKOUT1,
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DNS_CMU_DNS_CLKOUT0,
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DNS_CMU_DNS_CLKOUT1,
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DPUB_CMU_DPUB_CLKOUT0,
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DPUB_CMU_DPUB_CLKOUT1,
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DPUF0_CMU_DPUF0_CLKOUT0,
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DPUF0_CMU_DPUF0_CLKOUT1,
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DPUF1_CMU_DPUF1_CLKOUT0,
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DPUF1_CMU_DPUF1_CLKOUT1,
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DSU_CMU_DSU_CLKOUT0,
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DSU_CMU_DSU_CLKOUT1,
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G3D_CMU_G3D_CLKOUT0,
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G3D_CMU_G3D_CLKOUT1,
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G3D_EMBEDDED_CMU_G3D_CLKOUT0,
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G3D_EMBEDDED_CMU_G3D_CLKOUT1,
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HSI0_CMU_HSI0_CLKOUT0,
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HSI0_CMU_HSI0_CLKOUT1,
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HSI1_CMU_HSI1_CLKOUT0,
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HSI1_CMU_HSI1_CLKOUT1,
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ITP_CMU_ITP_CLKOUT0,
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ITP_CMU_ITP_CLKOUT1,
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LME_CMU_LME_CLKOUT0,
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LME_CMU_LME_CLKOUT1,
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M2M_CMU_M2M_CLKOUT0,
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M2M_CMU_M2M_CLKOUT1,
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MCFP0_CMU_MCFP0_CLKOUT0,
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MCFP0_CMU_MCFP0_CLKOUT1,
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MCFP1_CMU_MCFP1_CLKOUT0,
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MCFP1_CMU_MCFP1_CLKOUT1,
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MCSC_CMU_MCSC_CLKOUT0,
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MCSC_CMU_MCSC_CLKOUT1,
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MFC0_CMU_MFC0_CLKOUT0,
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MFC0_CMU_MFC0_CLKOUT1,
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MFC1_CMU_MFC1_CLKOUT0,
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MFC1_CMU_MFC1_CLKOUT1,
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MIF_CMU_MIF_CLKOUT0,
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MIF_CMU_MIF_CLKOUT1,
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NPU_CMU_NPU_CLKOUT0,
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NPU_CMU_NPU_CLKOUT1,
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NPU01_CMU_NPU_CLKOUT0,
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NPU01_CMU_NPU_CLKOUT1,
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NPU10_CMU_NPU_CLKOUT0,
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NPU10_CMU_NPU_CLKOUT1,
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NPUS_CMU_NPUS_CLKOUT0,
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NPUS_CMU_NPUS_CLKOUT1,
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PERIC0_CMU_PERIC0_CLKOUT0,
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PERIC0_CMU_PERIC0_CLKOUT1,
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PERIC1_CMU_PERIC1_CLKOUT0,
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PERIC1_CMU_PERIC1_CLKOUT1,
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PERIC2_CMU_PERIC2_CLKOUT0,
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PERIC2_CMU_PERIC2_CLKOUT1,
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PERIS_CMU_PERIS_CLKOUT0,
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PERIS_CMU_PERIS_CLKOUT1,
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SSP_CMU_SSP_CLKOUT0,
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SSP_CMU_SSP_CLKOUT1,
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SSP_EMBEDDED_CMU_SSP_CLKOUT0,
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SSP_EMBEDDED_CMU_SSP_CLKOUT1,
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TAA_CMU_TAA_CLKOUT0,
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TAA_CMU_TAA_CLKOUT1,
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VPC_CMU_VPC_CLKOUT0,
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VPC_CMU_VPC_CLKOUT1,
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VPD_CMU_VPD_CLKOUT0,
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VPD_CMU_VPD_CLKOUT1,
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VTS_CMU_VTS_CLKOUT0,
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VTS_CMU_VTS_CLKOUT1,
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YUVPP_CMU_YUVPP_CLKOUT0,
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YUVPP_CMU_YUVPP_CLKOUT1,
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OSCCTRL_RCO_400 = ((MASK_OF_ID & YUVPP_CMU_YUVPP_CLKOUT1) | USER_MUX_TYPE) + 1,
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MUX_CLKCMU_ALIVE_BUS_USER,
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MUX_CLK_RCO_ALIVE_USER,
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MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
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MUX_CLKCMU_AUD_CPU_USER,
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MUX_CLKCMU_AUD_BUS_USER,
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MUX_CP_PCMC_CLK_USER,
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MUX_CLKCMU_BUS0_BUS_USER,
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MUX_CLKCMU_BUS1_BUS_USER,
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MUX_CLKCMU_BUS1_SBIC_USER,
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MUX_CLKCMU_BUS2_BUS_USER,
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MUX_CLKCMU_CMGP_BUS_USER,
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MUX_CLKCMU_CMGP_PERI_USER,
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MUX_CLKCMU_CMGP_ADC_USER,
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MUX_CLKCMU_CORE_BUS_USER,
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MUX_CLKCMU_CPUCL0_SWITCH_USER,
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MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
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MUX_CLKCMU_CPUCL0_BUSP_USER,
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MUX_CLKCMU_CPUCL1_SWITCH_USER,
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MUX_CLKCMU_CPUCL2_SWITCH_USER,
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MUX_CLKCMU_CSIS_CSIS_USER,
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MUX_CLKCMU_CSIS_OIS_MCU_USER,
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MUX_CLKCMU_CSIS_PDP_USER,
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MUX_CLKCMU_DNS_BUS_USER,
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MUX_CLKCMU_DPUB_BUS_USER,
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MUX_CLKCMU_DPUF0_BUS_USER,
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MUX_CLKCMU_DPUF1_BUS_USER,
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MUX_CLKCMU_DSU_SWITCH_USER,
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MUX_CLKCMU_G3D_BUS_USER,
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MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER,
|
|
MUX_CLKCMU_G3D_SHADER_USER,
|
|
MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER,
|
|
MUX_CLKCMU_HSI0_BUS_USER,
|
|
MUX_CLKCMU_HSI0_USB31DRD_USER,
|
|
MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
|
|
MUX_CLKCMU_HSI0_DPGTC_USER,
|
|
MUX_CLKAUD_HSI0_BUS_USER,
|
|
MUX_CLKAUD_HSI0_USB31DRD_USER,
|
|
MUX_CLK_USB20PHY_USER,
|
|
MUX_CLKCMU_HSI1_BUS_USER,
|
|
MUX_CLKCMU_HSI1_PCIE_USER,
|
|
MUX_CLKCMU_HSI1_MMC_CARD_USER,
|
|
MUX_CLKCMU_HSI1_UFS_EMBD_USER,
|
|
MUX_CLKCMU_ITP_BUS_USER,
|
|
MUX_CLKCMU_LME_BUS_USER,
|
|
MUX_CLKCMU_M2M_BUS_USER,
|
|
MUX_CLKCMU_MCFP0_BUS_USER,
|
|
MUX_CLKCMU_MCFP1_MCFP1_USER,
|
|
MUX_CLKCMU_MCFP1_ORBMCH_USER,
|
|
MUX_CLKCMU_MCSC_BUS_USER,
|
|
MUX_CLKCMU_MCSC_GDC_USER,
|
|
MUX_CLKCMU_MFC0_MFC0_USER,
|
|
MUX_CLKCMU_MFC0_WFD_USER,
|
|
MUX_CLKCMU_MFC1_MFC1_USER,
|
|
MUX_CLKCMU_MIF_BUSP_USER,
|
|
CLKMUX_MIF_DDRPHY2X,
|
|
MUX_CLKCMU_NPU_BUS_USER,
|
|
MUX_CLKCMU_NPU01_BUS_USER,
|
|
MUX_CLKCMU_NPU10_BUS_USER,
|
|
MUX_CLKCMU_NPUS_BUS_USER,
|
|
MUX_CLKCMU_PERIC0_BUS_USER,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
MUX_CLKCMU_PERIC1_BUS_USER,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
MUX_CLKCMU_PERIC2_BUS_USER,
|
|
MUX_CLKCMU_PERIS_BUS_USER,
|
|
CLKCMU_MIF_DDRPHY2X_S2D,
|
|
MUX_CLKCMU_SSP_BUS_USER,
|
|
MUX_CLKCMU_SSP_SSPCORE_USER,
|
|
MUX_CLKCMU_TAA_BUS_USER,
|
|
MUX_CLKCMU_VPC_BUS_USER,
|
|
MUX_CLKCMU_VPD_BUS_USER,
|
|
MUX_CLKCMU_VTS_BUS_USER,
|
|
MUX_CLKAUD_VTS_DMIC0_USER,
|
|
MUX_CLKAUD_VTS_DMIC1_USER,
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
|
MUX_CLK_RCO_VTS_USER,
|
|
MUX_CLKCMU_YUVPP_BUS_USER,
|
|
MUX_CLKCMU_YUVPP_FRC_USER,
|
|
MUX_HCHGEN_CLK_AUD_CPU = ((MASK_OF_ID & MUX_CLKCMU_YUVPP_FRC_USER) | CONST_MUX_TYPE) + 1,
|
|
MUX_CLK_CPUCL0_CORE_STR,
|
|
MUX_CLK_CPUCL1_CORE_STR,
|
|
MUX_CLK_CPUCL2_CORE_STR,
|
|
MUX_CLK_DSU_CLUSTER_STR,
|
|
MUX_CLK_G3D_SHADER_STR,
|
|
MUX_CLK_PERIS_GIC,
|
|
end_of_mux,
|
|
num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,
|
|
|
|
CLKCMU_VTS_BUS = DIV_TYPE,
|
|
DIV_CLK_ALIVE_BUS,
|
|
CLKCMU_CMGP_BUS,
|
|
DIV_CLK_ALIVE_I3C_PMIC,
|
|
CLKCMU_CMGP_PERI,
|
|
CLKCMU_CMGP_ADC,
|
|
DIV_CLK_ALIVE_DBGCORE_UART,
|
|
DIV_CLK_AUD_CPU,
|
|
DIV_CLK_AUD_AUDIF,
|
|
DIV_CLK_AUD_CPU_PCLKDBG,
|
|
DIV_CLK_AUD_DSIF,
|
|
DIV_CLK_AUD_UAIF0,
|
|
DIV_CLK_AUD_UAIF1,
|
|
DIV_CLK_AUD_UAIF2,
|
|
DIV_CLK_AUD_UAIF3,
|
|
DIV_CLK_AUD_CPU_ACLK,
|
|
DIV_CLK_AUD_BUS,
|
|
DIV_CLK_AUD_BUSP,
|
|
DIV_CLK_AUD_CNT,
|
|
DIV_CLK_AUD_UAIF4,
|
|
DIV_CLK_AUD_UAIF5,
|
|
DIV_CLK_AUD_SCLK,
|
|
DIV_CLK_AUD_DMIC1,
|
|
DIV_CLK_AUD_UAIF6,
|
|
CLKAUD_VTS_DMIC0,
|
|
CLKAUD_HSI0_BUS,
|
|
CLKAUD_HSI0_USB31DRD,
|
|
DIV_CLK_AUD_PCMC,
|
|
DIV_CLK_BUS0_BUSP,
|
|
DIV_CLK_BUS1_BUSP,
|
|
DIV_CLK_BUS2_BUSP,
|
|
DIV_CLK_CMGP_I2C0,
|
|
DIV_CLK_CMGP_USI1,
|
|
DIV_CLK_CMGP_USI0,
|
|
DIV_CLK_CMGP_USI2,
|
|
DIV_CLK_CMGP_USI3,
|
|
DIV_CLK_CMGP_I2C1,
|
|
DIV_CLK_CMGP_I2C2,
|
|
DIV_CLK_CMGP_I2C3,
|
|
DIV_CLK_CMGP_I3C,
|
|
CLKCMU_ALIVE_BUS,
|
|
DIV_CLKCMU_G3D_SWITCH,
|
|
CLKCMU_PERIC0_BUS,
|
|
CLKCMU_PERIS_BUS,
|
|
DIV_CLKCMU_DPUF0_ALT,
|
|
CLKCMU_MFC0_MFC0,
|
|
CLKCMU_VPD_BUS,
|
|
CLKCMU_PERIC1_BUS,
|
|
CLKCMU_CPUCL2_SWITCH,
|
|
CLKCMU_CPUCL0_SWITCH,
|
|
CLKCMU_CORE_BUS,
|
|
CLKCMU_TAA_BUS,
|
|
CLKCMU_ITP_BUS,
|
|
CLKCMU_AUD_CPU,
|
|
CLKCMU_HPM,
|
|
CLKCMU_CPUCL0_DBG_BUS,
|
|
CLKCMU_CIS_CLK0,
|
|
CLKCMU_CIS_CLK1,
|
|
CLKCMU_CIS_CLK2,
|
|
CLKCMU_CIS_CLK3,
|
|
CLKCMU_CMU_BOOST_MIF,
|
|
CLKCMU_NPU_BUS,
|
|
CLKCMU_MFC0_WFD,
|
|
CLKCMU_MIF_BUSP,
|
|
CLKCMU_PERIC0_IP0,
|
|
CLKCMU_PERIC1_IP0,
|
|
DIV_CLKCMU_DPUF0,
|
|
CLKCMU_CPUCL1_SWITCH,
|
|
CLKCMU_HSI0_BUS,
|
|
CLKCMU_YUVPP_BUS,
|
|
CLKCMU_CIS_CLK4,
|
|
CLKCMU_CMU_BOOST,
|
|
CLKCMU_BUS1_BUS,
|
|
CLKCMU_CSIS_CSIS,
|
|
CLKCMU_MCFP0_BUS,
|
|
CLKCMU_MCSC_BUS,
|
|
CLKCMU_DNS_BUS,
|
|
CLKCMU_NPUS_BUS,
|
|
CLKCMU_HSI1_BUS,
|
|
CLKCMU_MCSC_GDC,
|
|
CLKCMU_CSIS_OIS_MCU,
|
|
CLKCMU_SSP_SSPCORE,
|
|
CLKCMU_CIS_CLK5,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
CLKCMU_M2M_BUS,
|
|
DIV_CLKCMU_DPUB_ALT,
|
|
DIV_CLKCMU_DPUB,
|
|
CLKCMU_MFC1_MFC1,
|
|
CLKCMU_BUS1_SBIC,
|
|
CLKCMU_LME_BUS,
|
|
CLKCMU_MCFP1_MCFP1,
|
|
CLKCMU_VPC_BUS,
|
|
CLKCMU_BUS0_BUS,
|
|
CLKCMU_BUS2_BUS,
|
|
CLKCMU_HSI0_USB31DRD,
|
|
CLKCMU_HSI0_DPGTC,
|
|
CLKCMU_AUD_BUS,
|
|
CLKCMU_MCFP1_ORBMCH,
|
|
CLKCMU_CSIS_PDP,
|
|
CP_SHARED0_CLK,
|
|
CP_SHARED1_CLK,
|
|
CP_SHARED2_CLK,
|
|
CP_HISPEEDY_CLK,
|
|
CLKCMU_PERIC0_IP1,
|
|
CLKCMU_PERIC1_IP1,
|
|
CLKCMU_SSP_BUS,
|
|
CLKCMU_YUVPP_FRC,
|
|
CLKCMU_G3D_BUS,
|
|
CLKCMU_PERIC2_BUS,
|
|
CLKCMU_PERIC2_IP0,
|
|
CLKCMU_PERIC2_IP1,
|
|
DIV_CLKCMU_DPUF1,
|
|
DIV_CLKCMU_DPUF1_ALT,
|
|
CLKCMU_CPUCL0_BUSP,
|
|
CLKCMU_DSU_SWITCH,
|
|
CLKCMU_HSI1_MMC_CARD,
|
|
CLKCMU_HSI1_UFS_EMBD,
|
|
DIV_CLK_CORE_BUSP,
|
|
DIV_CLK_CPUCL0_SHORTSTOP_CORE,
|
|
DIV_CLK_CPUCL0_DBG_BUS,
|
|
DIV_CLK_CPUCL0_DBG_PCLKDBG,
|
|
DIV_CLK_CPUCL1_SHORTSTOP_CORE,
|
|
DIV_CLK_CPUCL1_HTU,
|
|
DIV_CLK_CPUCL2_SHORTSTOP_CORE,
|
|
DIV_CLK_CPUCL2_HTU,
|
|
DIV_CLK_CSIS_BUSP,
|
|
DIV_CLK_DNS_BUSP,
|
|
DIV_CLK_DPUB_BUSP,
|
|
DIV_CLK_DPUF0_BUSP,
|
|
DIV_CLK_DPUF1_BUSP,
|
|
DIV_CLK_DSU_SHORTSTOP_CLUSTER,
|
|
DIV_CLK_CLUSTER_ACLK,
|
|
DIV_CLK_CLUSTER_PCLK,
|
|
DIV_CLK_CLUSTER_PERIPHCLK,
|
|
DIV_CLK_CLUSTER_ATCLK,
|
|
DIV_CLK_CLUSTER_BCLK,
|
|
DIV_CLK_G3D_BUSP,
|
|
DIV_CLK_ITP_BUSP,
|
|
DIV_CLK_LME_BUSP,
|
|
DIV_CLK_M2M_BUSP,
|
|
DIV_CLK_MCFP0_BUSP,
|
|
DIV_CLK_MCFP1_BUSP,
|
|
DIV_CLK_MCSC_BUSP,
|
|
DIV_CLK_MFC0_BUSP,
|
|
DIV_CLK_MFC1_BUSP,
|
|
DIV_CLK_NPU_BUSP,
|
|
DIV_CLK_NPU01_BUSP,
|
|
DIV_CLK_NPU10_BUSP,
|
|
DIV_CLK_NPUS_BUSP,
|
|
DIV_CLK_PERIC0_USI00_USI,
|
|
DIV_CLK_PERIC0_USI01_USI,
|
|
DIV_CLK_PERIC0_USI02_USI,
|
|
DIV_CLK_PERIC0_USI03_USI,
|
|
DIV_CLK_PERIC0_USI04_USI,
|
|
DIV_CLK_PERIC0_USI05_USI,
|
|
DIV_CLK_PERIC0_USI_I2C,
|
|
DIV_CLK_PERIC0_UART_DBG,
|
|
DIV_CLK_PERIC0_USI13_USI,
|
|
DIV_CLK_PERIC0_USI14_USI,
|
|
DIV_CLK_PERIC0_USI15_USI,
|
|
DIV_CLK_PERIC1_UART_BT,
|
|
DIV_CLK_PERIC1_USI_I2C,
|
|
DIV_CLK_PERIC1_USI18_USI,
|
|
DIV_CLK_PERIC1_USI12_USI,
|
|
DIV_CLK_PERIC1_USI11_USI,
|
|
DIV_CLK_PERIC1_USI16_USI,
|
|
DIV_CLK_PERIC1_USI17_USI,
|
|
DIV_CLK_PERIC2_USI08_USI,
|
|
DIV_CLK_PERIC2_USI_I2C,
|
|
DIV_CLK_PERIC2_USI06_USI,
|
|
DIV_CLK_PERIC2_USI07_USI,
|
|
DIV_CLK_PERIC2_USI09_USI,
|
|
DIV_CLK_PERIC2_USI10_USI,
|
|
DIV_CLK_PERIS_BUSP,
|
|
DIV_CLK_SSP_BUSP,
|
|
DIV_CLK_TAA_BUSP,
|
|
DIV_CLK_VPC_BUSP,
|
|
DIV_CLK_VPD_BUSP,
|
|
DIV_CLK_VTS_DMIC_IF,
|
|
DIV_CLK_VTS_DMIC_IF_DIV2,
|
|
DIV_CLK_VTS_BUS,
|
|
DIV_CLK_VTS_DMIC_AUD,
|
|
DIV_CLK_VTS_DMIC_AUD_DIV2,
|
|
DIV_CLK_VTS_SERIAL_LIF,
|
|
DIV_CLK_VTS_DMIC_AHB,
|
|
DIV_CLK_VTS_SERIAL_LIF_CORE,
|
|
DIV_CLK_YUVPP_BUSP,
|
|
DIV_CLK_CPUCL0_CORE = ((MASK_OF_ID & DIV_CLK_YUVPP_BUSP) | CONST_DIV_TYPE) + 1,
|
|
DIV_CLK_CPUCL1_CORE,
|
|
DIV_CLK_CPUCL2_CORE,
|
|
DIV_CLK_CSIS_CSIS,
|
|
DIV_CLK_CSIS_PDP,
|
|
DIV_CLK_DNS_BUS,
|
|
DIV_CLK_DSU_CLUSTER,
|
|
DIV_CLK_G3D_SHADER,
|
|
DIV_CLK_G3D_BUSD,
|
|
DIV_CLK_ITP_BUS,
|
|
DIV_CLK_LME_BUS,
|
|
DIV_CLK_MCFP0_BUS,
|
|
DIV_CLK_MCFP1_MCFP1,
|
|
DIV_CLK_MCFP1_ORBMCH,
|
|
DIV_CLK_MCSC_BUS,
|
|
DIV_CLK_MCSC_GDC,
|
|
DIV_CLK_MFC0_MFC0,
|
|
DIV_CLK_MFC1_MFC1,
|
|
DIV_CLK_NPU_BUS,
|
|
DIV_CLK_NPU01_BUS,
|
|
DIV_CLK_NPU10_BUS,
|
|
DIV_CLK_NPUS_BUS,
|
|
DIV_CLK_TAA_BUS,
|
|
DIV_CLK_VPC_BUS,
|
|
DIV_CLK_VPD_BUS,
|
|
DIV_CLK_YUVPP_BUS,
|
|
DIV_CLK_YUVPP_FRC,
|
|
end_of_div,
|
|
num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,
|
|
|
|
GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK = GATE_TYPE,
|
|
GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
|
|
GATE_CLKCMU_VTS_BUS,
|
|
GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
|
GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
|
|
GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK,
|
|
GATE_CLKCMU_CMGP_BUS,
|
|
GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK,
|
|
GATE_CLKCMU_CMGP_PERI,
|
|
GATE_CLKCMU_CMGP_ADC,
|
|
CLKCMU_VTS_DMIC,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM,
|
|
GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU,
|
|
GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA,
|
|
GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK,
|
|
CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
|
|
GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
|
GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
|
|
GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
|
|
GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5,
|
|
GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK,
|
|
CLKAUD_VTS_DMIC1,
|
|
GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
|
GATE_CLKAUD_VTS_DMIC0,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK,
|
|
GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK,
|
|
GATE_CLKAUD_HSI0_BUS,
|
|
GATE_CLKAUD_HSI0_USB31DRD,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK,
|
|
CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0,
|
|
GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0,
|
|
GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK,
|
|
CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1,
|
|
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
|
|
GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
|
|
GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK,
|
|
GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
GATE_CLKCMU_ALIVE_BUS,
|
|
CLKCMU_MIF01_SWITCH,
|
|
GATE_CLKCMU_MFC0_MFC0,
|
|
GATE_CLKCMU_HSI1_BUS,
|
|
GATE_CLKCMU_DPUF0_BUS,
|
|
GATE_CLKCMU_G3D_SWITCH,
|
|
GATE_CLKCMU_PERIS_BUS,
|
|
GATE_CLKCMU_VPD_BUS,
|
|
GATE_CLKCMU_PERIC0_BUS,
|
|
GATE_CLKCMU_PERIC1_BUS,
|
|
GATE_CLKCMU_CPUCL2_SWITCH,
|
|
GATE_CLKCMU_CPUCL0_SWITCH,
|
|
GATE_CLKCMU_CORE_BUS,
|
|
GATE_CLKCMU_TAA_BUS,
|
|
GATE_CLKCMU_ITP_BUS,
|
|
GATE_CLKCMU_AUD_CPU,
|
|
GATE_CLKCMU_HPM,
|
|
GATE_CLKCMU_HSI1_PCIE,
|
|
GATE_CLKCMU_CPUCL0_DBG_BUS,
|
|
GATE_CLKCMU_CIS_CLK0,
|
|
GATE_CLKCMU_CIS_CLK1,
|
|
GATE_CLKCMU_CIS_CLK3,
|
|
GATE_CLKCMU_CIS_CLK2,
|
|
GATE_CLKCMU_NPU_BUS,
|
|
GATE_CLKCMU_MFC0_WFD,
|
|
GATE_CLKCMU_MIF_BUSP,
|
|
GATE_CLKCMU_PERIC0_IP0,
|
|
GATE_CLKCMU_PERIC1_IP0,
|
|
GATE_CLKCMU_DPUF0,
|
|
GATE_CLKCMU_CPUCL1_SWITCH,
|
|
GATE_CLKCMU_HSI0_BUS,
|
|
GATE_CLKCMU_YUVPP_BUS,
|
|
GATE_CLKCMU_CIS_CLK4,
|
|
GATE_CLKCMU_BUS1_BUS,
|
|
GATE_CLKCMU_CSIS_CSIS,
|
|
GATE_CLKCMU_MCFP0_BUS,
|
|
GATE_CLKCMU_MCSC_BUS,
|
|
GATE_CLKCMU_DNS_BUS,
|
|
GATE_CLKCMU_NPUS_BUS,
|
|
GATE_CLKCMU_MCSC_GDC,
|
|
GATE_CLKCMU_CSIS_OIS_MCU,
|
|
GATE_CLKCMU_SSP_SSPCORE,
|
|
GATE_CLKCMU_CIS_CLK5,
|
|
GATE_CLKCMU_M2M_BUS,
|
|
GATE_CLKCMU_DPUB_BUS,
|
|
GATE_CLKCMU_DPUB,
|
|
GATE_CLKCMU_MFC1_MFC1,
|
|
GATE_CLKCMU_BUS1_SBIC,
|
|
GATE_CLKCMU_LME_BUS,
|
|
GATE_CLKCMU_MCFP1_MCFP1,
|
|
GATE_CLKCMU_VPC_BUS,
|
|
GATE_CLKCMU_BUS0_BUS,
|
|
GATE_CLKCMU_BUS2_BUS,
|
|
GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY,
|
|
GATE_CLKCMU_HSI0_USB31DRD_CPY,
|
|
GATE_CLKCMU_HSI0_DPGTC_CPY,
|
|
GATE_CLKCMU_AUD_BUS,
|
|
GATE_CLKCMU_MCFP1_ORBMCH,
|
|
GATE_CLKCMU_CSIS_PDP,
|
|
CP_UCPU_CLK,
|
|
CP_LCPU_CLK,
|
|
GATE_CP_SHARED0_CLK,
|
|
GATE_CP_SHARED1_CLK,
|
|
GATE_CP_SHARED2_CLK,
|
|
GATE_CP_HISPEEDY_CLK,
|
|
GATE_CLKCMU_PERIC0_IP1,
|
|
GATE_CLKCMU_PERIC1_IP1,
|
|
GATE_CLKCMU_SSP_BUS,
|
|
GATE_CLKCMU_YUVPP_FRC,
|
|
GATE_CLKCMU_G3D_BUS,
|
|
GATE_CLKCMU_PERIC2_IP0,
|
|
GATE_CLKCMU_PERIC2_BUS,
|
|
GATE_CLKCMU_PERIC2_IP1,
|
|
CLKCMU_MIF23_SWITCH,
|
|
GATE_CLKCMU_DPUF1_BUS,
|
|
GATE_CLKCMU_DPUF1,
|
|
GATE_CLKCMU_CPUCL0_BUSP,
|
|
GATE_CLKCMU_DSU_SWITCH,
|
|
GATE_CLKCMU_HSI1_UFS_EMBD,
|
|
GATE_CLKCMU_HSI1_MMC_CARD,
|
|
CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE,
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
|
|
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS,
|
|
CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
|
|
CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN,
|
|
CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN,
|
|
CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK,
|
|
CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN,
|
|
CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2,
|
|
CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK,
|
|
CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN,
|
|
CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4,
|
|
GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5,
|
|
GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0,
|
|
GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA,
|
|
GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB,
|
|
GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1,
|
|
CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK,
|
|
GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK,
|
|
GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0,
|
|
GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1,
|
|
GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2,
|
|
CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON,
|
|
GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA,
|
|
GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP,
|
|
GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV,
|
|
GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA,
|
|
GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP,
|
|
GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV,
|
|
GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK,
|
|
GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE,
|
|
CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK,
|
|
CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK,
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
|
|
CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C,
|
|
GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK,
|
|
CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN,
|
|
CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP,
|
|
CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS,
|
|
GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
|
|
GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
|
|
GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
|
|
CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
|
|
GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
|
|
GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK,
|
|
GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK,
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL,
|
|
GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
|
|
GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
|
|
GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
|
GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
|
GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
|
GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK,
|
|
CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK,
|
|
GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK,
|
|
GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK,
|
|
GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK,
|
|
GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK,
|
|
GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK,
|
|
GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK,
|
|
GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK,
|
|
GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK,
|
|
CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK,
|
|
GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK,
|
|
GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1,
|
|
CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2,
|
|
CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK,
|
|
GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK,
|
|
CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK,
|
|
GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M,
|
|
GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C,
|
|
GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK,
|
|
CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK,
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK,
|
|
CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK,
|
|
CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S,
|
|
GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK,
|
|
CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI,
|
|
GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI,
|
|
GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK,
|
|
CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
|
|
CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK,
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK,
|
|
GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK,
|
|
CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK,
|
|
GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
|
|
GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
|
|
GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
|
|
GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
|
|
GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10,
|
|
GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK,
|
|
CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3,
|
|
GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3,
|
|
GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK,
|
|
GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
|
CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
|
GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
|
|
CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK,
|
|
GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK,
|
|
GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK,
|
|
CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK,
|
|
GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM,
|
|
CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS,
|
|
GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK,
|
|
CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C,
|
|
GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK,
|
|
CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN,
|
|
CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK,
|
|
CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK,
|
|
CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK,
|
|
CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK,
|
|
GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE,
|
|
GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM,
|
|
GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK,
|
|
GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK,
|
|
CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK,
|
|
CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN,
|
|
GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK,
|
|
CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
|
CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
|
CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
|
|
GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK,
|
|
GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2,
|
|
GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK,
|
|
GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS,
|
|
CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C,
|
|
GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK,
|
|
CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM,
|
|
GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK,
|
|
end_of_gate,
|
|
num_of_gate = (end_of_gate - GATE_TYPE) & MASK_OF_ID,
|
|
|
|
};
|
|
#endif
|