159 lines
6.5 KiB
C
Executable file
159 lines
6.5 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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#ifndef EXYNOS_CM_H
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#define EXYNOS_CM_H
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/******************************************************************************/
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/* Common defines */
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/******************************************************************************/
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#define CM_MAGIC_STRING_LEN (16)
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#define CM_SSS_DEBUG_MEM_SIZE (PAGE_SIZE)
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uint8_t sss_time_magic[CM_MAGIC_STRING_LEN] = "SSSDEBUGTIME";
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uint8_t cm_name[CM_MAGIC_STRING_LEN] = "CryptoManagerV60";
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/******************************************************************************/
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/* defines for log dump */
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/******************************************************************************/
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/* log dump name*/
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#define CM_LOG_DSS_NAME1 "log_cm_1"
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#define CM_LOG_DSS_NAME2 "log_cm_2"
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/******************************************************************************/
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/* struct defines for cm_sss_debug_mem */
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/******************************************************************************/
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struct cm_sss_debug_info {
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uint8_t magic[CM_MAGIC_STRING_LEN];
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uint32_t dbg_req;
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uint32_t dbg_ack;
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uint32_t dbg_ack_int_stat;
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uint32_t dbg_to_int_stat;
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uint32_t dbg_to_history;
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uint32_t dbg_ack_history;
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uint64_t dbg_req_cancel_cnt;
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uint64_t dbg_req_period_cnt;
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uint64_t dbg_to_cnt;
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uint64_t reserved[8];
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};
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struct cm_sss_sema_state_info {
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uint64_t arbiter_state;
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uint64_t core_state_ap;
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uint64_t core_state_cp;
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uint64_t az_fsm_state;
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uint64_t az_req_ap;
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uint64_t az_req_cp;
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uint8_t reserved[16]; /* for 16byte align */
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};
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struct cm_sss_debug_mem {
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uint8_t magic[CM_MAGIC_STRING_LEN];
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struct cm_sss_debug_info ap_info;
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struct cm_sss_debug_info cp_info;
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struct cm_sss_sema_state_info st_info;
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};
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/******************************************************************************/
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/* Define SYSREG regarding HW_SEMA */
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/******************************************************************************/
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/* Offset of System Register for debugging */
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#define SYSREG_OFFSET_DBG_STATE (0x4)
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#define SYSREG_OFFSET_DBG_REQ_CANCEL_CNT_AP (0x8)
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#define SYSREG_OFFSET_DBG_REQ_CANCEL_CNT_CP (0xC)
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#define SYSREG_OFFSET_DBG_REQ_PERIOD_CNT_AP (0x10)
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#define SYSREG_OFFSET_DBG_REQ_PERIOD_CNT_CP (0x14)
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#define SYSREG_OFFSET_DBG_TO_CNT_AP (0x18) /* timeout */
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#define SYSREG_OFFSET_DBG_TO_CNT_CP (0x1C) /* timeout */
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/* HW_SEMA_MEC_DBG */
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#define DBG_REQ_AP_SHIFT (0)
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#define DBG_REQ_CP_SHIFT (1)
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#define DBG_ACK_AP_SHIFT (2)
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#define DBG_ACK_CP_SHIFT (3)
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#define DBG_ACK_INT_STAT_AP_SHIFT (4)
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#define DBG_TO_INT_STAT_AP_SHIFT (5)
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#define DBG_ACK_INT_STAT_CP_SHIFT (6)
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#define DBG_TO_INT_STAT_CP_SHIFT (7)
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#define DBG_TO_HISTORY_AP_SHIFT (12)
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#define DBG_ACK_HISTORY_AP_SHIFT (13)
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#define DBG_TO_HISTORY_CP_SHIFT (14)
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#define DBG_ACK_HISTORY_CP_SHIFT (15)
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#define HW_SEMA_MEC_DBG_REQ_MASK (3 << 0)
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#define HW_SEMA_MEC_DBG_REQ_AP (1 << DBG_REQ_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_REQ_CP (1 << DBG_REQ_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_ACK_MASK (3 << 2)
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#define HW_SEMA_MEC_DBG_ACK_AP (1 << DBG_ACK_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_ACK_CP (1 << DBG_ACK_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_INT_STATUS_MASK (0xF << 4)
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#define HW_SEMA_MEC_DBG_ACK_INT_STATUS_AP (1 << DBG_ACK_INT_STAT_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_TO_INT_STATUS_AP (1 << DBG_TO_INT_STAT_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_ACK_INT_STATUS_CP (1 << DBG_ACK_INT_STAT_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_TO_INT_STATUS_CP (1 << DBG_TO_INT_STAT_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_INT_HISTORY_MASK (0xF << 12)
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#define HW_SEMA_MEC_DBG_TO_HISTORY_AP (1 << DBG_TO_HISTORY_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_ACK_HISTORY_AP (1 << DBG_ACK_HISTORY_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_TO_HISTORY_CP (1 << DBG_TO_HISTORY_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_ACK_HISTORY_CP (1 << DBG_ACK_HISTORY_CP_SHIFT)
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/* HW_SEMA_MEC_DBG_STATE */
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#define DBQ_ARBITER_FSM_STAT_SHIFT (0)
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#define DBG_CORE_FSM_STAT_AP_SHIFT (4)
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#define DBG_CORE_FSM_STAT_CP_SHIFT (10)
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#define DBG_AZ_FSM_STAT_SHIFT (16)
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#define DBG_AZ_REQ_AP_SHIFT (29)
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#define DBG_AZ_REQ_CP_SHIFT (30)
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#define HW_SEMA_MEC_DBG_ARBITER_STAT_MASK (0xF << 0)
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#define HW_SEMA_MEC_DBQ_ARBITER_FSM_STAT (0xF << DBQ_ARBITER_FSM_STAT_SHIFT)
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#define HW_SEMA_MEC_DBG_CORE_STAT_MASK (0xFFF << 4)
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#define HW_SEMA_MEC_DBG_CORE_FSM_STAT_AP (0x3F << DBG_CORE_FSM_STAT_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_CORE_FSM_STAT_CP (0x3F << DBG_CORE_FSM_STAT_CP_SHIFT)
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#define HW_SEMA_MEC_DBG_AZ_STAT_MASK (0x7FFF << 16)
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#define HW_SEMA_MEC_DBG_AZ_FSM_STAT (0x1FFF << DBG_AZ_FSM_STAT_SHIFT)
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#define HW_SEMA_MEC_DBG_AZ_REQ_AP (1 << DBG_AZ_REQ_AP_SHIFT)
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#define HW_SEMA_MEC_DBG_AZ_REQ_CP (1 << DBG_AZ_REQ_CP_SHIFT)
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/* State define of DBG_ARBITER_STATE */
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#define ARBITER_ST_IDLE (1 << 0)
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#define ARBITER_ST_INIT (1 << 1)
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#define ARBITER_ST_CHECK (1 << 2)
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#define ARBITER_ST_STAY (1 << 3)
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/* State define of DBG_CORE_STATE */
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#define CORE_FSM_ST_IDLE (1 << 0)
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#define CORE_FSM_ST_INIT (1 << 1)
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#define CORE_FSM_ST_WAIT_SEMA (1 << 2)
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#define CORE_FSM_ST_DECODE (1 << 3)
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#define CORE_FSM_ST_DATA (1 << 4)
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#define CORE_FSM_ST_DONE (1 << 5)
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/* State define of DBG_AZ_STATE */
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#define AZ_FSM_ST_IDLE (0 << 0)
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#define AZ_FSM_ST_INIT (1 << 0)
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#define AZ_FSM_ST_END (1 << 1)
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#define AZ_FSM_ST_INT_SET (1 << 2)
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#define AZ_FSM_ST_IP_SEL (1 << 3)
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#define AZ_FSM_ST_START (1 << 4)
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#define AZ_FSM_ST_WAIT (1 << 5)
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#define AZ_FSM_ST_DONE (1 << 6)
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#define AZ_FSM_ST_ERROR (1 << 7)
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#define AZ_FSM_ST_SW_RESET (1 << 8)
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#define AZ_FSM_ST_SW_RESET_WAIT (1 << 9)
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#define AZ_FSM_ST_SW_RESET_CNT_INIT (1 << 10)
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#define AZ_FSM_ST_PKE_INT_SET (1 << 11)
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#define AZ_FSM_ST_PKE_SEL (1 << 12)
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/* counter definition for debugging */
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#define HW_SEMA_MEC_DBG_REQ_CANCLE_CNT_AP_MASK (0xFFFFFFFF)
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#define HW_SEMA_MEC_DBG_REQ_CANCLE_CNT_CP_MASK (0xFFFFFFFF)
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#define HW_SEMA_MEC_DBG_REQ_PERIOD_CNT_AP_MASK (0xFFFFFFFF)
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#define HW_SEMA_MEC_DBG_REQ_PERIOD_CNT_CP_MASK (0xFFFFFFFF)
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#define HW_SEMA_MEC_DBG_TO_CNT_AP_MASK (0xFFFFFFFF)
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#define HW_SEMA_MEC_DBG_TO_CNT_CP_MASK (0xFFFFFFFF)
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#endif
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