129 lines
3.6 KiB
C
Executable file
129 lines
3.6 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Samsung Exynos SoC series dsp driver
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*
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* Copyright (c) 2019 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*/
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#ifndef __HW_P0_DSP_HW_P0_MEMORY_H__
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#define __HW_P0_DSP_HW_P0_MEMORY_H__
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#include "dsp-memory.h"
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#define DSP_P0_MEMORY_MAX_SIZE (SZ_16M)
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#define DSP_P0_FW_EXTENSION "bin"
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#define DSP_P0_MASTER_FW_NAME "dsp_master" // master boot + stack
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#define DSP_P0_MASTER_FW_IOVA (0x30000000)
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#define DSP_P0_MASTER_FW_SIZE (SZ_1M)
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#define DSP_P0_FW_NAME "dsp"
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#define DSP_P0_FW_IOVA (0x30100000)
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#define DSP_P0_FW_SIZE (SZ_1M * 8)
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#define DSP_P0_DHCP_MEM_IOVA (0x31000000)
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#define DSP_P0_DHCP_MEM_SIZE (SZ_4K)
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#define DSP_P0_FW_LOG_IOVA (DSP_P0_DHCP_MEM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_FW_LOG_SIZE (SZ_1M)
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#define DSP_P0_IVP_PM_NAME "dsp_ivp_pm"
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#define DSP_P0_IVP_PM_IOVA (DSP_P0_FW_LOG_IOVA + DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_IVP_PM_SIZE (SZ_16M)
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#define DSP_P0_IVP_DM_NAME "dsp_ivp_dm"
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#define DSP_P0_IVP_DM_IOVA (DSP_P0_IVP_PM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_IVP_DM_SIZE (SZ_128K)
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#define DSP_P0_MBOX_MEMORY_IOVA (DSP_P0_IVP_DM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_MBOX_MEMORY_SIZE (SZ_8K)
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#define DSP_P0_MBOX_POOL_IOVA (DSP_P0_MBOX_MEMORY_IOVA + \
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DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_MBOX_POOL_SIZE (SZ_128K)
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#define DSP_P0_DL_OUT_IOVA (DSP_P0_MBOX_POOL_IOVA + DSP_P0_MEMORY_MAX_SIZE)
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#define DSP_P0_DL_OUT_SIZE (SZ_1M)
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#define DSP_P0_HW_BASE_ADDR (0x20000000)
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#define DSP_P0_SM_BASE_ADDR (0x120100)
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#define DSP_P0_SM(n) (DSP_P0_SM_BASE_ADDR + (n) * 4)
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#define DSP_P0_DHCP_IDX(n) (0x4 * (n))
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#define DSP_P0_SM_USERDEFINED_COUNT (64)
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#define DSP_P0_SM_USERDEFINED_SIZE (SZ_4 * DSP_P0_SM_USERDEFINED_COUNT)
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#define DSP_P0_SM_USERDEFINED_BASE (DSP_P0_SM(0))
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#define DSP_P0_SM_USERDEFINED(n) (DSP_P0_SM_USERDEFINED_BASE + 0x4 * (n))
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#define DSP_P0_SM_FW_INFO_COUNT (192)
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#define DSP_P0_SM_FW_INFO_SIZE (SZ_4 * DSP_P0_SM_FW_INFO_COUNT)
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#define DSP_P0_SM_FW_INFO_BASE (DSP_P0_SM(DSP_P0_SM_USERDEFINED_COUNT))
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#define DSP_P0_SM_FW_INFO(n) (DSP_P0_SM_FW_INFO_BASE + 0x4 * (n))
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enum dsp_p0_dhcp_used_count {
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DSP_P0_DHCP_TO_CC_MBOX = 0,
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DSP_P0_DHCP_TO_HOST_MBOX = 8,
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DSP_P0_DHCP_LOG_QUEUE = 16,
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DSP_P0_DHCP_TO_CC_INT_STATUS = 24,
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DSP_P0_DHCP_TO_HOST_INT_STATUS,
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DSP_P0_DHCP_FW_RESERVED_SIZE,
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DSP_P0_DHCP_IVP_PM_IOVA,
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DSP_P0_DHCP_RESERVED0,
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DSP_P0_DHCP_RESERVED1,
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DSP_P0_DHCP_RESERVED2,
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DSP_P0_DHCP_IVP_PM_SIZE,
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DSP_P0_DHCP_IVP_DM_IOVA,
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DSP_P0_DHCP_IVP_DM_SIZE,
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DSP_P0_DHCP_RESERVED3,
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DSP_P0_DHCP_RESERVED4,
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DSP_P0_DHCP_RESERVED5,
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DSP_P0_DHCP_RESERVED6,
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DSP_P0_DHCP_MAILBOX_VERSION,
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DSP_P0_DHCP_MESSAGE_VERSION,
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DSP_P0_DHCP_FW_LOG_MEMORY_IOVA,
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DSP_P0_DHCP_FW_LOG_MEMORY_SIZE,
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DSP_P0_DHCP_TO_CC_MBOX_MEMORY_IOVA,
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DSP_P0_DHCP_TO_CC_MBOX_MEMORY_SIZE,
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DSP_P0_DHCP_TO_CC_MBOX_POOL_IOVA,
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DSP_P0_DHCP_TO_CC_MBOX_POOL_SIZE,
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DSP_P0_DHCP_NPU_FW_IOVA,
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DSP_P0_DHCP_KERNEL_MODE,
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DSP_P0_DHCP_DL_OUT_IOVA,
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DSP_P0_DHCP_DL_OUT_SIZE,
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DSP_P0_DHCP_DEBUG_LAYER_START,
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DSP_P0_DHCP_DEBUG_LAYER_END,
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DSP_P0_DHCP_CHIPID_REV,
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DSP_P0_DHCP_PRODUCT_ID,
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DSP_P0_DHCP_DNC_FREQUENCY,
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DSP_P0_DHCP_DSP_FREQUENCY,
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DSP_P0_DHCP_RESERVED7,
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DSP_P0_DHCP_RESERVED8,
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DSP_P0_DHCP_INTERRUPT_MODE,
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DSP_P0_DHCP_DRIVER_VERSION,
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DSP_P0_DHCP_FIRMWARE_VERSION,
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DSP_P0_DHCP_USED_COUNT,
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};
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enum dsp_p0_priv_mem_id {
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DSP_P0_PRIV_MEM_FW,
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DSP_P0_PRIV_MEM_DHCP,
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DSP_P0_PRIV_MEM_FW_LOG,
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DSP_P0_PRIV_MEM_IVP_PM,
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DSP_P0_PRIV_MEM_IVP_DM,
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DSP_P0_PRIV_MEM_MBOX_MEMORY,
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DSP_P0_PRIV_MEM_MBOX_POOL,
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DSP_P0_PRIV_MEM_DL_OUT,
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DSP_P0_PRIV_MEM_COUNT,
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};
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enum dsp_p0_reserved_mem_id {
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DSP_P0_RESERVED_MEM_FW_MASTER,
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DSP_P0_RESERVED_MEM_COUNT,
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};
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int dsp_hw_p0_memory_register_ops(void);
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#endif
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