218 lines
5.8 KiB
C
Executable file
218 lines
5.8 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __EXYNOS_SCI_DBG_H_
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#define __EXYNOS_SCI_DBG_H_
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#include <linux/time.h>
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#define EXYNOS_SCI_DBG_MODULE_NAME "exynos-sci_dbg"
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#define LLC_DSS_NAME "log_llc"
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#define BCM_ESS_NAME "log_bcm"
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#define LLC_DUMP_DATA_Q_SIZE 8
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#define LLC_SLICE_END (0x1)
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#define LLC_BANK_END (0x1)
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#define LLC_SET_END (0x1FF)
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#define LLC_WAY_END (0xF)
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#define LLC_QWORD_END (0x7)
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#define LLC_ID_MAX 8
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#define SCI_BASE 0x1A000000
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#define ArrDbgCntl 0x05C
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#define ArrDbgRDataHi 0x06C
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#define ArrDbgRDataMi 0x070
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#define ArrDbgRDataLo 0x074
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#define CCMControl1 0x0A8
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#define PM_SCI_DBG_CTL 0x140
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#define LLCControl 0x544
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#define LLCId_0 0x5C0
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#define LLCIdAllocLkup_0 0x5C4
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#define LLCAddrMatch 0x4C0
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#define LLCAddrMask 0x4C4
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#if defined(CONFIG_SOC_S5E9925_EVT0)
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#define DebugSrc10_offset 0x2C0
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#define DebugSrc32_offset 0x2C4
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#define DebugCtrl_offset 0x2D4
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#else
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#define DebugSrc10_offset 0x2C4
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#define DebugSrc32_offset 0x2C8
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#define DebugCtrl_offset 0x2DC
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#endif
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#define SMC_MIF0_BASE 0x1C03F000
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#define SMC_MIF1_BASE 0x1C13F000
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#define SMC_MIF2_BASE 0x1C23F000
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#define SMC_MIF3_BASE 0x1C33F000
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#define SYSREG_MIF0_BASE 0x1C020000
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#define SYSREG_MIF1_BASE 0x1C120000
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#define SYSREG_MIF2_BASE 0x1C220000
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#define SYSREG_MIF3_BASE 0x1C320000
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#define PPC_DEBUG0_BASE 0x1C050000
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#define PPC_DEBUG1_BASE 0x1C150000
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#define PPC_DEBUG2_BASE 0x1C250000
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#define PPC_DEBUG3_BASE 0x1C350000
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#define PPC_DEBUG_CCI 0x1A230000
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#define SYSREG_CORE_PPC_BASE 0x1A021000
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#if defined(CONFIG_SOC_S5E9925_EVT0)
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#define TREX_IRPS0_BASE 0x1A8F4000
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#define TREX_IRPS1_BASE 0x1A904000
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#define TREX_IRPS2_BASE 0x1A914000
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#define TREX_IRPS3_BASE 0x1A924000
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#else
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#define TREX_IRPS0_BASE 0x1A904000
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#define TREX_IRPS1_BASE 0x1A914000
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#define TREX_IRPS2_BASE 0x1A924000
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#define TREX_IRPS3_BASE 0x1A934000
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#endif
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#define LLC_USER_CONFIG_MATCH 0x400
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#define LLC_USER_CONFIG_USER 0x404
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#define CACHEAID_BASE 0x1A300000
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#define CACHEAID_USER 0x100
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#define CACHEAID_CTRL 0x104
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#define CACHEAID_GLOBAL_CTRL 0x0
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#define CACHEAID_DEFAULT_CTRL 0x10
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#define CACHEAID_PMU_ACCESS_CTRL 0x20
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#define CACHEAID_PMU_ACCESS_INFO 0x24
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/* SCI_PPC_WRAPPER offset */
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#define SCI_PPC_PMNC 0x4
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#define SCI_PPC_CNTENS 0x8
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#define SCI_PPC_INTENS 0x10
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#define SCI_PPC_FLAG 0x18
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#define SCI_PPC_PMCNT0_LOW 0x34
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#define SCI_PPC_PMCNT1_LOW 0x38
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#define SCI_PPC_PMCNT2_LOW 0x3C
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#define SCI_PPC_PMCNT3_LOW 0x40
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#define SCI_PPC_CCNT_LOW 0x48
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/* SMC_PPC_WRAPPER offset */
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#define SMC_PPC_PMNC 0x4
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#define SMC_PPC_CNTENS 0x8
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#define SMC_PPC_CCNT 0x2C
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#define SMC_PPC_CCNT_LOW 0x0048
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#define SMC_PPC_CCNT_HIGH 0x0058
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#define SMC_PPC_PMCNT0 0x0034
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#define SMC_PPC_PMCNT1 0x0038
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#define SMC_PPC_PMCNT2 0x003C
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#define SMC_PPC_PMCNT3 0x0040
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#define SMC_PPC_PMCNT4 0x00B4
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#define SMC_PPC_PMCNT5 0x00B8
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#define SMC_PPC_PMCNT6 0x00BC
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#define SMC_PPC_PMCNT7 0x00C0
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/* SMC_ALL_BASE offset */
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#define SMC_DBG_BLK_CTL0 0x294
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#define SMC_DBG_BLK_CTL1 0x298
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#define SMC_DBG_BLK_CTL2 0x29C
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#define SMC_DBG_BLK_CTL3 0x2A0
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#define SMC_DBG_BLK_CTL4 0x2A4
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#define SMC_DBG_BLK_CTL5 0x2A8
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#define SMC_DBG_BLK_CTL6 0x2AC
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#define SMC_DBG_BLK_CTL7 0x2B0
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#define SMC_DBG_BLK_CTL8 0x2B4
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#define SMC_DBG_BLK_CTL(x) (SMC_DBG_BLK_CTL0 + ((x)*4))
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#define SMC_GLOBAL_DBG_CTL 0x290
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#define SMC_SPARE_CFG_CTL 0x48C
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#define LLC_En_Bit (25)
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#define DisableLlc_Bit (9)
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#define NUM_OF_SMC_DBG_BLK_CTL (9)
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#define NUM_OF_SYSREG_MIF (4)
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/* IPC common definition */
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#define SCI_DBG_ONE_BIT_MASK (0x1)
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#define SCI_DBG_ERR_MASK (0x7)
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#define SCI_DBG_ERR_SHIFT (13)
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#define SCI_DBG_CMD_IDX_MASK (0x3F)
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#define SCI_DBG_CMD_IDX_SHIFT (0)
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#define SCI_DBG_DATA_MASK (0x3F)
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#define SCI_DBG_DATA_SHIFT (6)
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#define SCI_DBG_IPC_DIR_SHIFT (12)
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#define SCI_DBG_CMD_GET(cmd_data, mask, shift) ((cmd_data & (mask << shift)) >> shift)
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#define SCI_DBG_CMD_CLEAR(mask, shift) (~(mask << shift))
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#define SCI_DBG_CMD_SET(data, mask, shift) ((data & mask) << shift)
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#define SCI_DBG_DBGGEN
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#ifdef SCI_DBG_DBGGEN
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#define SCI_DBG_DBG(x...) pr_info("sci_dbg_dbg: " x)
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#else
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#define SCI_DBG_DBG(x...) do {} while (0)
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#endif
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#define SCI_DBG_INFO(x...) pr_info("sci_dbg_info: " x)
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#define SCI_DBG_ERR(x...) pr_err("sci_dbg_err: " x)
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struct exynos_ppc_dump_addr {
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u32 p_addr;
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u32 p_size;
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};
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struct exynos_sci_dbg_dump_addr {
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u32 p_addr;
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u32 p_size;
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u32 buff_size;
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void __iomem *v_addr;
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void __iomem *cnt_sfr_base;
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void __iomem *trex_core_base;
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void __iomem *sci_base;
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void __iomem *smc_base;
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void __iomem *sysreg_mif_base[4];
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void __iomem *smc_mif_base[4];
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void __iomem *ppc_dbg_base[4];
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void __iomem *trex_irps_base[4];
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void __iomem *debug_base;
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};
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struct exynos_sci_dbg_dump_data {
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u32 index;
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u64 time;
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u32 count[5];
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} __attribute__((packed));
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struct exynos_smc_dump_data {
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u32 index;
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u32 smc_ch;
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u64 time;
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u32 count[10];
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} __attribute__((packed));
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struct exynos_sci_dbg_data {
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struct device *dev;
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spinlock_t lock;
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struct exynos_sci_dbg_dump_addr dump_addr;
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struct exynos_sci_dbg_dump_data dump_data;
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bool dump_enable;
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struct hrtimer hrtimer;
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struct exynos_smc_dump_data smc_dump_data[4];
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bool smc_dump_enable;
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struct hrtimer smc_hrtimer;
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void __iomem *sci_base;
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void __iomem *cacheaid_base;
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};
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bool get_exynos_sci_llc_debug_mode(void);
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extern void smc_ppc_enable(unsigned int enable);
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extern void sci_ppc_enable(unsigned int enable);
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extern struct platform_driver exynos_sci_dbg_driver;
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#endif /* __EXYNOS_SCI_DBG_H_ */
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