166 lines
5.7 KiB
C
Executable file
166 lines
5.7 KiB
C
Executable file
/* include/uapi/linux/hwmcfrc.h
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*
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* Userspace API for Samsung MCFRC driver
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*
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* Copyright (c) 2020 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Igor Kovliga <i.kovliga@samsung.com>
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* Sergei Ilichev <s.ilichev@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __HWMCFRC_H__
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#define __HWMCFRC_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#ifndef __cplusplus
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#include <stdbool.h>
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#endif
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/*
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* NOTE: THESE ENUMS ARE ALSO USED BY USERSPACE TO SPECIFY SETTINGS AND THEY'RE
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* SUPPOSED TO WORK WITH FUTURE HARDWARE AS WELL (WHICH MAY OR MAY NOT
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* SUPPORT ALL THE SETTINGS.
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*
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* FOR THAT REASON, YOU MUST NOT CHANGE THE ORDER OF VALUES,
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* AND NEW VALUES MUST BE ADDED AT THE END OF THE ENUMS TO AVOID
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* API BREAKAGES.
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*/
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#define MCFRC_DBG_MODE (0)
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/**
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* @brief The available MC FRC functions
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*/
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enum hwMCFRC_processing_mode {
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MCFRC_MODE_FULL_CURR = 0, /**< full interpolation mode (fill curr by timeout)*/
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MCFRC_MODE_FALL_CURR = 1, /**< copy mode - fallback previous frame*/
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MCFRC_MODE_FULL_PREV = 2, /**< full interpolation mode (fill prev by timeout)*/
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MCFRC_MODE_FALL_PREV = 3 /**< copy mode - fallback current frame*/
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};
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/**
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* @brief the image format and size
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*/
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struct hwMCFRC_img_info {
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__u32 height; /**< height of the image (luma component)*/
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__u32 width; /**< width of the image (luma component)*/
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__u32 stride; /**< stride of the image (luma component)*/
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__u32 height_uv; /**< height of the image (chroma component)*/
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__u32 width_uv; /**< width of the image (chroma component)*/
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__u32 offset; /**< width of the image (chroma component)*/
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__u32 offset_uv; /**< width of the image (chroma component)*/
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//__u32 stride_uv; /**< stride of the image (chroma component)*/
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};
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/**
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* @brief the type of the buffer sent to the driver
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*/
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enum hwMCFRC_buffer_type {
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HWMCFRC_BUFFER_NONE, /**< no buffer is set */
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HWMCFRC_BUFFER_DMABUF, /**< DMA buffer */
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HWMCFRC_BUFFER_USERPTR /**< a pointer to user memory */
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};
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/**
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* @brief the struct holding the description of a buffer
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*
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* A buffer can either be represented by a DMA file descriptor OR by a pointer
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* to user memory. The len must be initialized with the size of the buffer,
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* and the type must be set to the correct type.
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*/
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struct hwMCFRC_buffer {
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union {
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__s32 fd; /**< the DMA file descriptor, if the buffer is a DMA buffer. This is in a union with userptr, only one should be set. */
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unsigned long userptr; /**< the ptr to user memory, if the buffer is in user memory. This is in a union with fd, only one should be set. */
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};
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size_t len; /**< the declared buffer length, in bytes */
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__u8 type; /**< the declared buffer type @sa hwMCFRC_buffer_type */
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};
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/**
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* @brief parameters for HW processing
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*
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* The fields needs to be explicitly set by userspace to the desired values,
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* using the corresponding enumerations.
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*/
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struct hwMCFRC_config {
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enum hwMCFRC_processing_mode mode; /**< mode of MC FRC */
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__u32 phase; /**< phase parameter of MC FRC */
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__u32 dbl_on; /**< switching deblock of MC FRC */
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};
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#define REG_COMMAND_TYPE_READ (0x1<<0)
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#define REG_COMMAND_TYPE_WRITE (0x1<<1)
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#define REG_COMMAND_TYPE_END (0x1<<31)
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struct hwMCFRC_reg_command {
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__u32 type;
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__u32 address;
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__u32 data_write;
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__u32 data_read;
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};
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#define HWMCFRC_REG_PROGRAMM_MAX_LEN (64)
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struct hwMCFRC_reg_programm {
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struct hwMCFRC_reg_command command[HWMCFRC_REG_PROGRAMM_MAX_LEN];
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};
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#define RESULTS_LEN (64)
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/**
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* @brief the task information to be sent to the driver
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*
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* This is the struct holding all the task information that the driver needs
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* to process a task.
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*
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* The client needs to fill it in with the necessary information and send it
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* to the driver through the IOCTL.
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*/
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struct hwMCFRC_task {
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struct hwMCFRC_img_info img_markup; /**< info related to the image sent to the HW for processing */
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struct hwMCFRC_buffer buf_inout[5]; /**< info related to the buffer sent to the HW for processing: in1, in2, out, params, temp*/
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struct hwMCFRC_config config; /**< the configuration for HW IP */
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__u32 results[RESULTS_LEN];
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#if MCFRC_DBG_MODE // remove debug parameters
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/* for debugging purposes*/
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__u32 dbg_control_flags;
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struct hwMCFRC_reg_programm programms[5];
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#endif
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};
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#define DBG_CONTROL_FLAG_0 (1<<0)
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#define DBG_CONTROL_FLAG_1 (1<<1)
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#define DBG_CONTROL_FLAG_2 (1<<2)
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#define DBG_CONTROL_FLAG_3 (1<<3)
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#define DBG_CONTROL_FLAG_4 (1<<4)
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#define DBG_CONTROL_FLAG_5 (1<<5)
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#define DBG_CONTROL_FLAG_6 (1<<6)
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#define DBG_CONTROL_FLAG_7 (1<<7)
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#define DBG_CONTROL_FLAG_8 (1<<8)
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#define DBG_CONTROL_FLAG_9 (1<<9)
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#define DBG_CONTROL_FLAG_10 (1<<10)
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#define DBG_CONTROL_FLAG_11 (1<<11)
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#define DBG_CONTROL_FLAG_12 (1<<12)
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#define DBG_CONTROL_FLAG_13 (1<<13)
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#define DBG_CONTROL_FLAG_14 (1<<14)
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#define DBG_CONTROL_FLAG_15 (1<<15)
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#define HWMCFRC_IOC_PROCESS _IOWR('M', 0, struct hwMCFRC_task)
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#define HWMCFRC_IOC_PROCESS_DBG_01 _IOWR('M', 1, struct hwMCFRC_task)
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#define HWMCFRC_IOC_PROCESS_DBG_02 _IOWR('M', 2, struct hwMCFRC_task)
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#define HWMCFRC_IOC_PROCESS_DBG_03 _IOWR('M', 3, struct hwMCFRC_task)
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#define HWMCFRC_IOC_PROCESS_DBG_04 _IOWR('M', 4, struct hwMCFRC_task)
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#define HWMCFRC_IOC_PROCESS_DBG_05 _IOWR('M', 5, struct hwMCFRC_task)
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#endif // __HWMCFRC_H__
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