Gabor Juhos ca185b2a86 clk: qcom: gcc-qcs404: fix initial rate of GPLL3 ... commit 36d202241d234fa4ac50743510d098ad52bd193a upstream. The comment before the config of the GPLL3 PLL says that the PLL should run at 930 MHz. In contrary to this, calculating the frequency from the current configuration values by using 19.2 MHz as input frequency defined in 'qcs404.dtsi', it gives 921.6 MHz: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x0 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 921600000.00000000000000000000 Set 'alpha_hi' in the configuration to a value used in downstream kernels [1][2] in order to get the correct output rate: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x70 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 930000000.00000000000000000000 The change is based on static code analysis, compile tested only. [1] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/kernel.lnx.5.4.r56-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L335 [2} https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r49-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L127 Cc: stable@vger.kernel.org Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20241022-fix-gcc-qcs404-gpll3-v1-1-c4d30d634d19@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2024-12-17 13:20:50 +01:00
..
a53-pll.c
apcs-msm8916.c
apss-ipq-pll.c
apss-ipq6018.c
camcc-sdm845.c
clk-alpha-pll.c
clk-alpha-pll.h
clk-branch.c
clk-branch.h
clk-cpu-8996.c
clk-hfpll.c
clk-hfpll.h
clk-krait.c
clk-krait.h
clk-pll.c
clk-pll.h
clk-rcg.c
clk-rcg.h
clk-rcg2.c
clk-regmap-divider.c
clk-regmap-divider.h
clk-regmap-mux-div.c
clk-regmap-mux-div.h
clk-regmap-mux.c
clk-regmap-mux.h
clk-regmap.c
clk-regmap.h
clk-rpm.c
clk-rpmh.c	Revert "clk: qcom: clk-rpmh: Fix overflow in BCM vote"	2024-11-24 00:23:02 +01:00
clk-smd-rpm.c
clk-spmi-pmic-div.c
common.c
common.h
dispcc-sc7180.c
dispcc-sdm845.c
dispcc-sm8250.c	Revert "clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks"	2024-11-24 00:23:00 +01:00
gcc-apq8084.c
gcc-ipq806x.c
gcc-ipq4019.c
gcc-ipq6018.c
gcc-ipq8074.c
gcc-mdm9615.c
gcc-msm8660.c
gcc-msm8916.c
gcc-msm8939.c
gcc-msm8960.c
gcc-msm8974.c
gcc-msm8994.c
gcc-msm8996.c
gcc-msm8998.c
gcc-qcs404.c	clk: qcom: gcc-qcs404: fix initial rate of GPLL3	2024-12-17 13:20:50 +01:00
gcc-sc7180.c
gcc-sdm660.c
gcc-sdm845.c
gcc-sm8150.c
gcc-sm8250.c	Revert "clk: qcom: gcc-sm8250: Do not turn off PCIe GDSCs during gdsc_disable()"	2024-11-24 00:23:02 +01:00
gdsc.c
gdsc.h
gpucc-msm8998.c
gpucc-sc7180.c
gpucc-sdm845.c
gpucc-sm8150.c
gpucc-sm8250.c
hfpll.c
Kconfig
kpss-xcc.c
krait-cc.c
lcc-ipq806x.c
lcc-mdm9615.c
lcc-msm8960.c
lpasscc-sdm845.c
lpasscorecc-sc7180.c
Makefile
mmcc-apq8084.c
mmcc-msm8960.c
mmcc-msm8974.c
mmcc-msm8996.c
mmcc-msm8998.c
mss-sc7180.c
q6sstop-qcs404.c
reset.c
reset.h
turingcc-qcs404.c
videocc-sc7180.c
videocc-sdm845.c
videocc-sm8150.c
videocc-sm8250.c