559 lines
20 KiB
C
Executable file
559 lines
20 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
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*/
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#ifndef _UFS_CAL_TABLE_
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#define _UFS_CAL_TABLE_
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#define UFS_CAL_VER 0
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#include "ufs-cal-if.h"
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struct ufs_cal_phy_cfg {
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u32 mib;
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u32 addr;
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u32 val;
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u32 flg;
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u32 lyr;
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u8 board;
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};
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enum {
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PHY_CFG_NONE = 0,
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PHY_PCS_COMN,
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PHY_PCS_RXTX,
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PHY_PMA_COMN,
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PHY_PMA_TRSV,
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PHY_PLL_WAIT,
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PHY_CDR_WAIT,
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PHY_CDR_AFC_WAIT,
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UNIPRO_STD_MIB,
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UNIPRO_DBG_MIB,
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UNIPRO_DBG_APB,
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PHY_PCS_RX,
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PHY_PCS_TX,
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PHY_PCS_RX_PRD,
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PHY_PCS_TX_PRD,
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UNIPRO_DBG_PRD,
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PHY_PMA_TRSV_LANE1_SQ_OFF,
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PHY_PMA_TRSV_SQ,
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COMMON_WAIT,
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PHY_PCS_RX_LR_PRD,
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PHY_PCS_TX_LR_PRD,
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PHY_PCS_RX_PRD_ROUND_OFF,
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PHY_PCS_TX_PRD_ROUND_OFF,
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UNIPRO_ADAPT_LENGTH,
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PHY_EMB_CDR_WAIT,
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PHY_EMB_CAL_WAIT,
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HCI_AH8_THIBERN,
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HCI_AH8_REFCLKGATINGTING,
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HCI_AH8_ACTIVE_LANE,
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HCI_AH8_CMN,
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HCI_AH8_TRSV,
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HCI_STD,
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};
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enum {
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PMD_PWM_G1 = 0,
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PMD_PWM_G2,
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PMD_PWM_G3,
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PMD_PWM_G4,
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PMD_PWM_G5,
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PMD_PWM,
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PMD_HS_G1,
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PMD_HS_G2,
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PMD_HS_G3,
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PMD_HS_G4,
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PMD_HS,
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PMD_ALL,
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};
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#undef USE_38_4_MHZ
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#define USE_38_4_MHZ /* 38.4MHz */
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static struct ufs_cal_phy_cfg init_cfg_evt0[] = {
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/* mib(just to monitor), sfr offset, value, .. */
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{0x0000, 0x44, 0x00, PMD_ALL, UNIPRO_DBG_PRD, BRD_ALL},
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{0x200, 0x2800, 0x40, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#ifdef USE_38_4_MHZ /* 38.4MHz */
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{0x202, 0x2808, 0x22, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#else /* 26MHz */
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{0x202, 0x2808, 0x12, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#endif
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{0x12, 0x2048, 0x00, PMD_ALL, PHY_PCS_RX_PRD_ROUND_OFF, BRD_ALL},
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{0xAA, 0x22A8, 0x00, PMD_ALL, PHY_PCS_TX_PRD_ROUND_OFF, BRD_ALL},
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{0xA9, 0x22A4, 0x02, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0xAB, 0x22AC, 0x00, PMD_ALL, PHY_PCS_TX_LR_PRD, BRD_ALL},
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{0x11, 0x2044, 0x00, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x1B, 0x206C, 0x00, PMD_ALL, PHY_PCS_RX_LR_PRD, BRD_ALL},
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{0x2F, 0x20BC, 0x79, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x84, 0x2210, 0x01, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x04, 0x2010, 0x01, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0x25, 0x2094, 0xF6, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x7F, 0x21FC, 0x00, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0x200, 0x2800, 0x0, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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{0x155E, 0x3178, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x3000, 0x5000, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x3001, 0x5004, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x4021, 0x6084, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x4020, 0x6080, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x0000, 0x140, 0x08, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x014, 0x29, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x064, 0x34, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x11C, 0x14, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x150, 0x88, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x804, 0x44, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x808, 0x44, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x80C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x810, 0x18, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x814, 0xC0, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x81C, 0x1C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xBB0, 0x8C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xBB8, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xA24, 0x60, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8CC, 0x15, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8D0, 0x30, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8D4, 0x77, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8D8, 0x77, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8DC, 0x05, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8E0, 0x61, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8E4, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8E8, 0x40, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8EC, 0x77, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8F0, 0xFF, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8F4, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8F8, 0x40, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8FC, 0x1B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x900, 0x1B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x904, 0x1B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x908, 0x6C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x934, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x938, 0x12, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x93C, 0x5E, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x960, 0x22, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x964, 0x28, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x968, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x96C, 0x07, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x970, 0x3F, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x974, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x978, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x97C, 0x22, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x980, 0x50, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x98C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x990, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x994, 0x22, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x998, 0x50, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAAC, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAB0, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xABC, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAC0, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAC4, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAC8, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xACC, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAD0, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x140, 0x0C, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x140, 0x00, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0xC74, 0x01, PMD_ALL, PHY_EMB_CAL_WAIT, BRD_ALL},
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{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
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};
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static struct ufs_cal_phy_cfg init_cfg_evt1[] = {
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/* mib(just to monitor), sfr offset, value, .. */
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{0x0000, 0x44, 0x00, PMD_ALL, UNIPRO_DBG_PRD, BRD_ALL},
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{0x200, 0x2800, 0x40, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#ifdef USE_38_4_MHZ /* 38.4MHz */
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{0x202, 0x2808, 0x22, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#else /* 26MHz */
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{0x202, 0x2808, 0x12, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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#endif
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{0x12, 0x2048, 0x00, PMD_ALL, PHY_PCS_RX_PRD_ROUND_OFF, BRD_ALL},
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{0xAA, 0x22A8, 0x00, PMD_ALL, PHY_PCS_TX_PRD_ROUND_OFF, BRD_ALL},
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{0xA9, 0x22A4, 0x02, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0xAB, 0x22AC, 0x00, PMD_ALL, PHY_PCS_TX_LR_PRD, BRD_ALL},
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{0x11, 0x2044, 0x00, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x1B, 0x206C, 0x00, PMD_ALL, PHY_PCS_RX_LR_PRD, BRD_ALL},
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{0x2F, 0x20BC, 0x79, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x84, 0x2210, 0x01, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x04, 0x2010, 0x01, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0x25, 0x2094, 0xF6, PMD_ALL, PHY_PCS_RX, BRD_ALL},
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{0x7F, 0x21FC, 0x00, PMD_ALL, PHY_PCS_TX, BRD_ALL},
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{0x200, 0x2800, 0x0, PMD_ALL, PHY_PCS_COMN, BRD_ALL},
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{0x155E, 0x3178, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x3000, 0x5000, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x3001, 0x5004, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x4021, 0x6084, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x4020, 0x6080, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x0000, 0x140, 0x08, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x014, 0x39, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x02C, 0x44, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x030, 0xC4, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x034, 0xC3, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x03C, 0x88, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x058, 0x1A, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x064, 0x34, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x150, 0x88, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x19C, 0x4C, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x1A0, 0x4C, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x804, 0x44, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x808, 0x44, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x80C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x810, 0x18, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x814, 0xC0, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x81C, 0x1C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xBB0, 0x8C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x9F0, 0xD0, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xA20, 0xFA, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xA24, 0x60, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8D0, 0x30, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8E4, 0x05, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x8F4, 0x05, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x934, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x938, 0x12, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x93C, 0x5E, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAAC, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0xAB0, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
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{0x0000, 0x140, 0x0C, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0x140, 0x00, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
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{0x0000, 0xC74, 0x01, PMD_ALL, PHY_EMB_CAL_WAIT, BRD_ALL},
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{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
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};
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static struct ufs_cal_phy_cfg post_init_cfg_evt0[] = {
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/* mib(just to monitor), sfr offset, value, .. */
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{0x15D2, 0x3348, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL},
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{0x15D3, 0x334C, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL},
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{0x9529, 0x38A4, 0x01, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL},
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{0x15A4, 0x3290, 0x3E8, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x9529, 0x38A4, 0x00, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL},
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{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
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};
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static struct ufs_cal_phy_cfg post_init_cfg_evt1[] = {
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/* mib(just to monitor), sfr offset, value, .. */
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{0x15D2, 0x3348, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL},
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{0x15D3, 0x334C, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL},
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{0x9529, 0x38A4, 0x01, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL},
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{0x15A4, 0x3290, 0x3E8, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL},
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{0x9529, 0x38A4, 0x00, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL},
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{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
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};
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static struct ufs_cal_phy_cfg calib_of_pwm[] = {
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/* mib(just to monitor), sfr offset, value, .. */
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{0x2041, 0x4104, 8064, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x2042, 0x4108, 28224, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x2043, 0x410C, 20160, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x15B0, 0x32C0, 12000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x15B1, 0x32C4, 32000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x15B2, 0x32C8, 16000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL},
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{0x0000, 0x7888, 8064, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
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{0x0000, 0x788C, 28224, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
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{0x0000, 0x7890, 20160, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
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{0x0000, 0x78B8, 12000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
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{0x0000, 0x78BC, 32000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78C0, 16000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_pwm[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg calib_of_hs_rate_a[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x15D4, 0x3350, 0x1, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
|
|
{0x2041, 0x4104, 8064, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x2042, 0x4108, 28224, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x2043, 0x410C, 20160, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B0, 0x32C0, 12000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B1, 0x32C4, 32000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B2, 0x32C8, 16000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
|
|
{0x0000, 0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_hs_rate_a[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg calib_of_hs_rate_b[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x15D4, 0x3350, 0x1, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
|
|
{0x2041, 0x4104, 8064, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x2042, 0x4108, 28224, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x2043, 0x410C, 20160, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B0, 0x32C0, 12000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B1, 0x32C4, 32000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
{0x15B2, 0x32C8, 16000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL},
|
|
|
|
{0x0000, 0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
{0x0000, 0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_hs_rate_b[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_ah8_cfg_evt0[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x504, 0x00, PMD_HS, HCI_AH8_THIBERN, BRD_ALL},
|
|
{0x0000, 0x508, 0x00, PMD_HS, HCI_AH8_REFCLKGATINGTING, BRD_ALL},
|
|
{0x0000, 0x51C, 0x00, PMD_HS, HCI_AH8_ACTIVE_LANE, BRD_ALL},
|
|
{0x0000, 0x524, 0x35B60, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
// Retry Number & Access Number
|
|
{0x0000, 0x520, 0x130014, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
// need to lane# check
|
|
{0x0000, 0x610, 0x000009F4, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x650, 0x00000008, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x614, 0x00000A00, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x654, 0x0000003A, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x618, 0x00000B64, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x658, 0x00000030, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x61C, 0x00000B64, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x65C, 0x00000033, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
{0x0000, 0x690, 0x401E0000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x6D0, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x694, 0x000009F4, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6D4, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x698, 0x00000A00, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6D8, 0x00000030, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x69C, 0x00000B64, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6DC, 0x00000032, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x6A0, 0x00000B64, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6E0, 0x00000022, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_ah8_cfg_evt1[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x504, 0x00, PMD_HS, HCI_AH8_THIBERN, BRD_ALL},
|
|
{0x0000, 0x508, 0x00, PMD_HS, HCI_AH8_REFCLKGATINGTING, BRD_ALL},
|
|
{0x0000, 0x51C, 0x00, PMD_HS, HCI_AH8_ACTIVE_LANE, BRD_ALL},
|
|
{0x0000, 0x524, 0x35B60, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
// Retry Number & Access Number
|
|
{0x0000, 0x520, 0x120013, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
// need to lane# check
|
|
{0x0000, 0x610, 0x000009F4, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x650, 0x00000008, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x614, 0x00000A00, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x654, 0x0000003A, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x618, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x658, 0x00000051, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
{0x0000, 0x690, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x6D0, 0x00000011, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x694, 0x401E0000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x6D4, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x698, 0x000009F4, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6D8, 0x00000000, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
{0x0000, 0x69C, 0x00000A00, PMD_HS, HCI_AH8_TRSV, BRD_ALL},
|
|
{0x0000, 0x6DC, 0x00000030, PMD_HS, HCI_AH8_CMN, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg lane1_sq_off[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x9F4, 0x08, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, BRD_ALL},
|
|
{0x0000, 0xA00, 0x3A, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_h8_enter[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x9F4, 0x08, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL},
|
|
{0x0000, 0xA00, 0x3A, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL},
|
|
{0x0000, 0x000, 0x51, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
|
|
|
|
{0x0000, 0xB64, 0x30, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0xB64, 0x33, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg pre_h8_exit[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x000, 0x11, PMD_ALL, PHY_PMA_COMN, BRD_ALL},
|
|
{0x0000, 0x000, 0x0A, PMD_ALL, COMMON_WAIT, BRD_ALL},
|
|
{0x0000, 0x9F4, 0x00, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL},
|
|
{0x0000, 0xA00, 0x30, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL},
|
|
|
|
{0x0000, 0xB64, 0x32, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0xB64, 0x22, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_init[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0xB44, 0xA3, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0xA24, 0x24, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0x844, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0xA14, 0x58, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_set_1[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0xB44, 0xAB, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_set_2[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0xA14, 0x70, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0x920, 0x1C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg eom_prepare[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0x0000, 0x870, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0xB8C, 0xE3, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0x8C8, 0x33, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
{0x0000, 0x91C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0x0000, 0xB90, 0x14, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0x0000, 0x870, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL},
|
|
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg init_cfg_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_init_cfg_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg calib_of_pwm_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_pwm_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg calib_of_hs_rate_a_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_hs_rate_a_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg calib_of_hs_rate_b_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_calib_of_hs_rate_b_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg lane1_sq_off_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg post_h8_enter_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg pre_h8_exit_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_init_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_set_1_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
|
|
static struct ufs_cal_phy_cfg loopback_set_2_card[] = {
|
|
/* mib(just to monitor), sfr offset, value, .. */
|
|
{0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL}
|
|
};
|
|
#endif /* _UFS_CAL_TABLE_ */
|