5738327c02
[ Upstream commit 86f271f22bbb6391410a07e08d6ca3757fda01fa ] Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf Link: https://lore.kernel.org/linux-pci/16e1fcae-1ea7-46be-b157-096e05661b15@siemens.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Sasha Levin <sashal@kernel.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-dra7xx.c | ||
| pci-exynos.c | ||
| pci-imx6.c | ||
| pci-keystone.c | ||
| pci-layerscape-ep.c | ||
| pci-layerscape.c | ||
| pci-meson.c | ||
| pcie-al.c | ||
| pcie-armada8k.c | ||
| pcie-artpec6.c | ||
| pcie-designware-ep.c | ||
| pcie-designware-host.c | ||
| pcie-designware-plat.c | ||
| pcie-designware.c | ||
| pcie-designware.h | ||
| pcie-exynos-common.h | ||
| pcie-exynos-dbg.c | ||
| pcie-exynos-dbg.h | ||
| pcie-exynos-rc.c | ||
| pcie-exynos-rc.h | ||
| pcie-exynosS5E9925-rc-cal.c | ||
| pcie-exynosS5E9925-rc-cal_s5300.c | ||
| pcie-hisi.c | ||
| pcie-histb.c | ||
| pcie-intel-gw.c | ||
| pcie-kirin.c | ||
| pcie-qcom.c | ||
| pcie-spear13xx.c | ||
| pcie-tegra194.c | ||
| pcie-uniphier-ep.c | ||
| pcie-uniphier.c | ||