e8ca71be6c
[ Upstream commit 3fb0fdb3bbe7aed495109b3296b06c2409734023 ] On 32-bit kernels, the stackprotector canary is quite nasty -- it is stored at %gs:(20), which is nasty because 32-bit kernels use %fs for percpu storage. It's even nastier because it means that whether %gs contains userspace state or kernel state while running kernel code depends on whether stackprotector is enabled (this is CONFIG_X86_32_LAZY_GS), and this setting radically changes the way that segment selectors work. Supporting both variants is a maintenance and testing mess. Merely rearranging so that percpu and the stack canary share the same segment would be messy as the 32-bit percpu address layout isn't currently compatible with putting a variable at a fixed offset. Fortunately, GCC 8.1 added options that allow the stack canary to be accessed as %fs:__stack_chk_guard, effectively turning it into an ordinary percpu variable. This lets us get rid of all of the code to manage the stack canary GDT descriptor and the CONFIG_X86_32_LAZY_GS mess. (That name is special. We could use any symbol we want for the %fs-relative mode, but for CONFIG_SMP=n, gcc refuses to let us use any name other than __stack_chk_guard.) Forcibly disable stackprotector on older compilers that don't support the new options and turn the stack canary into a percpu variable. The "lazy GS" approach is now used for all 32-bit configurations. Also makes load_gs_index() work on 32-bit kernels. On 64-bit kernels, it loads the GS selector and updates the user GSBASE accordingly. (This is unchanged.) On 32-bit kernels, it loads the GS selector and updates GSBASE, which is now always the user base. This means that the overall effect is the same on 32-bit and 64-bit, which avoids some ifdeffery. [ bp: Massage commit message. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/c0ff7dba14041c7e5d1cae5d4df052f03759bef3.1613243844.git.luto@kernel.org Stable-dep-of: e3f269ed0acc ("x86/pm: Work around false positive kmemleak report in msr_build_context()") Signed-off-by: Sasha Levin <sashal@kernel.org>
163 lines
3.8 KiB
ArmAsm
Executable file
163 lines
3.8 KiB
ArmAsm
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright C 2016, Oracle and/or its affiliates. All rights reserved.
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*/
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.code32
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.text
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#define _pa(x) ((x) - __START_KERNEL_map)
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#include <linux/elfnote.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/asm.h>
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#include <asm/boot.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <xen/interface/elfnote.h>
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__HEAD
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/*
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* Entry point for PVH guests.
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*
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* Xen ABI specifies the following register state when we come here:
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*
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* - `ebx`: contains the physical memory address where the loader has placed
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* the boot start info structure.
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* - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
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* - `cr4`: all bits are cleared.
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* - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
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* and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
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* - `ds`, `es`: must be a 32-bit read/write data segment with a base of
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* ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all
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* unspecified.
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* - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
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* of '0x67'.
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* - `eflags`: bit 17 (VM) must be cleared. Bit 9 (IF) must be cleared.
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* Bit 8 (TF) must be cleared. Other bits are all unspecified.
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*
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* All other processor registers and flag bits are unspecified. The OS is in
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* charge of setting up it's own stack, GDT and IDT.
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*/
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#define PVH_GDT_ENTRY_CS 1
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#define PVH_GDT_ENTRY_DS 2
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#define PVH_CS_SEL (PVH_GDT_ENTRY_CS * 8)
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#define PVH_DS_SEL (PVH_GDT_ENTRY_DS * 8)
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SYM_CODE_START_LOCAL(pvh_start_xen)
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cld
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lgdt (_pa(gdt))
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mov $PVH_DS_SEL,%eax
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mov %eax,%ds
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mov %eax,%es
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mov %eax,%ss
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/* Stash hvm_start_info. */
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mov $_pa(pvh_start_info), %edi
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mov %ebx, %esi
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mov _pa(pvh_start_info_sz), %ecx
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shr $2,%ecx
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rep
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movsl
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mov $_pa(early_stack_end), %esp
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/* Enable PAE mode. */
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mov %cr4, %eax
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orl $X86_CR4_PAE, %eax
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mov %eax, %cr4
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#ifdef CONFIG_X86_64
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/* Enable Long mode. */
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mov $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* Enable pre-constructed page tables. */
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mov $_pa(init_top_pgt), %eax
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mov %eax, %cr3
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mov $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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/* Jump to 64-bit mode. */
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ljmp $PVH_CS_SEL, $_pa(1f)
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/* 64-bit entry point. */
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.code64
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1:
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/* Set base address in stack canary descriptor. */
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mov $MSR_GS_BASE,%ecx
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mov $_pa(canary), %eax
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xor %edx, %edx
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wrmsr
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call xen_prepare_pvh
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/* startup_64 expects boot_params in %rsi. */
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mov $_pa(pvh_bootparams), %rsi
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mov $_pa(startup_64), %rax
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jmp *%rax
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#else /* CONFIG_X86_64 */
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call mk_early_pgtbl_32
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mov $_pa(initial_page_table), %eax
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mov %eax, %cr3
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mov %cr0, %eax
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or $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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ljmp $PVH_CS_SEL, $1f
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1:
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call xen_prepare_pvh
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mov $_pa(pvh_bootparams), %esi
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/* startup_32 doesn't expect paging and PAE to be on. */
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ljmp $PVH_CS_SEL, $_pa(2f)
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2:
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mov %cr0, %eax
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and $~X86_CR0_PG, %eax
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mov %eax, %cr0
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mov %cr4, %eax
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and $~X86_CR4_PAE, %eax
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mov %eax, %cr4
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ljmp $PVH_CS_SEL, $_pa(startup_32)
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#endif
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SYM_CODE_END(pvh_start_xen)
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.section ".init.data","aw"
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.balign 8
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SYM_DATA_START_LOCAL(gdt)
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.word gdt_end - gdt_start
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.long _pa(gdt_start)
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.word 0
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SYM_DATA_END(gdt)
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SYM_DATA_START_LOCAL(gdt_start)
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.quad 0x0000000000000000 /* NULL descriptor */
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#ifdef CONFIG_X86_64
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.quad GDT_ENTRY(0xa09a, 0, 0xfffff) /* PVH_CS_SEL */
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#else
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.quad GDT_ENTRY(0xc09a, 0, 0xfffff) /* PVH_CS_SEL */
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#endif
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.quad GDT_ENTRY(0xc092, 0, 0xfffff) /* PVH_DS_SEL */
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SYM_DATA_END_LABEL(gdt_start, SYM_L_LOCAL, gdt_end)
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.balign 16
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SYM_DATA_LOCAL(canary, .fill 48, 1, 0)
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SYM_DATA_START_LOCAL(early_stack)
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.fill BOOT_STACK_SIZE, 1, 0
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SYM_DATA_END_LABEL(early_stack, SYM_L_LOCAL, early_stack_end)
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ELFNOTE(Xen, XEN_ELFNOTE_PHYS32_ENTRY,
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_ASM_PTR (pvh_start_xen - __START_KERNEL_map))
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