271 lines
10 KiB
C
Executable file
271 lines
10 KiB
C
Executable file
/*
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* s2mps24-private.h - Voltage regulator driver for the s2mps24
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*
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* Copyright (C) 2020 Samsung Electrnoics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __LINUX_MFD_S2MPS24_REGULATOR_EVT0_H
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#define __LINUX_MFD_S2MPS24_REGULATOR_EVT0_H
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/* PMIC Registers(EVT0) */
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#define S2MPS24_REG_INT1_EVT0 0x00
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#define S2MPS24_REG_INT2_EVT0 0x01
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#define S2MPS24_REG_INT3_EVT0 0x02
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#define S2MPS24_REG_INT4_EVT0 0x03
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#define S2MPS24_REG_INT5_EVT0 0x04
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#define S2MPS24_REG_INT1M_EVT0 0x05
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#define S2MPS24_REG_INT2M_EVT0 0x06
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#define S2MPS24_REG_INT3M_EVT0 0x07
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#define S2MPS24_REG_INT4M_EVT0 0x08
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#define S2MPS24_REG_INT5M_EVT0 0x09
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#define S2MPS24_REG_STATUS1_EVT0 0x0A
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#define S2MPS24_REG_STATUS2_EVT0 0x0B
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#define S2MPS24_REG_OFFSRC1_EVT0 0x0C
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#define S2MPS24_REG_OFFSRC2_EVT0 0x0D
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#define S2MPS24_REG_CTRL1_EVT0 0x12
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#define S2MPS24_REG_CTRL2_EVT0 0x13
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#define S2MPS24_REG_CTRL3_EVT0 0x14
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#define S2MPS24_REG_ETC_OTP1_EVT0 0x15
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#define S2MPS24_REG_ETC_OTP2_EVT0 0x16
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#define S2MPS24_REG_UVLO_OTP_EVT0 0x17
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#define S2MPS24_REG_CFG1_EVT0 0x18
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#define S2MPS24_REG_CFG2_EVT0 0x19
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#define S2MPS24_REG_BUCK1S_CTRL_EVT0 0x1A
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#define S2MPS24_REG_BUCK1S_OUT1_EVT0 0x1B
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#define S2MPS24_REG_BUCK1S_OUT2_EVT0 0x1C
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#define S2MPS24_REG_BUCK2S_CTRL_EVT0 0x1D
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#define S2MPS24_REG_BUCK2S_OUT1_EVT0 0x1E
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#define S2MPS24_REG_BUCK2S_OUT2_EVT0 0x1F
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#define S2MPS24_REG_BUCK3S_CTRL_EVT0 0x20
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#define S2MPS24_REG_BUCK3S_OUT1_EVT0 0x21
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#define S2MPS24_REG_BUCK3S_OUT2_EVT0 0x22
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#define S2MPS24_REG_BUCK4S_CTRL_EVT0 0x23
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#define S2MPS24_REG_BUCK4S_OUT1_EVT0 0x24
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#define S2MPS24_REG_BUCK4S_OUT2_EVT0 0x25
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#define S2MPS24_REG_BUCK5S_CTRL_EVT0 0x26
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#define S2MPS24_REG_BUCK5S_OUT1_EVT0 0x27
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#define S2MPS24_REG_BUCK5S_OUT2_EVT0 0x28
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#define S2MPS24_REG_BUCK6S_CTRL_EVT0 0x29
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#define S2MPS24_REG_BUCK6S_OUT1_EVT0 0x2A
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#define S2MPS24_REG_BUCK7S_CTRL_EVT0 0x2B
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#define S2MPS24_REG_BUCK7S_OUT1_EVT0 0x2C
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#define S2MPS24_REG_BUCK8S_CTRL_EVT0 0x2D
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#define S2MPS24_REG_BUCK8S_OUT1_EVT0 0x2E
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#define S2MPS24_REG_BB_CTRL_EVT0 0x2F
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#define S2MPS24_REG_BB_OUT_EVT0 0x30
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#define S2MPS24_REG_BUCK_DVS1_EVT0 0x31
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#define S2MPS24_REG_BUCK_DVS2_EVT0 0x32
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#define S2MPS24_REG_BUCK_DVS3_EVT0 0x33
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#define S2MPS24_REG_BUCK_DVS4_EVT0 0x34
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#define S2MPS24_REG_BUCK_DVS5_EVT0 0x35
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#define S2MPS24_REG_BUCK_DVS6_EVT0 0x36
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#define S2MPS24_REG_DVS_LDO1_CTRL_EVT0 0x37
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#define S2MPS24_REG_DVS_LDO2_CTRL_EVT0 0x38
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#define S2MPS24_REG_DVS_LDO3_CTRL_EVT0 0x39
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#define S2MPS24_REG_DVS_LDO22_CTRL_EVT0 0x3A
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#define S2MPS24_REG_LDO_RAMP1_EVT0 0X3B
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#define S2MPS24_REG_LDO1S_CTRL_EVT0 0x3C
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#define S2MPS24_REG_LDO2S_CTRL_EVT0 0x3D
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#define S2MPS24_REG_LDO3S_CTRL_EVT0 0x3E
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#define S2MPS24_REG_LDO4S_CTRL_EVT0 0x3F
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#define S2MPS24_REG_LDO5S_CTRL_EVT0 0x40
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#define S2MPS24_REG_LDO6S_CTRL_EVT0 0x41
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#define S2MPS24_REG_LDO7S_CTRL_EVT0 0x42
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#define S2MPS24_REG_LDO8S_CTRL_EVT0 0X43
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#define S2MPS24_REG_LDO9S_CTRL_EVT0 0X44
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#define S2MPS24_REG_LDO10S_CTRL_EVT0 0X45
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#define S2MPS24_REG_LDO11S_CTRL_EVT0 0X46
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#define S2MPS24_REG_LDO12S_CTRL_EVT0 0X47
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#define S2MPS24_REG_LDO13S_CTRL_EVT0 0X48
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#define S2MPS24_REG_LDO14S_CTRL_EVT0 0X49
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#define S2MPS24_REG_LDO15S_CTRL_EVT0 0X4A
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#define S2MPS24_REG_LDO16S_CTRL_EVT0 0X4B
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#define S2MPS24_REG_LDO17S_CTRL_EVT0 0X4C
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#define S2MPS24_REG_LDO18S_CTRL_EVT0 0X4D
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#define S2MPS24_REG_LDO19S_CTRL_EVT0 0X4E
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#define S2MPS24_REG_LDO20S_CTRL_EVT0 0X4F
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#define S2MPS24_REG_LDO21S_CTRL_EVT0 0X50
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#define S2MPS24_REG_LDO22S_CTRL_EVT0 0X51
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#define S2MPS24_REG_LDO_DSCH1_EVT0 0x52
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#define S2MPS24_REG_LDO_DSCH2_EVT0 0x53
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#define S2MPS24_REG_LDO_DSCH3_EVT0 0x54
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#define S2MPS24_REG_LDO_DSCH4_EVT0 0x55
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#define S2MPS24_REG_LDO_DSCH5_EVT0 0x56
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#define S2MPS24_REG_IOCONF_EVT0 0x57
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#define S2MPS24_REG_IPTAT_EVT0 0x58
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#define S2MPS24_REG_ONSEQ_CTRL1_EVT0 0x59
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#define S2MPS24_REG_ONSEQ_CTRL2_EVT0 0x5A
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#define S2MPS24_REG_ONSEQ_CTRL3_EVT0 0x5B
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#define S2MPS24_REG_ONSEQ_CTRL4_EVT0 0x5C
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#define S2MPS24_REG_ONSEQ_CTRL5_EVT0 0x5D
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#define S2MPS24_REG_ONSEQ_CTRL6_EVT0 0x5E
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#define S2MPS24_REG_ONSEQ_CTRL7_EVT0 0x5F
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#define S2MPS24_REG_ONSEQ_CTRL8_EVT0 0x60
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#define S2MPS24_REG_ONSEQ_CTRL9_EVT0 0x61
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#define S2MPS24_REG_ONSEQ_CTRL10_EVT0 0x62
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#define S2MPS24_REG_ONSEQ_CTRL11_EVT0 0x63
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#define S2MPS24_REG_ONSEQ_CTRL12_EVT0 0x64
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#define S2MPS24_REG_ONSEQ_CTRL13_EVT0 0x65
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#define S2MPS24_REG_ONSEQ_CTRL14_EVT0 0x66
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#define S2MPS24_REG_ONSEQ_CTRL15_EVT0 0x67
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#define S2MPS24_REG_ONSEQ_CTRL16_EVT0 0x68
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#define S2MPS24_REG_ONSEQ_CTRL17_EVT0 0x69
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#define S2MPS24_REG_ONSEQ_CTRL18_EVT0 0x6A
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#define S2MPS24_REG_ONSEQ_CTRL19_EVT0 0x6B
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#define S2MPS24_REG_ONSEQ_CTRL20_EVT0 0x6C
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#define S2MPS24_REG_ONSEQ_CTRL21_EVT0 0x6D
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#define S2MPS24_REG_ONSEQ_CTRL22_EVT0 0x6E
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#define S2MPS24_REG_ONSEQ_CTRL23_EVT0 0x6F
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#define S2MPS24_REG_ONSEQ_CTRL24_EVT0 0x70
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#define S2MPS24_REG_ONSEQ_CTRL25_EVT0 0x71
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#define S2MPS24_REG_ONSEQ_CTRL26_EVT0 0x72
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#define S2MPS24_REG_ONSEQ_CTRL27_EVT0 0x73
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#define S2MPS24_REG_OFF_SEQ_CTRL1_EVT0 0x74
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#define S2MPS24_REG_OFF_SEQ_CTRL2_EVT0 0x75
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#define S2MPS24_REG_OFF_SEQ_CTRL3_EVT0 0x76
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#define S2MPS24_REG_OFF_SEQ_CTRL4_EVT0 0x77
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#define S2MPS24_REG_OFF_SEQ_CTRL5_EVT0 0x78
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#define S2MPS24_REG_OFF_SEQ_CTRL6_EVT0 0x79
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#define S2MPS24_REG_OFF_SEQ_CTRL7_EVT0 0x7A
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#define S2MPS24_REG_OFF_SEQ_CTRL8_EVT0 0x7B
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#define S2MPS24_REG_OFF_SEQ_CTRL9_EVT0 0x7C
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#define S2MPS24_REG_OFF_SEQ_CTRL10_EVT0 0x7D
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#define S2MPS24_REG_OFF_SEQ_CTRL11_EVT0 0x7E
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#define S2MPS24_REG_OFF_SEQ_CTRL12_EVT0 0x7F
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#define S2MPS24_REG_OFF_SEQ_CTRL13_EVT0 0x80
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#define S2MPS24_REG_OFF_SEQ_CTRL14_EVT0 0x81
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#define S2MPS24_REG_OFF_SEQ_CTRL15_EVT0 0x82
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#define S2MPS24_REG_OFF_SEQ_CTRL16_EVT0 0x83
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#define S2MPS24_REG_CONTROL_SEL1_EVT0 0x84
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#define S2MPS24_REG_CONTROL_SEL2_EVT0 0x85
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#define S2MPS24_REG_CONTROL_SEL3_EVT0 0x86
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#define S2MPS24_REG_CONTROL_SEL4_EVT0 0x87
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#define S2MPS24_REG_CONTROL_SEL5_EVT0 0x88
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#define S2MPS24_REG_CONTROL_SEL6_EVT0 0x89
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#define S2MPS24_REG_CONTROL_SEL7_EVT0 0x8A
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#define S2MPS24_REG_CONTROL_SEL8_EVT0 0x8B
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#define S2MPS24_REG_CONTROL_SEL9_EVT0 0x8C
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#define S2MPS24_REG_CONTROL_SEL10_EVT0 0x8D
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#define S2MPS24_REG_CONTROL_SEL11_EVT0 0x8E
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#define S2MPS24_REG_CONTROL_SEL12_EVT0 0x8F
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#define S2MPS24_REG_CONTROL_SEL13_EVT0 0x90
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#define S2MPS24_REG_CONTROL_SEL14_EVT0 0x91
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#define S2MPS24_REG_CONTROL_SEL15_EVT0 0x92
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#define S2MPS24_REG_CONTROL_SEL16_EVT0 0x93
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#define S2MPS24_REG_OFF_CTRL1_EVT0 0x94
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#define S2MPS24_REG_OFF_CTRL2_EVT0 0x95
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#define S2MPS24_REG_OFF_CTRL3_EVT0 0x96
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#define S2MPS24_REG_OFF_CTRL4_EVT0 0x97
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#define S2MPS24_REG_OFF_CTRL5_EVT0 0x98
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#define S2MPS24_REG_SUB_CTRL_EVT0 0x99
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#define S2MPS24_REG_AFM_WARN1_EVT0 0x9A
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#define S2MPS24_REG_AFM_WARN1_X_EVT0 0x9B
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#define S2MPS24_REG_AFM_WARN1_Y_EVT0 0x9C
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#define S2MPS24_REG_AFM_WARN1_Z_EVT0 0x9D
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#define S2MPS24_REG_AFM_WARN2_EVT0 0x9E
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#define S2MPS24_REG_AFM_WARN2_X_EVT0 0x9F
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#define S2MPS24_REG_AFM_WARN2_Y_EVT0 0xA0
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#define S2MPS24_REG_AFM_WARN2_Z_EVT0 0xA1
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#define S2MPS24_REG_AFM_WARN3_EVT0 0xA2
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#define S2MPS24_REG_AFM_WARN3_X_EVT0 0xA3
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#define S2MPS24_REG_AFM_WARN3_Y_EVT0 0xA4
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#define S2MPS24_REG_AFM_WARN3_Z_EVT0 0xA5
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#define S2MPS24_REG_AFM_WARN4_EVT0 0xA6
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#define S2MPS24_REG_AFM_WARN4_X_EVT0 0xA7
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#define S2MPS24_REG_AFM_WARN4_Y_EVT0 0xA8
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#define S2MPS24_REG_AFM_WARN4_Z_EVT0 0xA9
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#define S2MPS24_REG_BUCK_OI_EN1_EVT0 0xAA
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#define S2MPS24_REG_BUCK_OI_EN2_EVT0 0xAB
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#define S2MPS24_REG_BUCK_OI_PD_EN1_EVT0 0XAC
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#define S2MPS24_REG_BUCK_OI_PD_EN2_EVT0 0XAD
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#define S2MPS24_REG_BUCK_OI_CTRL1_EVT0 0xAE
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#define S2MPS24_REG_BUCK_OI_CTRL2_EVT0 0xAF
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#define S2MPS24_REG_BUCK_OI_CTRL3_EVT0 0xB0
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#define S2MPS24_REG_BUCK_OI_CTRL4_EVT0 0xB1
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#define S2MPS24_REG_BUCK_OI_CTRL5_EVT0 0xB2
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#define S2MPS24_REG_BUCK_OI_CTRL6_EVT0 0xB3
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#define S2MPS24_REG_BUCK_OI_CTRL7_EVT0 0xB4
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#define S2MPS24_REG_BUCK_OVP_EN1_EVT0 0xB5
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#define S2MPS24_REG_BUCK_OVP_EN2_EVT0 0xB6
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#define S2MPS24_REG_SEQ_CTRL_EVT0 0xB7
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#define S2MPS24_REG_CFG_PM2_EVT0 0xB8
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#define S2MPS24_REG_PSI_CTRL1_EVT0 0xB9
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#define S2MPS24_REG_PSI_CTRL2_EVT0 0xBA
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#define S2MPS24_REG_OFF_SEQ_SKIP_EVT0 0xBB
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#define S2MPS24_REG_SEL_HW_GPIO_EVT0 0xBC
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#define S2MPS24_REG_ETX_EN_EVT0 0xBD
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#define PSI_CTRL3_EVT0 0xBE
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/* CONTROL_SEL */
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#define S2MPS24_CONTROL_SEL_NUM_EVT0 16
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#define S2MPS24_CONTROL_SEL_MAX_VAL_EVT0 0xFF
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#define S2MPS24_PWREN_MIF_MASK_EVT0 0x00
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#define S2MPS24_PWREN_CPUCL0_MASK_EVT0 0x01
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#define S2MPS24_PWREN_CPUCL1_MASK_EVT0 0x02
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#define S2MPS24_PWREN_CPUCL2_MASK_EVT0 0x03
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#define S2MPS24_PWREN_G3D_MASK_EVT0 0x04
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#define S2MPS24_PWREN_NPU_MASK_EVT0 0x05
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#define S2MPS24_PWREN_CP_MASK_EVT0 0x06
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#define S2MPS24_PWREN_CLK_MASK_EVT0 0x07
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#define S2MPS24_PWREN_RF0_MASK_EVT0 0x08
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#define S2MPS24_PWREN_RF1_MASK_EVT0 0x09
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#define S2MPS24_PWREN_NFC_MASK_EVT0 0x0A
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#define S2MPS24_PWREN_CPUCL0_CPUCL1_MASK_EVT0 0x0C
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#define S2MPS24_PWREN_CPUCL0_CPUCL2_MASK_EVT0 0x0D
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#define S2MPS24_PWREN_RF0_RF1_MASK_EVT0 0x0E
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#define S2MPS24_PWREN_CLK_RF0_RF1_NFC_MASK_EVT0 0x0F
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/* BUCKs 1S ~ 8S */
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#define S2MPS24_BUCK_MIN1_EVT0 300000
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#define S2MPS24_BUCK_STEP1_EVT0 6250
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/* BUCK BB */
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#define S2MPS24_BB_MIN1_EVT0 2600000
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#define S2MPS24_BB_STEP1_EVT0 12500
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/* LDOs 1S/2S/3S/22S */
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#define S2MPS24_LDO_MIN1_EVT0 300000
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#define S2MPS24_LDO_STEP1_EVT0 25000
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/* LDOs 4S/5S/10S/11S/13S/14S/15S/16S */
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#define S2MPS24_LDO_MIN2_EVT0 725000
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#define S2MPS24_LDO_STEP2_EVT0 12500
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/* LDOs 6S/7S/8S/9S/12S/17S/18S/19S/20S/21S */
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#define S2MPS24_LDO_MIN3_EVT0 1800000
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#define S2MPS24_LDO_STEP3_EVT0 25000
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#endif /* __LINUX_MFD_S2MPS24_REGULATOR_EVT0_H */
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