kernel_samsung_a53x/arch/x86/kvm/svm
Sean Christopherson 5007c03ef5 KVM: nSVM: Ignore nCR3[4:0] when loading PDPTEs from memory
commit f559b2e9c5c5308850544ab59396b7d53cfc67bd upstream.

Ignore nCR3[4:0] when loading PDPTEs from memory for nested SVM, as bits
4:0 of CR3 are ignored when PAE paging is used, and thus VMRUN doesn't
enforce 32-byte alignment of nCR3.

In the absolute worst case scenario, failure to ignore bits 4:0 can result
in an out-of-bounds read, e.g. if the target page is at the end of a
memslot, and the VMM isn't using guard pages.

Per the APM:

  The CR3 register points to the base address of the page-directory-pointer
  table. The page-directory-pointer table is aligned on a 32-byte boundary,
  with the low 5 address bits 4:0 assumed to be 0.

And the SDM's much more explicit:

  4:0    Ignored

Note, KVM gets this right when loading PDPTRs, it's only the nSVM flow
that is broken.

Fixes: e4e517b4be01 ("KVM: MMU: Do not unconditionally read PDPTE from guest memory")
Reported-by: Kirk Swidowski <swidowski@google.com>
Cc: Andy Nguyen <theflow@google.com>
Cc: 3pvd <3pvd@google.com>
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-ID: <20241009140838.1036226-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-11-23 23:22:01 +01:00
..
avic.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
nested.c KVM: nSVM: Ignore nCR3[4:0] when loading PDPTEs from memory 2024-11-23 23:22:01 +01:00
pmu.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
sev.c KVM: SVM: Flush pages under kvm->lock to fix UAF in svm_register_enc_region() 2024-11-19 09:22:38 +01:00
svm.c Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
svm.h Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
vmenter.S Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00