99 lines
3.6 KiB
C
Executable file
99 lines
3.6 KiB
C
Executable file
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_CWSR_H__
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#define __AMDGPU_CWSR_H__
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//max cwsr ring within one drm handle
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#define AMDGPU_CWSR_MAX_RING (8)
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//support up to 128 WB
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#define AMDGPU_CWSR_WB_SIZE (2 * PAGE_SIZE)
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//each EOP needs 2K bytes, add 2K byte for page alignment.
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//support up to 8 cwsr ring, 8 Pages are reserved.
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#define AMDGPU_CWSR_MEC_HQD_EOP_SIZE (PAGE_SIZE)
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//each MQD has 2K bytes. add 2K byte for page alignment.
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//support up to 8 cwsr ring, 8 Pages are reserved.
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#define AMDGPU_CWSR_MQD_SIZE (PAGE_SIZE)
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//each ring bo has 8K bytes. Totally, 16 Pages are reserved.
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#define AMDGPU_CWSR_RING_BUF_SIZE (2 * PAGE_SIZE)
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#define AMDGPU_CWSR_RING_MAX_DW (1024)
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//0x7ffe000
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#define AMDGPU_CWSR_WB_OFFSET (AMDGPU_VA_RESERVED_SIZE - \
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AMDGPU_CWSR_WB_SIZE)
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//0x7ff6000
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#define AMDGPU_CWSR_HQD_EOP_OFFSET (AMDGPU_CWSR_WB_OFFSET - \
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AMDGPU_CWSR_MEC_HQD_EOP_SIZE * 8)
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//0x7fee000
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#define AMDGPU_CWSR_MQD_OFFSET (AMDGPU_CWSR_HQD_EOP_OFFSET - \
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AMDGPU_CWSR_MQD_SIZE * 8)
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//0x7fde000
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#define AMDGPU_CWSR_RING_BUF_OFFSET (AMDGPU_CWSR_MQD_OFFSET - \
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AMDGPU_CWSR_RING_BUF_SIZE * 8)
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/*
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* Size of the per-process TBA+TMA buffer: 2 pages
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*
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* The first page is the TBA used for the CWSR ISA code. The second
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* page is used as TMA for daisy changing a user-mode trap handler.
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*/
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#define AMDGPU_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2)
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#define AMDGPU_CWSR_TMA_OFFSET (AMDGPU_CWSR_RING_BUF_OFFSET - \
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PAGE_SIZE)
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#define AMDGPU_CWSR_TBA_OFFSET (AMDGPU_CWSR_TMA_OFFSET - \
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PAGE_SIZE)
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//sr buffer needs around 8M bytes for NV14
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#define AMDGPU_CWSR_SR_OFFSET 0x1100000
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#define AMDGPU_CWSR_VGPR_SIZE_PER_CU(asic_family) \
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((asic_family) == CHIP_ARCTURUS ? 0x80000 : 0x40000)
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#define AMDGPU_CWSR_SGPR_SIZE_PER_CU 0x4000
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#define AMDGPU_CWSR_LDS_SIZE_PER_CU 0x10000
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#define AMDGPU_CWSR_HWREG_SIZE_PER_CU 0x1000
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#define AMDGPU_CWSR_WG_CONTEXT_DATA_SIZE_PER_CU(asic_family) \
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(AMDGPU_CWSR_VGPR_SIZE_PER_CU(asic_family) + \
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AMDGPU_CWSR_SGPR_SIZE_PER_CU + AMDGPU_CWSR_LDS_SIZE_PER_CU + \
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AMDGPU_CWSR_HWREG_SIZE_PER_CU)
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#define AMDGPU_CWSR_WAVES_PER_CU 32
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#define AMDGPU_CWSR_CNTL_STACK_BYTES_PER_WAVE 8
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extern int cwsr_enable;
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int amdgpu_cwsr_init(struct amdgpu_ctx *ctx);
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void amdgpu_cwsr_deinit(struct amdgpu_ctx *ctx);
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int amdgpu_cwsr_dequeue(struct amdgpu_ring *ring);
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int amdgpu_cwsr_relaunch(struct amdgpu_ring *ring);
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int amdgpu_cwsr_init_queue(struct amdgpu_ring *ring);
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void amdgpu_cwsr_deinit_queue(struct amdgpu_ring *ring);
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#endif
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