2499 lines
115 KiB
C
Executable file
2499 lines
115 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* ALSA SoC - Samsung Abox SoC layer for version 3.1
|
|
*
|
|
* Copyright (c) 2018 Samsung Electronics Co. Ltd.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __SND_SOC_ABOX_SOC_31_H
|
|
#define __SND_SOC_ABOX_SOC_31_H
|
|
|
|
#include "abox_soc.h"
|
|
|
|
/* System */
|
|
#define ABOX_IP_INDEX 0x0000
|
|
#define ABOX_VERSION 0x0004
|
|
#define ABOX_SYSPOWER_CTRL 0x0010
|
|
#define ABOX_SYSPOWER_STATUS 0x0014
|
|
#define ABOX_SYSTEM_CONFIG0 0x0020
|
|
#define ABOX_SYSTEM_CONFIG1 0x0024
|
|
#define ABOX_REMAP_MASK 0x0028
|
|
#define ABOX_REMAP_ADDR 0x002C
|
|
#define ABOX_DYN_CLOCK_OFF 0x0030
|
|
#define ABOX_DYN_CLOCK_OFF1 0x0034
|
|
#define ABOX_DYN_CLOCK_OFF2 0x0038
|
|
#define ABOX_QCHANNEL_DISABLE 0x0048
|
|
#define ABOX_TICK_DIV_RATIO 0x0050
|
|
#define ABOX_TICK_GEN 0x0054
|
|
#define ABOX_ROUTE_CTRL0 0x0060
|
|
#define ABOX_ROUTE_CTRL1 0x0064
|
|
#define ABOX_ROUTE_CTRL2 0x006C
|
|
#define ABOX_ROUTE_CTRL3 0x0070
|
|
#define ABOX_ROUTE_CTRL4 0x0074
|
|
#define ABOX_ROUTE_CTRL5 0x007C
|
|
#define ABOX_ROUTE_CTRL_CONNECT 0x0080
|
|
#define ABOX_ROUTE_PDI_CTRL0 0x0090
|
|
#define ABOX_ROUTE_PDI_CTRL1 0x0094
|
|
#define ABOX_ROUTE_PDI_CTRL2 0x00A0
|
|
#define ABOX_ROUTE_UDMA_SIFM 0x00B0
|
|
|
|
/* ABOX_VERSION */
|
|
#define ABOX_VERSION_H 31
|
|
#define ABOX_VERSION_L 8
|
|
#define ABOX_VERSION_MASK ABOX_FLD(VERSION)
|
|
/* ABOX_SYSPOWER_CTRL */
|
|
#define ABOX_SYSPOWER_CTRL_H 0
|
|
#define ABOX_SYSPOWER_CTRL_L 0
|
|
#define ABOX_SYSPOWER_CTRL_MASK ABOX_FLD(SYSPOWER_CTRL)
|
|
/* ABOX_SYSPOWER_STATUS */
|
|
#define ABOX_SYSPOWER_STATUS_H 0
|
|
#define ABOX_SYSPOWER_STATUS_L 0
|
|
#define ABOX_SYSPOWER_STATUS_MASK ABOX_FLD(SYSPOWER_STATUS)
|
|
/* ABOX_DYN_CLOCK_OFF */
|
|
#define ABOX_DYN_CLOCK_OFF_H 31
|
|
#define ABOX_DYN_CLOCK_OFF_L 0
|
|
#define ABOX_DYN_CLOCK_OFF_MASK ABOX_FLD(DYN_CLOCK_OFF)
|
|
/* ABOX_QCHANNEL_DISABLE */
|
|
#define ABOX_QCHANNEL_DISABLE_BASE 0
|
|
#define ABOX_QCHANNEL_DISABLE_ITV 1
|
|
#define ABOX_QCHANNEL_DISABLE_H(x) ABOX_H(QCHANNEL_DISABLE, 0, x)
|
|
#define ABOX_QCHANNEL_DISABLE_L(x) ABOX_L(QCHANNEL_DISABLE, 0, x)
|
|
#define ABOX_QCHANNEL_DISABLE_MASK(x) ABOX_FLD_X(QCHANNEL_DISABLE, x)
|
|
/* ABOX_ROUTE_CTRL0 */
|
|
/* ABOX_ROUTE_CTRL1 */
|
|
#define ABOX_ROUTE_UAIF_SPK_BASE 0
|
|
#define ABOX_ROUTE_UAIF_SPK_ITV 8
|
|
#define ABOX_ROUTE_UAIF_SPK_H(x) ABOX_H(ROUTE_UAIF_SPK, 3, x)
|
|
#define ABOX_ROUTE_UAIF_SPK_L(x) ABOX_L(ROUTE_UAIF_SPK, 0, x)
|
|
#define ABOX_ROUTE_UAIF_SPK_MASK(x) ABOX_FLD_X(ROUTE_UAIF_SPK, x)
|
|
/* ABOX_ROUTE_CTRL2 */
|
|
#define ABOX_ROUTE_DSIF_H 3
|
|
#define ABOX_ROUTE_DSIF_L 0
|
|
#define ABOX_ROUTE_DSIF_MASK ABOX_FLD(ROUTE_DSIF)
|
|
/* ABOX_ROUTE_CTRL3 */
|
|
/* ABOX_ROUTE_CTRL4 */
|
|
#define ABOX_ROUTE_NSRC_BASE 0
|
|
#define ABOX_ROUTE_NSRC_ITV 8
|
|
#define ABOX_ROUTE_NSRC_H(x) ABOX_H(ROUTE_NSRC, 4, x)
|
|
#define ABOX_ROUTE_NSRC_L(x) ABOX_L(ROUTE_NSRC, 0, x)
|
|
#define ABOX_ROUTE_NSRC_MASK(x) ABOX_FLD_X(ROUTE_NSRC, x)
|
|
/* ABOX_ROUTE_CTRL5 */
|
|
#define ABOX_ROUTE_SPUST_H 12
|
|
#define ABOX_ROUTE_SPUST_L 8
|
|
#define ABOX_ROUTE_SPUST_MASK ABOX_FLD(ROUTE_SPUST)
|
|
#define ABOX_ROUTE_SPUSM_H 4
|
|
#define ABOX_ROUTE_SPUSM_L 0
|
|
#define ABOX_ROUTE_SPUSM_MASK ABOX_FLD(ROUTE_SPUSM)
|
|
/* ABOX_ROUTE_CONNECT */
|
|
#define ABOX_NSRC_CONNECTION_TYPE_BASE 0
|
|
#define ABOX_NSRC_CONNECTION_TYPE_ITV 1
|
|
#define ABOX_NSRC_CONNECTION_TYPE_H(x) ABOX_H(NSRC_CONNECTION_TYPE, 0, x)
|
|
#define ABOX_NSRC_CONNECTION_TYPE_L(x) ABOX_L(NSRC_CONNECTION_TYPE, 0, x)
|
|
#define ABOX_NSRC_CONNECTION_TYPE_MASK(x) ABOX_FLD_X(NSRC_CONNECTION_TYPE, x)
|
|
/* ABOX_PDI_CTRL0 */
|
|
/* ABOX_PDI_CTRL1 */
|
|
#define ABOX_ROUTE_BI_PDI_SPK_BASE 0
|
|
#define ABOX_ROUTE_BI_PDI_SPK_ITV 8
|
|
#define ABOX_ROUTE_BI_PDI_SPK_H(x) ABOX_H(ROUTE_BI_PDI_SPK, 3, x)
|
|
#define ABOX_ROUTE_BI_PDI_SPK_L(x) ABOX_L(ROUTE_BI_PDI_SPK, 0, x)
|
|
#define ABOX_ROUTE_BI_PDI_SPK_MASK(x) ABOX_FLD_X(ROUTE_BI_PDI_SPK, x)
|
|
/* ABOX_PDI_CTRL2 */
|
|
#define ABOX_ROUTE_TX_PDI_SPK_BASE 0
|
|
#define ABOX_ROUTE_TX_PDI_SPK_ITV 8
|
|
#define ABOX_ROUTE_TX_PDI_SPK_H(x) ABOX_H(ROUTE_TX_PDI_SPK, 3, x)
|
|
#define ABOX_ROUTE_TX_PDI_SPK_L(x) ABOX_L(ROUTE_TX_PDI_SPK, 0, x)
|
|
#define ABOX_ROUTE_TX_PDI_SPK_MASK(x) ABOX_FLD_X(ROUTE_TX_PDI_SPK, x)
|
|
/* ABOX_UDMA_SIFM */
|
|
#define ABOX_ROUTE_UDMA_SIFM_BASE 0
|
|
#define ABOX_ROUTE_UDMA_SIFM_ITV 8
|
|
#define ABOX_ROUTE_UDMA_SIFM_H(x) ABOX_H(ROUTE_UDMA_SIFM, 3, x)
|
|
#define ABOX_ROUTE_UDMA_SIFM_L(x) ABOX_L(ROUTE_UDMA_SIFM, 0, x)
|
|
#define ABOX_ROUTE_UDMA_SIFM_MASK(x) ABOX_FLD_X(ROUTE_UDMA_SIFM, x)
|
|
/* System HELPERS */
|
|
#define ABOX_ROUTE_CTRL_UAIF_SPK(x) \
|
|
ABOX_SFR_FLD(ROUTE_CTRL0, ROUTE_UAIF_SPK, 0, x)
|
|
#define ABOX_ROUTE_CTRL_DSIF ABOX_ROUTE_CTRL2
|
|
#define ABOX_ROUTE_CTRL_NSRC(x) \
|
|
ABOX_SFR_FLD(ROUTE_CTRL3, ROUTE_NSRC, 0, x)
|
|
#define ABOX_ROUTE_CTRL_SIFT ABOX_ROUTE_CTRL5
|
|
#define ABOX_ROUTE_CTRL_SIFM ABOX_ROUTE_CTRL5
|
|
#define ABOX_ROUTE_CTRL_BI_PDI_SPK(x) \
|
|
ABOX_SFR_FLD(ROUTE_PDI_CTRL0, ROUTE_BI_PDI_SPK, 0, x)
|
|
#define ABOX_ROUTE_CTRL_TX_PDI_SPK ABOX_ROUTE_PDI_CTRL2
|
|
|
|
/* SPUS */
|
|
#define ABOX_SPUS_CTRL_FC0 0x0200
|
|
#define ABOX_SPUS_CTRL_FC1 0x0204
|
|
#define ABOX_SPUS_CTRL_FC2 0x0208
|
|
#define ABOX_SPUS_CTRL_FC3 0x020C
|
|
#define ABOX_SPUS_CTRL_FC4 0x0210
|
|
#define ABOX_SPUS_CTRL_FC5 0x0214
|
|
#define ABOX_SPUS_CTRL_SIFS_SEL0 0x0240
|
|
#define ABOX_SPUS_CTRL_SIFS_SEL1 0x0244
|
|
#define ABOX_SPUS_CTRL_SIFM_SEL 0x0250
|
|
#define ABOX_SPUS_CTRL_TUNE_SEL 0x0254
|
|
#define ABOX_SPUS_CTRL_MIXP_FORMAT 0x0260
|
|
#define ABOX_SPUS_CTRL_SIFS_CH_CTRL0 0x0264
|
|
#define ABOX_SPUS_CTRL_SIFS_CH_CTRL1 0x0268
|
|
#define ABOX_SPUS_CTRL_FLUSH 0x0270
|
|
#define ABOX_SPUS_CTRL_ASRC_ID0 0x0280
|
|
#define ABOX_SPUS_CTRL_ASRC_ID1 0x0284
|
|
#define ABOX_SPUS_CTRL_ASRC_ID2 0x0288
|
|
#define ABOX_SPUS_CTRL_SIFS_CH_SEL0 0x0290
|
|
#define ABOX_SPUS_CTRL_SIFS_CH_SEL1 0x0294
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT0 0x02A0
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT1 0x02A4
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT2 0x02A8
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT3 0x02AC
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT4 0x02B0
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT5 0x02B4
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT6 0x02B8
|
|
#define ABOX_SPUS_LATENCY_CTRL0 0x02D0
|
|
#define ABOX_SPUS_LATENCY_CTRL1 0x02D4
|
|
#define ABOX_SPUS_LATENCY_CTRL2 0x02D8
|
|
#define ABOX_SPUS_LATENCY_CTRL3 0x02DC
|
|
|
|
/* ABOX_SPUS_CTRL_FCx */
|
|
#define ABOX_FUNC_CHAIN_SRC_BASE 0
|
|
#define ABOX_FUNC_CHAIN_SRC_ITV 16
|
|
#define ABOX_FUNC_CHAIN_SRC_DSG_H(x) ABOX_H(FUNC_CHAIN_SRC, 10, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_DSG_L(x) ABOX_L(FUNC_CHAIN_SRC, 10, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_DSG_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_DSG, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_DRC_H(x) ABOX_H(FUNC_CHAIN_SRC, 9, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_DRC_L(x) ABOX_L(FUNC_CHAIN_SRC, 9, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_DRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_DRC, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_BQF_H(x) ABOX_H(FUNC_CHAIN_SRC, 8, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_BQF_L(x) ABOX_L(FUNC_CHAIN_SRC, 8, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_BQF_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_BQF, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_USG_H(x) ABOX_H(FUNC_CHAIN_SRC, 7, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_USG_L(x) ABOX_L(FUNC_CHAIN_SRC, 7, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_USG_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_USG, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_IN_H(x) ABOX_H(FUNC_CHAIN_SRC, 6, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_IN_L(x) ABOX_L(FUNC_CHAIN_SRC, 5, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_IN_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_IN, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_SIFS_H(x) ABOX_H(FUNC_CHAIN_SRC, 4, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_SIFS_L(x) ABOX_L(FUNC_CHAIN_SRC, 2, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_SIFS_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_SIFS, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_MIXP_H(x) ABOX_H(FUNC_CHAIN_SRC, 1, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_MIXP_L(x) ABOX_L(FUNC_CHAIN_SRC, 1, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_MIXP_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_MIXP, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_OUT_H(x) ABOX_H(FUNC_CHAIN_SRC, 4, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_OUT_L(x) ABOX_L(FUNC_CHAIN_SRC, 1, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_OUT_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_OUT, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_ASRC_H(x) ABOX_H(FUNC_CHAIN_SRC, 0, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_ASRC_L(x) ABOX_L(FUNC_CHAIN_SRC, 0, x)
|
|
#define ABOX_FUNC_CHAIN_SRC_ASRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_ASRC, x)
|
|
/* ABOX_SPUS_CTRL_SIFS_SELx */
|
|
#define ABOX_SIFS_OUT_SEL_BASE -8
|
|
#define ABOX_SIFS_OUT_SEL_ITV 8
|
|
#define ABOX_SIFS_OUT_SEL_H(x) ABOX_H(SIFS_OUT_SEL, 3, x)
|
|
#define ABOX_SIFS_OUT_SEL_L(x) ABOX_L(SIFS_OUT_SEL, 0, x)
|
|
#define ABOX_SIFS_OUT_SEL_MASK(x) ABOX_FLD_X(SIFS_OUT_SEL, x)
|
|
/* ABOX_SPUS_CTRL_SIFM_SEL */
|
|
#define ABOX_SIFST_IN_SEL_H 11
|
|
#define ABOX_SIFST_IN_SEL_L 8
|
|
#define ABOX_SIFST_IN_SEL_MASK ABOX_FLD(SIFST_IN_SEL)
|
|
#define ABOX_SIFSM_IN_SEL_H 3
|
|
#define ABOX_SIFSM_IN_SEL_L 0
|
|
#define ABOX_SIFSM_IN_SEL_MASK ABOX_FLD(SIFSM_IN_SEL)
|
|
/* ABOX_SPUS_CTRL_TUNE_SEL */
|
|
#define ABOX_TUNE_SEL_BASE 0
|
|
#define ABOX_TUNE_SEL_ITV 16
|
|
#define ABOX_POST_TUNE_SEL_H(x) ABOX_H(TUNE_SEL, 11, x)
|
|
#define ABOX_POST_TUNE_SEL_L(x) ABOX_L(TUNE_SEL, 8, x)
|
|
#define ABOX_POST_TUNE_SEL_MASK(x) ABOX_FLD_X(POST_TUNE_SEL, x)
|
|
#define ABOX_PRE_TUNE_SEL_H(x) ABOX_H(TUNE_SEL, 3, x)
|
|
#define ABOX_PRE_TUNE_SEL_L(x) ABOX_L(TUNE_SEL, 0, x)
|
|
#define ABOX_PRE_TUNE_SEL_MASK(x) ABOX_FLD_X(PRE_TUNE_SEL, x)
|
|
/* ABOX_SPUS_CTRL_MIXP_FORMAT */
|
|
#define ABOX_STMIX_FORMAT_H 20
|
|
#define ABOX_STMIX_FORMAT_L 16
|
|
#define ABOX_STMIX_FORMAT_MASK ABOX_FLD(STMIX_FORMAT)
|
|
#define ABOX_MIXP_FORMAT_H 4
|
|
#define ABOX_MIXP_FORMAT_L 0
|
|
#define ABOX_MIXP_FORMAT_MASK ABOX_FLD(MIXP_FORMAT)
|
|
/* ABOX_SPUS_CTRL_SIFS_CH_CTRLx */
|
|
#define ABOX_SIFS_CH_NUM_BASE 0
|
|
#define ABOX_SIFS_CH_NUM_ITV 8
|
|
#define ABOX_SIFS_CH_NUM_EN_H(x) ABOX_H(SIFS_CH_NUM, 3, x)
|
|
#define ABOX_SIFS_CH_NUM_EN_L(x) ABOX_L(SIFS_CH_NUM, 3, x)
|
|
#define ABOX_SIFS_CH_NUM_EN_MASK(x) ABOX_FLD_X(SIFS_CH_NUM_EN, x)
|
|
#define ABOX_SIFS_CH_NUM_H(x) ABOX_H(SIFS_CH_NUM, 2, x)
|
|
#define ABOX_SIFS_CH_NUM_L(x) ABOX_L(SIFS_CH_NUM, 0, x)
|
|
#define ABOX_SIFS_CH_NUM_MASK(x) ABOX_FLD_X(SIFS_CH_NUM, x)
|
|
/* ABOX_SPUS_CTRL_FLUSH */
|
|
#define ABOX_MIXP_LD_FLUSH_H 29
|
|
#define ABOX_MIXP_LD_FLUSH_L 29
|
|
#define ABOX_MIXP_LD_FLUSH_MASK ABOX_FLD(MIXP_LD_FLUSH)
|
|
#define ABOX_MIXP_FLUSH_H 28
|
|
#define ABOX_MIXP_FLUSH_L 28
|
|
#define ABOX_MIXP_FLUSH_MASK ABOX_FLD(MIXP_FLUSH)
|
|
#define ABOX_STMIX_LD_FLUSH_H 13
|
|
#define ABOX_STMIX_LD_FLUSH_L 13
|
|
#define ABOX_STMIX_LD_FLUSH_MASK ABOX_FLD(STMIX_LD_FLUSH)
|
|
#define ABOX_STMIX_FLUSH_H 12
|
|
#define ABOX_STMIX_FLUSH_L 12
|
|
#define ABOX_STMIX_FLUSH_MASK ABOX_FLD(STMIX_FLUSH)
|
|
#define ABOX_TUNE_FLUSH_BASE 8
|
|
#define ABOX_TUNE_FLUSH_ITV 1
|
|
#define ABOX_TUNE_FLUSH_H(x) ABOX_H(TUNE_FLUSH, 0, x)
|
|
#define ABOX_TUNE_FLUSH_L(x) ABOX_L(TUNE_FLUSH, 0, x)
|
|
#define ABOX_TUNE_FLUSH_MASK(x) ABOX_FLD_X(TUNE_FLUSH, x)
|
|
#define ABOX_SIFS_FLUSH_BASE -1
|
|
#define ABOX_SIFS_FLUSH_ITV 1
|
|
#define ABOX_SIFS_FLUSH_H(x) ABOX_H(SIFS_FLUSH, 0, x)
|
|
#define ABOX_SIFS_FLUSH_L(x) ABOX_L(SIFS_FLUSH, 0, x)
|
|
#define ABOX_SIFS_FLUSH_MASK(x) ABOX_FLD_X(SIFS_FLUSH, x)
|
|
/* ABOX_SPUS_CTRL_ASRC_IDx */
|
|
#define ABOX_SRC_ASRC_ID_BASE 0
|
|
#define ABOX_SRC_ASRC_ID_ITV 8
|
|
#define ABOX_SRC_ASRC_ID_H(x) ABOX_H(SRC_ASRC_ID, 3, x)
|
|
#define ABOX_SRC_ASRC_ID_L(x) ABOX_L(SRC_ASRC_ID, 0, x)
|
|
#define ABOX_SRC_ASRC_ID_MASK(x) ABOX_FLD_X(SRC_ASRC_ID, x)
|
|
/* ABOX_SPUS_CTRL_SIFS_CH_SELx */
|
|
#define ABOX_SIFS_CH_SEL_BASE 0
|
|
#define ABOX_SIFS_CH_SEL_ITV 8
|
|
#define ABOX_SIFS_CH_SEL_H(x) ABOX_H(SIFS_CH_SEL, 7, x)
|
|
#define ABOX_SIFS_CH_SEL_L(x) ABOX_L(SIFS_CH_SEL, 0, x)
|
|
#define ABOX_SIFS_CH_SEL_MASK(x) ABOX_FLD_X(SIFS_CH_SEL, x)
|
|
/* ABOX_SPUS_CTRL_SIFS_CNTx */
|
|
#define ABOX_SIFS_CNT_VAL_BASE 0
|
|
#define ABOX_SIFS_CNT_VAL_ITV 32
|
|
#define ABOX_SIFS_CNT_VAL_H(x) ABOX_H(SIFS_CNT_VAL, 23, x)
|
|
#define ABOX_SIFS_CNT_VAL_L(x) ABOX_L(SIFS_CNT_VAL, 0, x)
|
|
#define ABOX_SIFS_CNT_VAL_MASK(x) ABOX_FLD_X(SIFS_CNT_VAL, x)
|
|
/* ABOX_SPUS_LATENCY_CTRL0 */
|
|
#define ABOX_MIXP_DUMMY_START_H 28
|
|
#define ABOX_MIXP_DUMMY_START_L 28
|
|
#define ABOX_MIXP_DUMMY_START_MASK ABOX_FLD(MIXP_DUMMY_START)
|
|
#define ABOX_TUNE1_DUMMY_START_H 17
|
|
#define ABOX_TUNE1_DUMMY_START_L 17
|
|
#define ABOX_TUNE1_DUMMY_START_MASK ABOX_FLD(TUNE1_DUMMY_START)
|
|
#define ABOX_TUNE0_DUMMY_START_H 16
|
|
#define ABOX_TUNE0_DUMMY_START_L 16
|
|
#define ABOX_TUNE0_DUMMY_START_MASK ABOX_FLD(TUNE0_DUMMY_START)
|
|
#define ABOX_RDMA_ASRC_DUMMY_START_BASE 0
|
|
#define ABOX_RDMA_ASRC_DUMMY_START_ITV 1
|
|
#define ABOX_RDMA_ASRC_DUMMY_START_H(x) ABOX_H(RDMA_ASRC_DUMMY_START, 0, x)
|
|
#define ABOX_RDMA_ASRC_DUMMY_START_L(x) ABOX_L(RDMA_ASRC_DUMMY_START, 0, x)
|
|
#define ABOX_RDMA_ASRC_DUMMY_START_MASK(x) \
|
|
ABOX_FLD_X(RDMA_ASRC_DUMMY_START, x)
|
|
/* ABOX_SPUS_LATENCY_CTRL1 ... 3 */
|
|
#define ABOX_RDMA_START_ASRC_NUM_BASE 0
|
|
#define ABOX_RDMA_START_ASRC_NUM_ITV 8
|
|
#define ABOX_RDMA_START_ASRC_NUM_H(x) ABOX_H(RDMA_START_ASRC_NUM, 7, x)
|
|
#define ABOX_RDMA_START_ASRC_NUM_L(x) ABOX_L(RDMA_START_ASRC_NUM, 0, x)
|
|
#define ABOX_RDMA_START_ASRC_NUM_MASK(x) ABOX_FLD_X(RDMA_START_ASRC_NUM, x)
|
|
/* SPUS HELPERS */
|
|
#define ABOX_SPUS_CTRL_FC_SRC(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_FC0, FUNC_CHAIN_SRC, 0, x)
|
|
#define ABOX_SIFS_CH_NUM(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_SIFS_CH_CTRL0, SIFS_CH_NUM, 0, x)
|
|
#define ABOX_SPUS_CTRL_SIFS_OUT_SEL(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_SIFS_SEL0, SIFS_OUT_SEL, -1, x)
|
|
#define ABOX_SPUS_CTRL_SRC_ASRC_ID(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_ASRC_ID0, SRC_ASRC_ID, 0, x)
|
|
#define ABOX_SIFS_CH_SEL(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_SIFS_CH_SEL0, SIFS_CH_SEL, 0, x)
|
|
#define ABOX_SPUS_CTRL_SIFS_CNT_VAL(x) \
|
|
ABOX_SFR_FLD(SPUS_CTRL_SIFS_CNT0, SIFS_CNT_VAL, 0, x)
|
|
#define ABOX_SPUS_CTRL_MIXP_DUMMY_START ABOX_SPUS_LATENCY_CTRL0
|
|
#define ABOX_SPUS_CTRL_RDMA_ASRC_DUMMY_START ABOX_SPUS_LATENCY_CTRL0
|
|
#define ABOX_SPUS_CTRL_RDMA_START_ASRC_NUM(x) \
|
|
ABOX_SFR_FLD(SPUS_LATENCY_CTRL1, RDMA_START_ASRC_NUM, 0, x)
|
|
|
|
/* SPUS_SBANK */
|
|
#define ABOX_SPUS_SBANK_RDMA_BASE 0x0300
|
|
#define ABOX_SPUS_SBANK_RDMA_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_RDMA(x) ABOX_SFR(SPUS_SBANK_RDMA, 0x0, x)
|
|
#define ABOX_SPUS_SBANK_ASRC_BASE 0x0340
|
|
#define ABOX_SPUS_SBANK_ASRC_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_ASRC(x) ABOX_SFR(SPUS_SBANK_ASRC, 0x0, x)
|
|
#define ABOX_SPUS_SBANK_MIXP 0x0380
|
|
#define ABOX_SPUS_SBANK_SIDETONE 0x0390
|
|
#define ABOX_SPUS_SBANK_STMIX 0x0394
|
|
#define ABOX_SPUS_SBANK_USG_BASE 0x03A0
|
|
#define ABOX_SPUS_SBANK_USG_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_USG(x) ABOX_SFR(SPUS_SBANK_USG, 0x0, x)
|
|
#define ABOX_SPUS_SBANK_BQF_BASE 0x03B0
|
|
#define ABOX_SPUS_SBANK_BQF_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_BQF(x) ABOX_SFR(SPUS_SBANK_BQF, 0x0, x)
|
|
#define ABOX_SPUS_SBANK_DRC_BASE 0x03C0
|
|
#define ABOX_SPUS_SBANK_DRC_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_DRC(x) ABOX_SFR(SPUS_SBANK_DRC, 0x0, x)
|
|
#define ABOX_SPUS_SBANK_DSG_BASE 0x03D0
|
|
#define ABOX_SPUS_SBANK_DSG_ITV 0x0004
|
|
#define ABOX_SPUS_SBANK_DSG(x) ABOX_SFR(SPUS_SBANK_DSG, 0x0, x)
|
|
|
|
/* SPUM */
|
|
#define ABOX_SPUM_CTRL_FC0 0x0400
|
|
#define ABOX_SPUM_CTRL_FC1 0x0404
|
|
#define ABOX_SPUM_CTRL_FC2 0x0408
|
|
#define ABOX_SPUM_CTRL_FC3 0x040C
|
|
#define ABOX_SPUM_CTRL_SIFS_SEL 0x0440
|
|
#define ABOX_SPUM_CTRL_TUNE_SEL 0x0444
|
|
#define ABOX_SPUM_CTRL_FLUSH 0x0460
|
|
#define ABOX_SPUM_CTRL_SIFM_CH_CTRL0 0x0464
|
|
#define ABOX_SPUM_CTRL_SIFM_CH_CTRL1 0x0468
|
|
#define ABOX_SPUM_CTRL_ASRC_ID0 0x0480
|
|
#define ABOX_SPUM_CTRL_ASRC_ID1 0x0484
|
|
#define ABOX_SPUM_CTRL_SIFM_CH_SEL0 0x0490
|
|
#define ABOX_SPUM_CTRL_SIFM_CH_SEL1 0x0494
|
|
|
|
/* ABOX_SPUM_CTRL_FCx */
|
|
#define ABOX_FUNC_CHAIN_NSRC_BASE 0
|
|
#define ABOX_FUNC_CHAIN_NSRC_ITV 16
|
|
#define ABOX_FUNC_CHAIN_NSRC_DSG_H(x) ABOX_H(FUNC_CHAIN_NSRC, 7, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_DSG_L(x) ABOX_L(FUNC_CHAIN_NSRC, 7, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_DSG_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_DSG, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_DRC_H(x) ABOX_H(FUNC_CHAIN_NSRC, 6, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_DRC_L(x) ABOX_L(FUNC_CHAIN_NSRC, 6, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_DRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_DRC, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_BQF_H(x) ABOX_H(FUNC_CHAIN_NSRC, 5, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_BQF_L(x) ABOX_L(FUNC_CHAIN_NSRC, 5, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_BQF_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_BQF, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_USG_H(x) ABOX_H(FUNC_CHAIN_NSRC, 4, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_USG_L(x) ABOX_L(FUNC_CHAIN_NSRC, 4, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_USG_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_USG, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_OUT_H(x) ABOX_H(FUNC_CHAIN_NSRC, 3, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_OUT_L(x) ABOX_L(FUNC_CHAIN_NSRC, 3, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_OUT_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_OUT, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_ASRC_H(x) ABOX_H(FUNC_CHAIN_NSRC, 0, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_ASRC_L(x) ABOX_L(FUNC_CHAIN_NSRC, 0, x)
|
|
#define ABOX_FUNC_CHAIN_NSRC_ASRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_ASRC, x)
|
|
/* ABOX_SPUM_CTRL_SIFS_SEL */
|
|
#define ABOX_SIFMS_OUT_SEL_H 2
|
|
#define ABOX_SIFMS_OUT_SEL_L 0
|
|
#define ABOX_SIFMS_OUT_SEL_MASK ABOX_FLD(SIFMS_OUT_SEL)
|
|
/* ABOX_SPUM_CTRL_TUNE_SEL */
|
|
/* ABOX_SPUM_CTRL_FLUSH */
|
|
#define ABOX_SIFMS_FLUSH_H 0
|
|
#define ABOX_SIFMS_FLUSH_L 0
|
|
#define ABOX_SIFMS_FLUSH_MASK ABOX_FLD(SIFMS_FLUSH)
|
|
/* ABOX_SPUM_CTRL_SIFM_CH_CTRLx */
|
|
#define ABOX_SIFM_CH_NUM_BASE 0
|
|
#define ABOX_SIFM_CH_NUM_ITV 8
|
|
#define ABOX_SIFM_CH_NUM_EN_H(x) ABOX_H(SIFM_CH_NUM, 3, x)
|
|
#define ABOX_SIFM_CH_NUM_EN_L(x) ABOX_L(SIFM_CH_NUM, 3, x)
|
|
#define ABOX_SIFM_CH_NUM_EN_MASK(x) ABOX_FLD_X(SIFM_CH_NUM_EN, x)
|
|
#define ABOX_SIFM_CH_NUM_H(x) ABOX_H(SIFM_CH_NUM, 2, x)
|
|
#define ABOX_SIFM_CH_NUM_L(x) ABOX_L(SIFM_CH_NUM, 0, x)
|
|
#define ABOX_SIFM_CH_NUM_MASK(x) ABOX_FLD_X(SIFM_CH_NUM, x)
|
|
/* ABOX_SPUM_ASRC_IDx */
|
|
#define ABOX_NSRC_ASRC_ID_BASE 0
|
|
#define ABOX_NSRC_ASRC_ID_ITV 8
|
|
#define ABOX_NSRC_ASRC_ID_H(x) ABOX_H(NSRC_ASRC_ID, 2, x)
|
|
#define ABOX_NSRC_ASRC_ID_L(x) ABOX_L(NSRC_ASRC_ID, 0, x)
|
|
#define ABOX_NSRC_ASRC_ID_MASK(x) ABOX_FLD_X(NSRC_ASRC_ID, x)
|
|
/* ABOX_SPUM_CTRL_SIFM_CH_SELx */
|
|
#define ABOX_SIFM_CH_SEL_BASE 0
|
|
#define ABOX_SIFM_CH_SEL_ITV 8
|
|
#define ABOX_SIFM_CH_SEL_H(x) ABOX_H(SIFM_CH_SEL, 7, x)
|
|
#define ABOX_SIFM_CH_SEL_L(x) ABOX_L(SIFM_CH_SEL, 0, x)
|
|
#define ABOX_SIFM_CH_SEL_MASK(x) ABOX_FLD_X(SIFM_CH_SEL, x)
|
|
/* SPUM HELPERS */
|
|
#define ABOX_SPUM_CTRL_FC ABOX_SPUM_CTRL_FC0
|
|
#define ABOX_SPUM_CTRL_FC_NSRC(x) \
|
|
ABOX_SFR_FLD(SPUM_CTRL_FC, FUNC_CHAIN_NSRC, 0, x)
|
|
#define ABOX_SIFM_CH_NUM(x) \
|
|
ABOX_SFR_FLD(SPUM_CTRL_SIFM_CH_CTRL0, SIFM_CH_NUM, 0, x)
|
|
#define ABOX_SPUM_CTRL_ASRC_ID ABOX_SPUM_CTRL_ASRC_ID0
|
|
#define ABOX_SPUM_CTRL_NSRC_ASRC_ID(x) \
|
|
ABOX_SFR_FLD(SPUM_CTRL_ASRC_ID, NSRC_ASRC_ID, 0, x)
|
|
#define ABOX_SIFM_CH_SEL(x) \
|
|
ABOX_SFR_FLD(SPUM_CTRL_SIFM_CH_SEL0, SIFM_CH_SEL, 0, x)
|
|
|
|
/* SPUM_SBANK */
|
|
#define ABOX_SPUM_SBANK_NSRC_BASE 0x0500
|
|
#define ABOX_SPUM_SBANK_NSRC_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_NSRC(x) ABOX_SFR(SPUM_SBANK_NSRC, 0x0, x)
|
|
#define ABOX_SPUM_SBANK_ASRC_BASE 0x0540
|
|
#define ABOX_SPUM_SBANK_ASRC_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_ASRC(x) ABOX_SFR(SPUM_SBANK_ASRC, 0x0, x)
|
|
#define ABOX_SPUM_SBANK_USG_BASE 0x05A0
|
|
#define ABOX_SPUM_SBANK_USG_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_USG(x) ABOX_SFR(SPUM_SBANK_USG, 0x0, x)
|
|
#define ABOX_SPUM_SBANK_BQF_BASE 0x05B0
|
|
#define ABOX_SPUM_SBANK_BQF_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_BQF(x) ABOX_SFR(SPUM_SBANK_BQF, 0x0, x)
|
|
#define ABOX_SPUM_SBANK_DRC_BASE 0x05C0
|
|
#define ABOX_SPUM_SBANK_DRC_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_DRC(x) ABOX_SFR(SPUM_SBANK_DRC, 0x0, x)
|
|
#define ABOX_SPUM_SBANK_DSG_BASE 0x05D0
|
|
#define ABOX_SPUM_SBANK_DSG_ITV 0x0004
|
|
#define ABOX_SPUM_SBANK_DSG(x) ABOX_SFR(SPUM_SBANK_DSG, 0x0, x)
|
|
|
|
/* ABOX_SPUS_SBANK_RDMAx */
|
|
/* ABOX_SPUS_SBANK_ASRCx */
|
|
/* ABOX_SPUM_SBANK_NSRCx */
|
|
/* ABOX_SPUM_SBANK_ASRCx */
|
|
#define ABOX_SBANK_SIZE_H 29
|
|
#define ABOX_SBANK_SIZE_L 20
|
|
#define ABOX_SBANK_SIZE_MASK ABOX_FLD(SBANK_SIZE)
|
|
#define ABOX_SBANK_STR_H 13
|
|
#define ABOX_SBANK_STR_L 4
|
|
#define ABOX_SBANK_STR_MASK ABOX_FLD(SBANK_STR)
|
|
|
|
/* AUDEN */
|
|
#define ABOX_AUDEN_FC_MAIN_CTRL0 0x0600
|
|
#define ABOX_AUDEN_FC_MAIN_CTRL1 0x0604
|
|
#define ABOX_AUDEN_FC_MAIN_CTRL2 0x0608
|
|
#define ABOX_AUDEN_FC_ASRC_CTRL0 0x0610
|
|
#define ABOX_AUDEN_FC_ASRC_CTRL1 0x0614
|
|
#define ABOX_AUDEN_FC_ASRC_CTRL2 0x0618
|
|
#define ABOX_AUDEN_FC_MIXP_CTRL0 0x0620
|
|
#define ABOX_AUDEN_FC_MIXP_CTRL1 0x0624
|
|
#define ABOX_AUDEN_FC_MIXP_CTRL2 0x0628
|
|
#define ABOX_AUDEN_FC_WDMA_CTRL0 0x0630
|
|
#define ABOX_AUDEN_FC_WDMA_CTRL1 0x0634
|
|
#define ABOX_AUDEN_MIXP_CTRL_BASE 0x0640
|
|
#define ABOX_AUDEN_MIXP_CTRL_ITV 0x0004
|
|
#define ABOX_AUDEN_MIXP_CTRL(x) ABOX_SFR(AUDEN_MIXP_CTRL, 0x0, x)
|
|
#define ABOX_AUDEN_ASRC_PERF_CON_BASE 0x0650
|
|
#define ABOX_AUDEN_ASRC_PERF_CON_ITV 0x0004
|
|
#define ABOX_AUDEN_ASRC_PERF_CON(x) ABOX_SFR(AUDEN_ASRC_PERF_CON, 0x0, x)
|
|
#define ABOX_AUDEN_ASRC_DUMMY_CTRL_BASE 0x0690
|
|
#define ABOX_AUDEN_ASRC_DUMMY_CTRL_ITV 0x0004
|
|
#define ABOX_AUDEN_ASRC_DUMMY_CTRL(x) ABOX_SFR(AUDEN_ASRC_DUMMY_CTRL, 0x0, x)
|
|
|
|
/* AUDEN_SBANK */
|
|
#define ABOX_AUDEN_SBANK_RDMA_BASE 0x0700
|
|
#define ABOX_AUDEN_SBANK_RDMA_ITV 0x0004
|
|
#define ABOX_AUDEN_SBANK_RDMA(x) ABOX_SFR(AUDEN_SBANK_RDMA, 0x0, x)
|
|
#define ABOX_AUDEN_SBANK_ASRC_BASE 0x0740
|
|
#define ABOX_AUDEN_SBANK_ASRC_ITV 0x0004
|
|
#define ABOX_AUDEN_SBANK_ASRC(x) ABOX_SFR(AUDEN_SBANK_ASRC, 0x0, x)
|
|
#define ABOX_AUDEN_SBANK_MIXP_BASE 0x0780
|
|
#define ABOX_AUDEN_SBANK_MIXP_ITV 0x0004
|
|
#define ABOX_AUDEN_SBANK_MIXP(x) ABOX_SFR(AUDEN_SBANK_MIXP, 0x0, x)
|
|
|
|
/* AUDEN_SYNC_CTRL */
|
|
#define ABOX_AUDEN_MIXP_SYNC_BASE 0x0800
|
|
#define ABOX_AUDEN_MIXP_SYNC_ITV 0x0010
|
|
#define ABOX_AUDEN_MIXP_SYNC_CTRL(x) ABOX_SFR(AUDEN_MIXP_SYNC, 0x0, x)
|
|
#define ABOX_AUDEN_MIXP_SYNC_EN(x) ABOX_SFR(AUDEN_MIXP_SYNC, 0x4, x)
|
|
#define ABOX_AUDEN_MIXP_SYNC_RESTART(x) ABOX_SFR(AUDEN_MIXP_SYNC, 0x8, x)
|
|
#define ABOX_AUDEN_RDMA_WDMA_BUF_RATIO0 0x0840
|
|
#define ABOX_AUDEN_RDMA_WDMA_BUF_RATIO1 0x0844
|
|
|
|
/* SOUNDWIRE */
|
|
#define ABOX_SOUNDWIRE_INFO 0x0900
|
|
#define ABOX_SOUNDWIRE_DEBUG 0x0904
|
|
#define ABOX_SW_PDI_CTRL0 0x0910
|
|
#define ABOX_SW_PDI_CTRL1 0x0914
|
|
#define ABOX_SW_PDI_CTRL2 0x0918
|
|
#define ABOX_SW_PDI_CTRL3 0x091C
|
|
|
|
/* ABOX_SOUNDWIRE_INFO */
|
|
#define ABOX_KEEPER_CTRL_BASE 4
|
|
#define ABOX_KEEPER_CTRL_ITV 4
|
|
#define ABOX_KEEPER_CTRL_H(x) ABOX_H(KEEPER_CTRL, 1, x)
|
|
#define ABOX_KEEPER_CTRL_L(x) ABOX_L(KEEPER_CTRL, 0, x)
|
|
#define ABOX_KEEPER_CTRL_MASK(x) ABOX_FLD_X(KEEPER_CTRL, x)
|
|
#define ABOX_SW_HYS_CTRL_BASE 1
|
|
#define ABOX_SW_HYS_CTRL_ITV 1
|
|
#define ABOX_SW_HYS_CTRL_H(x) ABOX_H(SW_HYS_CTRL, 0, x)
|
|
#define ABOX_SW_HYS_CTRL_L(x) ABOX_L(SW_HYS_CTRL, 0, x)
|
|
#define ABOX_SW_HYS_CTRL_MASK(x) ABOX_FLD_X(SW_HYS_CTRL, x)
|
|
#define ABOX_SW_ENABLE_H 0
|
|
#define ABOX_SW_ENABLE_L(x) 0
|
|
#define ABOX_SW_ENABLE_MASK(x) ABOX_FLD(SW_ENABLE)
|
|
/* ABOX_SOUNDWIRE_DEBUG */
|
|
#define ABOX_DEBUG_EN_H 0
|
|
#define ABOX_DEBUG_EN_L(x) 0
|
|
#define ABOX_DEBUG_EN_MASK(x) ABOX_FLD(DEBUG_EN)
|
|
/* ABOX_SW_PDI_CTRL0 */
|
|
/* ABOX_SW_PDI_CTRL1 */
|
|
#define ABOX_BI_PDI_FORMAT_BASE 0
|
|
#define ABOX_BI_PDI_FORMAT_ITV 8
|
|
#define ABOX_BI_PDI_FORMAT_H(x) ABOX_H(BI_PDI_FORMAT, 4, x)
|
|
#define ABOX_BI_PDI_FORMAT_L(x) ABOX_L(BI_PDI_FORMAT, 0, x)
|
|
#define ABOX_BI_PDI_FORMAT_MASK(x) ABOX_FLD_X(BI_PDI_FORMAT, x)
|
|
/* ABOX_SW_PDI_CTRL2 */
|
|
#define ABOX_TX_PDI_FORMAT_BASE 0
|
|
#define ABOX_TX_PDI_FORMAT_ITV 8
|
|
#define ABOX_TX_PDI_FORMAT_H(x) ABOX_H(TX_PDI_FORMAT, 4, x)
|
|
#define ABOX_TX_PDI_FORMAT_L(x) ABOX_L(TX_PDI_FORMAT, 0, x)
|
|
#define ABOX_TX_PDI_FORMAT_MASK(x) ABOX_FLD_X(TX_PDI_FORMAT, x)
|
|
/* ABOX_SW_PDI_CTRL3 */
|
|
#define ABOX_RX_PDI_FORMAT_BASE 0
|
|
#define ABOX_RX_PDI_FORMAT_ITV 8
|
|
#define ABOX_RX_PDI_FORMAT_H(x) ABOX_H(RX_PDI_FORMAT, 4, x)
|
|
#define ABOX_RX_PDI_FORMAT_L(x) ABOX_L(RX_PDI_FORMAT, 0, x)
|
|
#define ABOX_RX_PDI_FORMAT_MASK(x) ABOX_FLD_X(RX_PDI_FORMAT, x)
|
|
/* SOUNDWIRE HELPERS */
|
|
#define ABOX_SW_PDI_CTRL_BI_PDI(x) \
|
|
ABOX_SFR_FLD(SW_PDI_CTRL0, BI_PDI_FORMAT, 0, x)
|
|
#define ABOX_SW_PDI_CTRL_TX_PDI ABOX_SW_PDI_CTRL2
|
|
#define ABOX_SW_PDI_CTRL_RX_PDI ABOX_SW_PDI_CTRL3
|
|
|
|
/* UAIF */
|
|
#define ABOX_UAIF_BASE 0x0C00
|
|
#define ABOX_UAIF_ITV 0x0010
|
|
#define ABOX_UAIF_CTRL0(x) ABOX_SFR(UAIF, 0x0, x)
|
|
#define ABOX_UAIF_CTRL1(x) ABOX_SFR(UAIF, 0x4, x)
|
|
#define ABOX_UAIF_IRQ_CTRL(x) ABOX_SFR(UAIF, 0x8, x)
|
|
#define ABOX_UAIF_STATUS(x) ABOX_SFR(UAIF, 0xC, x)
|
|
/* ABOX_UAIF_CTRL0 */
|
|
#define ABOX_START_FIFO_DIFF_MIC_H 31
|
|
#define ABOX_START_FIFO_DIFF_MIC_L 28
|
|
#define ABOX_START_FIFO_DIFF_MIC_MASK ABOX_FLD(START_FIFO_DIFF_MIC)
|
|
#define ABOX_START_FIFO_DIFF_SPK_H 27
|
|
#define ABOX_START_FIFO_DIFF_SPK_L 24
|
|
#define ABOX_START_FIFO_DIFF_SPK_MASK ABOX_FLD(START_FIFO_DIFF_SPK)
|
|
#define ABOX_START_FIFO_SIZE_MIC_H 23
|
|
#define ABOX_START_FIFO_SIZE_MIC_L 20
|
|
#define ABOX_START_FIFO_SIZE_MIC_MASK ABOX_FLD(START_FIFO_SIZE_MIC)
|
|
#define ABOX_START_FIFO_SIZE_SPK_H 19
|
|
#define ABOX_START_FIFO_SIZE_SPK_L 16
|
|
#define ABOX_START_FIFO_SIZE_SPK_MASK ABOX_FLD(START_FIFO_SIZE_SPK)
|
|
#define ABOX_DATA_MODE_H 4
|
|
#define ABOX_DATA_MODE_L 4
|
|
#define ABOX_DATA_MODE_MASK ABOX_FLD(DATA_MODE)
|
|
#define ABOX_IRQ_MODE_H 3
|
|
#define ABOX_IRQ_MODE_L 3
|
|
#define ABOX_IRQ_MODE_MASK ABOX_FLD(IRQ_MODE)
|
|
#define ABOX_MODE_H 2
|
|
#define ABOX_MODE_L 2
|
|
#define ABOX_MODE_MASK ABOX_FLD(MODE)
|
|
#define ABOX_MIC_ENABLE_H 1
|
|
#define ABOX_MIC_ENABLE_L 1
|
|
#define ABOX_MIC_ENABLE_MASK ABOX_FLD(MIC_ENABLE)
|
|
#define ABOX_SPK_ENABLE_H 0
|
|
#define ABOX_SPK_ENABLE_L 0
|
|
#define ABOX_SPK_ENABLE_MASK ABOX_FLD(SPK_ENABLE)
|
|
/* ABOX_UAIF_CTRL1 */
|
|
#define ABOX_FORMAT_H 28
|
|
#define ABOX_FORMAT_L 24
|
|
#define ABOX_FORMAT_MASK ABOX_FLD(FORMAT)
|
|
#define ABOX_BCLK_POLARITY_H 23
|
|
#define ABOX_BCLK_POLARITY_L 23
|
|
#define ABOX_BCLK_POLARITY_MASK ABOX_FLD(BCLK_POLARITY)
|
|
#define ABOX_WS_MODE_H 22
|
|
#define ABOX_WS_MODE_L 22
|
|
#define ABOX_WS_MODE_MASK ABOX_FLD(WS_MODE)
|
|
#define ABOX_WS_POLAR_H 21
|
|
#define ABOX_WS_POLAR_L 21
|
|
#define ABOX_WS_POLAR_MASK ABOX_FLD(WS_POLAR)
|
|
#define ABOX_SLOT_MAX_H 20
|
|
#define ABOX_SLOT_MAX_L 18
|
|
#define ABOX_SLOT_MAX_MASK ABOX_FLD(SLOT_MAX)
|
|
#define ABOX_SBIT_MAX_H 17
|
|
#define ABOX_SBIT_MAX_L 12
|
|
#define ABOX_SBIT_MAX_MASK ABOX_FLD(SBIT_MAX)
|
|
#define ABOX_VALID_STR_H 11
|
|
#define ABOX_VALID_STR_L 6
|
|
#define ABOX_VALID_STR_MASK ABOX_FLD(VALID_STR)
|
|
#define ABOX_VALID_END_H 5
|
|
#define ABOX_VALID_END_L 0
|
|
#define ABOX_VALID_END_MASK ABOX_FLD(VALID_END)
|
|
/* ABOX_UAIF_IRQ_CTRL */
|
|
#define ABOX_FILTER_CNT_H 6
|
|
#define ABOX_FILTER_CNT_L 0
|
|
#define ABOX_FILTER_CNT ABOX_FLD(FILTER_CNT)
|
|
/* ABOX_UAIF_STATUS */
|
|
#define ABOX_ERROR_OF_MIC_H 1
|
|
#define ABOX_ERROR_OF_MIC_L 1
|
|
#define ABOX_ERROR_OF_MIC_MASK ABOX_FLD(ERROR_OF_MIC)
|
|
#define ABOX_ERROR_OF_SPK_H 0
|
|
#define ABOX_ERROR_OF_SPK_L 0
|
|
#define ABOX_ERROR_OF_SPK_MASK ABOX_FLD(ERROR_OF_SPK)
|
|
|
|
/* DSIF */
|
|
#define ABOX_DSIF_CTRL 0x0CF0
|
|
#define ABOX_DSIF_STATUS 0x0CF4
|
|
/* ABOX_DSIF_CTRL */
|
|
#define ABOX_DSIF_MODE_H 3
|
|
#define ABOX_DSIF_MODE_L 3
|
|
#define ABOX_DSIF_MODE_MASK ABOX_FLD(DSIF_MODE)
|
|
#define ABOX_DSIF_BCLK_POLARITY_H 2
|
|
#define ABOX_DSIF_BCLK_POLARITY_L 2
|
|
#define ABOX_DSIF_BCLK_POLARITY_MASK ABOX_FLD(DSIF_BCLK_POLARITY)
|
|
#define ABOX_ORDER_H 1
|
|
#define ABOX_ORDER_L 1
|
|
#define ABOX_ORDER_MASK ABOX_FLD(ORDER)
|
|
#define ABOX_ENABLE_H 0
|
|
#define ABOX_ENABLE_L 0
|
|
#define ABOX_ENABLE_MASK ABOX_FLD(ENABLE)
|
|
/* ABOX_DSIF_STATUS */
|
|
#define ABOX_ERROR_H 0
|
|
#define ABOX_ERROR_L 0
|
|
#define ABOX_ERROR_MASK ABOX_FLD(ERROR)
|
|
|
|
/* SPDYIF */
|
|
#define ABOX_SPDYIF_CTRL 0x0D00
|
|
/* ABOX_SPDYIF_CTRL */
|
|
#define ABOX_START_FIFO_DIFF_H 4
|
|
#define ABOX_START_FIFO_DIFF_L 1
|
|
#define ABOX_START_FIFO_DIFF_MASK ABOX_FLD(START_FIFO_DIFF)
|
|
|
|
/* RDMA */
|
|
#define ABOX_RDMA_BASE 0x1000
|
|
#define ABOX_RDMA_ITV 0x0100
|
|
#define ABOX_RDMA_CTRL(x) ABOX_SFR(RDMA, 0x00, x)
|
|
#define ABOX_RDMA_BUF_RESTART(x) ABOX_SFR(RDMA, 0x04, x)
|
|
#define ABOX_RDMA_CTRL0(x) ABOX_RDMA_CTRL(x)
|
|
#define ABOX_RDMA_CTRL1(x) ABOX_RDMA_BUF_RESTART(x)
|
|
#define ABOX_RDMA_BUF_STR(x) ABOX_SFR(RDMA, 0x08, x)
|
|
#define ABOX_RDMA_BUF_END(x) ABOX_SFR(RDMA, 0x0C, x)
|
|
#define ABOX_RDMA_BUF_OFFSET(x) ABOX_SFR(RDMA, 0x10, x)
|
|
#define ABOX_RDMA_STR_POINT(x) ABOX_SFR(RDMA, 0x14, x)
|
|
#define ABOX_RDMA_VOL_FACTOR(x) ABOX_SFR(RDMA, 0x18, x)
|
|
#define ABOX_RDMA_VOL_CHANGE(x) ABOX_SFR(RDMA, 0x1C, x)
|
|
#define ABOX_RDMA_SBANK_LIMIT(x) ABOX_SFR(RDMA, 0x20, x)
|
|
#define ABOX_RDMA_BIT_CTRL(x) ABOX_SFR(RDMA, 0x24, x)
|
|
#define ABOX_RDMA_DITHER_SEED(x) ABOX_SFR(RDMA, 0x28, x)
|
|
#define ABOX_RDMA_STATUS(x) ABOX_SFR(RDMA, 0x30, x)
|
|
#define ABOX_RDMA_STATUS_ADD(x) ABOX_SFR(RDMA, 0x38, x)
|
|
/* ABOX_RDMA_CTRL0 */
|
|
#define ABOX_RDMA_BURST_LEN_H 22
|
|
#define ABOX_RDMA_BURST_LEN_L 19
|
|
#define ABOX_RDMA_BURST_LEN_MASK ABOX_FLD(RDMA_BURST_LEN)
|
|
#define ABOX_RDMA_ENABLE_H 0
|
|
#define ABOX_RDMA_ENABLE_L 0
|
|
#define ABOX_RDMA_ENABLE_MASK ABOX_FLD(RDMA_ENABLE)
|
|
/* ABOX_RDMA_VOL_FACTOR */
|
|
#define ABOX_RDMA_VOL_FACTOR_H 23
|
|
#define ABOX_RDMA_VOL_FACTOR_L 0
|
|
#define ABOX_RDMA_VOL_FACTOR_MASK ABOX_FLD(RDMA_VOL_FACTOR)
|
|
/* ABOX_RDMA_STATUS */
|
|
#define ABOX_RDMA_PROGRESS_H 31
|
|
#define ABOX_RDMA_PROGRESS_L 31
|
|
#define ABOX_RDMA_PROGRESS_MASK ABOX_FLD(RDMA_PROGRESS)
|
|
#define ABOX_RDMA_RBUF_OFFSET_H 27
|
|
#define ABOX_RDMA_RBUF_OFFSET_L 20
|
|
#define ABOX_RDMA_RBUF_OFFSET_MASK ABOX_FLD(RDMA_RBUF_OFFSET)
|
|
#define ABOX_RDMA_RBUF_CNT_H 19
|
|
#define ABOX_RDMA_RBUF_CNT_L 0
|
|
#define ABOX_RDMA_RBUF_CNT_MASK ABOX_FLD(RDMA_RBUF_CNT)
|
|
/* ABOX_RDMA_STATUS_ADD */
|
|
#define ABOX_RDMA_RBUF_CURRENT_ADDRESS_H 30
|
|
#define ABOX_RDMA_RBUF_CURRENT_ADDRESS_L 0
|
|
#define ABOX_RDMA_RBUF_CURRENT_ADDRESS_MASK ABOX_FLD(RDMA_RBUF_CURRENT_ADDRESS)
|
|
|
|
/* SPUS ASRC */
|
|
#define ABOX_SPUS_ASRC_BASE 0x2000
|
|
#define ABOX_SPUS_ASRC_ITV 0x0100
|
|
#define ABOX_SPUS_ASRC_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x00, x)
|
|
#define ABOX_SPUS_ASRC_IS_DEFAULT(x) ABOX_SFR(SPUS_ASRC, 0x10, x)
|
|
#define ABOX_SPUS_ASRC_IS_TPLIMIT(x) ABOX_SFR(SPUS_ASRC, 0x14, x)
|
|
#define ABOX_SPUS_ASRC_OS_DEFAULT(x) ABOX_SFR(SPUS_ASRC, 0x18, x)
|
|
#define ABOX_SPUS_ASRC_OS_TPLIMIT(x) ABOX_SFR(SPUS_ASRC, 0x1C, x)
|
|
#define ABOX_SPUS_ASRC_DITHER_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x20, x)
|
|
#define ABOX_SPUS_ASRC_SEED(x) ABOX_SFR(SPUS_ASRC, 0x24, x)
|
|
#define ABOX_SPUS_ASRC_SEED_IN(x) ABOX_SFR(SPUS_ASRC, 0x24, x)
|
|
#define ABOX_SPUS_ASRC_SEED_OUT(x) ABOX_SFR(SPUS_ASRC, 0x28, x)
|
|
#define ABOX_SPUS_ASRC_FILTER_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x2C, x)
|
|
|
|
/* WDMA */
|
|
#define ABOX_WDMA_BASE 0x3000
|
|
#define ABOX_WDMA_ITV 0x0100
|
|
#define ABOX_WDMA_CTRL(x) ABOX_SFR(WDMA, 0x00, x)
|
|
#define ABOX_WDMA_BUF_RESTART(x) ABOX_SFR(WDMA, 0x04, x)
|
|
#define ABOX_WDMA_CTRL0(x) ABOX_WDMA_CTRL(x)
|
|
#define ABOX_WDMA_CTRL1(x) ABOX_WDMA_BUF_RESTART(x)
|
|
#define ABOX_WDMA_BUF_STR(x) ABOX_SFR(WDMA, 0x08, x)
|
|
#define ABOX_WDMA_BUF_END(x) ABOX_SFR(WDMA, 0x0C, x)
|
|
#define ABOX_WDMA_BUF_OFFSET(x) ABOX_SFR(WDMA, 0x10, x)
|
|
#define ABOX_WDMA_STR_POINT(x) ABOX_SFR(WDMA, 0x14, x)
|
|
#define ABOX_WDMA_VOL_FACTOR(x) ABOX_SFR(WDMA, 0x18, x)
|
|
#define ABOX_WDMA_VOL_CHANGE(x) ABOX_SFR(WDMA, 0x1C, x)
|
|
#define ABOX_WDMA_SBANK_LIMIT(x) ABOX_SFR(WDMA, 0x20, x)
|
|
#define ABOX_WDMA_BIT_CTRL(x) ABOX_SFR(WDMA, 0x24, x)
|
|
#define ABOX_WDMA_DITHER_SEED(x) ABOX_SFR(WDMA, 0x28, x)
|
|
#define ABOX_WDMA_STATUS(x) ABOX_SFR(WDMA, 0x30, x)
|
|
#define ABOX_WDMA_STATUS_ADD(x) ABOX_SFR(WDMA, 0x38, x)
|
|
#define ABOX_WDMA_DUAL_CTRL(x) ABOX_SFR(WDMA, 0x80, x)
|
|
#define ABOX_WDMA_DUAL_BUF_STR(x) ABOX_SFR(WDMA, 0x88, x)
|
|
#define ABOX_WDMA_DUAL_BUF_END(x) ABOX_SFR(WDMA, 0x8C, x)
|
|
#define ABOX_WDMA_DUAL_BUF_OFFSET(x) ABOX_SFR(WDMA, 0x90, x)
|
|
#define ABOX_WDMA_DUAL_STR_POINT(x) ABOX_SFR(WDMA, 0x94, x)
|
|
#define ABOX_WDMA_DUAL_STATUS(x) ABOX_SFR(WDMA, 0xB0, x)
|
|
#define ABOX_WDMA_DUAL_STATUS_ADD(x) ABOX_SFR(WDMA, 0xB8, x)
|
|
/* ABOX_WDMA_CTRL */
|
|
#define ABOX_WDMA_ENABLE_H 0
|
|
#define ABOX_WDMA_ENABLE_L 0
|
|
#define ABOX_WDMA_ENABLE_MASK ABOX_FLD(WDMA_ENABLE)
|
|
/* ABOX_WDMA_STATUS */
|
|
#define ABOX_WDMA_PROGRESS_H 31
|
|
#define ABOX_WDMA_PROGRESS_L 31
|
|
#define ABOX_WDMA_PROGRESS_MASK ABOX_FLD(WDMA_PROGRESS)
|
|
#define ABOX_WDMA_WBUF_OFFSET_H 27
|
|
#define ABOX_WDMA_WBUF_OFFSET_L 20
|
|
#define ABOX_WDMA_WBUF_OFFSET_MASK ABOX_FLD(WDMA_WBUF_OFFSET)
|
|
#define ABOX_WDMA_WBUF_CNT_H 19
|
|
#define ABOX_WDMA_WBUF_CNT_L 0
|
|
#define ABOX_WDMA_WBUF_CNT_MASK ABOX_FLD(WDMA_WBUF_CNT)
|
|
/* ABOX_WDMA_STATUS_ADD */
|
|
#define ABOX_WDMA_WBUF_CURRENT_ADDRESS_H 30
|
|
#define ABOX_WDMA_WBUF_CURRENT_ADDRESS_L 0
|
|
#define ABOX_WDMA_WBUF_CURRENT_ADDRESS_MASK ABOX_FLD(WDMA_WBUF_CURRENT_ADDRESS)
|
|
|
|
/* WDMA_DEBUG */
|
|
#define ABOX_WDMA_DEBUG_BASE 0x3800
|
|
#define ABOX_WDMA_DEBUG_ITV 0x0100
|
|
#define ABOX_WDMA_DEBUG_CTRL(x) ABOX_SFR(WDMA_DEBUG, 0x00, x)
|
|
#define ABOX_WDMA_DEBUG_BUF_RESTART(x) ABOX_SFR(WDMA_DEBUG, 0x04, x)
|
|
#define ABOX_WDMA_DEBUG_BUF_STR(x) ABOX_SFR(WDMA_DEBUG, 0x08, x)
|
|
#define ABOX_WDMA_DEBUG_BUF_END(x) ABOX_SFR(WDMA_DEBUG, 0x0C, x)
|
|
#define ABOX_WDMA_DEBUG_BUF_OFFSET(x) ABOX_SFR(WDMA_DEBUG, 0x10, x)
|
|
#define ABOX_WDMA_DEBUG_STR_POINT(x) ABOX_SFR(WDMA_DEBUG, 0x14, x)
|
|
#define ABOX_WDMA_DEBUG_VOL_FACTOR(x) ABOX_SFR(WDMA_DEBUG, 0x18, x)
|
|
#define ABOX_WDMA_DEBUG_VOL_CHANGE(x) ABOX_SFR(WDMA_DEBUG, 0x1C, x)
|
|
#define ABOX_WDMA_DEBUG_SBANK_LIMIT(x) ABOX_SFR(WDMA_DEBUG, 0x20, x)
|
|
#define ABOX_WDMA_DEBUG_STATUS(x) ABOX_SFR(WDMA_DEBUG, 0x30, x)
|
|
#define ABOX_WDMA_DEBUG_STATUS_ADD(x) ABOX_SFR(WDMA_DEBUG, 0x38, x)
|
|
|
|
/* ABOX_xDMA_CTRL */
|
|
#define ABOX_DMA_DEBUG_SRC_H 29
|
|
#define ABOX_DMA_DEBUG_SRC_L 24
|
|
#define ABOX_DMA_DEBUG_SRC_MASK ABOX_FLD(DMA_DEBUG_SRC)
|
|
#define ABOX_DMA_SYNC_MODE_H 24
|
|
#define ABOX_DMA_SYNC_MODE_L 24
|
|
#define ABOX_DMA_SYNC_MODE_MASK ABOX_FLD(DMA_SYNC_MODE)
|
|
#define ABOX_DMA_BURST_LEN_H 22
|
|
#define ABOX_DMA_BURST_LEN_L 19
|
|
#define ABOX_DMA_BURST_LEN_MASK ABOX_FLD(DMA_BURST_LEN)
|
|
#define ABOX_DMA_FUNC_H 18
|
|
#define ABOX_DMA_FUNC_L 16
|
|
#define ABOX_DMA_FUNC_MASK ABOX_FLD(DMA_FUNC)
|
|
#define ABOX_DMA_AUTO_FADE_IN_H 15
|
|
#define ABOX_DMA_AUTO_FADE_IN_L 15
|
|
#define ABOX_DMA_AUTO_FADE_IN_MASK ABOX_FLD(DMA_AUTO_FADE_IN)
|
|
#define ABOX_DMA_PACKED_H 14
|
|
#define ABOX_DMA_PACKED_L 14
|
|
#define ABOX_DMA_PACKED_MASK ABOX_FLD(DMA_PACKED)
|
|
#define ABOX_DMA_REDUCE_H 13
|
|
#define ABOX_DMA_REDUCE_L 13
|
|
#define ABOX_DMA_REDUCE_MASK ABOX_FLD(DMA_REDUCE)
|
|
#define ABOX_DMA_EXPAND_H 13
|
|
#define ABOX_DMA_EXPAND_L 13
|
|
#define ABOX_DMA_EXPAND_MASK ABOX_FLD(DMA_EXPAND)
|
|
#define ABOX_DMA_WIDTH_H 12
|
|
#define ABOX_DMA_WIDTH_L 11
|
|
#define ABOX_DMA_WIDTH_MASK ABOX_FLD(DMA_WIDTH)
|
|
#define ABOX_DMA_CHANNELS_H 10
|
|
#define ABOX_DMA_CHANNELS_L 8
|
|
#define ABOX_DMA_CHANNELS_MASK ABOX_FLD(DMA_CHANNELS)
|
|
#define ABOX_DMA_FORMAT_H 12
|
|
#define ABOX_DMA_FORMAT_L 8
|
|
#define ABOX_DMA_FORMAT_MASK ABOX_FLD(DMA_FORMAT)
|
|
#define ABOX_DMA_BUF_UPDATE_H 5
|
|
#define ABOX_DMA_BUF_UPDATE_L 5
|
|
#define ABOX_DMA_BUF_UPDATE_MASK ABOX_FLD(DMA_BUF_UPDATE)
|
|
#define ABOX_DMA_BUF_TYPE_H 4
|
|
#define ABOX_DMA_BUF_TYPE_L 4
|
|
#define ABOX_DMA_BUF_TYPE_MASK ABOX_FLD(DMA_BUF_TYPE)
|
|
#define ABOX_DMA_DUMMY_START_H 1
|
|
#define ABOX_DMA_DUMMY_START_L 1
|
|
#define ABOX_DMA_DUMMY_START_MASK ABOX_FLD(DMA_DUMMY_START)
|
|
#define ABOX_DMA_ENABLE_H 0
|
|
#define ABOX_DMA_ENABLE_L 0
|
|
#define ABOX_DMA_ENABLE_MASK ABOX_FLD(DMA_ENABLE)
|
|
/* ABOX_xDMA_BUF_RESTART */
|
|
#define ABOX_DMA_RESTART_H 0
|
|
#define ABOX_DMA_RESTART_L 0
|
|
#define ABOX_DMA_RESTART_MASK ABOX_FLD(DMA_RESTART)
|
|
/* ABOX_xDMA_BUF_STR */
|
|
#define ABOX_DMA_BUF_STR_H 31
|
|
#define ABOX_DMA_BUF_STR_L 4
|
|
#define ABOX_DMA_BUF_STR_MASK ABOX_FLD(DMA_BUF_STR)
|
|
/* ABOX_xDMA_BUF_END */
|
|
#define ABOX_DMA_BUF_END_H 31
|
|
#define ABOX_DMA_BUF_END_L 4
|
|
#define ABOX_DMA_BUF_END_MASK ABOX_FLD(DMA_BUF_END)
|
|
/* ABOX_xDMA_BUF_OFFSET */
|
|
#define ABOX_DMA_BUF_OFFSET_H 15
|
|
#define ABOX_DMA_BUF_OFFSET_L 4
|
|
#define ABOX_DMA_BUF_OFFSET_MASK ABOX_FLD(DMA_BUF_OFFSET)
|
|
/* ABOX_xDMA_STR_POINT */
|
|
#define ABOX_DMA_STR_POINT_H 31
|
|
#define ABOX_DMA_STR_POINT_L 4
|
|
#define ABOX_DMA_STR_POINT_MASK ABOX_FLD(DMA_STR_POINT)
|
|
/* ABOX_xDMA_VOL_FACTOR */
|
|
#define ABOX_DMA_VOL_FACTOR_H 23
|
|
#define ABOX_DMA_VOL_FACTOR_L 0
|
|
#define ABOX_DMA_VOL_FACTOR_MASK ABOX_FLD(DMA_VOL_FACTOR)
|
|
/* ABOX_xDMA_VOL_CHANGE */
|
|
#define ABOX_DMA_VOL_CHANGE_H 23
|
|
#define ABOX_DMA_VOL_CHANGE_L 0
|
|
#define ABOX_DMA_VOL_CHANGE_MASK ABOX_FLD(DMA_VOL_CHANGE)
|
|
/* ABOX_xDMA_SBANK_LIMIT */
|
|
#define ABOX_DMA_SBANK_LIMIT_H 13
|
|
#define ABOX_DMA_SBANK_LIMIT_L 4
|
|
#define ABOX_DMA_SBANK_LIMIT_MASK ABOX_FLD(DMA_SBANK_LIMIT)
|
|
/* ABOX_xDMA_BIT_CTRL */
|
|
#define ABOX_DMA_DITHER_ON_H 15
|
|
#define ABOX_DMA_DITHER_ON_L 15
|
|
#define ABOX_DMA_DITHER_ON_MASK ABOX_FLD(DMA_DITHER_ON)
|
|
#define ABOX_DMA_DITHER_STRENGTH_H 14
|
|
#define ABOX_DMA_DITHER_STRENGTH_L 8
|
|
#define ABOX_DMA_DITHER_STRENGTH_MASK ABOX_FLD(DMA_DITHER_STRENGTH)
|
|
#define ABOX_DMA_DITHER_WIDTH_H 5
|
|
#define ABOX_DMA_DITHER_WIDTH_L 4
|
|
#define ABOX_DMA_DITHER_WIDTH_MASK ABOX_FLD(DMA_DITHER_WIDTH)
|
|
#if (ABOX_SOC_VERSION(3, 1, 0) < CONFIG_SND_SOC_SAMSUNG_ABOX_VERSION)
|
|
#define ABOX_DMA_DST_BIT_WIDTH_H 17
|
|
#define ABOX_DMA_DST_BIT_WIDTH_L 16
|
|
#define ABOX_DMA_DST_BIT_WIDTH_MASK ABOX_FLD(DMA_DST_BIT_WIDTH)
|
|
#else
|
|
#define ABOX_DMA_DST_BIT_WIDTH_H 1
|
|
#define ABOX_DMA_DST_BIT_WIDTH_L 0
|
|
#define ABOX_DMA_DST_BIT_WIDTH_MASK ABOX_FLD(DMA_DST_BIT_WIDTH)
|
|
#endif
|
|
#define ABOX_DMA_DITHER_TYPE_H 1
|
|
#define ABOX_DMA_DITHER_TYPE_L 0
|
|
#define ABOX_DMA_DITHER_TYPE_MASK ABOX_FLD(DMA_DITHER_TYPE)
|
|
/* ABOX_xDMA_DITHER_SEED */
|
|
#define ABOX_DMA_DITHER_IN_SEED_H 31
|
|
#define ABOX_DMA_DITHER_IN_SEED_L 0
|
|
#define ABOX_DMA_DITHER_IN_SEED_MASK ABOX_FLD(DMA_DITHER_IN_SEED)
|
|
#define ABOX_DMA_DITHER_SEED_H 31
|
|
#define ABOX_DMA_DITHER_SEED_L 0
|
|
#define ABOX_DMA_DITHER_SEED_MASK ABOX_FLD(DMA_DITHER_SEED)
|
|
/* ABOX_xDMA_STATUS */
|
|
#define ABOX_DMA_PROGRESS_H 31
|
|
#define ABOX_DMA_PROGRESS_L 31
|
|
#define ABOX_DMA_PROGRESS_MASK ABOX_FLD(DMA_PROGRESS)
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_H 27
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_L 20
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_MASK ABOX_FLD(DMA_BUF_OFFSET_CNT)
|
|
#define ABOX_DMA_BUF_CNT_H 19
|
|
#define ABOX_DMA_BUF_CNT_L 0
|
|
#define ABOX_DMA_BUF_CNT_MASK ABOX_FLD(DMA_BUF_CNT)
|
|
/* ABOX_xDMA_STATUS_ADD */
|
|
#define ABOX_DMA_BUF_CURRENT_ADDRESS_H 30
|
|
#define ABOX_DMA_BUF_CURRENT_ADDRESS_L 0
|
|
#define ABOX_DMA_BUF_CURRENT_ADDRESS_MASK ABOX_FLD(DMA_BUF_CURRENT_ADDRESS)
|
|
|
|
/* SPUM ASRC */
|
|
#define ABOX_SPUM_ASRC_BASE 0x4000
|
|
#define ABOX_SPUM_ASRC_ITV 0x0100
|
|
#define ABOX_SPUM_ASRC_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x0, x)
|
|
#define ABOX_SPUM_ASRC_IS_DEFAULT(x) ABOX_SFR(SPUM_ASRC, 0x10, x)
|
|
#define ABOX_SPUM_ASRC_IS_TPLIMIT(x) ABOX_SFR(SPUM_ASRC, 0x14, x)
|
|
#define ABOX_SPUM_ASRC_OS_DEFAULT(x) ABOX_SFR(SPUM_ASRC, 0x18, x)
|
|
#define ABOX_SPUM_ASRC_OS_TPLIMIT(x) ABOX_SFR(SPUM_ASRC, 0x1C, x)
|
|
#define ABOX_SPUM_ASRC_DITHER_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x20, x)
|
|
#define ABOX_SPUM_ASRC_SEED(x) ABOX_SFR(SPUM_ASRC, 0x24, x)
|
|
#define ABOX_SPUM_ASRC_SEED_IN(x) ABOX_SFR(SPUM_ASRC, 0x24, x)
|
|
#define ABOX_SPUM_ASRC_SEED_OUT(x) ABOX_SFR(SPUM_ASRC, 0x28, x)
|
|
#define ABOX_SPUM_ASRC_FILTER_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x2C, x)
|
|
|
|
/* ABOX_SPUS_ASRCx_CTRL */
|
|
/* ABOX_SPUM_ASRCx_CTRL */
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_H 27
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_L 24
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_MASK ABOX_FLD(ASRC_OS_SOURCE_SEL)
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_H 23
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_L 20
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_MASK ABOX_FLD(ASRC_IS_SOURCE_SEL)
|
|
#define ABOX_ASRC_TICKDIV_H 19
|
|
#define ABOX_ASRC_TICKDIV_L 16
|
|
#define ABOX_ASRC_TICKDIV_MASK ABOX_FLD(ASRC_TICKDIV)
|
|
#define ABOX_ASRC_TICKNUM_H 15
|
|
#define ABOX_ASRC_TICKNUM_L 8
|
|
#define ABOX_ASRC_TICKNUM_MASK ABOX_FLD(ASRC_TICKNUM)
|
|
#define ABOX_ASRC_BIT_WIDTH_H 7
|
|
#define ABOX_ASRC_BIT_WIDTH_L 6
|
|
#define ABOX_ASRC_BIT_WIDTH_MASK ABOX_FLD(ASRC_BIT_WIDTH)
|
|
#define ABOX_ASRC_DCMF_RATIO_H 5
|
|
#define ABOX_ASRC_DCMF_RATIO_L 4
|
|
#define ABOX_ASRC_DCMF_RATIO_MASK ABOX_FLD(ASRC_DCMF_RATIO)
|
|
#define ABOX_ASRC_OVSF_RATIO_H 3
|
|
#define ABOX_ASRC_OVSF_RATIO_L 2
|
|
#define ABOX_ASRC_OVSF_RATIO_MASK ABOX_FLD(ASRC_OVSF_RATIO)
|
|
#define ABOX_ASRC_OS_SYNC_MODE_H 1
|
|
#define ABOX_ASRC_OS_SYNC_MODE_L 1
|
|
#define ABOX_ASRC_OS_SYNC_MODE_MASK ABOX_FLD(ASRC_OS_SYNC_MODE)
|
|
#define ABOX_ASRC_IS_SYNC_MODE_H 0
|
|
#define ABOX_ASRC_IS_SYNC_MODE_L 0
|
|
#define ABOX_ASRC_IS_SYNC_MODE_MASK ABOX_FLD(ASRC_IS_SYNC_MODE)
|
|
/* ABOX_SPUS_ASRCx_IS_PARA0 */
|
|
/* ABOX_SPUM_ASRCx_IS_PARA0 */
|
|
#define ABOX_ASRC_IS_DEFAULT_H 16
|
|
#define ABOX_ASRC_IS_DEFAULT_L 0
|
|
#define ABOX_ASRC_IS_DEFAULT_MASK ABOX_FLD(ASRC_IS_DEFAULT)
|
|
/* ABOX_SPUS_ASRCx_IS_PARA1 */
|
|
/* ABOX_SPUM_ASRCx_IS_PARA1 */
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_H 16
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_L 0
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_MASK ABOX_FLD(ASRC_IS_TPERIOD_LIMIT)
|
|
/* ABOX_SPUS_ASRCx_OS_PARA0 */
|
|
/* ABOX_SPUM_ASRCx_OS_PARA0 */
|
|
#define ABOX_ASRC_OS_DEFAULT_H 16
|
|
#define ABOX_ASRC_OS_DEFAULT_L 0
|
|
#define ABOX_ASRC_OS_DEFAULT_MASK ABOX_FLD(ASRC_OS_DEFAULT)
|
|
/* ABOX_SPUS_ASRCx_OS_PARA1 */
|
|
/* ABOX_SPUM_ASRCx_OS_PARA1 */
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_H 16
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_L 0
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_MASK ABOX_FLD(ASRC_OS_TPERIOD_LIMIT)
|
|
/* ABOX_SPUS_ASRCx_DITHER_CTRL */
|
|
/* ABOX_SPUM_ASRCx_DITHER_CTRL */
|
|
#define ABOX_ASRC_DITHER_IN_ON_H 25
|
|
#define ABOX_ASRC_DITHER_IN_ON_L 25
|
|
#define ABOX_ASRC_DITHER_IN_ON_MASK ABOX_FLD(ASRC_DITHER_IN_ON)
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_H 24
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_L 18
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_MASK ABOX_FLD(ASRC_DITHER_IN_STRENGTH)
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_H 17
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_L 16
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_MASK ABOX_FLD(ASRC_DITHER_IN_WIDTH)
|
|
#define ABOX_ASRC_DITHER_OUT_ON_H 9
|
|
#define ABOX_ASRC_DITHER_OUT_ON_L 9
|
|
#define ABOX_ASRC_DITHER_OUT_ON_MASK ABOX_FLD(ASRC_DITHER_OUT_ON)
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_H 8
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_L 2
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_MASK ABOX_FLD(ASRC_DITHER_OUT_STRENGTH)
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_H 1
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_L 0
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_MASK ABOX_FLD(ASRC_DITHER_OUT_WIDTH)
|
|
#define ABOX_ASRC_DITHER_TYPE_H 1
|
|
#define ABOX_ASRC_DITHER_TYPE_L 0
|
|
#define ABOX_ASRC_DITHER_TYPE_MASK ABOX_FLD(ASRC_DITHER_TYPE)
|
|
/* ABOX_SPUS_ASRCx_SEED */
|
|
/* ABOX_SPUM_ASRCx_SEED */
|
|
#define ABOX_ASRC_DIHER_SEED_H 31
|
|
#define ABOX_ASRC_DIHER_SEED_L 0
|
|
#define ABOX_ASRC_DIHER_SEED_MASK ABOX_FLD(ASRC_DITHER_SEED)
|
|
/* ABOX_SPUS_ASRCx_SEED_IN */
|
|
/* ABOX_SPUM_ASRCx_SEED_IN */
|
|
#define ABOX_ASRC_DIHER_IN_SEED_H 31
|
|
#define ABOX_ASRC_DIHER_IN_SEED_L 0
|
|
#define ABOX_ASRC_DIHER_IN_SEED_MASK ABOX_FLD(ASRC_DITHER_IN_SEED)
|
|
/* ABOX_SPUS_ASRCx_SEED_OUT */
|
|
/* ABOX_SPUM_ASRCx_SEED_OUT */
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_H 31
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_L 0
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_MASK ABOX_FLD(ASRC_DITHER_OUT_SEED)
|
|
/* ABOX_SPUS_ASRCx_FILTER_CTRL */
|
|
/* ABOX_SPUM_ASRCx_FILTER_CTRL */
|
|
#define ABOX_ASRC_APF_COEF_SEL_H 6
|
|
#define ABOX_ASRC_APF_COEF_SEL_L 6
|
|
#define ABOX_ASRC_APF_COEF_SEL_MASK ABOX_FLD(ASRC_APF_COEF_SEL)
|
|
#define ABOX_ASRC_APF_FILTER_SEL_H 5
|
|
#define ABOX_ASRC_APF_FILTER_SEL_L 5
|
|
#define ABOX_ASRC_APF_FILTER_SEL_MASK ABOX_FLD(ASRC_APF_FILTER_SEL)
|
|
#define ABOX_ASRC_TRF_ON_H 4
|
|
#define ABOX_ASRC_TRF_ON_L 4
|
|
#define ABOX_ASRC_TRF_ON_MASK ABOX_FLD(ASRC_TRF_ON)
|
|
#define ABOX_ASRC_TRF_GAIN_H 3
|
|
#define ABOX_ASRC_TRF_GAIN_L 0
|
|
#define ABOX_ASRC_TRF_GAIN_MASK ABOX_FLD(ASRC_TRF_GAIN)
|
|
|
|
/* CA7 */
|
|
#define ABOX_CA7_R_BASE 0x5000
|
|
#define ABOX_CA7_R_ITV 0x0004
|
|
#define ABOX_CA7_R(x) ABOX_SFR(CA7_R, 0x0, x)
|
|
#define ABOX_CA7_PC ABOX_CA7_R(15)
|
|
|
|
/* CA32 */
|
|
#define ABOX_CA32_CORE0_BASE 0x5000
|
|
#define ABOX_CA32_CORE0_ITV 0x0004
|
|
#define ABOX_CA32_CORE0_R(x) ABOX_SFR(CA32_CORE0, 0x0, x)
|
|
#define ABOX_CA32_CORE0_PC ABOX_CA32_CORE0_R(31)
|
|
#define ABOX_CA32_CORE1_BASE 0x5080
|
|
#define ABOX_CA32_CORE1_ITV 0x0004
|
|
#define ABOX_CA32_CORE1_R(x) ABOX_SFR(CA32_CORE1, 0x0, x)
|
|
#define ABOX_CA32_CORE1_PC ABOX_CA32_CORE1_R(31)
|
|
#define ABOX_CA32_STATUS 0x5100
|
|
#define ABOX_CA32_CNT_CTRL 0x5104
|
|
#define ABOX_CA32_CNT_CTRL1 0x5108
|
|
#define ABOX_CA32_CNT_STATUS0 0x510C
|
|
#define ABOX_CA32_CNT_STATUS1 0x5110
|
|
#define ABOX_CA32_CNT_STATUS2 0x5114
|
|
#define ABOX_CA32_CNT_STATUS3 0x5118
|
|
|
|
/* APF_COEF */
|
|
#define ABOX_APF_BASE 0x7000
|
|
#define ABOX_APF_ITV 0x0100
|
|
#define ABOX_COEF_2EVEN0(x) ABOX_SFR(APF, 0x00, x)
|
|
#define ABOX_COEF_2EVEN1(x) ABOX_SFR(APF, 0x04, x)
|
|
#define ABOX_COEF_2EVEN2(x) ABOX_SFR(APF, 0x08, x)
|
|
#define ABOX_COEF_2EVEN3(x) ABOX_SFR(APF, 0x0C, x)
|
|
#define ABOX_COEF_2EVEN4(x) ABOX_SFR(APF, 0x10, x)
|
|
#define ABOX_COEF_2EVEN5(x) ABOX_SFR(APF, 0x14, x)
|
|
#define ABOX_COEF_2EVEN6(x) ABOX_SFR(APF, 0x18, x)
|
|
#define ABOX_COEF_2EVEN7(x) ABOX_SFR(APF, 0x1C, x)
|
|
#define ABOX_COEF_2EVEN8(x) ABOX_SFR(APF, 0x20, x)
|
|
#define ABOX_COEF_2EVEN9(x) ABOX_SFR(APF, 0x24, x)
|
|
#define ABOX_COEF_2ODD0(x) ABOX_SFR(APF, 0x28, x)
|
|
#define ABOX_COEF_2ODD1(x) ABOX_SFR(APF, 0x2C, x)
|
|
#define ABOX_COEF_2ODD2(x) ABOX_SFR(APF, 0x30, x)
|
|
#define ABOX_COEF_2ODD3(x) ABOX_SFR(APF, 0x34, x)
|
|
#define ABOX_COEF_2ODD4(x) ABOX_SFR(APF, 0x38, x)
|
|
#define ABOX_COEF_2ODD5(x) ABOX_SFR(APF, 0x3C, x)
|
|
#define ABOX_COEF_2ODD6(x) ABOX_SFR(APF, 0x40, x)
|
|
#define ABOX_COEF_2ODD7(x) ABOX_SFR(APF, 0x44, x)
|
|
#define ABOX_COEF_2ODD8(x) ABOX_SFR(APF, 0x48, x)
|
|
#define ABOX_COEF_4EVEN0(x) ABOX_SFR(APF, 0x4C, x)
|
|
#define ABOX_COEF_4EVEN1(x) ABOX_SFR(APF, 0x50, x)
|
|
#define ABOX_COEF_4EVEN2(x) ABOX_SFR(APF, 0x54, x)
|
|
#define ABOX_COEF_4ODD0(x) ABOX_SFR(APF, 0x58, x)
|
|
#define ABOX_COEF_4ODD1(x) ABOX_SFR(APF, 0x5C, x)
|
|
#define ABOX_COEF_8EVEN0(x) ABOX_SFR(APF, 0x60, x)
|
|
#define ABOX_COEF_8EVEN1(x) ABOX_SFR(APF, 0x64, x)
|
|
#define ABOX_COEF_8EVEN2(x) ABOX_SFR(APF, 0x68, x)
|
|
#define ABOX_COEF_8ODD0(x) ABOX_SFR(APF, 0x6C, x)
|
|
#define ABOX_COEF_8ODD1(x) ABOX_SFR(APF, 0x70, x)
|
|
|
|
/* AUDEN_RDMA */
|
|
#define ABOX_AUDEN_RDMA_BASE 0x8000
|
|
#define ABOX_AUDEN_RDMA_ITV 0x0100
|
|
#define ABOX_AUDEN_RDMA_CTRL(x) ABOX_SFR(AUDEN_RDMA, 0x00, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_RESTART(x) ABOX_SFR(AUDEN_RDMA, 0x04, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_STR(x) ABOX_SFR(AUDEN_RDMA, 0x08, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_END(x) ABOX_SFR(AUDEN_RDMA, 0x0C, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_OFFSET(x) ABOX_SFR(AUDEN_RDMA, 0x10, x)
|
|
#define ABOX_AUDEN_RDMA_STR_POINT(x) ABOX_SFR(AUDEN_RDMA, 0x14, x)
|
|
#define ABOX_AUDEN_RDMA_VOL_FACTOR(x) ABOX_SFR(AUDEN_RDMA, 0x18, x)
|
|
#define ABOX_AUDEN_RDMA_VOL_CHANGE(x) ABOX_SFR(AUDEN_RDMA, 0x1C, x)
|
|
#define ABOX_AUDEN_RDMA_SBANK_LIMIT(x) ABOX_SFR(AUDEN_RDMA, 0x20, x)
|
|
#define ABOX_AUDEN_RDMA_BIT_CTRL(x) ABOX_SFR(AUDEN_RDMA, 0x24, x)
|
|
#define ABOX_AUDEN_RDMA_DITHER_SEED(x) ABOX_SFR(AUDEN_RDMA, 0x28, x)
|
|
#define ABOX_AUDEN_RDMA_CONTINUOUS_CNT(x) ABOX_SFR(AUDEN_RDMA, 0x2C, x)
|
|
#define ABOX_AUDEN_RDMA_STATUS(x) ABOX_SFR(AUDEN_RDMA, 0x30, x)
|
|
#define ABOX_AUDEN_RDMA_STATUS_ADD(x) ABOX_SFR(AUDEN_RDMA, 0x38, x)
|
|
|
|
/* AUDEN_ASRC */
|
|
#define ABOX_AUDEN_ASRC_BASE 0x9000
|
|
#define ABOX_AUDEN_ASRC_ITV 0x0100
|
|
#define ABOX_AUDEN_ASRC_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x00, x)
|
|
#define ABOX_AUDEN_ASRC_IS_DEFAULT(x) ABOX_SFR(AUDEN_ASRC, 0x10, x)
|
|
#define ABOX_AUDEN_ASRC_IS_TPLIMIT(x) ABOX_SFR(AUDEN_ASRC, 0x14, x)
|
|
#define ABOX_AUDEN_ASRC_OS_DEFAULT(x) ABOX_SFR(AUDEN_ASRC, 0x18, x)
|
|
#define ABOX_AUDEN_ASRC_OS_TPLIMIT(x) ABOX_SFR(AUDEN_ASRC, 0x1C, x)
|
|
#define ABOX_AUDEN_ASRC_DITHER_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x20, x)
|
|
#define ABOX_AUDEN_ASRC_SEED(x) ABOX_SFR(AUDEN_ASRC, 0x24, x)
|
|
#define ABOX_AUDEN_ASRC_SEED_IN(x) ABOX_SFR(AUDEN_ASRC, 0x24, x)
|
|
#define ABOX_AUDEN_ASRC_SEED_OUT(x) ABOX_SFR(AUDEN_ASRC, 0x28, x)
|
|
#define ABOX_AUDEN_ASRC_FILTER_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x2C, x)
|
|
|
|
/* AUDEN_WDMA */
|
|
#define ABOX_AUDEN_WDMA_BASE 0xA000
|
|
#define ABOX_AUDEN_WDMA_ITV 0x0100
|
|
#define ABOX_AUDEN_WDMA_CTRL(x) ABOX_SFR(AUDEN_WDMA, 0x00, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_RESTART(x) ABOX_SFR(AUDEN_WDMA, 0x04, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_STR(x) ABOX_SFR(AUDEN_WDMA, 0x08, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_END(x) ABOX_SFR(AUDEN_WDMA, 0x0C, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_OFFSET(x) ABOX_SFR(AUDEN_WDMA, 0x10, x)
|
|
#define ABOX_AUDEN_WDMA_STR_POINT(x) ABOX_SFR(AUDEN_WDMA, 0x14, x)
|
|
#define ABOX_AUDEN_WDMA_VOL_FACTOR(x) ABOX_SFR(AUDEN_WDMA, 0x18, x)
|
|
#define ABOX_AUDEN_WDMA_VOL_CHANGE(x) ABOX_SFR(AUDEN_WDMA, 0x1C, x)
|
|
#define ABOX_AUDEN_WDMA_SBANK_LIMIT(x) ABOX_SFR(AUDEN_WDMA, 0x20, x)
|
|
#define ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(x) ABOX_SFR(AUDEN_WDMA, 0x24, x)
|
|
#define ABOX_AUDEN_WDMA_STATUS(x) ABOX_SFR(AUDEN_WDMA, 0x30, x)
|
|
#define ABOX_AUDEN_WDMA_DONE_STATUS(x) ABOX_SFR(AUDEN_WDMA, 0x34, x)
|
|
#define ABOX_AUDEN_WDMA_STATUS_ADD(x) ABOX_SFR(AUDEN_WDMA, 0x38, x)
|
|
|
|
/* SIDETONE */
|
|
#define ABOX_SIDETONE_CTRL 0xB000
|
|
#define ABOX_SIDETONE_GAIN_CTRL 0xB004
|
|
#define ABOX_SIDETONE_FILTER_CTRL0 0xB008
|
|
#define ABOX_SIDETONE_FILTER_CTRL1 0xB00C
|
|
#define ABOX_SIDETONE_HPF_COEF0 0xB010
|
|
#define ABOX_SIDETONE_HPF_COEF1 0xB014
|
|
#define ABOX_SIDETONE_HPF_COEF2 0xB018
|
|
#define ABOX_SIDETONE_HPF_COEF3 0xB01C
|
|
#define ABOX_SIDETONE_HPF_COEF4 0xB020
|
|
#define ABOX_SIDETONE_PEAK0_COEF0 0xB024
|
|
#define ABOX_SIDETONE_PEAK0_COEF1 0xB028
|
|
#define ABOX_SIDETONE_PEAK0_COEF2 0xB02C
|
|
#define ABOX_SIDETONE_PEAK0_COEF3 0xB030
|
|
#define ABOX_SIDETONE_PEAK0_COEF4 0xB034
|
|
#define ABOX_SIDETONE_PEAK1_COEF0 0xB038
|
|
#define ABOX_SIDETONE_PEAK1_COEF1 0xB03C
|
|
#define ABOX_SIDETONE_PEAK1_COEF2 0xB040
|
|
#define ABOX_SIDETONE_PEAK1_COEF3 0xB044
|
|
#define ABOX_SIDETONE_PEAK1_COEF4 0xB048
|
|
#define ABOX_SIDETONE_PEAK2_COEF0 0xB04C
|
|
#define ABOX_SIDETONE_PEAK2_COEF1 0xB050
|
|
#define ABOX_SIDETONE_PEAK2_COEF2 0xB054
|
|
#define ABOX_SIDETONE_PEAK2_COEF3 0xB058
|
|
#define ABOX_SIDETONE_PEAK2_COEF4 0xB05C
|
|
#define ABOX_SIDETONE_LOWSH_COEF0 0xB060
|
|
#define ABOX_SIDETONE_LOWSH_COEF1 0xB064
|
|
#define ABOX_SIDETONE_LOWSH_COEF2 0xB068
|
|
#define ABOX_SIDETONE_LOWSH_COEF3 0xB06C
|
|
#define ABOX_SIDETONE_LOWSH_COEF4 0xB070
|
|
#define ABOX_SIDETONE_HIGHSH_COEF0 0xB074
|
|
#define ABOX_SIDETONE_HIGHSH_COEF1 0xB078
|
|
#define ABOX_SIDETONE_HIGHSH_COEF2 0xB07C
|
|
#define ABOX_SIDETONE_HIGHSH_COEF3 0xB080
|
|
#define ABOX_SIDETONE_HIGHSH_COEF4 0xB084
|
|
|
|
/* ABOX_SIDETONE_CTRL */
|
|
#define ABOX_SDTN_GAIN_OUT_ENABLE_H 31
|
|
#define ABOX_SDTN_GAIN_OUT_ENABLE_L 31
|
|
#define ABOX_SDTN_GAIN_OUT_ENABLE_MASK ABOX_FLD(SDTN_GAIN_OUT_ENABLE)
|
|
#define ABOX_SDTN_GAIN_IN_ENABLE_H 30
|
|
#define ABOX_SDTN_GAIN_IN_ENABLE_L 30
|
|
#define ABOX_SDTN_GAIN_IN_ENABLE_MASK ABOX_FLD(SDTN_GAIN_IN_ENABLE)
|
|
#define ABOX_SDTN_EQ_ENABLE_H 29
|
|
#define ABOX_SDTN_EQ_ENABLE_L 29
|
|
#define ABOX_SDTN_EQ_ENABLE_MASK ABOX_FLD(SDTN_EQ_ENABLE)
|
|
#define ABOX_SDTN_HPF_ENABLE_H 28
|
|
#define ABOX_SDTN_HPF_ENABLE_L 28
|
|
#define ABOX_SDTN_HPF_ENABLE_MASK ABOX_FLD(SDTN_HPF_ENABLE)
|
|
#define ABOX_SDTN_FLUSH_H 24
|
|
#define ABOX_SDTN_FLUSH_L 24
|
|
#define ABOX_SDTN_FLUSH_MASK ABOX_FLD(SDTN_FLUSH)
|
|
#define ABOX_SDTN_BYPASS_ENABLE_H 22
|
|
#define ABOX_SDTN_BYPASS_ENABLE_L 22
|
|
#define ABOX_SDTN_BYPASS_ENABLE_MASK ABOX_FLD(SDTN_BYPASS_ENABLE)
|
|
#define ABOX_SDTN_ZERO_OUTPUT_H 21
|
|
#define ABOX_SDTN_ZERO_OUTPUT_L 21
|
|
#define ABOX_SDTN_ZERO_OUTPUT_MASK ABOX_FLD(SDTN_ZERO_OUTPUT)
|
|
#define ABOX_SDTN_OUT2_ENABLE_H 20
|
|
#define ABOX_SDTN_OUT2_ENABLE_L 20
|
|
#define ABOX_SDTN_OUT2_ENABLE_MASK ABOX_FLD(SDTN_OUT2_ENABLE)
|
|
#define ABOX_SDTN_CH_SEL_OUT2_H 18
|
|
#define ABOX_SDTN_CH_SEL_OUT2_L 16
|
|
#define ABOX_SDTN_CH_SEL_OUT2_MASK ABOX_FLD(SDTN_CH_SEL_OUT2)
|
|
#define ABOX_SDTN_CH_SEL_OUT_H 14
|
|
#define ABOX_SDTN_CH_SEL_OUT_L 12
|
|
#define ABOX_SDTN_CH_SEL_OUT_MASK ABOX_FLD(SDTN_CH_SEL_OUT)
|
|
#define ABOX_SDTN_CH_SEL_IN_H 10
|
|
#define ABOX_SDTN_CH_SEL_IN_L 8
|
|
#define ABOX_SDTN_CH_SEL_IN_MASK ABOX_FLD(SDTN_CH_SEL_IN)
|
|
#define ABOX_SDTN_OUT_BITWIDTH_H 6
|
|
#define ABOX_SDTN_OUT_BITWIDTH_L 5
|
|
#define ABOX_SDTN_OUT_BITWIDTH_MASK ABOX_FLD(SDTN_OUT_BITWIDTH)
|
|
#define ABOX_SDTN_FORMAT_H 4
|
|
#define ABOX_SDTN_FORMAT_L 0
|
|
#define ABOX_SDTN_FORMAT_MASK ABOX_FLD(SDTN_FORMAT)
|
|
/* ABOX_SIDETONE_GAIN_CTRL */
|
|
#define ABOX_SDTN_GAIN_OUT_H 23
|
|
#define ABOX_SDTN_GAIN_OUT_L 16
|
|
#define ABOX_SDTN_GAIN_OUT_MASK ABOX_FLD(SDTN_GAIN_OUT)
|
|
#define ABOX_SDTN_GAIN_IN_H 7
|
|
#define ABOX_SDTN_GAIN_IN_L 0
|
|
#define ABOX_SDTN_GAIN_IN_MASK ABOX_FLD(SDTN_GAIN_IN)
|
|
/* ABOX_SIDETONE_FILTER_CTRL0 */
|
|
#define ABOX_SDTN_HEADROOM_HIGHSH_H 22
|
|
#define ABOX_SDTN_HEADROOM_HIGHSH_L 20
|
|
#define ABOX_SDTN_HEADROOM_HIGHSH_MASK ABOX_FLD(SDTN_HEADROOM_HIGHSH)
|
|
#define ABOX_SDTN_HEADROOM_LOWSH_H 18
|
|
#define ABOX_SDTN_HEADROOM_LOWSH_L 16
|
|
#define ABOX_SDTN_HEADROOM_LOWSH_MASK ABOX_FLD(SDTN_HEADROOM_LOWSH)
|
|
#define ABOX_SDTN_HEADROOM_PEAK2_H 14
|
|
#define ABOX_SDTN_HEADROOM_PEAK2_L 12
|
|
#define ABOX_SDTN_HEADROOM_PEAK2_MASK ABOX_FLD(SDTN_HEADROOM_PEAK2)
|
|
#define ABOX_SDTN_HEADROOM_PEAK1_H 10
|
|
#define ABOX_SDTN_HEADROOM_PEAK1_L 8
|
|
#define ABOX_SDTN_HEADROOM_PEAK1_MASK ABOX_FLD(SDTN_HEADROOM_PEAK1)
|
|
#define ABOX_SDTN_HEADROOM_PEAK0_H 6
|
|
#define ABOX_SDTN_HEADROOM_PEAK0_L 4
|
|
#define ABOX_SDTN_HEADROOM_PEAK0_MASK ABOX_FLD(SDTN_HEADROOM_PEAK0)
|
|
#define ABOX_SDTN_HEADROOM_HPF_H 2
|
|
#define ABOX_SDTN_HEADROOM_HPF_L 0
|
|
#define ABOX_SDTN_HEADROOM_HPF_MASK ABOX_FLD(SDTN_HEADROOM_HPF)
|
|
/* ABOX_SIDETONE_FILTER_CTRL1 */
|
|
#define ABOX_SDTN_POSTAMP_HIGHSH_H 21
|
|
#define ABOX_SDTN_POSTAMP_HIGHSH_L 20
|
|
#define ABOX_SDTN_POSTAMP_HIGHSH_MASK ABOX_FLD(SDTN_POSTAMP_HIGHSH)
|
|
#define ABOX_SDTN_POSTAMP_LOWSH_H 17
|
|
#define ABOX_SDTN_POSTAMP_LOWSH_L 16
|
|
#define ABOX_SDTN_POSTAMP_LOWSH_MASK ABOX_FLD(SDTN_POSTAMP_LOWSH)
|
|
#define ABOX_SDTN_POSTAMP_PEAK2_H 13
|
|
#define ABOX_SDTN_POSTAMP_PEAK2_L 12
|
|
#define ABOX_SDTN_POSTAMP_PEAK2_MASK ABOX_FLD(SDTN_POSTAMP_PEAK2)
|
|
#define ABOX_SDTN_POSTAMP_PEAK1_H 9
|
|
#define ABOX_SDTN_POSTAMP_PEAK1_L 8
|
|
#define ABOX_SDTN_POSTAMP_PEAK1_MASK ABOX_FLD(SDTN_POSTAMP_PEAK1)
|
|
#define ABOX_SDTN_POSTAMP_PEAK0_H 5
|
|
#define ABOX_SDTN_POSTAMP_PEAK0_L 4
|
|
#define ABOX_SDTN_POSTAMP_PEAK0_MASK ABOX_FLD(SDTN_POSTAMP_PEAK0)
|
|
#define ABOX_SDTN_POSTAMP_HPF_H 1
|
|
#define ABOX_SDTN_POSTAMP_HPF_L 0
|
|
#define ABOX_SDTN_POSTAMP_HPF_MASK ABOX_FLD(SDTN_POSTAMP_HPF)
|
|
/* ABOX_SIDETONE_*_COEF$ */
|
|
#define ABOX_SDTN_COEF_H 31
|
|
#define ABOX_SDTN_COEF_L 0
|
|
#define ABOX_SDTN_COEF_MASK ABOX_FLD(SDTN_COEF)
|
|
|
|
/* UDMA_CTRL */
|
|
#define ABOX_UDMA_CTRL 0xC000
|
|
#define ABOX_UDMA_SBANK_RDMA_BASE 0xC040
|
|
#define ABOX_UDMA_SBANK_RDMA_ITV 0x0004
|
|
#define ABOX_UDMA_SBANK_RDMA(x) ABOX_SFR(UDMA_SBANK_RDMA, 0x0, x)
|
|
#define ABOX_UDMA_SBANK_SIFM_BASE 0xC060
|
|
#define ABOX_UDMA_SBANK_SIFM_ITV 0x0004
|
|
#define ABOX_UDMA_SBANK_SIFM(x) ABOX_SFR(UDMA_SBANK_SIFM, 0x0, x)
|
|
#define ABOX_UDMA_TRIGGER_RD_BASE 0xC080
|
|
#define ABOX_UDMA_TRIGGER_RD_ITV 0x0010
|
|
#define ABOX_UDMA_TRIGGER_CTRL_RD(x) ABOX_SFR(UDMA_TRIGGER_RD, 0x0, x)
|
|
#define ABOX_UDMA_TRIGGER_CNT_RD(x) ABOX_SFR(UDMA_TRIGGER_RD, 0x4, x)
|
|
#define ABOX_UDMA_TRIGGER_OFFSET_RD(x) ABOX_SFR(UDMA_TRIGGER_RD, 0x8, x)
|
|
#define ABOX_UDMA_TRIGGER_WR_BASE 0xC0A0
|
|
#define ABOX_UDMA_TRIGGER_WR_ITV 0x0010
|
|
#define ABOX_UDMA_TRIGGER_CTRL_WR(x) ABOX_SFR(UDMA_TRIGGER_WR, 0x0, x)
|
|
#define ABOX_UDMA_TRIGGER_CNT_WR(x) ABOX_SFR(UDMA_TRIGGER_WR, 0x4, x)
|
|
#define ABOX_UDMA_TRIGGER_OFFSET_WR(x) ABOX_SFR(UDMA_TRIGGER_WR, 0x8, x)
|
|
/* UDMA_CTRL */
|
|
#define ABOX_UDMA_SIFS1_FLUSH_H 1
|
|
#define ABOX_UDMA_SIFS1_FLUSH_L 1
|
|
#define ABOX_UDMA_SIFS1_FLUSH_MASK ABOX_FLD(UDMA_SIFS1_FLUSH)
|
|
#define ABOX_UDMA_SIFS0_FLUSH_H 0
|
|
#define ABOX_UDMA_SIFS0_FLUSH_L 0
|
|
#define ABOX_UDMA_SIFS0_FLUSH_MASK ABOX_FLD(UDMA_SIFS0_FLUSH)
|
|
/* UDMA_SBANK_SIFM$ */
|
|
/* UDMA_TRIGGER_CTRL_RD$ */
|
|
/* UDMA_TRIGGER_CTRL_WR$ */
|
|
#define ABOX_UDMA_TRIGGER_METHOD_H 0
|
|
#define ABOX_UDMA_TRIGGER_METHOD_L 0
|
|
#define ABOX_UDMA_TRIGGER_METHOD_MASK ABOX_FLD(UDMA_TRIGGER_METHOD)
|
|
/* UDMA_TRIGGER_CNT_RD$ */
|
|
/* UDMA_TRIGGER_CNT_WR$ */
|
|
#define ABOX_UDMA_TRIGGER_CNT_VAL_H 0
|
|
#define ABOX_UDMA_TRIGGER_CNT_VAL_L 0
|
|
#define ABOX_UDMA_TRIGGER_CNT_VAL_MASK ABOX_FLD(UDMA_TRIGGER_CNT_VAL)
|
|
/* UDMA_TRIGGER_OFFSET_RD$ */
|
|
/* UDMA_TRIGGER_OFFSET_WR$ */
|
|
#define ABOX_UDMA_TRIGGER_OFFSET_H 0
|
|
#define ABOX_UDMA_TRIGGER_OFFSET_L 0
|
|
#define ABOX_UDMA_TRIGGER_OFFSET_MASK ABOX_FLD(UDMA_TRIGGER_OFFSET)
|
|
|
|
/* UDMA_RD */
|
|
#define ABOX_UDMA_RD_BASE 0xC100
|
|
#define ABOX_UDMA_RD_ITV 0x0100
|
|
#define ABOX_UDMA_RD_CTRL(x) ABOX_SFR(UDMA_RD, 0x00, x)
|
|
#define ABOX_UDMA_RD_BUF_RESTART(x) ABOX_SFR(UDMA_RD, 0x04, x)
|
|
#define ABOX_UDMA_RD_BUF_STR(x) ABOX_SFR(UDMA_RD, 0x08, x)
|
|
#define ABOX_UDMA_RD_BUF_END(x) ABOX_SFR(UDMA_RD, 0x0C, x)
|
|
#define ABOX_UDMA_RD_BUF_OFFSET(x) ABOX_SFR(UDMA_RD, 0x10, x)
|
|
#define ABOX_UDMA_RD_STR_POINT(x) ABOX_SFR(UDMA_RD, 0x14, x)
|
|
#define ABOX_UDMA_RD_VOL_FACTOR(x) ABOX_SFR(UDMA_RD, 0x18, x)
|
|
#define ABOX_UDMA_RD_VOL_CHANGE(x) ABOX_SFR(UDMA_RD, 0x1C, x)
|
|
#define ABOX_UDMA_RD_SBANK_LIMIT(x) ABOX_SFR(UDMA_RD, 0x20, x)
|
|
#define ABOX_UDMA_RD_STATUS(x) ABOX_SFR(UDMA_RD, 0x30, x)
|
|
#define ABOX_UDMA_RD_STATUS_ADD(x) ABOX_SFR(UDMA_RD, 0x38, x)
|
|
|
|
/* UDMA_WR */
|
|
#define ABOX_UDMA_WR_BASE 0xC700
|
|
#define ABOX_UDMA_WR_ITV 0x0100
|
|
#define ABOX_UDMA_WR_CTRL(x) ABOX_SFR(UDMA_WR, 0x00, x)
|
|
#define ABOX_UDMA_WR_BUF_RESTART(x) ABOX_SFR(UDMA_WR, 0x04, x)
|
|
#define ABOX_UDMA_WR_BUF_STR(x) ABOX_SFR(UDMA_WR, 0x08, x)
|
|
#define ABOX_UDMA_WR_BUF_END(x) ABOX_SFR(UDMA_WR, 0x0C, x)
|
|
#define ABOX_UDMA_WR_BUF_OFFSET(x) ABOX_SFR(UDMA_WR, 0x10, x)
|
|
#define ABOX_UDMA_WR_STR_POINT(x) ABOX_SFR(UDMA_WR, 0x14, x)
|
|
#define ABOX_UDMA_WR_VOL_FACTOR(x) ABOX_SFR(UDMA_WR, 0x18, x)
|
|
#define ABOX_UDMA_WR_VOL_CHANGE(x) ABOX_SFR(UDMA_WR, 0x1C, x)
|
|
#define ABOX_UDMA_WR_SBANK_LIMIT(x) ABOX_SFR(UDMA_WR, 0x20, x)
|
|
#define ABOX_UDMA_WR_STATUS(x) ABOX_SFR(UDMA_WR, 0x30, x)
|
|
#define ABOX_UDMA_WR_STATUS_ADD(x) ABOX_SFR(UDMA_WR, 0x38, x)
|
|
#define ABOX_UDMA_WR_DUAL_CTRL(x) ABOX_SFR(UDMA_WR, 0x80, x)
|
|
#define ABOX_UDMA_WR_DUAL_BUF_STR(x) ABOX_SFR(UDMA_WR, 0x88, x)
|
|
#define ABOX_UDMA_WR_DUAL_BUF_END(x) ABOX_SFR(UDMA_WR, 0x8C, x)
|
|
#define ABOX_UDMA_WR_DUAL_BUF_OFFSET(x) ABOX_SFR(UDMA_WR, 0x90, x)
|
|
#define ABOX_UDMA_WR_DUAL_STR_POINT(x) ABOX_SFR(UDMA_WR, 0x94, x)
|
|
#define ABOX_UDMA_WR_DUAL_STATUS(x) ABOX_SFR(UDMA_WR, 0xB0, x)
|
|
#define ABOX_UDMA_WR_DUAL_STATUS_ADD(x) ABOX_SFR(UDMA_WR, 0xB8, x)
|
|
|
|
/* UDMA_WR_DEBUG */
|
|
#define ABOX_UDMA_WR_DEBUG_BASE 0xCD00
|
|
#define ABOX_UDMA_WR_DEBUG_ITV 0x0100
|
|
#define ABOX_UDMA_WR_DEBUG_CTRL(x) ABOX_SFR(UDMA_WR_DEBUG, 0x00, x)
|
|
#define ABOX_UDMA_WR_DEBUG_BUF_RESTART(x) ABOX_SFR(UDMA_WR_DEBUG, 0x04, x)
|
|
#define ABOX_UDMA_WR_DEBUG_BUF_STR(x) ABOX_SFR(UDMA_WR_DEBUG, 0x08, x)
|
|
#define ABOX_UDMA_WR_DEBUG_BUF_END(x) ABOX_SFR(UDMA_WR_DEBUG, 0x0C, x)
|
|
#define ABOX_UDMA_WR_DEBUG_BUF_OFFSET(x) ABOX_SFR(UDMA_WR_DEBUG, 0x10, x)
|
|
#define ABOX_UDMA_WR_DEBUG_STR_POINT(x) ABOX_SFR(UDMA_WR_DEBUG, 0x14, x)
|
|
#define ABOX_UDMA_WR_DEBUG_VOL_FACTOR(x) ABOX_SFR(UDMA_WR_DEBUG, 0x18, x)
|
|
#define ABOX_UDMA_WR_DEBUG_VOL_CHANGE(x) ABOX_SFR(UDMA_WR_DEBUG, 0x1C, x)
|
|
#define ABOX_UDMA_WR_DEBUG_SBANK_LIMIT(x) ABOX_SFR(UDMA_WR_DEBUG, 0x20, x)
|
|
#define ABOX_UDMA_WR_DEBUG_STATUS(x) ABOX_SFR(UDMA_WR_DEBUG, 0x30, x)
|
|
#define ABOX_UDMA_WR_DEBUG_STATUS_ADD(x) ABOX_SFR(UDMA_WR_DEBUG, 0x38, x)
|
|
|
|
/* ATUNE */
|
|
#define ATUNE_OFFSET 0x30000
|
|
#define ATUNE_BASE(x) ((x) + ATUNE_OFFSET)
|
|
|
|
#define ATUNE_SPUS_DSGAIN_BASE ATUNE_BASE(0x0000)
|
|
#define ATUNE_SPUS_DSGAIN_ITV 0x0040
|
|
#define ATUNE_SPUS_DSGAIN_CTRL(x) ATUNE_SFR(SPUS_DSGAIN, 0x00, x)
|
|
#define ATUNE_SPUS_DSGAIN_VOL_CHANGE_FIN(x) ATUNE_SFR(SPUS_DSGAIN, 0x08, x)
|
|
#define ATUNE_SPUS_DSGAIN_VOL_CHANGE_FOUT(x) ATUNE_SFR(SPUS_DSGAIN, 0x0C, x)
|
|
#define ATUNE_SPUS_DSGAIN_GAIN0(x) ATUNE_SFR(SPUS_DSGAIN, 0x10, x)
|
|
#define ATUNE_SPUS_DSGAIN_GAIN1(x) ATUNE_SFR(SPUS_DSGAIN, 0x14, x)
|
|
#define ATUNE_SPUS_DSGAIN_GAIN2(x) ATUNE_SFR(SPUS_DSGAIN, 0x18, x)
|
|
#define ATUNE_SPUS_DSGAIN_GAIN3(x) ATUNE_SFR(SPUS_DSGAIN, 0x1C, x)
|
|
#define ATUNE_SPUS_DSGAIN_BIT_CTRL(x) ATUNE_SFR(SPUS_DSGAIN, 0x20, x)
|
|
#define ATUNE_SPUS_USGAIN_BASE ATUNE_BASE(0x0080)
|
|
#define ATUNE_SPUS_USGAIN_ITV 0x0040
|
|
#define ATUNE_SPUS_USGAIN_CTRL(x) ATUNE_SFR(SPUS_USGAIN, 0x00, x)
|
|
#define ATUNE_SPUS_USGAIN_VOL_CHANGE_FIN(x) ATUNE_SFR(SPUS_USGAIN, 0x08, x)
|
|
#define ATUNE_SPUS_USGAIN_VOL_CHANGE_FOUT(x) ATUNE_SFR(SPUS_USGAIN, 0x0C, x)
|
|
#define ATUNE_SPUS_USGAIN_GAIN0(x) ATUNE_SFR(SPUS_USGAIN, 0x10, x)
|
|
#define ATUNE_SPUS_USGAIN_GAIN1(x) ATUNE_SFR(SPUS_USGAIN, 0x14, x)
|
|
#define ATUNE_SPUS_USGAIN_GAIN2(x) ATUNE_SFR(SPUS_USGAIN, 0x18, x)
|
|
#define ATUNE_SPUS_USGAIN_GAIN3(x) ATUNE_SFR(SPUS_USGAIN, 0x1C, x)
|
|
#define ATUNE_SPUS_BQF_CTRL_BASE ATUNE_BASE(0x0100)
|
|
#define ATUNE_SPUS_BQF_CTRL_ITV 0x0004
|
|
#define ATUNE_SPUS_BQF_CTRL(x) ATUNE_SFR(SPUS_BQF_CTRL, 0x00, x)
|
|
#define ATUNE_SPUS_BQF_CH_BASE ATUNE_BASE(0x0110)
|
|
#define ATUNE_SPUS_BQF_CH_ITV 0x0400
|
|
#define ATUNE_SPUS_BQF_CH0_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x000, x)
|
|
#define ATUNE_SPUS_BQF_CH0_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x004, x)
|
|
#define ATUNE_SPUS_BQF_CH0_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x008, x)
|
|
#define ATUNE_SPUS_BQF_CH0_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x00C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x010, x)
|
|
#define ATUNE_SPUS_BQF_CH0_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x014, x)
|
|
#define ATUNE_SPUS_BQF_CH0_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x018, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x01C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x020, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x024, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x028, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x02C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x030, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x034, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x038, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x03C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x040, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x044, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x048, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x04C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x050, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x054, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x058, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x05C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x060, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x064, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x068, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x06C, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x070, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x074, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x078, x)
|
|
#define ATUNE_SPUS_BQF_CH0_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x07C, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x080, x)
|
|
#define ATUNE_SPUS_BQF_CH1_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x084, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x088, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x08C, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x090, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x094, x)
|
|
#define ATUNE_SPUS_BQF_CH1_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x098, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x09C, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x0A0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x0A4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x0A8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x0AC, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x0B0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x0B4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x0B8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x0BC, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x0C0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x0C4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x0C8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x0CC, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x0D0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x0D4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x0D8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x0DC, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x0E0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x0E4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x0E8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x0EC, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x0F0, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x0F4, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x0F8, x)
|
|
#define ATUNE_SPUS_BQF_CH1_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x0FC, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x100, x)
|
|
#define ATUNE_SPUS_BQF_CH2_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x104, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x108, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x10C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x110, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x114, x)
|
|
#define ATUNE_SPUS_BQF_CH2_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x118, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x11C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x120, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x124, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x128, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x12C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x130, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x134, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x138, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x13C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x140, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x144, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x148, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x14C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x150, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x154, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x158, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x15C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x160, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x164, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x168, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x16C, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x170, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x174, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x178, x)
|
|
#define ATUNE_SPUS_BQF_CH2_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x17C, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x180, x)
|
|
#define ATUNE_SPUS_BQF_CH3_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x184, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x188, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x18C, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x190, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x194, x)
|
|
#define ATUNE_SPUS_BQF_CH3_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x198, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x19C, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x1A0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x1A4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x1A8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x1AC, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x1B0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x1B4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x1B8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x1BC, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x1C0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x1C4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x1C8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x1CC, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x1D0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x1D4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x1D8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x1DC, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x1E0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x1E4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x1E8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x1EC, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x1F0, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x1F4, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x1F8, x)
|
|
#define ATUNE_SPUS_BQF_CH3_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x1FC, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x200, x)
|
|
#define ATUNE_SPUS_BQF_CH4_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x204, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x208, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x20C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x210, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x214, x)
|
|
#define ATUNE_SPUS_BQF_CH4_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x218, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x21C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x220, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x224, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x228, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x22C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x230, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x234, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x238, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x23C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x240, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x244, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x248, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x24C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x250, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x254, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x258, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x25C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x260, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x264, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x268, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x26C, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x270, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x274, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x278, x)
|
|
#define ATUNE_SPUS_BQF_CH4_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x27C, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x280, x)
|
|
#define ATUNE_SPUS_BQF_CH5_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x284, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x288, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x28C, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x290, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x294, x)
|
|
#define ATUNE_SPUS_BQF_CH5_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x298, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x29C, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x2A0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x2A4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x2A8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x2AC, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x2B0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x2B4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x2B8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x2BC, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x2C0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x2C4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x2C8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x2CC, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x2D0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x2D4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x2D8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x2DC, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x2E0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x2E4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x2E8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x2EC, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x2F0, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x2F4, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x2F8, x)
|
|
#define ATUNE_SPUS_BQF_CH5_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x2FC, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x300, x)
|
|
#define ATUNE_SPUS_BQF_CH6_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x304, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x308, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x30C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x310, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x314, x)
|
|
#define ATUNE_SPUS_BQF_CH6_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x318, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x31C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x320, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x324, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x328, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x32C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x330, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x334, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x338, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x33C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x340, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x344, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x348, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x34C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x350, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x354, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x358, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x35C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x360, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x364, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x368, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x36C, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x370, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x374, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x378, x)
|
|
#define ATUNE_SPUS_BQF_CH6_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x37C, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HEADROOM(x) ATUNE_SFR(SPUS_BQF_CH, 0x380, x)
|
|
#define ATUNE_SPUS_BQF_CH7_POSTAMP(x) ATUNE_SFR(SPUS_BQF_CH, 0x384, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HPF_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x388, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HPF_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x38C, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HPF_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x390, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HPF_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x394, x)
|
|
#define ATUNE_SPUS_BQF_CH7_HPF_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x398, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ0_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x39C, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ0_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x3A0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ0_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x3A4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ0_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x3A8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ0_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x3AC, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ1_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x3B0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ1_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x3B4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ1_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x3B8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ1_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x3BC, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ1_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x3C0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ2_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x3C4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ2_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x3C8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ2_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x3CC, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ2_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x3D0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ2_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x3D4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ3_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x3D8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ3_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x3DC, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ3_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x3E0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ3_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x3E4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ3_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x3E8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ4_COEF0(x) ATUNE_SFR(SPUS_BQF_CH, 0x3EC, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ4_COEF1(x) ATUNE_SFR(SPUS_BQF_CH, 0x3F0, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ4_COEF2(x) ATUNE_SFR(SPUS_BQF_CH, 0x3F4, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ4_COEF3(x) ATUNE_SFR(SPUS_BQF_CH, 0x3F8, x)
|
|
#define ATUNE_SPUS_BQF_CH7_EQ4_COEF4(x) ATUNE_SFR(SPUS_BQF_CH, 0x3FC, x)
|
|
#define ATUNE_SPUS_DRC_BASE ATUNE_BASE(0x0A00)
|
|
#define ATUNE_SPUS_DRC_ITV 0x0080
|
|
#define ATUNE_SPUS_DRC_CTRL(x) ATUNE_SFR(SPUS_DRC, 0x00, x)
|
|
#define ATUNE_SPUS_DRC_COMP_LB0(x) ATUNE_SFR(SPUS_DRC, 0x04, x)
|
|
#define ATUNE_SPUS_DRC_COMP_LB1(x) ATUNE_SFR(SPUS_DRC, 0x08, x)
|
|
#define ATUNE_SPUS_DRC_COMP_LB2(x) ATUNE_SFR(SPUS_DRC, 0x0C, x)
|
|
#define ATUNE_SPUS_DRC_COMP_MB0(x) ATUNE_SFR(SPUS_DRC, 0x14, x)
|
|
#define ATUNE_SPUS_DRC_COMP_MB1(x) ATUNE_SFR(SPUS_DRC, 0x18, x)
|
|
#define ATUNE_SPUS_DRC_COMP_MB2(x) ATUNE_SFR(SPUS_DRC, 0x1C, x)
|
|
#define ATUNE_SPUS_DRC_COMP_HB0(x) ATUNE_SFR(SPUS_DRC, 0x24, x)
|
|
#define ATUNE_SPUS_DRC_COMP_HB1(x) ATUNE_SFR(SPUS_DRC, 0x28, x)
|
|
#define ATUNE_SPUS_DRC_COMP_HB2(x) ATUNE_SFR(SPUS_DRC, 0x2C, x)
|
|
#define ATUNE_SPUS_DRC_LMT_CTRL0(x) ATUNE_SFR(SPUS_DRC, 0x30, x)
|
|
#define ATUNE_SPUS_DRC_LMT_CTRL1(x) ATUNE_SFR(SPUS_DRC, 0x34, x)
|
|
#define ATUNE_SPUS_DRC_xPF0_COEF0(x) ATUNE_SFR(SPUS_DRC, 0x40, x)
|
|
#define ATUNE_SPUS_DRC_xPF0_COEF1(x) ATUNE_SFR(SPUS_DRC, 0x44, x)
|
|
#define ATUNE_SPUS_DRC_xPF0_COEF2(x) ATUNE_SFR(SPUS_DRC, 0x48, x)
|
|
#define ATUNE_SPUS_DRC_xPF0_COEF3(x) ATUNE_SFR(SPUS_DRC, 0x4C, x)
|
|
#define ATUNE_SPUS_DRC_xPF1_COEF0(x) ATUNE_SFR(SPUS_DRC, 0x50, x)
|
|
#define ATUNE_SPUS_DRC_xPF1_COEF1(x) ATUNE_SFR(SPUS_DRC, 0x54, x)
|
|
#define ATUNE_SPUS_DRC_xPF1_COEF2(x) ATUNE_SFR(SPUS_DRC, 0x58, x)
|
|
#define ATUNE_SPUS_DRC_xPF1_COEF3(x) ATUNE_SFR(SPUS_DRC, 0x5C, x)
|
|
#define ATUNE_SPUM_DSGAIN_BASE ATUNE_BASE(0x1000)
|
|
#define ATUNE_SPUM_DSGAIN_ITV 0x0040
|
|
#define ATUNE_SPUM_DSGAIN_CTRL(x) ATUNE_SFR(SPUM_DSGAIN, 0x00, x)
|
|
#define ATUNE_SPUM_DSGAIN_VOL_CHANGE_FIN(x) ATUNE_SFR(SPUM_DSGAIN, 0x08, x)
|
|
#define ATUNE_SPUM_DSGAIN_VOL_CHANGE_FOUT(x) ATUNE_SFR(SPUM_DSGAIN, 0x0C, x)
|
|
#define ATUNE_SPUM_DSGAIN_GAIN0(x) ATUNE_SFR(SPUM_DSGAIN, 0x10, x)
|
|
#define ATUNE_SPUM_DSGAIN_GAIN1(x) ATUNE_SFR(SPUM_DSGAIN, 0x14, x)
|
|
#define ATUNE_SPUM_DSGAIN_GAIN2(x) ATUNE_SFR(SPUM_DSGAIN, 0x18, x)
|
|
#define ATUNE_SPUM_DSGAIN_GAIN3(x) ATUNE_SFR(SPUM_DSGAIN, 0x1C, x)
|
|
#define ATUNE_SPUM_DSGAIN_BIT_CTRL(x) ATUNE_SFR(SPUM_DSGAIN, 0x20, x)
|
|
#define ATUNE_SPUM_USGAIN_BASE ATUNE_BASE(0x1080)
|
|
#define ATUNE_SPUM_USGAIN_ITV 0x0040
|
|
#define ATUNE_SPUM_USGAIN_CTRL(x) ATUNE_SFR(SPUM_USGAIN, 0x00, x)
|
|
#define ATUNE_SPUM_USGAIN_VOL_CHANGE_FIN(x) ATUNE_SFR(SPUM_USGAIN, 0x08, x)
|
|
#define ATUNE_SPUM_USGAIN_VOL_CHANGE_FOUT(x) ATUNE_SFR(SPUM_USGAIN, 0x0C, x)
|
|
#define ATUNE_SPUM_USGAIN_GAIN0(x) ATUNE_SFR(SPUM_USGAIN, 0x10, x)
|
|
#define ATUNE_SPUM_USGAIN_GAIN1(x) ATUNE_SFR(SPUM_USGAIN, 0x14, x)
|
|
#define ATUNE_SPUM_USGAIN_GAIN2(x) ATUNE_SFR(SPUM_USGAIN, 0x18, x)
|
|
#define ATUNE_SPUM_USGAIN_GAIN3(x) ATUNE_SFR(SPUM_USGAIN, 0x1C, x)
|
|
#define ATUNE_SPUM_BQF_CTRL_BASE ATUNE_BASE(0x1100)
|
|
#define ATUNE_SPUM_BQF_CTRL_ITV 0x0004
|
|
#define ATUNE_SPUM_BQF_CTRL(x) ATUNE_SFR(SPUM_BQF_CTRL, 0x00, x)
|
|
#define ATUNE_SPUM_BQF_CH_BASE ATUNE_BASE(0x1110)
|
|
#define ATUNE_SPUM_BQF_CH_ITV 0x0400
|
|
#define ATUNE_SPUM_BQF_CH0_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x000, x)
|
|
#define ATUNE_SPUM_BQF_CH0_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x004, x)
|
|
#define ATUNE_SPUM_BQF_CH0_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x008, x)
|
|
#define ATUNE_SPUM_BQF_CH0_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x00C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x010, x)
|
|
#define ATUNE_SPUM_BQF_CH0_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x014, x)
|
|
#define ATUNE_SPUM_BQF_CH0_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x018, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x01C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x020, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x024, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x028, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x02C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x030, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x034, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x038, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x03C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x040, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x044, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x048, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x04C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x050, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x054, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x058, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x05C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x060, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x064, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x068, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x06C, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x070, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x074, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x078, x)
|
|
#define ATUNE_SPUM_BQF_CH0_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x07C, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x080, x)
|
|
#define ATUNE_SPUM_BQF_CH1_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x084, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x088, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x08C, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x090, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x094, x)
|
|
#define ATUNE_SPUM_BQF_CH1_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x098, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x09C, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x0A0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x0A4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x0A8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x0AC, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x0B0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x0B4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x0B8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x0BC, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x0C0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x0C4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x0C8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x0CC, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x0D0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x0D4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x0D8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x0DC, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x0E0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x0E4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x0E8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x0EC, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x0F0, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x0F4, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x0F8, x)
|
|
#define ATUNE_SPUM_BQF_CH1_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x0FC, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x100, x)
|
|
#define ATUNE_SPUM_BQF_CH2_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x104, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x108, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x10C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x110, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x114, x)
|
|
#define ATUNE_SPUM_BQF_CH2_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x118, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x11C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x120, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x124, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x128, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x12C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x130, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x134, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x138, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x13C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x140, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x144, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x148, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x14C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x150, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x154, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x158, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x15C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x160, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x164, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x168, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x16C, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x170, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x174, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x178, x)
|
|
#define ATUNE_SPUM_BQF_CH2_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x17C, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x180, x)
|
|
#define ATUNE_SPUM_BQF_CH3_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x184, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x188, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x18C, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x190, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x194, x)
|
|
#define ATUNE_SPUM_BQF_CH3_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x198, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x19C, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x1A0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x1A4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x1A8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x1AC, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x1B0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x1B4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x1B8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x1BC, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x1C0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x1C4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x1C8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x1CC, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x1D0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x1D4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x1D8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x1DC, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x1E0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x1E4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x1E8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x1EC, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x1F0, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x1F4, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x1F8, x)
|
|
#define ATUNE_SPUM_BQF_CH3_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x1FC, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x200, x)
|
|
#define ATUNE_SPUM_BQF_CH4_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x204, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x208, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x20C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x210, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x214, x)
|
|
#define ATUNE_SPUM_BQF_CH4_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x218, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x21C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x220, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x224, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x228, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x22C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x230, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x234, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x238, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x23C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x240, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x244, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x248, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x24C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x250, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x254, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x258, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x25C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x260, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x264, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x268, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x26C, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x270, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x274, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x278, x)
|
|
#define ATUNE_SPUM_BQF_CH4_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x27C, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x280, x)
|
|
#define ATUNE_SPUM_BQF_CH5_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x284, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x288, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x28C, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x290, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x294, x)
|
|
#define ATUNE_SPUM_BQF_CH5_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x298, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x29C, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x2A0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x2A4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x2A8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x2AC, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x2B0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x2B4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x2B8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x2BC, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x2C0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x2C4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x2C8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x2CC, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x2D0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x2D4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x2D8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x2DC, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x2E0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x2E4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x2E8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x2EC, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x2F0, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x2F4, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x2F8, x)
|
|
#define ATUNE_SPUM_BQF_CH5_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x2FC, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x300, x)
|
|
#define ATUNE_SPUM_BQF_CH6_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x304, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x308, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x30C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x310, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x314, x)
|
|
#define ATUNE_SPUM_BQF_CH6_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x318, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x31C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x320, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x324, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x328, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x32C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x330, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x334, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x338, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x33C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x340, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x344, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x348, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x34C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x350, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x354, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x358, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x35C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x360, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x364, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x368, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x36C, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x370, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x374, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x378, x)
|
|
#define ATUNE_SPUM_BQF_CH6_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x37C, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HEADROOM(x) ATUNE_SFR(SPUM_BQF_CH, 0x380, x)
|
|
#define ATUNE_SPUM_BQF_CH7_POSTAMP(x) ATUNE_SFR(SPUM_BQF_CH, 0x384, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HPF_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x388, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HPF_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x38C, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HPF_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x390, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HPF_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x394, x)
|
|
#define ATUNE_SPUM_BQF_CH7_HPF_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x398, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ0_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x39C, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ0_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x3A0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ0_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x3A4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ0_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x3A8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ0_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x3AC, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ1_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x3B0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ1_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x3B4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ1_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x3B8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ1_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x3BC, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ1_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x3C0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ2_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x3C4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ2_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x3C8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ2_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x3CC, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ2_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x3D0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ2_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x3D4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ3_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x3D8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ3_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x3DC, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ3_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x3E0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ3_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x3E4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ3_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x3E8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ4_COEF0(x) ATUNE_SFR(SPUM_BQF_CH, 0x3EC, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ4_COEF1(x) ATUNE_SFR(SPUM_BQF_CH, 0x3F0, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ4_COEF2(x) ATUNE_SFR(SPUM_BQF_CH, 0x3F4, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ4_COEF3(x) ATUNE_SFR(SPUM_BQF_CH, 0x3F8, x)
|
|
#define ATUNE_SPUM_BQF_CH7_EQ4_COEF4(x) ATUNE_SFR(SPUM_BQF_CH, 0x3FC, x)
|
|
#define ATUNE_SPUM_DRC_BASE ATUNE_BASE(0x1A00)
|
|
#define ATUNE_SPUM_DRC_ITV 0x0080
|
|
#define ATUNE_SPUM_DRC_CTRL(x) ATUNE_SFR(SPUM_DRC, 0x00, x)
|
|
#define ATUNE_SPUM_DRC_COMP_LB0(x) ATUNE_SFR(SPUM_DRC, 0x04, x)
|
|
#define ATUNE_SPUM_DRC_COMP_LB1(x) ATUNE_SFR(SPUM_DRC, 0x08, x)
|
|
#define ATUNE_SPUM_DRC_COMP_LB2(x) ATUNE_SFR(SPUM_DRC, 0x0C, x)
|
|
#define ATUNE_SPUM_DRC_COMP_MB0(x) ATUNE_SFR(SPUM_DRC, 0x14, x)
|
|
#define ATUNE_SPUM_DRC_COMP_MB1(x) ATUNE_SFR(SPUM_DRC, 0x18, x)
|
|
#define ATUNE_SPUM_DRC_COMP_MB2(x) ATUNE_SFR(SPUM_DRC, 0x1C, x)
|
|
#define ATUNE_SPUM_DRC_COMP_HB0(x) ATUNE_SFR(SPUM_DRC, 0x24, x)
|
|
#define ATUNE_SPUM_DRC_COMP_HB1(x) ATUNE_SFR(SPUM_DRC, 0x28, x)
|
|
#define ATUNE_SPUM_DRC_COMP_HB2(x) ATUNE_SFR(SPUM_DRC, 0x2C, x)
|
|
#define ATUNE_SPUM_DRC_LMT_CTRL0(x) ATUNE_SFR(SPUM_DRC, 0x30, x)
|
|
#define ATUNE_SPUM_DRC_LMT_CTRL1(x) ATUNE_SFR(SPUM_DRC, 0x34, x)
|
|
#define ATUNE_SPUM_DRC_xPF0_COEF0(x) ATUNE_SFR(SPUM_DRC, 0x40, x)
|
|
#define ATUNE_SPUM_DRC_xPF0_COEF1(x) ATUNE_SFR(SPUM_DRC, 0x44, x)
|
|
#define ATUNE_SPUM_DRC_xPF0_COEF2(x) ATUNE_SFR(SPUM_DRC, 0x48, x)
|
|
#define ATUNE_SPUM_DRC_xPF0_COEF3(x) ATUNE_SFR(SPUM_DRC, 0x4C, x)
|
|
#define ATUNE_SPUM_DRC_xPF1_COEF0(x) ATUNE_SFR(SPUM_DRC, 0x50, x)
|
|
#define ATUNE_SPUM_DRC_xPF1_COEF1(x) ATUNE_SFR(SPUM_DRC, 0x54, x)
|
|
#define ATUNE_SPUM_DRC_xPF1_COEF2(x) ATUNE_SFR(SPUM_DRC, 0x58, x)
|
|
#define ATUNE_SPUM_DRC_xPF1_COEF3(x) ATUNE_SFR(SPUM_DRC, 0x5C, x)
|
|
#define ATUNE_MAX_REGISTERS ATUNE_SPUM_DRC_xPF1_COEF3(1)
|
|
/* ATUNE_SPUS_DSGAIN_CTRL_$ */
|
|
/* ATUNE_SPUM_DSGAIN_CTRL_$ */
|
|
/* ATUNE_SPUS_USGAIN_CTRL_$ */
|
|
/* ATUNE_SPUM_USGAIN_CTRL_$ */
|
|
#define ATUNE_SAMPLE_RATE_H 25
|
|
#define ATUNE_SAMPLE_RATE_L 24
|
|
#define ATUNE_SAMPLE_RATE_MASK ATUNE_FLD(SAMPLE_RATE)
|
|
#define ATUNE_FUNC_H 17
|
|
#define ATUNE_FUNC_L 16
|
|
#define ATUNE_FUNC_MASK ATUNE_FLD(FUNC)
|
|
#define ATUNE_FORMAT_H 8
|
|
#define ATUNE_FORMAT_L 4
|
|
#define ATUNE_FORMAT_MASK ATUNE_FLD(FORMAT)
|
|
#define ATUNE_ENABLE_H 0
|
|
#define ATUNE_ENABLE_L 0
|
|
#define ATUNE_ENABLE_MASK ATUNE_FLD(ENABLE)
|
|
/* ATUNE_SPUS_DSGAIN_VOL_CHANGE_FIN_$ */
|
|
/* ATUNE_SPUS_DSGAIN_VOL_CHANGE_FOUT_$ */
|
|
/* ATUNE_SPUM_DSGAIN_VOL_CHANGE_FIN_$ */
|
|
/* ATUNE_SPUM_DSGAIN_VOL_CHANGE_FOUT_$ */
|
|
/* ATUNE_SPUS_USGAIN_VOL_CHANGE_FIN_$ */
|
|
/* ATUNE_SPUS_USGAIN_VOL_CHANGE_FOUT_$ */
|
|
/* ATUNE_SPUM_USGAIN_VOL_CHANGE_FIN_$ */
|
|
/* ATUNE_SPUM_USGAIN_VOL_CHANGE_FOUT_$ */
|
|
#define ATUNE_VOL_CHANGE_H 31
|
|
#define ATUNE_VOL_CHANGE_L 0
|
|
#define ATUNE_VOL_CHANGE_MASK ATUNE_FLD(VOL_CHANGE)
|
|
/* ATUNE_SPUS_DSGAIN_GAINx_$ */
|
|
/* ATUNE_SPUM_DSGAIN_GAINx_$ */
|
|
/* ATUNE_SPUS_USGAIN_GAINx_$ */
|
|
/* ATUNE_SPUM_USGAIN_GAINx_$ */
|
|
#define ATUNE_CH_GAIN_BASE 0
|
|
#define ATUNE_CH_GAIN_ITV 16
|
|
#define ATUNE_CH_GAIN_INDEX_H(x) ATUNE_H(CH_GAIN, 8, x)
|
|
#define ATUNE_CH_GAIN_INDEX_L(x) ATUNE_L(CH_GAIN, 6, x)
|
|
#define ATUNE_CH_GAIN_INDEX_MASK(x) ATUNE_FLD_X(CH_GAIN_INDEX, x)
|
|
#define ATUNE_CH_GAIN_SHIFT_H(x) ATUNE_H(CH_GAIN, 5, x)
|
|
#define ATUNE_CH_GAIN_SHIFT_L(x) ATUNE_L(CH_GAIN, 0, x)
|
|
#define ATUNE_CH_GAIN_SHIFT_MASK(x) ATUNE_FLD_X(CH_GAIN_SHIFT, x)
|
|
#define ATUNE_CH_GAIN_H(x) ATUNE_H(CH_GAIN, 8, x)
|
|
#define ATUNE_CH_GAIN_L(x) ATUNE_L(CH_GAIN, 0, x)
|
|
#define ATUNE_CH_GAIN_MASK(x) ATUNE_FLD_X(CH_GAIN, x)
|
|
/* ATUNE_SPUS_DSGAIN_BIT_CTRL_$ */
|
|
/* ATUNE_SPUM_DSGAIN_BIT_CTRL_$ */
|
|
#define ATUNE_DITHER_OUTPUT_BIT_H 5
|
|
#define ATUNE_DITHER_OUTPUT_BIT_L 4
|
|
#define ATUNE_DITHER_OUTPUT_BIT_MASK ATUNE_FLD(DITHER_OUTPUT_BIT)
|
|
#define ATUNE_DITHER_TYPE_H 1
|
|
#define ATUNE_DITHER_TYPE_L 0
|
|
#define ATUNE_DITHER_TYPE_MASK ATUNE_FLD(DITHER_TYPE)
|
|
/* ATUNE_SPUS_BQF_CTRL_$ */
|
|
/* ATUNE_SPUM_BQF_CTRL_$ */
|
|
#define ATUNE_EQ_ENABLE_H 4
|
|
#define ATUNE_EQ_ENABLE_L 4
|
|
#define ATUNE_EQ_ENABLE_MASK ATUNE_FLD(EQ_ENABLE)
|
|
#define ATUNE_HPF_ENABLE_H 0
|
|
#define ATUNE_HPF_ENABLE_L 0
|
|
#define ATUNE_HPF_ENABLE_MASK ATUNE_FLD(HPF_ENABLE)
|
|
/* ATUNE_SPUS_BQF_CH0_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH1_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH2_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH3_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH4_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH5_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH6_HEADROOM_$ */
|
|
/* ATUNE_SPUS_BQF_CH7_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH0_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH1_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH2_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH3_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH4_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH5_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH6_HEADROOM_$ */
|
|
/* ATUNE_SPUM_BQF_CH7_HEADROOM_$ */
|
|
#define ATUNE_HEADROOM_EQ_BASE 4
|
|
#define ATUNE_HEADROOM_EQ_ITV 4
|
|
#define ATUNE_HEADROOM_EQ_H(x) ATUNE_H(HEADROOM_EQ, 2, x)
|
|
#define ATUNE_HEADROOM_EQ_L(x) ATUNE_L(HEADROOM_EQ, 0, x)
|
|
#define ATUNE_HEADROOM_EQ_MASK(x) ATUNE_FLD_X(HEADROOM_EQ, x)
|
|
#define ATUNE_HEADROOM_HPF_H 2
|
|
#define ATUNE_HEADROOM_HPF_L 0
|
|
#define ATUNE_HEADROOM_HPF_MASK ATUNE_FLD(HEADROOM_HPF)
|
|
/* ATUNE_SPUS_BQF_CH0_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH1_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH2_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH3_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH4_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH5_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH6_POSTAMP_$ */
|
|
/* ATUNE_SPUS_BQF_CH7_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH0_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH1_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH2_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH3_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH4_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH5_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH6_POSTAMP_$ */
|
|
/* ATUNE_SPUM_BQF_CH7_POSTAMP_$ */
|
|
#define ATUNE_POSTAMP_EQ_BASE 4
|
|
#define ATUNE_POSTAMP_EQ_ITV 4
|
|
#define ATUNE_POSTAMP_EQ_H(x) ATUNE_H(POSTAMP_EQ, 1, x)
|
|
#define ATUNE_POSTAMP_EQ_L(x) ATUNE_L(POSTAMP_EQ, 0, x)
|
|
#define ATUNE_POSTAMP_EQ_MASK(x) ATUNE_FLD_X(POSTAMP_EQ, x)
|
|
#define ATUNE_POSTAMP_HPF_H 1
|
|
#define ATUNE_POSTAMP_HPF_L 0
|
|
#define ATUNE_POSTAMP_HPF_MASK ATUNE_FLD(POSTAMP_HPF)
|
|
/* ATUNE_SPUS_BQF_CH0_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH1_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH2_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH3_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH4_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH5_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH6_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH7_HPF_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH0_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH1_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH2_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH3_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH4_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH5_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH6_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_BQF_CH7_EQx_COEFx_$ */
|
|
/* ATUNE_SPUS_DRC_xPF0_COEFx_$ */
|
|
/* ATUNE_SPUS_DRC_xPF1_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH0_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH1_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH2_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH3_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH4_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH5_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH6_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH7_HPF_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH0_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH1_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH2_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH3_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH4_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH5_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH6_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_BQF_CH7_EQx_COEFx_$ */
|
|
/* ATUNE_SPUM_DRC_xPF0_COEFx_$ */
|
|
/* ATUNE_SPUM_DRC_xPF1_COEFx_$ */
|
|
#define ATUNE_COEF_H 31
|
|
#define ATUNE_COEF_L 0
|
|
#define ATUNE_COEF_MASK ATUNE_FLD(COEF)
|
|
/* ATUNE_SPUS_DRC_CTRL_$ */
|
|
/* ATUNE_SPUM_SRC_CTRL_$ */
|
|
#define ATUNE_LIMIT_WINDOW_SIZE_H 31
|
|
#define ATUNE_LIMIT_WINDOW_SIZE_L 24
|
|
#define ATUNE_LIMIT_WINDOW_SIZE_MASK ATUNE_FLD(LIMIT_WINDOW_SIZE)
|
|
#define ATUNE_NOISE_THRS_H 23
|
|
#define ATUNE_NOISE_THRS_L 16
|
|
#define ATUNE_NOISE_THRS_MASK ATUNE_FLD(NOISE_THRS)
|
|
#define ATUNE_DRC_NG_ENABLE_HB_H 14
|
|
#define ATUNE_DRC_NG_ENABLE_HB_L 14
|
|
#define ATUNE_DRC_NG_ENABLE_HB_MASK ATUNE_FLD(DRC_NG_ENABLE_HB)
|
|
#define ATUNE_DRC_NG_ENABLE_MB_H 13
|
|
#define ATUNE_DRC_NG_ENABLE_MB_L 13
|
|
#define ATUNE_DRC_NG_ENABLE_MB_MASK ATUNE_FLD(DRC_NG_ENABLE_MB)
|
|
#define ATUNE_DRC_NG_ENABLE_LB_H 12
|
|
#define ATUNE_DRC_NG_ENABLE_LB_L 12
|
|
#define ATUNE_DRC_NG_ENABLE_LB_MASK ATUNE_FLD(DRC_NG_ENABLE_LB)
|
|
#define ATUNE_DRC_ENABLE_HB_H 10
|
|
#define ATUNE_DRC_ENABLE_HB_L 10
|
|
#define ATUNE_DRC_ENABLE_HB_MASK ATUNE_FLD(DRC_ENABLE_HB)
|
|
#define ATUNE_DRC_ENABLE_MB_H 9
|
|
#define ATUNE_DRC_ENABLE_MB_L 9
|
|
#define ATUNE_DRC_ENABLE_MB_MASK ATUNE_FLD(DRC_ENABLE_MB)
|
|
#define ATUNE_DRC_ENABLE_LB_H 8
|
|
#define ATUNE_DRC_ENABLE_LB_L 8
|
|
#define ATUNE_DRC_ENABLE_LB_MASK ATUNE_FLD(DRC_ENABLE_LB)
|
|
#define ATUNE_LIMIT_ENABLE_H 1
|
|
#define ATUNE_LIMIT_ENABLE_L 1
|
|
#define ATUNE_LIMIT_ENABLE_MASK ATUNE_FLD(LIMIT_ENABLE)
|
|
#define ATUNE_DRC_ENABLE_H 0
|
|
#define ATUNE_DRC_ENABLE_L 0
|
|
#define ATUNE_DRC_ENABLE_MASK ATUNE_FLD(DRC_ENABLE)
|
|
/* ATUNE_SPUS_DRC_COMP_LB0_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_MB0_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_HB0_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_LB0_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_MB0_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_HB0_$ */
|
|
#define ATUNE_MAKEUP_GAIN_H 31
|
|
#define ATUNE_MAKEUP_GAIN_L 16
|
|
#define ATUNE_MAKEUP_GAIN_MASK ATUNE_FLD(MAKEUP_GAIN)
|
|
#define ATUNE_THRS_H 15
|
|
#define ATUNE_THRS_L 8
|
|
#define ATUNE_THRS_MASK ATUNE_FLD(THRS)
|
|
#define ATUNE_RATIO_H 7
|
|
#define ATUNE_RATIO_L 4
|
|
#define ATUNE_RATIO_MASK ATUNE_FLD(RATIO)
|
|
#define ATUNE_RMS_ENABLE_H 2
|
|
#define ATUNE_RMS_ENABLE_L 2
|
|
#define ATUNE_RMS_ENABLE_MASK ATUNE_FLD(RMS_ENABLE)
|
|
#define ATUNE_MUTE_ENABLE_H 0
|
|
#define ATUNE_MUTE_ENABLE_L 0
|
|
#define ATUNE_MUTE_ENABLE_MASK ATUNE_FLD(MUTE_ENABLE)
|
|
/* ATUNE_SPUS_DRC_COMP_LB1_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_MB1_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_HB1_$ */
|
|
/* ATUNE_SPUS_DRC_LMT_CTRL1_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_LB1_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_MB1_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_HB1_$ */
|
|
/* ATUNE_SPUM_DRC_LMT_CTRL1_$ */
|
|
#define ATUNE_ATTACK_TIME_H 31
|
|
#define ATUNE_ATTACK_TIME_L 0
|
|
#define ATUNE_ATTACK_TIME_MASK ATUNE_FLD(ATTACK_TIME)
|
|
/* ATUNE_SPUS_DRC_COMP_LB2_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_MB2_$ */
|
|
/* ATUNE_SPUS_DRC_COMP_HB2_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_LB2_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_MB2_$ */
|
|
/* ATUNE_SPUM_DRC_COMP_HB2_$ */
|
|
#define ATUNE_RELEASE_TIME_H 31
|
|
#define ATUNE_RELEASE_TIME_L 0
|
|
#define ATUNE_RELEASE_TIME_MASK ATUNE_FLD(RELEASE_TIME)
|
|
/* ATUNE_SPUS_DRC_LMT_CTRL0_$ */
|
|
/* ATUNE_SPUM_DRC_LMT_CTRL0_$ */
|
|
#define ATUNE_THRESHOLD_H 31
|
|
#define ATUNE_THRESHOLD_L 0
|
|
#define ATUNE_THRESHOLD_MASK ATUNE_FLD(THRESHOLD)
|
|
/* ATUNE HELPERS */
|
|
#define ATUNE_SPUS_USGAIN_GAIN_CH(x, fx) \
|
|
ATUNE_SFR_FLD_X(SPUS_USGAIN_GAIN0, x, CH_GAIN, 0, fx)
|
|
#define ATUNE_SPUS_DSGAIN_GAIN_CH(x, fx) \
|
|
ATUNE_SFR_FLD_X(SPUS_DSGAIN_GAIN0, x, CH_GAIN, 0, fx)
|
|
#define ATUNE_SPUM_USGAIN_GAIN_CH(x, fx) \
|
|
ATUNE_SFR_FLD_X(SPUM_USGAIN_GAIN0, x, CH_GAIN, 0, fx)
|
|
#define ATUNE_SPUM_DSGAIN_GAIN_CH(x, fx) \
|
|
ATUNE_SFR_FLD_X(SPUM_DSGAIN_GAIN0, x, CH_GAIN, 0, fx)
|
|
|
|
#define ABOX_MAX_REGISTERS ATUNE_SPUM_DRC_xPF1_COEF3(1)
|
|
|
|
/* TIMER */
|
|
#define ABOX_TIMER_BASE 0x0600
|
|
#define ABOX_TIMER_ITV 0x0020
|
|
#define ABOX_TIMER_CTRL0(x) ABOX_SFR(TIMER, 0x0, x)
|
|
#define ABOX_TIMER_CTRL1(x) ABOX_SFR(TIMER, 0x4, x)
|
|
#define ABOX_TIMER_PRESET_LSB(x) ABOX_SFR(TIMER, 0x8, x)
|
|
#define ABOX_TIMER_PRESET_MSB(x) ABOX_SFR(TIMER, 0xC, x)
|
|
#define ABOX_TIMER_CURVALUD_LSB(x) ABOX_SFR(TIMER, 0x10, x)
|
|
#define ABOX_TIMER_CURVALUD_MSB(x) ABOX_SFR(TIMER, 0x14, x)
|
|
/* ABOX_TIMER_CTRL0 */
|
|
#define ABOX_TIMER_FLUSH_H 1
|
|
#define ABOX_TIMER_FLUSH_L 1
|
|
#define ABOX_TIMER_FLUSH_MASK ABOX_FLD(TIMER_FLUSH)
|
|
#define ABOX_TIMER_START_H 0
|
|
#define ABOX_TIMER_START_L 0
|
|
#define ABOX_TIMER_START_MASK ABOX_FLD(TIMER_START)
|
|
/* ABOX_TIMER_CTRL1 */
|
|
#define ABOX_TIMER_MODE_H 0
|
|
#define ABOX_TIMER_MODE_L 0
|
|
#define ABOX_TIMER_MODE_MASK ABOX_FLD(TIMER_MODE)
|
|
|
|
#define ABOX_TIMER_MAX_REGISTERS ABOX_TIMER_CURVALUD_MSB(5)
|
|
|
|
#define AUD_PLL_RATE_HZ_FOR_48000 (1179648000)
|
|
#define AUD_PLL_RATE_HZ_FOR_44100 (1083801600)
|
|
|
|
#define TIMER_RATE 26000000ULL
|
|
#define TIMER_MOD 2000000
|
|
/* Predefined rate of MUX_CLK_AUD_UAIF for slave mode */
|
|
#define UAIF_RATE_MUX_SLAVE 100000000
|
|
|
|
#define COUNT_SIFS 7
|
|
#define COUNT_SPUS 12
|
|
#define COUNT_SIFM 8
|
|
#define COUNT_SPUM 8
|
|
#define COUNT_ATUNE 2
|
|
|
|
enum abox_gic_target {
|
|
ABOX_GIC_CORE0,
|
|
ABOX_GIC_CP,
|
|
ABOX_GIC_AP,
|
|
ABOX_GIC_CORE1,
|
|
};
|
|
|
|
#if IS_ENABLED(CONFIG_SOC_EXYNOS2100)
|
|
enum abox_irq {
|
|
SGI_IPC_RECEIVED = 0x0,
|
|
SGI_IPC_SYSTEM = 0x1,
|
|
SGI_IPC_PCMPLAYBACK = 0x2,
|
|
SGI_IPC_PCMCAPTURE = 0x3,
|
|
SGI_IPC_OFFLOAD = 0x4,
|
|
SGI_IPC_ERAP = 0x5,
|
|
SGI_FLUSH = 0x7,
|
|
SGI_WDMA0_BUF_FULL = 0x8,
|
|
SGI_WDMA1_BUF_FULL = 0x9,
|
|
SGI_IPC_ABOX_CONFIG = 0xA,
|
|
SGI_RDMA0_BUF_EMPTY = 0xB,
|
|
SGI_RDMA1_BUF_EMPTY = 0xC,
|
|
SGI_RDMA2_BUF_EMPTY = 0xD,
|
|
SGI_RDMA3_BUF_EMPTY = 0xE,
|
|
SGI_ABOX_MSG = 0xF,
|
|
IRQ_CA32_0 = 0x20,
|
|
IRQ_CA32_1,
|
|
IRQ_CA32_AXI_ERR,
|
|
IRQ_CA32_PMU_IRQ_0,
|
|
IRQ_CA32_PMU_IRQ_1,
|
|
IRQ_TIMER0_DONE = IRQ_CA32_0 + 8,
|
|
IRQ_TIMER1_DONE,
|
|
IRQ_TIMER2_DONE,
|
|
IRQ_TIMER3_DONE,
|
|
IRQ_TIMER4_DONE,
|
|
IRQ_TIMER5_DONE,
|
|
IRQ_RDMA0_BUF_EMPTY = IRQ_CA32_0 + 20,
|
|
IRQ_RDMA1_BUF_EMPTY,
|
|
IRQ_RDMA2_BUF_EMPTY,
|
|
IRQ_RDMA3_BUF_EMPTY,
|
|
IRQ_RDMA4_BUF_EMPTY,
|
|
IRQ_RDMA5_BUF_EMPTY,
|
|
IRQ_RDMA6_BUF_EMPTY,
|
|
IRQ_RDMA7_BUF_EMPTY,
|
|
IRQ_RDMA8_BUF_EMPTY,
|
|
IRQ_RDMA9_BUF_EMPTY,
|
|
IRQ_RDMA10_BUF_EMPTY,
|
|
IRQ_RDMA11_BUF_EMPTY,
|
|
IRQ_RDMA0_FADE_DONE,
|
|
IRQ_RDMA1_FADE_DONE,
|
|
IRQ_RDMA2_FADE_DONE,
|
|
IRQ_RDMA3_FADE_DONE,
|
|
IRQ_RDMA4_FADE_DONE,
|
|
IRQ_RDMA5_FADE_DONE,
|
|
IRQ_RDMA6_FADE_DONE,
|
|
IRQ_RDMA7_FADE_DONE,
|
|
IRQ_RDMA8_FADE_DONE,
|
|
IRQ_RDMA9_FADE_DONE,
|
|
IRQ_RDMA10_FADE_DONE,
|
|
IRQ_RDMA11_FADE_DONE,
|
|
IRQ_WDMA0_BUF_FULL,
|
|
IRQ_WDMA1_BUF_FULL,
|
|
IRQ_WDMA2_BUF_FULL,
|
|
IRQ_WDMA3_BUF_FULL,
|
|
IRQ_WDMA4_BUF_FULL,
|
|
IRQ_WDMA5_BUF_FULL,
|
|
IRQ_WDMA6_BUF_FULL,
|
|
IRQ_WDMA7_BUF_FULL,
|
|
IRQ_WDMA0_DUAL_BUF_FULL,
|
|
IRQ_WDMA1_DUAL_BUF_FULL,
|
|
IRQ_WDMA2_DUAL_BUF_FULL,
|
|
IRQ_WDMA3_DUAL_BUF_FULL,
|
|
IRQ_WDMA4_DUAL_BUF_FULL,
|
|
IRQ_WDMA5_DUAL_BUF_FULL,
|
|
IRQ_WDMA6_DUAL_BUF_FULL,
|
|
IRQ_WDMA7_DUAL_BUF_FULL,
|
|
IRQ_WDMA_DBG0_BUF_FULL,
|
|
IRQ_WDMA_DBG1_BUF_FULL,
|
|
IRQ_WDMA_DBG2_BUF_FULL,
|
|
IRQ_WDMA_DBG3_BUF_FULL,
|
|
IRQ_WDMA_DBG4_BUF_FULL,
|
|
IRQ_WDMA_DBG5_BUF_FULL,
|
|
IRQ_WDMA0_FADE_DONE,
|
|
IRQ_WDMA1_FADE_DONE,
|
|
IRQ_WDMA2_FADE_DONE,
|
|
IRQ_WDMA3_FADE_DONE,
|
|
IRQ_WDMA4_FADE_DONE,
|
|
IRQ_WDMA5_FADE_DONE,
|
|
IRQ_WDMA6_FADE_DONE,
|
|
IRQ_WDMA7_FADE_DONE,
|
|
IRQ_WDMA_DBG0_FADE_DONE,
|
|
IRQ_WDMA_DBG1_FADE_DONE,
|
|
IRQ_WDMA_DBG2_FADE_DONE,
|
|
IRQ_WDMA_DBG3_FADE_DONE,
|
|
IRQ_WDMA_DBG4_FADE_DONE,
|
|
IRQ_WDMA_DBG5_FADE_DONE,
|
|
IRQ_RDMA0_ERR,
|
|
IRQ_RDMA1_ERR,
|
|
IRQ_RDMA2_ERR,
|
|
IRQ_RDMA3_ERR,
|
|
IRQ_RDMA4_ERR,
|
|
IRQ_RDMA5_ERR,
|
|
IRQ_RDMA6_ERR,
|
|
IRQ_RDMA7_ERR,
|
|
IRQ_RDMA8_ERR,
|
|
IRQ_RDMA9_ERR,
|
|
IRQ_RDMA10_ERR,
|
|
IRQ_RDMA11_ERR,
|
|
IRQ_WDMA0_ERR,
|
|
IRQ_WDMA1_ERR,
|
|
IRQ_WDMA2_ERR,
|
|
IRQ_WDMA3_ERR,
|
|
IRQ_WDMA4_ERR,
|
|
IRQ_WDMA5_ERR,
|
|
IRQ_WDMA6_ERR,
|
|
IRQ_WDMA7_ERR,
|
|
IRQ_WDMA0_DUAL_ERR,
|
|
IRQ_WDMA1_DUAL_ERR,
|
|
IRQ_WDMA2_DUAL_ERR,
|
|
IRQ_WDMA3_DUAL_ERR,
|
|
IRQ_WDMA4_DUAL_ERR,
|
|
IRQ_WDMA5_DUAL_ERR,
|
|
IRQ_WDMA6_DUAL_ERR,
|
|
IRQ_WDMA7_DUAL_ERR,
|
|
IRQ_WDMA_DBG0_ERR,
|
|
IRQ_WDMA_DBG1_ERR,
|
|
IRQ_WDMA_DBG2_ERR,
|
|
IRQ_WDMA_DBG3_ERR,
|
|
IRQ_WDMA_DBG4_ERR,
|
|
IRQ_WDMA_DBG5_ERR,
|
|
IRQ_INTR_SIFT_FADE_DONE = IRQ_CA32_0 + 118,
|
|
IRQ_INTR_SIFM_FADE_DONE,
|
|
IRQ_UAIF0_SPEAKER,
|
|
IRQ_UAIF0_MIC,
|
|
IRQ_UAIF1_SPEAKER,
|
|
IRQ_UAIF1_MIC,
|
|
IRQ_UAIF2_SPEAKER,
|
|
IRQ_UAIF2_MIC,
|
|
IRQ_UAIF3_SPEAKER,
|
|
IRQ_UAIF3_MIC,
|
|
IRQ_UAIF4_SPEAKER,
|
|
IRQ_UAIF4_MIC,
|
|
IRQ_UAIF5_SPEAKER,
|
|
IRQ_UAIF5_MIC,
|
|
IRQ_UAIF6_SPEAKER,
|
|
IRQ_UAIF6_MIC,
|
|
IRQ_DSIF_OVERFLOW = IRQ_CA32_0 + 136,
|
|
IRQ_INTR_UAIF0_HOLD = IRQ_CA32_0 + 140,
|
|
IRQ_INTR_UAIF0_RESUME,
|
|
IRQ_INTR_UAIF1_HOLD,
|
|
IRQ_INTR_UAIF1_RESUME,
|
|
IRQ_INTR_UAIF2_HOLD,
|
|
IRQ_INTR_UAIF2_RESUME,
|
|
IRQ_INTR_UAIF3_HOLD,
|
|
IRQ_INTR_UAIF3_RESUME,
|
|
IRQ_INTR_UAIF4_HOLD,
|
|
IRQ_INTR_UAIF4_RESUME,
|
|
IRQ_INTR_UAIF5_HOLD,
|
|
IRQ_INTR_UAIF5_RESUME,
|
|
IRQ_INTR_UAIF6_HOLD,
|
|
IRQ_INTR_UAIF6_RESUME,
|
|
IRQ_AUDEN_RDMA0_BUF_EMPTY = IRQ_CA32_0 + 160,
|
|
IRQ_AUDEN_RDMA1_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA2_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA3_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA4_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA5_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA6_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA7_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA8_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA9_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA10_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA11_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA0_FADE_DONE,
|
|
IRQ_AUDEN_RDMA1_FADE_DONE,
|
|
IRQ_AUDEN_RDMA2_FADE_DONE,
|
|
IRQ_AUDEN_RDMA3_FADE_DONE,
|
|
IRQ_AUDEN_RDMA4_FADE_DONE,
|
|
IRQ_AUDEN_RDMA5_FADE_DONE,
|
|
IRQ_AUDEN_RDMA6_FADE_DONE,
|
|
IRQ_AUDEN_RDMA7_FADE_DONE,
|
|
IRQ_AUDEN_RDMA8_FADE_DONE,
|
|
IRQ_AUDEN_RDMA9_FADE_DONE,
|
|
IRQ_AUDEN_RDMA10_FADE_DONE,
|
|
IRQ_AUDEN_RDMA11_FADE_DONE,
|
|
IRQ_AUDEN_WDMA0_BUF_FULL,
|
|
IRQ_AUDEN_WDMA1_BUF_FULL,
|
|
IRQ_AUDEN_WDMA2_BUF_FULL,
|
|
IRQ_AUDEN_WDMA3_BUF_FULL,
|
|
IRQ_AUDEN_WDMA4_BUF_FULL,
|
|
IRQ_AUDEN_WDMA5_BUF_FULL,
|
|
IRQ_AUDEN_WDMA6_BUF_FULL,
|
|
IRQ_AUDEN_WDMA7_BUF_FULL,
|
|
IRQ_AUDEN_WDMA0_FADE_DONE,
|
|
IRQ_AUDEN_WDMA1_FADE_DONE,
|
|
IRQ_AUDEN_WDMA2_FADE_DONE,
|
|
IRQ_AUDEN_WDMA3_FADE_DONE,
|
|
IRQ_AUDEN_WDMA4_FADE_DONE,
|
|
IRQ_AUDEN_WDMA5_FADE_DONE,
|
|
IRQ_AUDEN_WDMA6_FADE_DONE,
|
|
IRQ_AUDEN_WDMA7_FADE_DONE,
|
|
IRQ_AUDEN_RDMA0_ERR,
|
|
IRQ_AUDEN_RDMA1_ERR,
|
|
IRQ_AUDEN_RDMA2_ERR,
|
|
IRQ_AUDEN_RDMA3_ERR,
|
|
IRQ_AUDEN_RDMA4_ERR,
|
|
IRQ_AUDEN_RDMA5_ERR,
|
|
IRQ_AUDEN_RDMA6_ERR,
|
|
IRQ_AUDEN_RDMA7_ERR,
|
|
IRQ_AUDEN_RDMA8_ERR,
|
|
IRQ_AUDEN_RDMA9_ERR,
|
|
IRQ_AUDEN_RDMA10_ERR,
|
|
IRQ_AUDEN_RDMA11_ERR,
|
|
IRQ_AUDEN_WDMA0_ERR,
|
|
IRQ_AUDEN_WDMA1_ERR,
|
|
IRQ_AUDEN_WDMA2_ERR,
|
|
IRQ_AUDEN_WDMA3_ERR,
|
|
IRQ_AUDEN_WDMA4_ERR,
|
|
IRQ_AUDEN_WDMA5_ERR,
|
|
IRQ_AUDEN_WDMA6_ERR,
|
|
IRQ_AUDEN_WDMA7_ERR,
|
|
IRQ_AUDEN_MIXP0_SYNC,
|
|
IRQ_AUDEN_MIXP1_SYNC,
|
|
IRQ_AUDEN_MIXP2_SYNC,
|
|
IRQ_AUDEN_WDMA0_BUF_PRE,
|
|
IRQ_AUDEN_WDMA1_BUF_PRE,
|
|
IRQ_AUDEN_WDMA2_BUF_PRE,
|
|
IRQ_AUDEN_WDMA3_BUF_PRE,
|
|
IRQ_AUDEN_WDMA4_BUF_PRE,
|
|
IRQ_AUDEN_WDMA5_BUF_PRE,
|
|
IRQ_AUDEN_WDMA6_BUF_PRE,
|
|
IRQ_AUDEN_WDMA7_BUF_PRE,
|
|
IRQ_INTR_C2A0_M = IRQ_CA32_0 + 232,
|
|
IRQ_INTR_C2A0_S,
|
|
IRQ_INTR_C2A1_M,
|
|
IRQ_INTR_C2A1_S,
|
|
IRQ_MBOX_S_DSPAUD = IRQ_CA32_0 + 236,
|
|
IRQ_MBOX_NS_DSPAUD,
|
|
IRQ_MBOX_S_NPUAUD,
|
|
IRQ_MBOX_NS_NPUAUD,
|
|
IRQ_WDT,
|
|
IRQ_USB1_INTR_IN,
|
|
IRQ_USB2_INTR_IN,
|
|
IRQ_USB3_INTR_IN,
|
|
IRQ_USB4_INTR_IN,
|
|
IRQ_GPIO_INTR_IN,
|
|
IRQ_MBOX_VTS_INTR_IN,
|
|
IRQ_BT_INTR_IN,
|
|
IRQ_CP_INTR_IN,
|
|
IRQ_SW_INTR_MST_SYNC,
|
|
IRQ_CP2_INTR_IN = IRQ_CA32_0 + 253,
|
|
IRQ_TICK_CP_INT,
|
|
IRQ_TICK_CP_EXT,
|
|
IRQ_TICK_PCM,
|
|
IRQ_XDMAC_INTTC,
|
|
IRQ_XDMAC_INTTERR,
|
|
IRQ_INTR_FROM_VTS_SERIAL_LIF,
|
|
IRQ_PCM_COUNTER_INT_CPU,
|
|
IRQ_PCM_COUNTER_INT_DCPU,
|
|
IRQ_PCM_COUNTER_INT_PRD2,
|
|
IRQ_PCM_COUNTER_INT_PRD1,
|
|
IRQ_PCM_COUNTER_INT_POS4,
|
|
IRQ_PCM_COUNTER_INT_POS3,
|
|
IRQ_PCM_COUNTER_INT_POS2,
|
|
IRQ_PCM_COUNTER_INT_POS1,
|
|
IRQ_SPUS_POSTGAIN1_FADE_DONE = IRQ_CA32_0 + 270,
|
|
IRQ_SPUS_POSTGAIN0_FADE_DONE,
|
|
IRQ_SPUS_PREGAIN1_FADE_DONE,
|
|
IRQ_SPUS_PREGAIN0_FADE_DONE,
|
|
IRQ_SPUM_POSTGAIN1_FADE_DONE,
|
|
IRQ_SPUM_POSTGAIN0_FADE_DONE,
|
|
IRQ_SPUM_PREGAIN1_FADE_DONE,
|
|
IRQ_SPUM_PREGAIN0_FADE_DONE,
|
|
IRQ_CP2AUD_SWI0 = IRQ_CA32_0 + 280,
|
|
IRQ_CP2AUD_SWI1,
|
|
IRQ_CP2AUD_SWI2,
|
|
IRQ_CP2AUD_SWI3,
|
|
IRQ_CP2AUD_SWI4,
|
|
IRQ_CP2AUD_SWI5,
|
|
IRQ_INTR_GSMIRQ,
|
|
IRQ_UDMA_RD0_BUF_EMPTY = IRQ_CA32_0 + 290,
|
|
IRQ_UDMA_RD1_BUF_EMPTY,
|
|
IRQ_UDMA_RD0_ERR,
|
|
IRQ_UDMA_RD1_ERR,
|
|
IRQ_UDMA_RD0_FADE_DONE,
|
|
IRQ_UDMA_RD1_FADE_DONE,
|
|
IRQ_UDMA_WR0_BUF_FULL,
|
|
IRQ_UDMA_WR1_BUF_FULL,
|
|
IRQ_UDMA_WR0_DUAL_BUF_FULL,
|
|
IRQ_UDMA_WR1_DUAL_BUF_FULL,
|
|
IRQ_UDMA_WR_DBG0_BUF_FULL,
|
|
IRQ_UDMA_WR0_ERR,
|
|
IRQ_UDMA_WR1_ERR,
|
|
IRQ_UDMA_WR0_DUAL_ERR,
|
|
IRQ_UDMA_WR1_DUAL_ERR,
|
|
IRQ_UDMA_WR_DBG0_ERR,
|
|
IRQ_UDMA_WR0_FADE_DONE,
|
|
IRQ_UDMA_WR1_FADE_DONE,
|
|
IRQ_UDMA_WR_DBG0_FADE_DONE,
|
|
IRQ_COUNT,
|
|
};
|
|
#else
|
|
#error "irq table isn't defined"
|
|
#endif
|
|
|
|
#endif /* __SND_SOC_ABOX_SOC_31_H */
|