1221 lines
45 KiB
C
Executable file
1221 lines
45 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* ALSA SoC - Samsung Abox SoC layer for version 3
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*
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* Copyright (c) 2018 Samsung Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SND_SOC_ABOX_SOC_3_H
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#define __SND_SOC_ABOX_SOC_3_H
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/* System */
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#define ABOX_IP_INDEX 0x0000
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#define ABOX_VERSION 0x0004
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#define ABOX_SYSPOWER_CTRL 0x0010
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#define ABOX_SYSPOWER_STATUS 0x0014
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#define ABOX_SYSTEM_CONFIG0 0x0020
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#define ABOX_REMAP_MASK 0x0024
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#define ABOX_REMAP_ADDR 0x0028
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#define ABOX_DYN_CLOCK_OFF 0x0030
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#define ABOX_DYN_CLOCK_OFF1 0x0034
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#define ABOX_QCHANNEL_DISABLE 0x0038
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#define ABOX_ROUTE_CTRL0 0x0040
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#define ABOX_ROUTE_CTRL1 0x0044
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#define ABOX_ROUTE_CTRL2 0x0048
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#define ABOX_TICK_DIV_RATIO 0x0050
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#define ABOX_TICK_GEN 0x0054
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#define ABOX_MO_CTRL ABOX_TICK_GEN
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#define ABOX_ROUTE_CTRL3 0x0080
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#define ABOX_ROUTE_CTRL4 0x0084
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#define ABOX_SW_PDI_CTRL0 0x00A0
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#define ABOX_SW_PDI_CTRL1 0x00A4
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#define ABOX_SW_PDI_CTRL2 0x00A8
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#define ABOX_SW_PDI_CTRL3 0x00AC
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/* ABOX_VERSION */
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#define ABOX_VERSION_H 31
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#define ABOX_VERSION_L 8
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#define ABOX_VERSION_MASK ABOX_FLD(VERSION)
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/* ABOX_SYSPOWER_CTRL */
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#define ABOX_SYSPOWER_CTRL_H 0
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#define ABOX_SYSPOWER_CTRL_L 0
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#define ABOX_SYSPOWER_CTRL_MASK ABOX_FLD(SYSPOWER_CTRL)
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/* ABOX_SYSPOWER_STATUS */
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#define ABOX_SYSPOWER_STATUS_H 0
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#define ABOX_SYSPOWER_STATUS_L 0
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#define ABOX_SYSPOWER_STATUS_MASK ABOX_FLD(SYSPOWER_STATUS)
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/* ABOX_DYN_CLOCK_OFF */
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#define ABOX_DYN_CLOCK_OFF_H 30
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#define ABOX_DYN_CLOCK_OFF_L 0
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#define ABOX_DYN_CLOCK_OFF_MASK ABOX_FLD(DYN_CLOCK_OFF)
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/* ABOX_QCHANNEL_DISABLE */
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#define ABOX_QCHANNEL_DISABLE_BASE 0
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#define ABOX_QCHANNEL_DISABLE_ITV 1
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#define ABOX_QCHANNEL_DISABLE_H(x) ABOX_H(QCHANNEL_DISABLE, 0, x)
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#define ABOX_QCHANNEL_DISABLE_L(x) ABOX_L(QCHANNEL_DISABLE, 0, x)
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#define ABOX_QCHANNEL_DISABLE_MASK(x) ABOX_FLD_X(QCHANNEL_DISABLE, x)
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/* ABOX_ROUTE_CTRL0 */
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#define ABOX_ROUTE_DSIF_H 31
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#define ABOX_ROUTE_DSIF_L 28
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#define ABOX_ROUTE_DSIF_MASK ABOX_FLD(ROUTE_DSIF)
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#define ABOX_ROUTE_UAIF_SPK_BASE 0
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#define ABOX_ROUTE_UAIF_SPK_ITV 4
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#define ABOX_ROUTE_UAIF_SPK_H(x) ABOX_H(ROUTE_UAIF_SPK, 3, x)
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#define ABOX_ROUTE_UAIF_SPK_L(x) ABOX_L(ROUTE_UAIF_SPK, 0, x)
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#define ABOX_ROUTE_UAIF_SPK_MASK(x) ABOX_FLD_X(ROUTE_UAIF_SPK, x)
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/* ABOX_ROUTE_CTRL1 */
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#define ABOX_ROUTE_SPUSM_H 29
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#define ABOX_ROUTE_SPUSM_L 25
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#define ABOX_ROUTE_SPUSM_MASK ABOX_FLD(ROUTE_SPUSM)
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#define ABOX_ROUTE_NSRC_BASE 0
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#define ABOX_ROUTE_NSRC_ITV 5
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#define ABOX_ROUTE_NSRC_H(x) ABOX_H(ROUTE_NSRC, 4, x)
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#define ABOX_ROUTE_NSRC_L(x) ABOX_L(ROUTE_NSRC, 0, x)
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#define ABOX_ROUTE_NSRC_MASK(x) ABOX_FLD_X(ROUTE_NSRC, x)
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/* ABOX_ROUTE_CTRL2 */
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#define ABOX_RSRC_CONNECTION_TYPE_BASE 28
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#define ABOX_RSRC_CONNECTION_TYPE_ITV 1
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#define ABOX_RSRC_CONNECTION_TYPE_H(x) ABOX_H(RSRC_CONNECTION_TYPE, 0, x)
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#define ABOX_RSRC_CONNECTION_TYPE_L(x) ABOX_L(RSRC_CONNECTION_TYPE, 0, x)
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#define ABOX_RSRC_CONNECTION_TYPE_MASK(x) ABOX_FLD_X(RSRC_CONNECTION_TYPE, x)
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#define ABOX_NSRC_CONNECTION_TYPE_BASE 20
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#define ABOX_NSRC_CONNECTION_TYPE_ITV 1
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#define ABOX_NSRC_CONNECTION_TYPE_H(x) ABOX_H(NSRC_CONNECTION_TYPE, 0, x)
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#define ABOX_NSRC_CONNECTION_TYPE_L(x) ABOX_L(NSRC_CONNECTION_TYPE, 0, x)
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#define ABOX_NSRC_CONNECTION_TYPE_MASK(x) ABOX_FLD_X(NSRC_CONNECTION_TYPE, x)
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#define ABOX_ROUTE_RSRC_BASE 0
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#define ABOX_ROUTE_RSRC_ITV 4
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#define ABOX_ROUTE_RSRC_H(x) ABOX_H(ROUTE_RSRC, 3, x)
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#define ABOX_ROUTE_RSRC_L(x) ABOX_L(ROUTE_RSRC, 0, x)
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#define ABOX_ROUTE_RSRC_MASK(x) ABOX_FLD_X(ROUTE_RSRC, x)
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#define ABOX_ROUTE_SPUST_H 4
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#define ABOX_ROUTE_SPUST_L 0
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#define ABOX_ROUTE_SPUST_MASK ABOX_FLD(ROUTE_SPUST)
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/* ABOX_SW_PDI_CTRL0 */
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/* ABOX_SW_PDI_CTRL1 */
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#define ABOX_BI_PDI_FORMAT_BASE 0
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#define ABOX_BI_PDI_FORMAT_ITV 8
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#define ABOX_BI_PDI_FORMAT_H(x) ABOX_H(BI_PDI_FORMAT, 3, x)
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#define ABOX_BI_PDI_FORMAT_L(x) ABOX_L(BI_PDI_FORMAT, 0, x)
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#define ABOX_BI_PDI_FORMAT_MASK(x) ABOX_FLD_X(BI_PDI_FORMAT, x)
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/* ABOX_SW_PDI_CTRL2 */
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#define ABOX_TX_PDI_FORMAT_BASE 0
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#define ABOX_TX_PDI_FORMAT_ITV 8
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#define ABOX_TX_PDI_FORMAT_H(x) ABOX_H(TX_PDI_FORMAT, 3, x)
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#define ABOX_TX_PDI_FORMAT_L(x) ABOX_L(TX_PDI_FORMAT, 0, x)
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#define ABOX_TX_PDI_FORMAT_MASK(x) ABOX_FLD_X(TX_PDI_FORMAT, x)
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/* ABOX_SW_PDI_CTRL3 */
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#define ABOX_RX_PDI_FORMAT_BASE 0
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#define ABOX_RX_PDI_FORMAT_ITV 8
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#define ABOX_RX_PDI_FORMAT_H(x) ABOX_H(RX_PDI_FORMAT, 3, x)
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#define ABOX_RX_PDI_FORMAT_L(x) ABOX_L(RX_PDI_FORMAT, 0, x)
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#define ABOX_RX_PDI_FORMAT_MASK(x) ABOX_FLD_X(RX_PDI_FORMAT, x)
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/* SPUS */
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#define ABOX_SPUS_CTRL_FC0 0x0200
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#define ABOX_SPUS_CTRL0 ABOX_SPUS_CTRL_FC0
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#define ABOX_SPUS_CTRL1 0x0204
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#define ABOX_SPUS_CTRL2 0x0208
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#define ABOX_SPUS_CTRL3 0x020C
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#define ABOX_SPUS_CTRL4 0x0210
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#define ABOX_SPUS_CTRL5 0x0214
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#define ABOX_SPUS_CTRL_FC1 0x0218
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#define ABOX_SPUS_CTRL_FC2 0x021C
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#define ABOX_SPUS_SBANK_RDMA_BASE 0x0220
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#define ABOX_SPUS_SBANK_RDMA_ITV 0x0004
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#define ABOX_SPUS_SBANK_RDMA(x) ABOX_SFR(SPUS_SBANK_RDMA, 0x0, x)
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#define ABOX_SPUS_SBANK_ASRC_BASE 0x0250
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#define ABOX_SPUS_SBANK_ASRC_ITV 0x0004
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#define ABOX_SPUS_SBANK_ASRC(x) ABOX_SFR(SPUS_SBANK_ASRC, 0x0, x)
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#define ABOX_SPUS_SBANK_MIXP 0x0280
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#define ABOX_SPUS_SBANK_SIDETONE 0x0284
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#define ABOX_SPUS_CTRL_SIFS_CNT_BASE 0x0290
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#define ABOX_SPUS_CTRL_SIFS_CNT_ITV 0x0004
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#define ABOX_SPUS_CTRL_SIFS_CNT(x) \
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(((x) > 4) ? 0x0288 : \
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(((x) > 3) ? 0x028C : ABOX_SFR(SPUS_CTRL_SIFS_CNT, 0x0, x)))
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#define ABOX_SPUS_LATENCY_CTRL0 0x02A0
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#define ABOX_SPUS_LATENCY_CTRL1 0x02B0
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#define ABOX_SPUS_LATENCY_CTRL2 0x02B4
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#define ABOX_SPUS_LATENCY_CTRL3 0x02B8
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/* ABOX_SPUS_CTRL_FCx */
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#define ABOX_FUNC_CHAIN_SRC_BASE 0
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#define ABOX_FUNC_CHAIN_SRC_ITV 8
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#define ABOX_FUNC_CHAIN_SRC_IN_H(x) ABOX_H(FUNC_CHAIN_SRC, 6, x)
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#define ABOX_FUNC_CHAIN_SRC_IN_L(x) ABOX_L(FUNC_CHAIN_SRC, 5, x)
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#define ABOX_FUNC_CHAIN_SRC_IN_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_IN, x)
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#define ABOX_FUNC_CHAIN_SRC_OUT_H(x) ABOX_H(FUNC_CHAIN_SRC, 4, x)
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#define ABOX_FUNC_CHAIN_SRC_OUT_L(x) ABOX_L(FUNC_CHAIN_SRC, 1, x)
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#define ABOX_FUNC_CHAIN_SRC_OUT_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_OUT, x)
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#define ABOX_FUNC_CHAIN_SRC_ASRC_H(x) ABOX_H(FUNC_CHAIN_SRC, 0, x)
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#define ABOX_FUNC_CHAIN_SRC_ASRC_L(x) ABOX_L(FUNC_CHAIN_SRC, 0, x)
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#define ABOX_FUNC_CHAIN_SRC_ASRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_SRC_ASRC, x)
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/* ABOX_SPUS_CTRL1 */
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#define ABOX_SIFSM_IN_SEL_H 11
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#define ABOX_SIFSM_IN_SEL_L 8
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#define ABOX_SIFSM_IN_SEL_MASK ABOX_FLD(SIFSM_IN_SEL)
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#define ABOX_SIFS_OUT_SEL_BASE 8
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#define ABOX_SIFS_OUT_SEL_ITV 4
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#define ABOX_SIFS_OUT_SEL_H(x) ABOX_H(SIFS_OUT_SEL, 3, x)
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#define ABOX_SIFS_OUT_SEL_L(x) ABOX_L(SIFS_OUT_SEL, 0, x)
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#define ABOX_SIFS_OUT_SEL_MASK(x) ABOX_FLD_X(SIFS_OUT_SEL, x)
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#define ABOX_MIXP_FORMAT_H 4
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#define ABOX_MIXP_FORMAT_L 0
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#define ABOX_MIXP_FORMAT_MASK ABOX_FLD(MIXP_FORMAT)
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/* ABOX_SPUS_CTRL2 */
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#define ABOX_SIFST_IN_SEL_H 31
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#define ABOX_SIFST_IN_SEL_L 28
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#define ABOX_SIFST_IN_SEL_MASK ABOX_FLD(SIFST_IN_SEL)
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#define ABOX_MIXP_LD_FLUSH_H 1
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#define ABOX_MIXP_LD_FLUSH_L 1
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#define ABOX_MIXP_LD_FLUSH_MASK ABOX_FLD(MIXP_LD_FLUSH)
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#define ABOX_MIXP_FLUSH_H 0
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#define ABOX_MIXP_FLUSH_L 0
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#define ABOX_MIXP_FLUSH_MASK ABOX_FLD(MIXP_FLUSH)
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/* ABOX_SPUS_CTRL3 */
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#define ABOX_SIFS_FLUSH_BASE -1
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#define ABOX_SIFS_FLUSH_ITV 1
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#define ABOX_SIFS_FLUSH_H(x) ABOX_H(SIFS_FLUSH, 0, x)
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#define ABOX_SIFS_FLUSH_L(x) ABOX_L(SIFS_FLUSH, 0, x)
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#define ABOX_SIFS_FLUSH_MASK(x) ABOX_FLD_X(SIFS_FLUSH, x)
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/* ABOX_SPUS_CTRL4 */
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/* ABOX_SPUS_CTRL5 */
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#define ABOX_SRC_ASRC_ID_BASE 16
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#define ABOX_SRC_ASRC_ID_ITV 4
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#define ABOX_SRC_ASRC_ID_H(x) ABOX_H(SRC_ASRC_ID, 3, x)
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#define ABOX_SRC_ASRC_ID_L(x) ABOX_L(SRC_ASRC_ID, 0, x)
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#define ABOX_SRC_ASRC_ID_MASK(x) ABOX_FLD_X(SRC_ASRC_ID, x)
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/* ABOX_SPUS_CTRL_SIFS_CNTx */
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#define ABOX_SIFS_CNT_VAL_BASE 0
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#define ABOX_SIFS_CNT_VAL_ITV 32
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#define ABOX_SIFS_CNT_VAL_H(x) ABOX_H(SIFS_CNT_VAL, 23, x)
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#define ABOX_SIFS_CNT_VAL_L(x) ABOX_L(SIFS_CNT_VAL, 0, x)
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#define ABOX_SIFS_CNT_VAL_MASK(x) ABOX_FLD_X(SIFS_CNT_VAL, x)
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/* ABOX_SPUS_LATENCY_CTRL0 */
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#define ABOX_MIXP_DUMMY_START_H 16
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#define ABOX_MIXP_DUMMY_START_L 16
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#define ABOX_MIXP_DUMMY_START_MASK ABOX_FLD(MIXP_DUMMY_START)
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#define ABOX_RDMA_ASRC_DUMMY_START_BASE 0
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#define ABOX_RDMA_ASRC_DUMMY_START_ITV 1
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#define ABOX_RDMA_ASRC_DUMMY_START_H(x) ABOX_H(RDMA_ASRC_DUMMY_START, 0, x)
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#define ABOX_RDMA_ASRC_DUMMY_START_L(x) ABOX_L(RDMA_ASRC_DUMMY_START, 0, x)
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#define ABOX_RDMA_ASRC_DUMMY_START_MASK(x) \
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ABOX_FLD_X(RDMA_ASRC_DUMMY_START, x)
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/* ABOX_SPUS_LATENCY_CTRL1 ... 3 */
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#define ABOX_RDMA_START_ASRC_NUM_BASE 0
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#define ABOX_RDMA_START_ASRC_NUM_ITV 8
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#define ABOX_RDMA_START_ASRC_NUM_H(x) ABOX_H(RDMA_START_ASRC_NUM, 7, x)
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#define ABOX_RDMA_START_ASRC_NUM_L(x) ABOX_L(RDMA_START_ASRC_NUM, 0, x)
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#define ABOX_RDMA_START_ASRC_NUM_MASK(x) ABOX_FLD_X(RDMA_START_ASRC_NUM, x)
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/* SPUM */
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#define ABOX_SPUM_CTRL0 0x0300
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#define ABOX_SPUM_CTRL1 0x0304
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#define ABOX_SPUM_CTRL2 0x0308
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#define ABOX_SPUM_CTRL3 0x030C
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#define ABOX_SPUM_CTRL4 0x0310
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#define ABOX_SPUM_SBANK_RSRC_BASE 0x0320
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#define ABOX_SPUM_SBANK_RSRC_ITV 0x0004
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#define ABOX_SPUM_SBANK_RSRC(x) ABOX_SFR(SPUM_SBANK_RSRC, 0x0, x)
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#define ABOX_SPUM_SBANK_NSRC_BASE 0x0328
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#define ABOX_SPUM_SBANK_NSRC_ITV 0x0004
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#define ABOX_SPUM_SBANK_NSRC(x) ABOX_SFR(SPUM_SBANK_NSRC, 0x0, x)
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#define ABOX_SPUM_SBANK_RECP 0x0348
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#define ABOX_SPUM_SBANK_ASRC_BASE 0x034C
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#define ABOX_SPUM_SBANK_ASRC_ITV 0x0004
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#define ABOX_SPUM_SBANK_ASRC(x) ABOX_SFR(SPUM_SBANK_ASRC, 0x0, x)
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/* ABOX_SPUM_CTRL0 */
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#define ABOX_FUNC_CHAIN_NSRC_BASE 4
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#define ABOX_FUNC_CHAIN_NSRC_ITV 4
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#define ABOX_FUNC_CHAIN_NSRC_OUT_H(x) ABOX_H(FUNC_CHAIN_NSRC, 3, x)
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#define ABOX_FUNC_CHAIN_NSRC_OUT_L(x) ABOX_L(FUNC_CHAIN_NSRC, 3, x)
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#define ABOX_FUNC_CHAIN_NSRC_OUT_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_OUT, x)
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#define ABOX_FUNC_CHAIN_NSRC_ASRC_H(x) ABOX_H(FUNC_CHAIN_NSRC, 0, x)
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#define ABOX_FUNC_CHAIN_NSRC_ASRC_L(x) ABOX_L(FUNC_CHAIN_NSRC, 0, x)
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#define ABOX_FUNC_CHAIN_NSRC_ASRC_MASK(x) ABOX_FLD_X(FUNC_CHAIN_NSRC_ASRC, x)
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#define ABOX_FUNC_CHAIN_RSRC_RECP_H 1
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#define ABOX_FUNC_CHAIN_RSRC_RECP_L 1
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#define ABOX_FUNC_CHAIN_RSRC_RECP_MASK ABOX_FLD(FUNC_CHAIN_RSRC_RECP)
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#define ABOX_FUNC_CHAIN_RSRC_ASRC_H 0
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#define ABOX_FUNC_CHAIN_RSRC_ASRC_L 0
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#define ABOX_FUNC_CHAIN_RSRC_ASRC_MASK ABOX_FLD(FUNC_CHAIN_RSRC_ASRC)
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/* ABOX_SPUM_CTRL1 */
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#define ABOX_SIFMS_OUT_SEL_H 18
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#define ABOX_SIFMS_OUT_SEL_L 16
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#define ABOX_SIFMS_OUT_SEL_MASK ABOX_FLD(SIFMS_OUT_SEL)
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#define ABOX_RECP_SRC_FORMAT_BASE 3
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#define ABOX_RECP_SRC_FORMAT_ITV 5
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#define ABOX_RECP_SRC_FORMAT_H(x) ABOX_H(RECP_SRC_FORMAT, 4, x)
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#define ABOX_RECP_SRC_FORMAT_L(x) ABOX_L(RECP_SRC_FORMAT, 0, x)
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#define ABOX_RECP_SRC_FORMAT_MASK(x) ABOX_FLD_X(RECP_SRC_FORMAT, x)
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#define ABOX_RECP_SRC_VALID_H 1
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#define ABOX_RECP_SRC_VALID_L 0
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#define ABOX_RECP_SRC_VALID_MASK ABOX_FLD(RECP_SRC_VALID)
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/* ABOX_SPUM_CTRL2 */
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#define ABOX_RECP_LD_FLUSH_H 1
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#define ABOX_RECP_LD_FLUSH_L 1
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#define ABOX_RECP_LD_FLUSH_MASK ABOX_FLD(RECP_LD_FLUSH)
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#define ABOX_RECP_FLUSH_H 0
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#define ABOX_RECP_FLUSH_L 0
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#define ABOX_RECP_FLUSH_MASK ABOX_FLD(RECP_FLUSH)
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/* ABOX_SPUM_CTRL3 */
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#define ABOX_SIFMS_FLUSH_H 7
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#define ABOX_SIFMS_FLUSH_L 7
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#define ABOX_SIFMS_FLUSH_MASK ABOX_FLD(SIFMS_FLUSH)
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/* ABOX_SPUM_CTRL4 */
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#define ABOX_NSRC_ASRC_ID_BASE 4
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#define ABOX_NSRC_ASRC_ID_ITV 4
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#define ABOX_NSRC_ASRC_ID_H(x) ABOX_H(NSRC_ASRC_ID, 3, x)
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#define ABOX_NSRC_ASRC_ID_L(x) ABOX_L(NSRC_ASRC_ID, 0, x)
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#define ABOX_NSRC_ASRC_ID_MASK(x) ABOX_FLD_X(NSRC_ASRC_ID, x)
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#define ABOX_RSRC_ASRC_ID_H 2
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#define ABOX_RSRC_ASRC_ID_L 0
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#define ABOX_RSRC_ASRC_ID_MASK ABOX_FLD_X(RSRC_ASRC_ID, x)
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/* ABOX_SPUS_SBANK_RDMAx */
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/* ABOX_SPUS_SBANK_ASRCx */
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/* ABOX_SPUM_SBANK_NSRCx */
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/* ABOX_SPUM_SBANK_ASRCx */
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#define ABOX_SBANK_SIZE_H 29
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#define ABOX_SBANK_SIZE_L 20
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#define ABOX_SBANK_SIZE_MASK ABOX_FLD(SBANK_SIZE)
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#define ABOX_SBANK_STR_H 13
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#define ABOX_SBANK_STR_L 4
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#define ABOX_SBANK_STR_MASK ABOX_FLD(SBANK_STR)
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/* AUDEN */
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#define ABOX_AUDEN_FC0_MAIN_CTRL 0x0400
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#define ABOX_AUDEN_FC1_MAIN_CTRL 0x0404
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#define ABOX_AUDEN_FC2_ASRC_CTRL 0x0408
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#define ABOX_AUDEN_FC3_ASRC_CTRL 0x040C
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#define ABOX_AUDEN_FC4_MIXP_CTRL 0x0410
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#define ABOX_AUDEN_FC5_MIXP_CTRL 0x0414
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#define ABOX_AUDEN_FC6_WDMA_CTRL 0x0418
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#define ABOX_AUDEN_MIXP_CTRL_BASE 0x0420
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#define ABOX_AUDEN_MIXP_CTRL_ITV 0x0004
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#define ABOX_AUDEN_MIXP_CTRL(x) ABOX_SFR(AUDEN_MIXP_CTRL, 0x0, x)
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#define ABOX_AUDEN_SBANK_RDMA_BASE 0x0430
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#define ABOX_AUDEN_SBANK_RDMA_ITV 0x0004
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#define ABOX_AUDEN_SBANK_RDMA(x) ABOX_SFR(AUDEN_SBANK_RDMA, 0x0, x)
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#define ABOX_AUDEN_SBANK_ASRC_BASE 0x0460
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#define ABOX_AUDEN_SBANK_ASRC_ITV 0x0004
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#define ABOX_AUDEN_SBANK_ASRC(x) ABOX_SFR(AUDEN_SBANK_ASRC, 0x0, x)
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#define ABOX_AUDEN_SBANK_MIXP_BASE 0x0490
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#define ABOX_AUDEN_SBANK_MIXP_ITV 0x0004
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#define ABOX_AUDEN_SBANK_MIXP(x) ABOX_SFR(AUDEN_SBANK_MIXP, 0x0, x)
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#define ABOX_AUDEN_ASRC_PERF_CON_BASE 0x04A0
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#define ABOX_AUDEN_ASRC_PERF_CON_ITV 0x0004
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#define ABOX_AUDEN_ASRC_PERF_CON(x) ABOX_SFR(AUDEN_ASRC_PERF_CON, 0x0, x)
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/* UAIF */
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#define ABOX_UAIF_BASE 0x0500
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#define ABOX_UAIF_ITV 0x0010
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#define ABOX_UAIF_CTRL0(x) ABOX_SFR(UAIF, 0x0, x)
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#define ABOX_UAIF_CTRL1(x) ABOX_SFR(UAIF, 0x4, x)
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#define ABOX_UAIF_IRQ_CTRL(x) ABOX_SFR(UAIF, 0x8, x)
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#define ABOX_UAIF_STATUS(x) ABOX_SFR(UAIF, 0xC, x)
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/* ABOX_UAIF_CTRL0 */
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#define ABOX_START_FIFO_DIFF_MIC_H 31
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#define ABOX_START_FIFO_DIFF_MIC_L 28
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#define ABOX_START_FIFO_DIFF_MIC_MASK ABOX_FLD(START_FIFO_DIFF_MIC)
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#define ABOX_START_FIFO_DIFF_SPK_H 27
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#define ABOX_START_FIFO_DIFF_SPK_L 24
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#define ABOX_START_FIFO_DIFF_SPK_MASK ABOX_FLD(START_FIFO_DIFF_SPK)
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#define ABOX_START_FIFO_SIZE_MIC_H 23
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#define ABOX_START_FIFO_SIZE_MIC_L 20
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#define ABOX_START_FIFO_SIZE_MIC_MASK ABOX_FLD(START_FIFO_SIZE_MIC)
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#define ABOX_START_FIFO_SIZE_SPK_H 19
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#define ABOX_START_FIFO_SIZE_SPK_L 16
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#define ABOX_START_FIFO_SIZE_SPK_MASK ABOX_FLD(START_FIFO_SIZE_SPK)
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#define ABOX_DATA_MODE_H 4
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#define ABOX_DATA_MODE_L 4
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#define ABOX_DATA_MODE_MASK ABOX_FLD(DATA_MODE)
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#define ABOX_IRQ_MODE_H 3
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#define ABOX_IRQ_MODE_L 3
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#define ABOX_IRQ_MODE_MASK ABOX_FLD(IRQ_MODE)
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#define ABOX_MODE_H 2
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#define ABOX_MODE_L 2
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#define ABOX_MODE_MASK ABOX_FLD(MODE)
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#define ABOX_MIC_ENABLE_H 1
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#define ABOX_MIC_ENABLE_L 1
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#define ABOX_MIC_ENABLE_MASK ABOX_FLD(MIC_ENABLE)
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#define ABOX_SPK_ENABLE_H 0
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#define ABOX_SPK_ENABLE_L 0
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#define ABOX_SPK_ENABLE_MASK ABOX_FLD(SPK_ENABLE)
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/* ABOX_UAIF_CTRL1 */
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#define ABOX_FORMAT_H 28
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#define ABOX_FORMAT_L 24
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#define ABOX_FORMAT_MASK ABOX_FLD(FORMAT)
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#define ABOX_BCLK_POLARITY_H 23
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#define ABOX_BCLK_POLARITY_L 23
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#define ABOX_BCLK_POLARITY_MASK ABOX_FLD(BCLK_POLARITY)
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#define ABOX_WS_MODE_H 22
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#define ABOX_WS_MODE_L 22
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#define ABOX_WS_MODE_MASK ABOX_FLD(WS_MODE)
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#define ABOX_WS_POLAR_H 21
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#define ABOX_WS_POLAR_L 21
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#define ABOX_WS_POLAR_MASK ABOX_FLD(WS_POLAR)
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#define ABOX_SLOT_MAX_H 20
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#define ABOX_SLOT_MAX_L 18
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#define ABOX_SLOT_MAX_MASK ABOX_FLD(SLOT_MAX)
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#define ABOX_SBIT_MAX_H 17
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#define ABOX_SBIT_MAX_L 12
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#define ABOX_SBIT_MAX_MASK ABOX_FLD(SBIT_MAX)
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#define ABOX_VALID_STR_H 11
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#define ABOX_VALID_STR_L 6
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#define ABOX_VALID_STR_MASK ABOX_FLD(VALID_STR)
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#define ABOX_VALID_END_H 5
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#define ABOX_VALID_END_L 0
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#define ABOX_VALID_END_MASK ABOX_FLD(VALID_END)
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/* ABOX_UAIF_IRQ_CTRL */
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#define ABOX_FILTER_CNT_H 6
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#define ABOX_FILTER_CNT_L 0
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#define ABOX_FILTER_CNT ABOX_FLD(FILTER_CNT)
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/* ABOX_UAIF_STATUS */
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#define ABOX_ERROR_OF_MIC_H 1
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#define ABOX_ERROR_OF_MIC_L 1
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#define ABOX_ERROR_OF_MIC_MASK ABOX_FLD(ERROR_OF_MIC)
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#define ABOX_ERROR_OF_SPK_H 0
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#define ABOX_ERROR_OF_SPK_L 0
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#define ABOX_ERROR_OF_SPK_MASK ABOX_FLD(ERROR_OF_SPK)
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/* DSIF */
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#define ABOX_DSIF_CTRL 0x0570
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#define ABOX_DSIF_STATUS 0x0574
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/* ABOX_DSIF_CTRL */
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#define ABOX_DSIF_MODE_H 3
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#define ABOX_DSIF_MODE_L 3
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#define ABOX_DSIF_MODE_MASK ABOX_FLD(DSIF_MODE)
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#define ABOX_DSIF_BCLK_POLARITY_H 2
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#define ABOX_DSIF_BCLK_POLARITY_L 2
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#define ABOX_DSIF_BCLK_POLARITY_MASK ABOX_FLD(DSIF_BCLK_POLARITY)
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#define ABOX_ORDER_H 1
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#define ABOX_ORDER_L 1
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#define ABOX_ORDER_MASK ABOX_FLD(ORDER)
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#define ABOX_ENABLE_H 0
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#define ABOX_ENABLE_L 0
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#define ABOX_ENABLE_MASK ABOX_FLD(ENABLE)
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/* ABOX_DSIF_STATUS */
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#define ABOX_ERROR_H 0
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#define ABOX_ERROR_L 0
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#define ABOX_ERROR_MASK ABOX_FLD(ERROR)
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/* SPDYIF */
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#define ABOX_SPDYIF_CTRL 0x0580
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/* ABOX_SPDYIF_CTRL */
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#define ABOX_START_FIFO_DIFF_H 4
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#define ABOX_START_FIFO_DIFF_L 1
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#define ABOX_START_FIFO_DIFF_MASK ABOX_FLD(START_FIFO_DIFF)
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/* TIMER */
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#define ABOX_TIMER_BASE 0x0600
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#define ABOX_TIMER_ITV 0x0020
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#define ABOX_TIMER_CTRL0(x) ABOX_SFR(TIMER, 0x0, x)
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#define ABOX_TIMER_CTRL1(x) ABOX_SFR(TIMER, 0x4, x)
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#define ABOX_TIMER_PRESET_LSB(x) ABOX_SFR(TIMER, 0x8, x)
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#define ABOX_TIMER_PRESET_MSB(x) ABOX_SFR(TIMER, 0xC, x)
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#define ABOX_TIMER_CURVALUD_LSB(x) ABOX_SFR(TIMER, 0x10, x)
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#define ABOX_TIMER_CURVALUD_MSB(x) ABOX_SFR(TIMER, 0x14, x)
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/* ABOX_TIMER_CTRL0 */
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#define ABOX_TIMER_FLUSH_H 1
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#define ABOX_TIMER_FLUSH_L 1
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#define ABOX_TIMER_FLUSH_MASK ABOX_FLD(TIMER_FLUSH)
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#define ABOX_TIMER_START_H 0
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#define ABOX_TIMER_START_L 0
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#define ABOX_TIMER_START_MASK ABOX_FLD(TIMER_START)
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/* ABOX_TIMER_CTRL1 */
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#define ABOX_TIMER_MODE_H 0
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#define ABOX_TIMER_MODE_L 0
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#define ABOX_TIMER_MODE_MASK ABOX_FLD(TIMER_MODE)
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#define ABOX_TIMER_MAX_REGISTERS ABOX_TIMER_CURVALUD_MSB(5)
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/* RDMA */
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#define ABOX_RDMA_BASE 0x1000
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#define ABOX_RDMA_ITV 0x0100
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#define ABOX_RDMA_CTRL0(x) ABOX_SFR(RDMA, 0x00, x)
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#define ABOX_RDMA_CTRL1(x) ABOX_SFR(RDMA, 0x04, x)
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#define ABOX_RDMA_BUF_STR(x) ABOX_SFR(RDMA, 0x08, x)
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#define ABOX_RDMA_BUF_END(x) ABOX_SFR(RDMA, 0x0C, x)
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#define ABOX_RDMA_BUF_OFFSET(x) ABOX_SFR(RDMA, 0x10, x)
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#define ABOX_RDMA_STR_POINT(x) ABOX_SFR(RDMA, 0x14, x)
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#define ABOX_RDMA_VOL_FACTOR(x) ABOX_SFR(RDMA, 0x18, x)
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#define ABOX_RDMA_VOL_CHANGE(x) ABOX_SFR(RDMA, 0x1C, x)
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#define ABOX_RDMA_SBANK_LIMIT(x) ABOX_SFR(RDMA, 0x20, x)
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#define ABOX_RDMA_BIT_CTRL0(x) ABOX_SFR(RDMA, 0x24, x)
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#define ABOX_RDMA_BIT_CTRL1(x) ABOX_SFR(RDMA, 0x28, x)
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#define ABOX_RDMA_STATUS(x) ABOX_SFR(RDMA, 0x30, x)
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/* ABOX_RDMA_CTRL0 */
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#define ABOX_RDMA_BURST_LEN_H 22
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#define ABOX_RDMA_BURST_LEN_L 19
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#define ABOX_RDMA_BURST_LEN_MASK ABOX_FLD(RDMA_BURST_LEN)
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#define ABOX_RDMA_ENABLE_H 0
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#define ABOX_RDMA_ENABLE_L 0
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#define ABOX_RDMA_ENABLE_MASK ABOX_FLD(RDMA_ENABLE)
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/* ABOX_RDMA_STATUS */
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#define ABOX_RDMA_PROGRESS_H 31
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#define ABOX_RDMA_PROGRESS_L 31
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#define ABOX_RDMA_PROGRESS_MASK ABOX_FLD(RDMA_PROGRESS)
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#if (ABOX_SOC_VERSION(3, 0, 0) < CONFIG_SND_SOC_SAMSUNG_ABOX_VERSION)
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#define ABOX_RDMA_RBUF_OFFSET_H 27
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#define ABOX_RDMA_RBUF_OFFSET_L 20
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#define ABOX_RDMA_RBUF_OFFSET_MASK ABOX_FLD(RDMA_RBUF_OFFSET)
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#define ABOX_RDMA_RBUF_CNT_H 19
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#define ABOX_RDMA_RBUF_CNT_L 0
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#define ABOX_RDMA_RBUF_CNT_MASK ABOX_FLD(RDMA_RBUF_CNT)
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#else
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#define ABOX_RDMA_RBUF_OFFSET_H 27
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#define ABOX_RDMA_RBUF_OFFSET_L 12
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#define ABOX_RDMA_RBUF_OFFSET_MASK ABOX_FLD(RDMA_RBUF_OFFSET)
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#define ABOX_RDMA_RBUF_CNT_H 11
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#define ABOX_RDMA_RBUF_CNT_L 0
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#define ABOX_RDMA_RBUF_CNT_MASK ABOX_FLD(RDMA_RBUF_CNT)
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#endif
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/* ABOX_RDMA_VOL_FACTOR */
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#define ABOX_RDMA_VOL_FACTOR_H (23)
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#define ABOX_RDMA_VOL_FACTOR_L (0)
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#define ABOX_RDMA_VOL_FACTOR_MASK ABOX_FLD(RDMA_VOL_FACTOR)
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/* SPUS ASRC */
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#define ABOX_SPUS_ASRC_BASE 0x2000
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#define ABOX_SPUS_ASRC_ITV 0x0100
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#define ABOX_SPUS_ASRC_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x00, x)
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#define ABOX_SPUS_ASRC_IS_PARA0(x) ABOX_SFR(SPUS_ASRC, 0x10, x)
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#define ABOX_SPUS_ASRC_IS_PARA1(x) ABOX_SFR(SPUS_ASRC, 0x14, x)
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#define ABOX_SPUS_ASRC_OS_PARA0(x) ABOX_SFR(SPUS_ASRC, 0x18, x)
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#define ABOX_SPUS_ASRC_OS_PARA1(x) ABOX_SFR(SPUS_ASRC, 0x1C, x)
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#define ABOX_SPUS_ASRC_DITHER_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x20, x)
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#define ABOX_SPUS_ASRC_SEED_IN(x) ABOX_SFR(SPUS_ASRC, 0x24, x)
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#define ABOX_SPUS_ASRC_SEED_OUT(x) ABOX_SFR(SPUS_ASRC, 0x28, x)
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#define ABOX_SPUS_ASRC_FILTER_CTRL(x) ABOX_SFR(SPUS_ASRC, 0x2C, x)
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/* WDMA */
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#define ABOX_WDMA_BASE 0x3000
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#define ABOX_WDMA_ITV 0x0100
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#define ABOX_WDMA_CTRL(x) ABOX_SFR(WDMA, 0x00, x)
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#define ABOX_WDMA_BUF_STR(x) ABOX_SFR(WDMA, 0x08, x)
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#define ABOX_WDMA_BUF_END(x) ABOX_SFR(WDMA, 0x0C, x)
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#define ABOX_WDMA_BUF_OFFSET(x) ABOX_SFR(WDMA, 0x10, x)
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#define ABOX_WDMA_STR_POINT(x) ABOX_SFR(WDMA, 0x14, x)
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#define ABOX_WDMA_VOL_FACTOR(x) ABOX_SFR(WDMA, 0x18, x)
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#define ABOX_WDMA_VOL_CHANGE(x) ABOX_SFR(WDMA, 0x1C, x)
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#define ABOX_WDMA_SBANK_LIMIT(x) ABOX_SFR(WDMA, 0x20, x)
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#define ABOX_WDMA_BIT_CTRL0(x) ABOX_SFR(WDMA, 0x24, x)
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#define ABOX_WDMA_BIT_CTRL1(x) ABOX_SFR(WDMA, 0x28, x)
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#define ABOX_WDMA_STATUS(x) ABOX_SFR(WDMA, 0x30, x)
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#define ABOX_WDMA_DUAL_CTRL(x) ABOX_SFR(WDMA, 0x80, x)
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#define ABOX_WDMA_DUAL_BUF_STR(x) ABOX_SFR(WDMA, 0x88, x)
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#define ABOX_WDMA_DUAL_BUF_END(x) ABOX_SFR(WDMA, 0x8C, x)
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#define ABOX_WDMA_DUAL_BUF_OFFSET(x) ABOX_SFR(WDMA, 0x90, x)
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#define ABOX_WDMA_DUAL_STR_POINT(x) ABOX_SFR(WDMA, 0x94, x)
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#define ABOX_WDMA_DUAL_STATUS(x) ABOX_SFR(WDMA, 0xB0, x)
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/* ABOX_WDMA_CTRL */
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#define ABOX_WDMA_ENABLE_H 0
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#define ABOX_WDMA_ENABLE_L 0
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#define ABOX_WDMA_ENABLE_MASK ABOX_FLD(WDMA_ENABLE)
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/* ABOX_WDMA_STATUS */
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#define ABOX_WDMA_PROGRESS_H 31
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#define ABOX_WDMA_PROGRESS_L 31
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#define ABOX_WDMA_PROGRESS_MASK ABOX_FLD(WDMA_PROGRESS)
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#if (ABOX_SOC_VERSION(3, 0, 0) < CONFIG_SND_SOC_SAMSUNG_ABOX_VERSION)
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#define ABOX_WDMA_WBUF_OFFSET_H 27
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#define ABOX_WDMA_WBUF_OFFSET_L 20
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#define ABOX_WDMA_WBUF_OFFSET_MASK ABOX_FLD(WDMA_WBUF_OFFSET)
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#define ABOX_WDMA_WBUF_CNT_H 19
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#define ABOX_WDMA_WBUF_CNT_L 0
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#define ABOX_WDMA_WBUF_CNT_MASK ABOX_FLD(WDMA_WBUF_CNT)
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#else
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#define ABOX_WDMA_WBUF_OFFSET_H 27
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#define ABOX_WDMA_WBUF_OFFSET_L 12
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#define ABOX_WDMA_WBUF_OFFSET_MASK ABOX_FLD(WDMA_WBUF_OFFSET)
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#define ABOX_WDMA_WBUF_CNT_H 11
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#define ABOX_WDMA_WBUF_CNT_L 0
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#define ABOX_WDMA_WBUF_CNT_MASK ABOX_FLD(WDMA_WBUF_CNT)
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#endif
|
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|
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/* WDMA_DEBUG */
|
|
#define ABOX_WDMA_DEBUG_BASE 0x3800
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#define ABOX_WDMA_DEBUG_ITV 0x0100
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#define ABOX_WDMA_DEBUG_CTRL(x) ABOX_SFR(WDMA_DEBUG, 0x00, x)
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#define ABOX_WDMA_DEBUG_BUF_STR(x) ABOX_SFR(WDMA_DEBUG, 0x08, x)
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#define ABOX_WDMA_DEBUG_BUF_END(x) ABOX_SFR(WDMA_DEBUG, 0x0C, x)
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#define ABOX_WDMA_DEBUG_BUF_OFFSET(x) ABOX_SFR(WDMA_DEBUG, 0x10, x)
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#define ABOX_WDMA_DEBUG_STR_POINT(x) ABOX_SFR(WDMA_DEBUG, 0x14, x)
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#define ABOX_WDMA_DEBUG_VOL_FACTOR(x) ABOX_SFR(WDMA_DEBUG, 0x18, x)
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#define ABOX_WDMA_DEBUG_VOL_CHANGE(x) ABOX_SFR(WDMA_DEBUG, 0x1C, x)
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|
#define ABOX_WDMA_DEBUG_SBANK_LIMIT(x) ABOX_SFR(WDMA_DEBUG, 0x20, x)
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|
#define ABOX_WDMA_DEBUG_STATUS(x) ABOX_SFR(WDMA_DEBUG, 0x30, x)
|
|
|
|
/* ABOX_xDMA_CTRL */
|
|
#define ABOX_DMA_DEBUG_SRC_H 29
|
|
#define ABOX_DMA_DEBUG_SRC_L 24
|
|
#define ABOX_DMA_DEBUG_SRC_MASK ABOX_FLD(DMA_DEBUG_SRC)
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|
#define ABOX_DMA_BURST_LEN_H 22
|
|
#define ABOX_DMA_BURST_LEN_L 19
|
|
#define ABOX_DMA_BURST_LEN_MASK ABOX_FLD(DMA_BURST_LEN)
|
|
#define ABOX_DMA_FUNC_H 18
|
|
#define ABOX_DMA_FUNC_L 16
|
|
#define ABOX_DMA_FUNC_MASK ABOX_FLD(DMA_FUNC)
|
|
#define ABOX_DMA_AUTO_FADE_IN_H 15
|
|
#define ABOX_DMA_AUTO_FADE_IN_L 15
|
|
#define ABOX_DMA_AUTO_FADE_IN_MASK ABOX_FLD(DMA_AUTO_FADE_IN)
|
|
#define ABOX_DMA_PACKED_H 14
|
|
#define ABOX_DMA_PACKED_L 14
|
|
#define ABOX_DMA_PACKED_MASK ABOX_FLD(DMA_PACKED)
|
|
#define ABOX_DMA_REDUCE_H 13
|
|
#define ABOX_DMA_REDUCE_L 13
|
|
#define ABOX_DMA_REDUCE_MASK ABOX_FLD(DMA_REDUCE)
|
|
#define ABOX_DMA_WIDTH_H 12
|
|
#define ABOX_DMA_WIDTH_L 11
|
|
#define ABOX_DMA_WIDTH_MASK ABOX_FLD(DMA_WIDTH)
|
|
#define ABOX_DMA_CHANNELS_H 10
|
|
#define ABOX_DMA_CHANNELS_L 8
|
|
#define ABOX_DMA_CHANNELS_MASK ABOX_FLD(DMA_CHANNELS)
|
|
#define ABOX_DMA_FORMAT_H 12
|
|
#define ABOX_DMA_FORMAT_L 8
|
|
#define ABOX_DMA_FORMAT_MASK ABOX_FLD(DMA_FORMAT)
|
|
#define ABOX_DMA_BUF_UPDATE_H 5
|
|
#define ABOX_DMA_BUF_UPDATE_L 5
|
|
#define ABOX_DMA_BUF_UPDATE_MASK ABOX_FLD(DMA_BUF_UPDATE)
|
|
#define ABOX_DMA_BUF_TYPE_H 4
|
|
#define ABOX_DMA_BUF_TYPE_L 4
|
|
#define ABOX_DMA_BUF_TYPE_MASK ABOX_FLD(DMA_BUF_TYPE)
|
|
#define ABOX_DMA_DUMMY_START_H 1
|
|
#define ABOX_DMA_DUMMY_START_L 1
|
|
#define ABOX_DMA_DUMMY_START_MASK ABOX_FLD(DMA_DUMMY_START)
|
|
#define ABOX_DMA_ENABLE_H 0
|
|
#define ABOX_DMA_ENABLE_L 0
|
|
#define ABOX_DMA_ENABLE_MASK ABOX_FLD(DMA_ENABLE)
|
|
/* ABOX_xDMA_BUF_STR */
|
|
#define ABOX_DMA_BUF_STR_H 31
|
|
#define ABOX_DMA_BUF_STR_L 4
|
|
#define ABOX_DMA_BUF_STR_MASK ABOX_FLD(DMA_BUF_STR)
|
|
/* ABOX_xDMA_BUF_END */
|
|
#define ABOX_DMA_BUF_END_H 31
|
|
#define ABOX_DMA_BUF_END_L 4
|
|
#define ABOX_DMA_BUF_END_MASK ABOX_FLD(DMA_BUF_END)
|
|
/* ABOX_xDMA_BUF_OFFSET */
|
|
#define ABOX_DMA_BUF_OFFSET_H 15
|
|
#define ABOX_DMA_BUF_OFFSET_L 4
|
|
#define ABOX_DMA_BUF_OFFSET_MASK ABOX_FLD(DMA_BUF_OFFSET)
|
|
/* ABOX_xDMA_STR_POINT */
|
|
#define ABOX_DMA_STR_POINT_H 31
|
|
#define ABOX_DMA_STR_POINT_L 4
|
|
#define ABOX_DMA_STR_POINT_MASK ABOX_FLD(DMA_STR_POINT)
|
|
/* ABOX_xDMA_VOL_FACTOR */
|
|
#define ABOX_DMA_VOL_FACTOR_H 23
|
|
#define ABOX_DMA_VOL_FACTOR_L 0
|
|
#define ABOX_DMA_VOL_FACTOR_MASK ABOX_FLD(DMA_VOL_FACTOR)
|
|
/* ABOX_xDMA_VOL_CHANGE */
|
|
#define ABOX_DMA_VOL_CHANGE_H 23
|
|
#define ABOX_DMA_VOL_CHANGE_L 0
|
|
#define ABOX_DMA_VOL_CHANGE_MASK ABOX_FLD(DMA_VOL_CHANGE)
|
|
/* ABOX_xDMA_SBANK_LIMIT */
|
|
#define ABOX_DMA_SBANK_LIMIT_H 13
|
|
#define ABOX_DMA_SBANK_LIMIT_L 4
|
|
#define ABOX_DMA_SBANK_LIMIT_MASK ABOX_FLD(DMA_SBANK_LIMIT)
|
|
/* ABOX_xDMA_BIT_CTRL0 */
|
|
#define ABOX_DMA_DITHER_ON_H 15
|
|
#define ABOX_DMA_DITHER_ON_L 15
|
|
#define ABOX_DMA_DITHER_ON_MASK ABOX_FLD(DMA_DITHER_ON)
|
|
#define ABOX_DMA_DITHER_STRENGTH_H 14
|
|
#define ABOX_DMA_DITHER_STRENGTH_L 8
|
|
#define ABOX_DMA_DITHER_STRENGTH_MASK ABOX_FLD(DMA_DITHER_STRENGTH)
|
|
#define ABOX_DMA_DITHER_WIDTH_H 5
|
|
#define ABOX_DMA_DITHER_WIDTH_L 4
|
|
#define ABOX_DMA_DITHER_WIDTH_MASK ABOX_FLD(DMA_DITHER_WIDTH)
|
|
#define ABOX_DMA_DST_BIT_WIDTH_H 1
|
|
#define ABOX_DMA_DST_BIT_WIDTH_L 0
|
|
#define ABOX_DMA_DST_BIT_WIDTH_MASK ABOX_FLD(DMA_DST_BIT_WIDTH)
|
|
/* ABOX_xDMA_BIT_CTRL1 */
|
|
#define ABOX_DMA_DITHER_IN_SEED_H 31
|
|
#define ABOX_DMA_DITHER_IN_SEED_L 0
|
|
#define ABOX_DMA_DITHER_IN_SEED_MASK ABOX_FLD(DMA_DITHER_IN_SEED)
|
|
/* ABOX_xDMA_STATUS */
|
|
#define ABOX_DMA_PROGRESS_H 31
|
|
#define ABOX_DMA_PROGRESS_L 31
|
|
#define ABOX_DMA_PROGRESS_MASK ABOX_FLD(DMA_PROGRESS)
|
|
#if (ABOX_SOC_VERSION(3, 0, 0) < CONFIG_SND_SOC_SAMSUNG_ABOX_VERSION)
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_H 27
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_L 20
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_MASK ABOX_FLD(DMA_BUF_OFFSET_CNT)
|
|
#define ABOX_DMA_BUF_CNT_H 19
|
|
#define ABOX_DMA_BUF_CNT_L 0
|
|
#define ABOX_DMA_BUF_CNT_MASK ABOX_FLD(DMA_BUF_CNT)
|
|
#else
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_H 27
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_L 12
|
|
#define ABOX_DMA_BUF_OFFSET_CNT_MASK ABOX_FLD(DMA_BUF_OFFSET_CNT)
|
|
#define ABOX_DMA_BUF_CNT_H 11
|
|
#define ABOX_DMA_BUF_CNT_L 0
|
|
#define ABOX_DMA_BUF_CNT_MASK ABOX_FLD(DMA_BUF_CNT)
|
|
#endif
|
|
|
|
/* SPUM ASRC */
|
|
#define ABOX_SPUM_ASRC_BASE 0x4000
|
|
#define ABOX_SPUM_ASRC_ITV 0x0100
|
|
#define ABOX_SPUM_ASRC_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x0, x)
|
|
#define ABOX_SPUM_ASRC_IS_PARA0(x) ABOX_SFR(SPUM_ASRC, 0x10, x)
|
|
#define ABOX_SPUM_ASRC_IS_PARA1(x) ABOX_SFR(SPUM_ASRC, 0x14, x)
|
|
#define ABOX_SPUM_ASRC_OS_PARA0(x) ABOX_SFR(SPUM_ASRC, 0x18, x)
|
|
#define ABOX_SPUM_ASRC_OS_PARA1(x) ABOX_SFR(SPUM_ASRC, 0x1C, x)
|
|
#define ABOX_SPUM_ASRC_DITHER_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x20, x)
|
|
#define ABOX_SPUM_ASRC_SEED_IN(x) ABOX_SFR(SPUM_ASRC, 0x24, x)
|
|
#define ABOX_SPUM_ASRC_SEED_OUT(x) ABOX_SFR(SPUM_ASRC, 0x28, x)
|
|
#define ABOX_SPUM_ASRC_FILTER_CTRL(x) ABOX_SFR(SPUM_ASRC, 0x2C, x)
|
|
|
|
/* ABOX_SPUS_ASRCx_CTRL */
|
|
/* ABOX_SPUM_ASRCx_CTRL */
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_H 27
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_L 24
|
|
#define ABOX_ASRC_OS_SOURCE_SEL_MASK ABOX_FLD(ASRC_OS_SOURCE_SEL)
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_H 23
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_L 20
|
|
#define ABOX_ASRC_IS_SOURCE_SEL_MASK ABOX_FLD(ASRC_IS_SOURCE_SEL)
|
|
#define ABOX_ASRC_TICKDIV_H 19
|
|
#define ABOX_ASRC_TICKDIV_L 16
|
|
#define ABOX_ASRC_TICKDIV_MASK ABOX_FLD(ASRC_TICKDIV)
|
|
#define ABOX_ASRC_TICKNUM_H 15
|
|
#define ABOX_ASRC_TICKNUM_L 8
|
|
#define ABOX_ASRC_TICKNUM_MASK ABOX_FLD(ASRC_TICKNUM)
|
|
#define ABOX_ASRC_BIT_WIDTH_H 7
|
|
#define ABOX_ASRC_BIT_WIDTH_L 6
|
|
#define ABOX_ASRC_BIT_WIDTH_MASK ABOX_FLD(ASRC_BIT_WIDTH)
|
|
#define ABOX_ASRC_DCMF_RATIO_H 5
|
|
#define ABOX_ASRC_DCMF_RATIO_L 4
|
|
#define ABOX_ASRC_DCMF_RATIO_MASK ABOX_FLD(ASRC_DCMF_RATIO)
|
|
#define ABOX_ASRC_OVSF_RATIO_H 3
|
|
#define ABOX_ASRC_OVSF_RATIO_L 2
|
|
#define ABOX_ASRC_OVSF_RATIO_MASK ABOX_FLD(ASRC_OVSF_RATIO)
|
|
#define ABOX_ASRC_OS_SYNC_MODE_H 1
|
|
#define ABOX_ASRC_OS_SYNC_MODE_L 1
|
|
#define ABOX_ASRC_OS_SYNC_MODE_MASK ABOX_FLD(ASRC_OS_SYNC_MODE)
|
|
#define ABOX_ASRC_IS_SYNC_MODE_H 0
|
|
#define ABOX_ASRC_IS_SYNC_MODE_L 0
|
|
#define ABOX_ASRC_IS_SYNC_MODE_MASK ABOX_FLD(ASRC_IS_SYNC_MODE)
|
|
/* ABOX_SPUS_ASRCx_IS_PARA0 */
|
|
/* ABOX_SPUM_ASRCx_IS_PARA0 */
|
|
#define ABOX_ASRC_IS_DEFAULT_H 16
|
|
#define ABOX_ASRC_IS_DEFAULT_L 0
|
|
#define ABOX_ASRC_IS_DEFAULT_MASK ABOX_FLD(ASRC_IS_DEFAULT)
|
|
/* ABOX_SPUS_ASRCx_IS_PARA1 */
|
|
/* ABOX_SPUM_ASRCx_IS_PARA1 */
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_H 16
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_L 0
|
|
#define ABOX_ASRC_IS_TPERIOD_LIMIT_MASK ABOX_FLD(ASRC_IS_TPERIOD_LIMIT)
|
|
/* ABOX_SPUS_ASRCx_OS_PARA0 */
|
|
/* ABOX_SPUM_ASRCx_OS_PARA0 */
|
|
#define ABOX_ASRC_OS_DEFAULT_H 16
|
|
#define ABOX_ASRC_OS_DEFAULT_L 0
|
|
#define ABOX_ASRC_OS_DEFAULT_MASK ABOX_FLD(ASRC_OS_DEFAULT)
|
|
/* ABOX_SPUS_ASRCx_OS_PARA1 */
|
|
/* ABOX_SPUM_ASRCx_OS_PARA1 */
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_H 16
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_L 0
|
|
#define ABOX_ASRC_OS_TPERIOD_LIMIT_MASK ABOX_FLD(ASRC_OS_TPERIOD_LIMIT)
|
|
/* ABOX_SPUS_ASRCx_DITHER_CTRL */
|
|
/* ABOX_SPUM_ASRCx_DITHER_CTRL */
|
|
#define ABOX_ASRC_DITHER_IN_ON_H 25
|
|
#define ABOX_ASRC_DITHER_IN_ON_L 25
|
|
#define ABOX_ASRC_DITHER_IN_ON_MASK ABOX_FLD(ASRC_DITHER_IN_ON)
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_H 24
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_L 18
|
|
#define ABOX_ASRC_DITHER_IN_STRENGTH_MASK ABOX_FLD(ASRC_DITHER_IN_STRENGTH)
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_H 17
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_L 16
|
|
#define ABOX_ASRC_DITHER_IN_WIDTH_MASK ABOX_FLD(ASRC_DITHER_IN_WIDTH)
|
|
#define ABOX_ASRC_DITHER_OUT_ON_H 9
|
|
#define ABOX_ASRC_DITHER_OUT_ON_L 9
|
|
#define ABOX_ASRC_DITHER_OUT_ON_MASK ABOX_FLD(ASRC_DITHER_OUT_ON)
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_H 8
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_L 2
|
|
#define ABOX_ASRC_DITHER_OUT_STRENGTH_MASK ABOX_FLD(ASRC_DITHER_OUT_STRENGTH)
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_H 1
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_L 0
|
|
#define ABOX_ASRC_DITHER_OUT_WIDTH_MASK ABOX_FLD(ASRC_DITHER_OUT_WIDTH)
|
|
/* ABOX_SPUS_ASRCx_SEED_IN */
|
|
/* ABOX_SPUM_ASRCx_SEED_IN */
|
|
#define ABOX_ASRC_DIHER_IN_SEED_H 31
|
|
#define ABOX_ASRC_DIHER_IN_SEED_L 0
|
|
#define ABOX_ASRC_DIHER_IN_SEED_MASK ABOX_FLD(ASRC_DITHER_IN_SEED)
|
|
/* ABOX_SPUS_ASRCx_SEED_OUT */
|
|
/* ABOX_SPUM_ASRCx_SEED_OUT */
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_H 31
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_L 0
|
|
#define ABOX_ASRC_DIHER_OUT_SEED_MASK ABOX_FLD(ASRC_DITHER_OUT_SEED)
|
|
/* ABOX_SPUS_ASRCx_FILTER_CTRL */
|
|
/* ABOX_SPUM_ASRCx_FILTER_CTRL */
|
|
#define ABOX_ASRC_APF_COEF_SEL_H 6
|
|
#define ABOX_ASRC_APF_COEF_SEL_L 6
|
|
#define ABOX_ASRC_APF_COEF_SEL_MASK ABOX_FLD(ASRC_APF_COEF_SEL)
|
|
#define ABOX_ASRC_APF_FILTER_SEL_H 5
|
|
#define ABOX_ASRC_APF_FILTER_SEL_L 5
|
|
#define ABOX_ASRC_APF_FILTER_SEL_MASK ABOX_FLD(ASRC_APF_FILTER_SEL)
|
|
#define ABOX_ASRC_TRF_ON_H 4
|
|
#define ABOX_ASRC_TRF_ON_L 4
|
|
#define ABOX_ASRC_TRF_ON_MASK ABOX_FLD(ASRC_TRF_ON)
|
|
#define ABOX_ASRC_TRF_GAIN_H 3
|
|
#define ABOX_ASRC_TRF_GAIN_L 0
|
|
#define ABOX_ASRC_TRF_GAIN_MASK ABOX_FLD(ASRC_TRF_GAIN)
|
|
|
|
/* CA7 */
|
|
#define ABOX_CA7_R_BASE 0x5000
|
|
#define ABOX_CA7_R_ITV 0x0004
|
|
#define ABOX_CA7_R(x) ABOX_SFR(CA7_R, 0x0, x)
|
|
#define ABOX_CA7_PC ABOX_CA7_R(15)
|
|
|
|
/* CA32 */
|
|
#define ABOX_CA32_CORE0_BASE 0x5000
|
|
#define ABOX_CA32_CORE0_ITV 0x0004
|
|
#define ABOX_CA32_CORE0_R(x) ABOX_SFR(CA32_CORE0, 0x0, x)
|
|
#define ABOX_CA32_CORE0_PC ABOX_CA32_CORE0_R(31)
|
|
#define ABOX_CA32_CORE1_BASE 0x5080
|
|
#define ABOX_CA32_CORE1_ITV 0x0004
|
|
#define ABOX_CA32_CORE1_R(x) ABOX_SFR(CA32_CORE1, 0x0, x)
|
|
#define ABOX_CA32_CORE1_PC ABOX_CA32_CORE1_R(31)
|
|
#define ABOX_CA32_STATUS 0x5100
|
|
|
|
/* APF_COEF */
|
|
#define ABOX_APF_BASE 0x7000
|
|
#define ABOX_APF_ITV 0x0100
|
|
#define ABOX_COEF_2EVEN0(x) ABOX_SFR(APF, 0x00, x)
|
|
#define ABOX_COEF_2EVEN1(x) ABOX_SFR(APF, 0x04, x)
|
|
#define ABOX_COEF_2EVEN2(x) ABOX_SFR(APF, 0x08, x)
|
|
#define ABOX_COEF_2EVEN3(x) ABOX_SFR(APF, 0x0C, x)
|
|
#define ABOX_COEF_2EVEN4(x) ABOX_SFR(APF, 0x10, x)
|
|
#define ABOX_COEF_2EVEN5(x) ABOX_SFR(APF, 0x14, x)
|
|
#define ABOX_COEF_2EVEN6(x) ABOX_SFR(APF, 0x18, x)
|
|
#define ABOX_COEF_2EVEN7(x) ABOX_SFR(APF, 0x1C, x)
|
|
#define ABOX_COEF_2EVEN8(x) ABOX_SFR(APF, 0x20, x)
|
|
#define ABOX_COEF_2EVEN9(x) ABOX_SFR(APF, 0x24, x)
|
|
#define ABOX_COEF_2ODD0(x) ABOX_SFR(APF, 0x28, x)
|
|
#define ABOX_COEF_2ODD1(x) ABOX_SFR(APF, 0x2C, x)
|
|
#define ABOX_COEF_2ODD2(x) ABOX_SFR(APF, 0x30, x)
|
|
#define ABOX_COEF_2ODD3(x) ABOX_SFR(APF, 0x34, x)
|
|
#define ABOX_COEF_2ODD4(x) ABOX_SFR(APF, 0x38, x)
|
|
#define ABOX_COEF_2ODD5(x) ABOX_SFR(APF, 0x3C, x)
|
|
#define ABOX_COEF_2ODD6(x) ABOX_SFR(APF, 0x40, x)
|
|
#define ABOX_COEF_2ODD7(x) ABOX_SFR(APF, 0x44, x)
|
|
#define ABOX_COEF_2ODD8(x) ABOX_SFR(APF, 0x48, x)
|
|
#define ABOX_COEF_4EVEN0(x) ABOX_SFR(APF, 0x4C, x)
|
|
#define ABOX_COEF_4EVEN1(x) ABOX_SFR(APF, 0x50, x)
|
|
#define ABOX_COEF_4EVEN2(x) ABOX_SFR(APF, 0x54, x)
|
|
#define ABOX_COEF_4ODD0(x) ABOX_SFR(APF, 0x58, x)
|
|
#define ABOX_COEF_4ODD1(x) ABOX_SFR(APF, 0x5C, x)
|
|
#define ABOX_COEF_8EVEN0(x) ABOX_SFR(APF, 0x60, x)
|
|
#define ABOX_COEF_8EVEN1(x) ABOX_SFR(APF, 0x64, x)
|
|
#define ABOX_COEF_8EVEN2(x) ABOX_SFR(APF, 0x68, x)
|
|
#define ABOX_COEF_8ODD0(x) ABOX_SFR(APF, 0x6C, x)
|
|
#define ABOX_COEF_8ODD1(x) ABOX_SFR(APF, 0x70, x)
|
|
|
|
/* AUDEN_RDMA */
|
|
#define ABOX_AUDEN_RDMA_BASE 0x8000
|
|
#define ABOX_AUDEN_RDMA_ITV 0x0100
|
|
#define ABOX_AUDEN_RDMA_CTRL0(x) ABOX_SFR(AUDEN_RDMA, 0x00, x)
|
|
#define ABOX_AUDEN_RDMA_CTRL1(x) ABOX_SFR(AUDEN_RDMA, 0x04, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_STR(x) ABOX_SFR(AUDEN_RDMA, 0x08, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_END(x) ABOX_SFR(AUDEN_RDMA, 0x0C, x)
|
|
#define ABOX_AUDEN_RDMA_BUF_OFFSET(x) ABOX_SFR(AUDEN_RDMA, 0x10, x)
|
|
#define ABOX_AUDEN_RDMA_STR_POINT(x) ABOX_SFR(AUDEN_RDMA, 0x14, x)
|
|
#define ABOX_AUDEN_RDMA_VOL_FACTOR(x) ABOX_SFR(AUDEN_RDMA, 0x18, x)
|
|
#define ABOX_AUDEN_RDMA_VOL_CHANGE(x) ABOX_SFR(AUDEN_RDMA, 0x1C, x)
|
|
#define ABOX_AUDEN_RDMA_SBANK_LIMIT(x) ABOX_SFR(AUDEN_RDMA, 0x20, x)
|
|
#define ABOX_AUDEN_RDMA_STATUS(x) ABOX_SFR(AUDEN_RDMA, 0x30, x)
|
|
|
|
/* AUDEN_ASRC */
|
|
#define ABOX_AUDEN_ASRC_BASE 0x9000
|
|
#define ABOX_AUDEN_ASRC_ITV 0x0100
|
|
#define ABOX_AUDEN_ASRC_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x00, x)
|
|
#define ABOX_AUDEN_ASRC_IS_PARA0(x) ABOX_SFR(AUDEN_ASRC, 0x10, x)
|
|
#define ABOX_AUDEN_ASRC_IS_PARA1(x) ABOX_SFR(AUDEN_ASRC, 0x14, x)
|
|
#define ABOX_AUDEN_ASRC_OS_PARA0(x) ABOX_SFR(AUDEN_ASRC, 0x18, x)
|
|
#define ABOX_AUDEN_ASRC_OS_PARA1(x) ABOX_SFR(AUDEN_ASRC, 0x1C, x)
|
|
#define ABOX_AUDEN_ASRC_DITHER_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x20, x)
|
|
#define ABOX_AUDEN_ASRC_SEED_IN(x) ABOX_SFR(AUDEN_ASRC, 0x24, x)
|
|
#define ABOX_AUDEN_ASRC_SEED_OUT(x) ABOX_SFR(AUDEN_ASRC, 0x28, x)
|
|
#define ABOX_AUDEN_ASRC_FILTER_CTRL(x) ABOX_SFR(AUDEN_ASRC, 0x2C, x)
|
|
|
|
/* AUDEN_WDMA */
|
|
#define ABOX_AUDEN_WDMA_BASE 0xA000
|
|
#define ABOX_AUDEN_WDMA_ITV 0x0100
|
|
#define ABOX_AUDEN_WDMA_CTRL(x) ABOX_SFR(AUDEN_WDMA, 0x00, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_STR(x) ABOX_SFR(AUDEN_WDMA, 0x08, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_END(x) ABOX_SFR(AUDEN_WDMA, 0x0C, x)
|
|
#define ABOX_AUDEN_WDMA_BUF_OFFSET(x) ABOX_SFR(AUDEN_WDMA, 0x10, x)
|
|
#define ABOX_AUDEN_WDMA_STR_POINT(x) ABOX_SFR(AUDEN_WDMA, 0x14, x)
|
|
#define ABOX_AUDEN_WDMA_VOL_FACTOR(x) ABOX_SFR(AUDEN_WDMA, 0x18, x)
|
|
#define ABOX_AUDEN_WDMA_VOL_CHANGE(x) ABOX_SFR(AUDEN_WDMA, 0x1C, x)
|
|
#define ABOX_AUDEN_WDMA_SBANK_LIMIT(x) ABOX_SFR(AUDEN_WDMA, 0x20, x)
|
|
#define ABOX_AUDEN_WDMA_STATUS(x) ABOX_SFR(AUDEN_WDMA, 0x30, x)
|
|
|
|
/* SOUNDWIRE */
|
|
#define ABOX_SOUNDWIRE_INFO 0xB000
|
|
|
|
/* SIDETONE */
|
|
#define ABOX_SIDETONE_CTRL 0xB100
|
|
#define ABOX_SIDETONE_GAIN_CTRL 0xB104
|
|
#define ABOX_SIDETONE_FILTER_CTRL0 0xB108
|
|
#define ABOX_SIDETONE_FILTER_CTRL1 0xB10C
|
|
#define ABOX_SIDETONE_HPF_COEF0 0xB110
|
|
#define ABOX_SIDETONE_HPF_COEF1 0xB114
|
|
#define ABOX_SIDETONE_HPF_COEF2 0xB118
|
|
#define ABOX_SIDETONE_HPF_COEF3 0xB11C
|
|
#define ABOX_SIDETONE_HPF_COEF4 0xB120
|
|
#define ABOX_SIDETONE_PEAK0_COEF0 0xB124
|
|
#define ABOX_SIDETONE_PEAK0_COEF1 0xB128
|
|
#define ABOX_SIDETONE_PEAK0_COEF2 0xB12C
|
|
#define ABOX_SIDETONE_PEAK0_COEF3 0xB130
|
|
#define ABOX_SIDETONE_PEAK0_COEF4 0xB134
|
|
#define ABOX_SIDETONE_PEAK1_COEF0 0xB138
|
|
#define ABOX_SIDETONE_PEAK1_COEF1 0xB13C
|
|
#define ABOX_SIDETONE_PEAK1_COEF2 0xB140
|
|
#define ABOX_SIDETONE_PEAK1_COEF3 0xB144
|
|
#define ABOX_SIDETONE_PEAK1_COEF4 0xB148
|
|
#define ABOX_SIDETONE_PEAK2_COEF0 0xB14C
|
|
#define ABOX_SIDETONE_PEAK2_COEF1 0xB150
|
|
#define ABOX_SIDETONE_PEAK2_COEF2 0xB154
|
|
#define ABOX_SIDETONE_PEAK2_COEF3 0xB158
|
|
#define ABOX_SIDETONE_PEAK2_COEF4 0xB15C
|
|
#define ABOX_SIDETONE_LOWSH_COEF0 0xB160
|
|
#define ABOX_SIDETONE_LOWSH_COEF1 0xB164
|
|
#define ABOX_SIDETONE_LOWSH_COEF2 0xB168
|
|
#define ABOX_SIDETONE_LOWSH_COEF3 0xB16C
|
|
#define ABOX_SIDETONE_LOWSH_COEF4 0xB170
|
|
#define ABOX_SIDETONE_HIGHSH_COEF0 0xB174
|
|
#define ABOX_SIDETONE_HIGHSH_COEF1 0xB178
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#define ABOX_SIDETONE_HIGHSH_COEF2 0xB17C
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#define ABOX_SIDETONE_HIGHSH_COEF3 0xB180
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#define ABOX_SIDETONE_HIGHSH_COEF4 0xB184
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/* ABOX_SIDETONE_CTRL */
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#define ABOX_SDTN_GAIN_OUT_ENABLE_H 31
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#define ABOX_SDTN_GAIN_OUT_ENABLE_L 31
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#define ABOX_SDTN_GAIN_OUT_ENABLE_MASK ABOX_FLD(SDTN_GAIN_OUT_ENABLE)
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#define ABOX_SDTN_GAIN_IN_ENABLE_H 30
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#define ABOX_SDTN_GAIN_IN_ENABLE_L 30
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#define ABOX_SDTN_GAIN_IN_ENABLE_MASK ABOX_FLD(SDTN_GAIN_IN_ENABLE)
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#define ABOX_SDTN_EQ_ENABLE_H 29
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#define ABOX_SDTN_EQ_ENABLE_L 29
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#define ABOX_SDTN_EQ_ENABLE_MASK ABOX_FLD(SDTN_EQ_ENABLE)
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#define ABOX_SDTN_HPF_ENABLE_H 28
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#define ABOX_SDTN_HPF_ENABLE_L 28
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#define ABOX_SDTN_HPF_ENABLE_MASK ABOX_FLD(SDTN_HPF_ENABLE)
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#define ABOX_SDTN_FLUSH_H 24
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#define ABOX_SDTN_FLUSH_L 24
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#define ABOX_SDTN_FLUSH_MASK ABOX_FLD(SDTN_FLUSH)
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#define ABOX_SDTN_BYPASS_ENABLE_H 22
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#define ABOX_SDTN_BYPASS_ENABLE_L 22
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#define ABOX_SDTN_BYPASS_ENABLE_MASK ABOX_FLD(SDTN_BYPASS_ENABLE)
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#define ABOX_SDTN_ZERO_OUTPUT_H 21
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#define ABOX_SDTN_ZERO_OUTPUT_L 21
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#define ABOX_SDTN_ZERO_OUTPUT_MASK ABOX_FLD(SDTN_ZERO_OUTPUT)
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#define ABOX_SDTN_OUT2_ENABLE_H 20
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#define ABOX_SDTN_OUT2_ENABLE_L 20
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#define ABOX_SDTN_OUT2_ENABLE_MASK ABOX_FLD(SDTN_OUT2_ENABLE)
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#define ABOX_SDTN_CH_SEL_OUT2_H 18
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#define ABOX_SDTN_CH_SEL_OUT2_L 16
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#define ABOX_SDTN_CH_SEL_OUT2_MASK ABOX_FLD(SDTN_CH_SEL_OUT2)
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#define ABOX_SDTN_CH_SEL_OUT_H 14
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#define ABOX_SDTN_CH_SEL_OUT_L 12
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#define ABOX_SDTN_CH_SEL_OUT_MASK ABOX_FLD(SDTN_CH_SEL_OUT)
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#define ABOX_SDTN_CH_SEL_IN_H 10
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#define ABOX_SDTN_CH_SEL_IN_L 8
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#define ABOX_SDTN_CH_SEL_IN_MASK ABOX_FLD(SDTN_CH_SEL_IN)
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#define ABOX_SDTN_FORMAT_H 4
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#define ABOX_SDTN_FORMAT_L 0
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#define ABOX_SDTN_FORMAT_MASK ABOX_FLD(SDTN_FORMAT)
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/* ABOX_SIDETONE_GAIN_CTRL */
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#define ABOX_SDTN_GAIN_OUT_H 23
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#define ABOX_SDTN_GAIN_OUT_L 16
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#define ABOX_SDTN_GAIN_OUT_MASK ABOX_FLD(SDTN_GAIN_OUT)
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#define ABOX_SDTN_GAIN_IN_H 7
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#define ABOX_SDTN_GAIN_IN_L 0
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#define ABOX_SDTN_GAIN_IN_MASK ABOX_FLD(SDTN_GAIN_IN)
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/* ABOX_SIDETONE_FILTER_CTRL0 */
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#define ABOX_SDTN_HEADROOM_HIGHSH_H 22
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#define ABOX_SDTN_HEADROOM_HIGHSH_L 20
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#define ABOX_SDTN_HEADROOM_HIGHSH_MASK ABOX_FLD(SDTN_HEADROOM_HIGHSH)
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#define ABOX_SDTN_HEADROOM_LOWSH_H 18
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#define ABOX_SDTN_HEADROOM_LOWSH_L 16
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#define ABOX_SDTN_HEADROOM_LOWSH_MASK ABOX_FLD(SDTN_HEADROOM_LOWSH)
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#define ABOX_SDTN_HEADROOM_PEAK2_H 14
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#define ABOX_SDTN_HEADROOM_PEAK2_L 12
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#define ABOX_SDTN_HEADROOM_PEAK2_MASK ABOX_FLD(SDTN_HEADROOM_PEAK2)
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#define ABOX_SDTN_HEADROOM_PEAK1_H 10
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#define ABOX_SDTN_HEADROOM_PEAK1_L 8
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#define ABOX_SDTN_HEADROOM_PEAK1_MASK ABOX_FLD(SDTN_HEADROOM_PEAK1)
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#define ABOX_SDTN_HEADROOM_PEAK0_H 6
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#define ABOX_SDTN_HEADROOM_PEAK0_L 4
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#define ABOX_SDTN_HEADROOM_PEAK0_MASK ABOX_FLD(SDTN_HEADROOM_PEAK0)
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#define ABOX_SDTN_HEADROOM_HPF_H 2
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#define ABOX_SDTN_HEADROOM_HPF_L 0
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#define ABOX_SDTN_HEADROOM_HPF_MASK ABOX_FLD(SDTN_HEADROOM_HPF)
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/* ABOX_SIDETONE_FILTER_CTRL1 */
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#define ABOX_SDTN_POSTAMP_HIGHSH_H 21
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#define ABOX_SDTN_POSTAMP_HIGHSH_L 20
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#define ABOX_SDTN_POSTAMP_HIGHSH_MASK ABOX_FLD(SDTN_POSTAMP_HIGHSH)
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#define ABOX_SDTN_POSTAMP_LOWSH_H 17
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#define ABOX_SDTN_POSTAMP_LOWSH_L 16
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#define ABOX_SDTN_POSTAMP_LOWSH_MASK ABOX_FLD(SDTN_POSTAMP_LOWSH)
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#define ABOX_SDTN_POSTAMP_PEAK2_H 13
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#define ABOX_SDTN_POSTAMP_PEAK2_L 12
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#define ABOX_SDTN_POSTAMP_PEAK2_MASK ABOX_FLD(SDTN_POSTAMP_PEAK2)
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#define ABOX_SDTN_POSTAMP_PEAK1_H 9
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#define ABOX_SDTN_POSTAMP_PEAK1_L 8
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#define ABOX_SDTN_POSTAMP_PEAK1_MASK ABOX_FLD(SDTN_POSTAMP_PEAK1)
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#define ABOX_SDTN_POSTAMP_PEAK0_H 5
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#define ABOX_SDTN_POSTAMP_PEAK0_L 4
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#define ABOX_SDTN_POSTAMP_PEAK0_MASK ABOX_FLD(SDTN_POSTAMP_PEAK0)
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#define ABOX_SDTN_POSTAMP_HPF_H 1
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#define ABOX_SDTN_POSTAMP_HPF_L 0
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#define ABOX_SDTN_POSTAMP_HPF_MASK ABOX_FLD(SDTN_POSTAMP_HPF)
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/* ABOX_SIDETONE_*_COEFx */
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#define ABOX_SDTN_COEF_H 31
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#define ABOX_SDTN_COEF_L 0
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#define ABOX_SDTN_COEF_MASK ABOX_FLD(SDTN_COEF)
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#define ABOX_MAX_REGISTERS ABOX_SIDETONE_HIGHSH_COEF4
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#define AUD_PLL_RATE_HZ_FOR_48000 (1179648000)
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#define AUD_PLL_RATE_HZ_FOR_44100 (1083801600)
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#define TIMER_RATE 26000000ULL
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#define TIMER_MOD 2000000
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/* Predefined rate of MUX_CLK_AUD_UAIF for slave mode */
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#define UAIF_RATE_MUX_SLAVE 100000000
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#define COUNT_SIFS 6
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#define COUNT_SPUS 12
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#define COUNT_SIFM 5
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#define COUNT_SPUM 5
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enum abox_gic_target {
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ABOX_GIC_CORE0,
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ABOX_GIC_CP,
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ABOX_GIC_AP,
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ABOX_GIC_CORE1,
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};
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#if IS_ENABLED(CONFIG_SOC_EXYNOS9830)
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enum abox_irq {
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SGI_IPC_RECEIVED = 0x0,
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SGI_IPC_SYSTEM = 0x1,
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SGI_IPC_PCMPLAYBACK = 0x2,
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SGI_IPC_PCMCAPTURE = 0x3,
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SGI_IPC_OFFLOAD = 0x4,
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SGI_IPC_ERAP = 0x5,
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SGI_FLUSH = 0x7,
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SGI_WDMA0_BUF_FULL = 0x8,
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SGI_WDMA1_BUF_FULL = 0x9,
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SGI_IPC_ABOX_CONFIG = 0xA,
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SGI_RDMA0_BUF_EMPTY = 0xB,
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SGI_RDMA1_BUF_EMPTY = 0xC,
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SGI_RDMA2_BUF_EMPTY = 0xD,
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SGI_RDMA3_BUF_EMPTY = 0xE,
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SGI_ABOX_MSG = 0xF,
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IRQ_CA32_0 = 0x20,
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IRQ_CA32_1,
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IRQ_TIMER0_DONE,
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IRQ_TIMER1_DONE,
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IRQ_TIMER2_DONE,
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IRQ_TIMER3_DONE,
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IRQ_TIMER4_DONE,
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IRQ_TIMER5_DONE,
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IRQ_RDMA0_BUF_EMPTY,
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IRQ_RDMA1_BUF_EMPTY,
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IRQ_RDMA2_BUF_EMPTY,
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IRQ_RDMA3_BUF_EMPTY,
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IRQ_RDMA4_BUF_EMPTY,
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IRQ_RDMA5_BUF_EMPTY,
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IRQ_RDMA6_BUF_EMPTY,
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IRQ_RDMA7_BUF_EMPTY,
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IRQ_RDMA8_BUF_EMPTY,
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IRQ_RDMA9_BUF_EMPTY,
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IRQ_RDMA10_BUF_EMPTY,
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IRQ_RDMA11_BUF_EMPTY,
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IRQ_RDMA0_FADE_DONE,
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IRQ_RDMA1_FADE_DONE,
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IRQ_RDMA2_FADE_DONE,
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IRQ_RDMA3_FADE_DONE,
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IRQ_RDMA4_FADE_DONE,
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IRQ_RDMA5_FADE_DONE,
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IRQ_RDMA6_FADE_DONE,
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IRQ_RDMA7_FADE_DONE,
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IRQ_RDMA8_FADE_DONE,
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IRQ_RDMA9_FADE_DONE,
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IRQ_RDMA10_FADE_DONE,
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IRQ_RDMA11_FADE_DONE,
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IRQ_WDMA0_BUF_FULL,
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IRQ_WDMA1_BUF_FULL,
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IRQ_WDMA2_BUF_FULL,
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IRQ_WDMA3_BUF_FULL,
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IRQ_WDMA4_BUF_FULL,
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IRQ_WDMA0_DUAL_BUF_FULL,
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IRQ_WDMA1_DUAL_BUF_FULL,
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IRQ_WDMA2_DUAL_BUF_FULL,
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IRQ_WDMA3_DUAL_BUF_FULL,
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IRQ_WDMA4_DUAL_BUF_FULL,
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IRQ_WDMA_DBG0_BUF_FULL,
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IRQ_WDMA_DBG1_BUF_FULL,
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IRQ_WDMA_DBG2_BUF_FULL,
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IRQ_WDMA_DBG3_BUF_FULL,
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IRQ_WDMA_DBG4_BUF_FULL,
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IRQ_WDMA_DBG5_BUF_FULL,
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IRQ_WDMA0_FADE_DONE,
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IRQ_WDMA1_FADE_DONE,
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IRQ_WDMA2_FADE_DONE,
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IRQ_WDMA3_FADE_DONE,
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IRQ_WDMA4_FADE_DONE,
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IRQ_WDMA_DBG0_FADE_DONE,
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IRQ_WDMA_DBG1_FADE_DONE,
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IRQ_WDMA_DBG2_FADE_DONE,
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IRQ_WDMA_DBG3_FADE_DONE,
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IRQ_WDMA_DBG4_FADE_DONE,
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IRQ_WDMA_DBG5_FADE_DONE,
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IRQ_UAIF0_SPEAKER,
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|
IRQ_UAIF0_MIC,
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|
IRQ_UAIF1_SPEAKER,
|
|
IRQ_UAIF1_MIC,
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|
IRQ_UAIF2_SPEAKER,
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|
IRQ_UAIF2_MIC,
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|
IRQ_UAIF3_SPEAKER,
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IRQ_UAIF3_MIC,
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IRQ_UAIF4_SPEAKER,
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IRQ_UAIF4_MIC,
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IRQ_UAIF5_SPEAKER,
|
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IRQ_UAIF5_MIC,
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|
IRQ_UAIF6_SPEAKER,
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|
IRQ_UAIF6_MIC,
|
|
IRQ_DSIF_OVERFLOW,
|
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IRQ_WDT,
|
|
IRQ_RDMA0_ERR,
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|
IRQ_RDMA1_ERR,
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|
IRQ_RDMA2_ERR,
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|
IRQ_RDMA3_ERR,
|
|
IRQ_RDMA4_ERR,
|
|
IRQ_RDMA5_ERR,
|
|
IRQ_RDMA6_ERR,
|
|
IRQ_RDMA7_ERR,
|
|
IRQ_RDMA8_ERR,
|
|
IRQ_RDMA9_ERR,
|
|
IRQ_RDMA10_ERR,
|
|
IRQ_RDMA11_ERR,
|
|
IRQ_WDMA0_ERR,
|
|
IRQ_WDMA1_ERR,
|
|
IRQ_WDMA2_ERR,
|
|
IRQ_WDMA3_ERR,
|
|
IRQ_WDMA4_ERR,
|
|
IRQ_WDMA0_DUAL_ERR,
|
|
IRQ_WDMA1_DUAL_ERR,
|
|
IRQ_WDMA2_DUAL_ERR,
|
|
IRQ_WDMA3_DUAL_ERR,
|
|
IRQ_WDMA4_DUAL_ERR,
|
|
IRQ_WDMA_DBG0_ERR,
|
|
IRQ_WDMA_DBG1_ERR,
|
|
IRQ_WDMA_DBG2_ERR,
|
|
IRQ_WDMA_DBG3_ERR,
|
|
IRQ_WDMA_DBG4_ERR,
|
|
IRQ_WDMA_DBG5_ERR,
|
|
IRQ_CA32_AXIERR,
|
|
IRQ_CA32_PMUIRQ_0,
|
|
IRQ_CA32_PMUIRQ_1,
|
|
IRQ_USB1_INTR_IN,
|
|
IRQ_USB2_INTR_IN,
|
|
IRQ_USB3_INTR_IN,
|
|
IRQ_USB4_INTR_IN,
|
|
IRQ_GPIO_INTR_IN,
|
|
IRQ_MBOX_VTS_INTR_IN,
|
|
IRQ_RESERVED0,
|
|
IRQ_INTR_UAIF0_HOLD,
|
|
IRQ_INTR_UAIF0_RESUME,
|
|
IRQ_INTR_UAIF1_HOLD,
|
|
IRQ_INTR_UAIF1_RESUME,
|
|
IRQ_INTR_UAIF2_HOLD,
|
|
IRQ_INTR_UAIF2_RESUME,
|
|
IRQ_INTR_UAIF3_HOLD,
|
|
IRQ_INTR_UAIF3_RESUME,
|
|
IRQ_INTR_UAIF4_HOLD,
|
|
IRQ_INTR_UAIF4_RESUME,
|
|
IRQ_INTR_UAIF5_HOLD,
|
|
IRQ_INTR_UAIF5_RESUME,
|
|
IRQ_INTR_UAIF6_HOLD,
|
|
IRQ_INTR_UAIF6_RESUME,
|
|
IRQ_INTR_SIFM_FADE_DONE,
|
|
IRQ_BT_INTR_IN,
|
|
IRQ_AUDEN_RDMA0_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA1_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA2_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA3_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA4_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA5_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA6_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA7_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA8_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA9_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA10_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA11_BUF_EMPTY,
|
|
IRQ_AUDEN_RDMA0_FADE_DONE,
|
|
IRQ_AUDEN_RDMA1_FADE_DONE,
|
|
IRQ_AUDEN_RDMA2_FADE_DONE,
|
|
IRQ_AUDEN_RDMA3_FADE_DONE,
|
|
IRQ_AUDEN_RDMA4_FADE_DONE,
|
|
IRQ_AUDEN_RDMA5_FADE_DONE,
|
|
IRQ_AUDEN_RDMA6_FADE_DONE,
|
|
IRQ_AUDEN_RDMA7_FADE_DONE,
|
|
IRQ_AUDEN_RDMA8_FADE_DONE,
|
|
IRQ_AUDEN_RDMA9_FADE_DONE,
|
|
IRQ_AUDEN_RDMA10_FADE_DONE,
|
|
IRQ_AUDEN_RDMA11_FADE_DONE,
|
|
IRQ_AUDEN_WDMA0_BUF_FULL,
|
|
IRQ_AUDEN_WDMA1_BUF_FULL,
|
|
IRQ_AUDEN_WDMA2_BUF_FULL,
|
|
IRQ_AUDEN_WDMA3_BUF_FULL,
|
|
IRQ_AUDEN_WDMA4_BUF_FULL,
|
|
IRQ_AUDEN_WDMA5_BUF_FULL,
|
|
IRQ_AUDEN_WDMA6_BUF_FULL,
|
|
IRQ_AUDEN_WDMA7_BUF_FULL,
|
|
IRQ_AUDEN_WDMA0_FADE_DONE,
|
|
IRQ_AUDEN_WDMA1_FADE_DONE,
|
|
IRQ_AUDEN_WDMA2_FADE_DONE,
|
|
IRQ_AUDEN_WDMA3_FADE_DONE,
|
|
IRQ_AUDEN_WDMA4_FADE_DONE,
|
|
IRQ_AUDEN_WDMA5_FADE_DONE,
|
|
IRQ_AUDEN_WDMA6_FADE_DONE,
|
|
IRQ_AUDEN_WDMA7_FADE_DONE,
|
|
IRQ_AUDEN_RDMA0_ERR,
|
|
IRQ_AUDEN_RDMA1_ERR,
|
|
IRQ_AUDEN_RDMA2_ERR,
|
|
IRQ_AUDEN_RDMA3_ERR,
|
|
IRQ_AUDEN_RDMA4_ERR,
|
|
IRQ_AUDEN_RDMA5_ERR,
|
|
IRQ_AUDEN_RDMA6_ERR,
|
|
IRQ_AUDEN_RDMA7_ERR,
|
|
IRQ_AUDEN_RDMA8_ERR,
|
|
IRQ_AUDEN_RDMA9_ERR,
|
|
IRQ_AUDEN_RDMA10_ERR,
|
|
IRQ_AUDEN_RDMA11_ERR,
|
|
IRQ_AUDEN_WDMA0_ERR,
|
|
IRQ_AUDEN_WDMA1_ERR,
|
|
IRQ_AUDEN_WDMA2_ERR,
|
|
IRQ_AUDEN_WDMA3_ERR,
|
|
IRQ_AUDEN_WDMA4_ERR,
|
|
IRQ_AUDEN_WDMA5_ERR,
|
|
IRQ_AUDEN_WDMA6_ERR,
|
|
IRQ_AUDEN_WDMA7_ERR,
|
|
IRQ_CP_INTR_IN,
|
|
IRQ_SW_INTR_MST_SYNC,
|
|
IRQ_COUNT,
|
|
};
|
|
#else
|
|
#error "irq table isn't defined"
|
|
#endif
|
|
|
|
#endif /* __SND_SOC_ABOX_SOC_3_H */
|