1246 lines
103 KiB
C
Executable file
1246 lines
103 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Exynos2100 SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <soc/samsung/cal-if.h>
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#include <dt-bindings/clock/exynos2100.h>
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#include "../../soc/samsung/cal-if/exynos2100/cmucal-vclk.h"
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#include "../../soc/samsung/cal-if/exynos2100/cmucal-node.h"
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#include "../../soc/samsung/cal-if/exynos2100/cmucal-qch.h"
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#include "../../soc/samsung/cal-if/exynos2100/clkout_exynos2100.h"
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#include "composite.h"
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static struct samsung_clk_provider *exynos2100_clk_provider;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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/* fixed rate clocks generated outside the soc */
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struct samsung_fixed_rate exynos2100_fixed_rate_ext_clks[] = {
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FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
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};
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/* HWACG VCLK */
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struct init_vclk exynos2100_alive_hwacg_vclks[] = {
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HWACG_VCLK(GATE_ALIVE_CMU_ALIVE_QCH, ALIVE_CMU_ALIVE_QCH, "GATE_ALIVE_CMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_PMU_ALIVE_QCH, APBIF_PMU_ALIVE_QCH, "GATE_APBIF_PMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_RTC_QCH, APBIF_RTC_QCH, "GATE_APBIF_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2AP_QCH, APBIF_SYSREG_VGPIO2AP_QCH, "GATE_APBIF_SYSREG_VGPIO2AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2APM_QCH, APBIF_SYSREG_VGPIO2APM_QCH, "GATE_APBIF_SYSREG_VGPIO2APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2PMU_QCH, APBIF_SYSREG_VGPIO2PMU_QCH, "GATE_APBIF_SYSREG_VGPIO2PMU_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_TOP_RTC_QCH, APBIF_TOP_RTC_QCH, "GATE_APBIF_TOP_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CLKMON_QCH, CLKMON_QCH, "GATE_CLKMON_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DBGCORE_UART_QCH, DBGCORE_UART_QCH, "GATE_DBGCORE_UART_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DOUBLE_IP_BATCHER_QCH_APM, DOUBLE_IP_BATCHER_QCH_APM, "GATE_DOUBLE_IP_BATCHER_QCH_APM", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DOUBLE_IP_BATCHER_QCH_CPU, DOUBLE_IP_BATCHER_QCH_CPU, "GATE_DOUBLE_IP_BATCHER_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DOUBLE_IP_BATCHER_QCH_SEMA, DOUBLE_IP_BATCHER_QCH_SEMA, "GATE_DOUBLE_IP_BATCHER_QCH_SEMA", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DTZPC_ALIVE_QCH, DTZPC_ALIVE_QCH, "GATE_DTZPC_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GPIO_ALIVE_QCH, GPIO_ALIVE_QCH, "GATE_GPIO_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_QCH_GREBE", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH, HW_SCANDUMP_CLKSTOP_CTRL_QCH, "GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_I3C_PMIC_QCH_P, I3C_PMIC_QCH_P, "GATE_I3C_PMIC_QCH_P", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_I3C_PMIC_QCH_S, I3C_PMIC_QCH_S, "GATE_I3C_PMIC_QCH_S", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_INTMEM_QCH, INTMEM_QCH, "GATE_INTMEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_AP_QCH, MAILBOX_APM_AP_QCH, "GATE_MAILBOX_APM_AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_CP_QCH, MAILBOX_APM_CP_QCH, "GATE_MAILBOX_APM_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_QCH, MAILBOX_AP_CP_QCH, "GATE_MAILBOX_AP_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_S_QCH, MAILBOX_AP_CP_S_QCH, "GATE_MAILBOX_AP_CP_S_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_DBGCORE_QCH, MAILBOX_AP_DBGCORE_QCH, "GATE_MAILBOX_AP_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PEM_QCH, PEM_QCH, "GATE_PEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PMU_INTR_GEN_QCH, PMU_INTR_GEN_QCH, "GATE_PMU_INTR_GEN_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ROM_CRC32_HOST_QCH, ROM_CRC32_HOST_QCH, "GATE_ROM_CRC32_HOST_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_QCH, "GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, "GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SS_DBGCORE_QCH_GREBE, SS_DBGCORE_QCH_GREBE, "GATE_SS_DBGCORE_QCH_GREBE", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SS_DBGCORE_QCH_DBG, SS_DBGCORE_QCH_DBG, "GATE_SS_DBGCORE_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SWEEPER_P_ALIVE_QCH, SWEEPER_P_ALIVE_QCH, "GATE_SWEEPER_P_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_ALIVE_QCH, SYSREG_ALIVE_QCH, "GATE_SYSREG_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_LITE_ALIVE_QCH, VGEN_LITE_ALIVE_QCH, "GATE_VGEN_LITE_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_WDT_ALIVE_QCH, WDT_ALIVE_QCH, "GATE_WDT_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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struct init_vclk exynos2100_aud_hwacg_vclks[] = {
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HWACG_VCLK(UMUX_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, "UMUX_CLK_AUD_UAIF6", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CP_PCMC_CLK, MUX_CP_PCMC_CLK_USER, "UMUX_CP_PCMC_CLK", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLK_AUD_PCMC, MUX_CLK_AUD_PCMC, "UMUX_CLK_AUD_PCMC", NULL, 0, 0, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_QCH_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_QCH_BCLK0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_QCH_BCLK1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_QCH_BCLK2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_QCH_BCLK3", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK4, ABOX_QCH_BCLK4, "GATE_ABOX_QCH_BCLK4", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CNT, ABOX_QCH_CNT, "GATE_ABOX_QCH_CNT", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK5, ABOX_QCH_BCLK5, "GATE_ABOX_QCH_BCLK5", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CCLK_ASB, ABOX_QCH_CCLK_ASB, "GATE_ABOX_QCH_CCLK_ASB", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_SCLK, ABOX_QCH_SCLK, "GATE_ABOX_QCH_SCLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK6, ABOX_QCH_BCLK6, "GATE_ABOX_QCH_BCLK6", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK, ABOX_QCH_XCLK, "GATE_ABOX_QCH_XCLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_PCMC_CLK, ABOX_QCH_PCMC_CLK, "GATE_ABOX_QCH_PCMC_CLK", "UMUX_CP_PCMC_CLK", 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_AUD_CMU_AUD_QCH, AUD_CMU_AUD_QCH, "GATE_AUD_CMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BAAW_D_AUDVTS_QCH, BAAW_D_AUDVTS_QCH, "GATE_BAAW_D_AUDVTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_AUD_QCH, D_TZPC_AUD_QCH, "GATE_D_TZPC_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD0_QCH, MAILBOX_AUD0_QCH, "GATE_MAILBOX_AUD0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD1_QCH, MAILBOX_AUD1_QCH, "GATE_MAILBOX_AUD1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD2_QCH, MAILBOX_AUD2_QCH, "GATE_MAILBOX_AUD2_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD3_QCH, MAILBOX_AUD3_QCH, "GATE_MAILBOX_AUD3_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PPMU_AUD_QCH, PPMU_AUD_QCH, "GATE_PPMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SMMU_AUD_QCH_S1, SMMU_AUD_QCH_S1, "GATE_SMMU_AUD_QCH_S1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SMMU_AUD_QCH_S2, SMMU_AUD_QCH_S2, "GATE_SMMU_AUD_QCH_S2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_AUD_QCH, SYSREG_AUD_QCH, "GATE_SYSREG_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_AUD_QCH, TREX_AUD_QCH, "GATE_TREX_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_LITE_AUD_QCH, VGEN_LITE_AUD_QCH, "GATE_VGEN_LITE_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_WDT_AUD_QCH, WDT_AUD_QCH, "GATE_WDT_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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struct init_vclk exynos2100_bus0_hwacg_vclks[] = {
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HWACG_VCLK(GATE_ASYNCSFR_WR_SMC_QCH, ASYNCSFR_WR_SMC_QCH, "GATE_ASYNCSFR_WR_SMC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BAAW_P_VPC_QCH, BAAW_P_VPC_QCH, "GATE_BAAW_P_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BUS0_CMU_BUS0_QCH, BUS0_CMU_BUS0_QCH, "GATE_BUS0_CMU_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BUSIF_CMUTOPC_QCH, BUSIF_CMUTOPC_QCH, "GATE_BUSIF_CMUTOPC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CACHEAID_BUS0_QCH, CACHEAID_BUS0_QCH, "GATE_CACHEAID_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CMU_BUS0_CMUREF_QCH, CMU_BUS0_CMUREF_QCH, "GATE_CMU_BUS0_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_BUS0_QCH, D_TZPC_BUS0_QCH, "GATE_D_TZPC_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_BUS0_QCH, SYSREG_BUS0_QCH, "GATE_SYSREG_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_D0_BUS0_QCH, TREX_D0_BUS0_QCH, "GATE_TREX_D0_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_D1_BUS0_QCH, TREX_D1_BUS0_QCH, "GATE_TREX_D1_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_P_BUS0_QCH, TREX_P_BUS0_QCH, "GATE_TREX_P_BUS0_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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struct init_vclk exynos2100_bus1_hwacg_vclks[] = {
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HWACG_VCLK(UMUX_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS_USER, "UMUX_CLKCMU_BUS1_BUS", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BAAW_P_VTS_QCH, BAAW_P_VTS_QCH, "GATE_BAAW_P_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BUS1_CMU_BUS1_QCH, BUS1_CMU_BUS1_QCH, "GATE_BUS1_CMU_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CMU_BUS1_CMUREF_QCH, CMU_BUS1_CMUREF_QCH, "GATE_CMU_BUS1_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DIT_QCH, DIT_QCH, "GATE_DIT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_BUS1_QCH, D_TZPC_BUS1_QCH, "GATE_D_TZPC_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PDMA_QCH, PDMA_QCH, "GATE_PDMA_QCH", "UMUX_CLKCMU_BUS1_BUS", 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_QE_PDMA_QCH, QE_PDMA_QCH, "GATE_QE_PDMA_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_QE_SPDMA_QCH, QE_SPDMA_QCH, "GATE_QE_SPDMA_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SBIC_QCH, SBIC_QCH, "GATE_SBIC_QCH", "UMUX_CLKCMU_BUS1_BUS", 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SPDMA_QCH, SPDMA_QCH, "GATE_SPDMA_QCH", "UMUX_CLKCMU_BUS1_BUS", 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSMMU_S2_ACVPS_QCH, SYSMMU_S2_ACVPS_QCH, "GATE_SYSMMU_S2_ACVPS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSMMU_S2_DIT_QCH, SYSMMU_S2_DIT_QCH, "GATE_SYSMMU_S2_DIT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSMMU_S2_SBIC_QCH, SYSMMU_S2_SBIC_QCH, "GATE_SYSMMU_S2_SBIC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_BUS1_QCH, SYSREG_BUS1_QCH, "GATE_SYSREG_BUS1_QCH", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_D_BUS1_QCH, TREX_D_BUS1_QCH, "GATE_TREX_D_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_P_BUS1_QCH, TREX_P_BUS1_QCH, "GATE_TREX_P_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_RB_BUS1_QCH, TREX_RB_BUS1_QCH, "GATE_TREX_RB_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_LITE_BUS1_QCH, VGEN_LITE_BUS1_QCH, "GATE_VGEN_LITE_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_PDMA_QCH, VGEN_PDMA_QCH, "GATE_VGEN_PDMA_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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struct init_vclk exynos2100_bus2_hwacg_vclks[] = {
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HWACG_VCLK(GATE_BUS2_CMU_BUS2_QCH, BUS2_CMU_BUS2_QCH, "GATE_BUS2_CMU_BUS2_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CMU_BUS2_CMUREF_QCH, CMU_BUS2_CMUREF_QCH, "GATE_CMU_BUS2_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_BUS2_QCH, D_TZPC_BUS2_QCH, "GATE_D_TZPC_BUS2_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_BUS2_QCH, SYSREG_BUS2_QCH, "GATE_SYSREG_BUS2_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TREX_D_BUS2_QCH, TREX_D_BUS2_QCH, "GATE_TREX_D_BUS2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_P_BUS2_QCH, TREX_P_BUS2_QCH, "GATE_TREX_P_BUS2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_cmgp_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_CMGP_BUS, MUX_CLKCMU_CMGP_BUS_USER, "UMUX_CLKCMU_CMGP_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_CMGP_PERI, MUX_CLKCMU_CMGP_PERI_USER, "UMUX_CLKCMU_CMGP_PERI", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_CMGP_ADC, MUX_CLKCMU_CMGP_ADC_USER, "UMUX_CLKCMU_CMGP_ADC", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADC_CMGP_QCH_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_QCH_S0", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADC_CMGP_QCH_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_QCH_S1", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADC_CMGP_QCH_OSC, ADC_CMGP_QCH_OSC, "GATE_ADC_CMGP_QCH_OSC", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_APBIF_GPIO_CMGP_QCH, APBIF_GPIO_CMGP_QCH, "GATE_APBIF_GPIO_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMGP_CMU_CMGP_QCH, CMGP_CMU_CMGP_QCH, "GATE_CMGP_CMU_CMGP_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CMGP_QCH, D_TZPC_CMGP_QCH, "GATE_D_TZPC_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_CMGP_QCH, GPIO_CMGP_QCH, "GATE_GPIO_CMGP_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP0_QCH, I2C_CMGP0_QCH, "GATE_I2C_CMGP0_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP1_QCH, I2C_CMGP1_QCH, "GATE_I2C_CMGP1_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP2_QCH, I2C_CMGP2_QCH, "GATE_I2C_CMGP2_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP3_QCH, I2C_CMGP3_QCH, "GATE_I2C_CMGP3_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_P, I3C_CMGP_QCH_P, "GATE_I3C_CMGP_QCH_P", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_S, I3C_CMGP_QCH_S, "GATE_I3C_CMGP_QCH_S", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP_QCH, SYSREG_CMGP_QCH, "GATE_SYSREG_CMGP_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2APM_QCH, SYSREG_CMGP2APM_QCH, "GATE_SYSREG_CMGP2APM_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2CP_QCH, SYSREG_CMGP2CP_QCH, "GATE_SYSREG_CMGP2CP_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2PMU_AP_QCH, SYSREG_CMGP2PMU_AP_QCH, "GATE_SYSREG_CMGP2PMU_AP_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP0_QCH, USI_CMGP0_QCH, "GATE_USI_CMGP0_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP1_QCH, USI_CMGP1_QCH, "GATE_USI_CMGP1_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP2_QCH, USI_CMGP2_QCH, "GATE_USI_CMGP2_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP3_QCH, USI_CMGP3_QCH, "GATE_USI_CMGP3_QCH", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_top_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK0, DFTMUX_CMU_QCH_CIS_CLK0, "GATE_DFTMUX_CMU_QCH_CIS_CLK0", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK1, DFTMUX_CMU_QCH_CIS_CLK1, "GATE_DFTMUX_CMU_QCH_CIS_CLK1", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK2, DFTMUX_CMU_QCH_CIS_CLK2, "GATE_DFTMUX_CMU_QCH_CIS_CLK2", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK3, DFTMUX_CMU_QCH_CIS_CLK3, "GATE_DFTMUX_CMU_QCH_CIS_CLK3", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK4, DFTMUX_CMU_QCH_CIS_CLK4, "GATE_DFTMUX_CMU_QCH_CIS_CLK4", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK5, DFTMUX_CMU_QCH_CIS_CLK5, "GATE_DFTMUX_CMU_QCH_CIS_CLK5", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_core_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_TREX_D_CORE_QCH, TREX_D_CORE_QCH, "GATE_TREX_D_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_P0_CORE_QCH, TREX_P0_CORE_QCH, "GATE_TREX_P0_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_P1_CORE_QCH, TREX_P1_CORE_QCH, "GATE_TREX_P1_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_csis_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_CSIS_CSIS, MUX_CLKCMU_CSIS_CSIS_USER, "UMUX_CLKCMU_CSIS_CSIS", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_CSIS_PDP, MUX_CLKCMU_CSIS_PDP_USER, "UMUX_CLKCMU_CSIS_PDP", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_CSISX6_QCH_VOTF0, CSISX6_QCH_VOTF0, "GATE_CSISX6_QCH_VOTF0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSISX6_QCH_DMA, CSISX6_QCH_DMA, "GATE_CSISX6_QCH_DMA", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSISX6_QCH_MCB, CSISX6_QCH_MCB, "GATE_CSISX6_QCH_MCB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSISX6_QCH_VOTF1, CSISX6_QCH_VOTF1, "GATE_CSISX6_QCH_VOTF1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_CMU_CSIS_QCH, CSIS_CMU_CSIS_QCH, "GATE_CSIS_CMU_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CSIS_QCH, D_TZPC_CSIS_QCH, "GATE_D_TZPC_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0, MIPI_PHY_LINK_WRAP_QCH_CSIS0, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1, MIPI_PHY_LINK_WRAP_QCH_CSIS1, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2, MIPI_PHY_LINK_WRAP_QCH_CSIS2, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3, MIPI_PHY_LINK_WRAP_QCH_CSIS3, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4, MIPI_PHY_LINK_WRAP_QCH_CSIS4, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5, MIPI_PHY_LINK_WRAP_QCH_CSIS5, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5", "UMUX_CLKCMU_CSIS_CSIS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OIS_MCU_TOP_QCH, OIS_MCU_TOP_QCH, "GATE_OIS_MCU_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDP_TOP_QCH_PDP_TOP, PDP_TOP_QCH_PDP_TOP, "GATE_PDP_TOP_QCH_PDP_TOP", "UMUX_CLKCMU_CSIS_PDP", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDP_TOP_QCH_C2_PDP, PDP_TOP_QCH_C2_PDP, "GATE_PDP_TOP_QCH_C2_PDP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_QCH, PPMU_D0_QCH, "GATE_PPMU_D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_QCH, PPMU_D1_QCH, "GATE_PPMU_D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D2_QCH, PPMU_D2_QCH, "GATE_PPMU_D2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D3_QCH, PPMU_D3_QCH, "GATE_PPMU_D3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA0_QCH, QE_CSIS_DMA0_QCH, "GATE_QE_CSIS_DMA0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA1_QCH, QE_CSIS_DMA1_QCH, "GATE_QE_CSIS_DMA1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA2_QCH, QE_CSIS_DMA2_QCH, "GATE_QE_CSIS_DMA2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA3_QCH, QE_CSIS_DMA3_QCH, "GATE_QE_CSIS_DMA3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_AF1_QCH, QE_PDP_AF1_QCH, "GATE_QE_PDP_AF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_AF2_QCH, QE_PDP_AF2_QCH, "GATE_QE_PDP_AF2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG0_QCH, QE_PDP_STAT_IMG0_QCH, "GATE_QE_PDP_STAT_IMG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG1_QCH, QE_PDP_STAT_IMG1_QCH, "GATE_QE_PDP_STAT_IMG1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG2_QCH, QE_PDP_STAT_IMG2_QCH, "GATE_QE_PDP_STAT_IMG2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP0_QCH, QE_STRP0_QCH, "GATE_QE_STRP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP1_QCH, QE_STRP1_QCH, "GATE_QE_STRP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP2_QCH, QE_STRP2_QCH, "GATE_QE_STRP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP3_QCH, QE_STRP3_QCH, "GATE_QE_STRP3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL0_QCH, QE_ZSL0_QCH, "GATE_QE_ZSL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL1_QCH, QE_ZSL1_QCH, "GATE_QE_ZSL1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL2_QCH, QE_ZSL2_QCH, "GATE_QE_ZSL2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL3_QCH, QE_ZSL3_QCH, "GATE_QE_ZSL3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH, RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_CSIS_QCH_S1, SYSMMU_D0_CSIS_QCH_S1, "GATE_SYSMMU_D0_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_CSIS_QCH_S2, SYSMMU_D0_CSIS_QCH_S2, "GATE_SYSMMU_D0_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_CSIS_QCH_S1, SYSMMU_D1_CSIS_QCH_S1, "GATE_SYSMMU_D1_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_CSIS_QCH_S2, SYSMMU_D1_CSIS_QCH_S2, "GATE_SYSMMU_D1_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_CSIS_QCH_S1, SYSMMU_D2_CSIS_QCH_S1, "GATE_SYSMMU_D2_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_CSIS_QCH_S2, SYSMMU_D2_CSIS_QCH_S2, "GATE_SYSMMU_D2_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_CSIS_QCH_S1, SYSMMU_D3_CSIS_QCH_S1, "GATE_SYSMMU_D3_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_CSIS_QCH_S2, SYSMMU_D3_CSIS_QCH_S2, "GATE_SYSMMU_D3_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CSIS_QCH, SYSREG_CSIS_QCH, "GATE_SYSREG_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_QCH, VGEN_LITE_D0_QCH, "GATE_VGEN_LITE_D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_QCH, VGEN_LITE_D1_QCH, "GATE_VGEN_LITE_D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D2_QCH, VGEN_LITE_D2_QCH, "GATE_VGEN_LITE_D2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_dns_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_DNS_BUS, MUX_CLKCMU_DNS_BUS_USER, "UMUX_CLKCMU_DNS_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_DNS_QCH, DNS_QCH, "GATE_DNS_QCH", "UMUX_CLKCMU_DNS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DNS_QCH_VOTF0, DNS_QCH_VOTF0, "GATE_DNS_QCH_VOTF0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DNS_QCH_VOTF1, DNS_QCH_VOTF1, "GATE_DNS_QCH_VOTF1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DNS_QCH_VOTF2, DNS_QCH_VOTF2, "GATE_DNS_QCH_VOTF2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DNS_CMU_DNS_QCH, DNS_CMU_DNS_QCH, "GATE_DNS_CMU_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DNS_QCH, D_TZPC_DNS_QCH, "GATE_D_TZPC_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_DNS_QCH, PPMU_D0_DNS_QCH, "GATE_PPMU_D0_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_DNS_QCH, PPMU_D1_DNS_QCH, "GATE_PPMU_D1_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_DNS_QCH_S2, SYSMMU_D0_DNS_QCH_S2, "GATE_SYSMMU_D0_DNS_QCH_S2", "UMUX_CLKCMU_DNS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_DNS_QCH_S1, SYSMMU_D0_DNS_QCH_S1, "GATE_SYSMMU_D0_DNS_QCH_S1", "UMUX_CLKCMU_DNS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_DNS_QCH_S2, SYSMMU_D1_DNS_QCH_S2, "GATE_SYSMMU_D1_DNS_QCH_S2", "UMUX_CLKCMU_DNS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_DNS_QCH_S1, SYSMMU_D1_DNS_QCH_S1, "GATE_SYSMMU_D1_DNS_QCH_S1", "UMUX_CLKCMU_DNS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DNS_QCH, SYSREG_DNS_QCH, "GATE_SYSREG_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_DNS_QCH, VGEN_LITE_D0_DNS_QCH, "GATE_VGEN_LITE_D0_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_DNS_QCH, VGEN_LITE_D1_DNS_QCH, "GATE_VGEN_LITE_D1_DNS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_dpub_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_DPUB_BUS_USER, MUX_CLKCMU_DPUB_BUS_USER, "UMUX_CLKCMU_DPUB_BUS_USER", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_DPUB_QCH, DPUB_QCH, "GATE_DPUB_QCH", "UMUX_CLKCMU_DPUB_BUS_USER", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUB_CMU_DPUB_QCH, DPUB_CMU_DPUB_QCH, "GATE_DPUB_CMU_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUB_QCH, D_TZPC_DPUB_QCH, "GATE_D_TZPC_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUB_QCH, SYSREG_DPUB_QCH, "GATE_SYSREG_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_dpuf0_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_DPUF0_QCH_DMA, DPUF0_QCH_DMA, "GATE_DPUF0_QCH_DMA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF0_QCH_DPP, DPUF0_QCH_DPP, "GATE_DPUF0_QCH_DPP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF0_QCH_C2SERV, DPUF0_QCH_C2SERV, "GATE_DPUF0_QCH_C2SERV", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF0_CMU_DPUF0_QCH, DPUF0_CMU_DPUF0_QCH, "GATE_DPUF0_CMU_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUF0_QCH, D_TZPC_DPUF0_QCH, "GATE_D_TZPC_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF0D0_QCH, PPMU_DPUF0D0_QCH, "GATE_PPMU_DPUF0D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF0D1_QCH, PPMU_DPUF0D1_QCH, "GATE_PPMU_DPUF0D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D0_QCH_S1, SYSMMU_DPUF0D0_QCH_S1, "GATE_SYSMMU_DPUF0D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D0_QCH_S2, SYSMMU_DPUF0D0_QCH_S2, "GATE_SYSMMU_DPUF0D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D1_QCH_S1, SYSMMU_DPUF0D1_QCH_S1, "GATE_SYSMMU_DPUF0D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D1_QCH_S2, SYSMMU_DPUF0D1_QCH_S2, "GATE_SYSMMU_DPUF0D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUF0_QCH, SYSREG_DPUF0_QCH, "GATE_SYSREG_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_dpuf1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_DPUF1_QCH_DMA, DPUF1_QCH_DMA, "GATE_DPUF1_QCH_DMA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF1_QCH_DPP, DPUF1_QCH_DPP, "GATE_DPUF1_QCH_DPP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF1_QCH_C2SERV, DPUF1_QCH_C2SERV, "GATE_DPUF1_QCH_C2SERV", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF1_CMU_DPUF1_QCH, DPUF1_CMU_DPUF1_QCH, "GATE_DPUF1_CMU_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUF1_QCH, D_TZPC_DPUF1_QCH, "GATE_D_TZPC_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF1D0_QCH, PPMU_DPUF1D0_QCH, "GATE_PPMU_DPUF1D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF1D1_QCH, PPMU_DPUF1D1_QCH, "GATE_PPMU_DPUF1D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D0_QCH_S2, SYSMMU_DPUF1D0_QCH_S2, "GATE_SYSMMU_DPUF1D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D0_QCH_S1, SYSMMU_DPUF1D0_QCH_S1, "GATE_SYSMMU_DPUF1D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D1_QCH_S2, SYSMMU_DPUF1D1_QCH_S2, "GATE_SYSMMU_DPUF1D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D1_QCH_S1, SYSMMU_DPUF1D1_QCH_S1, "GATE_SYSMMU_DPUF1D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUF1_QCH, SYSREG_DPUF1_QCH, "GATE_SYSREG_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_dsu_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ACE_US_128TO256_D0_CLUSTER0_QCH, ACE_US_128TO256_D0_CLUSTER0_QCH, "GATE_ACE_US_128TO256_D0_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ACE_US_128TO256_D1_CLUSTER0_QCH, ACE_US_128TO256_D1_CLUSTER0_QCH, "GATE_ACE_US_128TO256_D1_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_STR_CPUCL0_3_QCH, BUSIF_STR_CPUCL0_3_QCH, "GATE_BUSIF_STR_CPUCL0_3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_SCLK, CLUSTER0_QCH_SCLK, "GATE_CLUSTER0_QCH_SCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_ATCLK, CLUSTER0_QCH_ATCLK, "GATE_CLUSTER0_QCH_ATCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PDBGCLK, CLUSTER0_QCH_PDBGCLK, "GATE_CLUSTER0_QCH_PDBGCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_GICCLK, CLUSTER0_QCH_GICCLK, "GATE_CLUSTER0_QCH_GICCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_DBG_PD, CLUSTER0_QCH_DBG_PD, "GATE_CLUSTER0_QCH_DBG_PD", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PCLK, CLUSTER0_QCH_PCLK, "GATE_CLUSTER0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PERIPHCLK, CLUSTER0_QCH_PERIPHCLK, "GATE_CLUSTER0_QCH_PERIPHCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_DSU_CMUREF_QCH, CMU_DSU_CMUREF_QCH, "GATE_CMU_DSU_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_DSU_SHORTSTOP_QCH, CMU_DSU_SHORTSTOP_QCH, "GATE_CMU_DSU_SHORTSTOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DSU_CMU_DSU_QCH, DSU_CMU_DSU_QCH, "GATE_DSU_CMU_DSU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DSU_QCH, HTU_DSU_QCH, "GATE_HTU_DSU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRET_CLUSTER0_0_QCH, PPC_INSTRRET_CLUSTER0_0_QCH, "GATE_PPC_INSTRRET_CLUSTER0_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRET_CLUSTER0_1_QCH, PPC_INSTRRET_CLUSTER0_1_QCH, "GATE_PPC_INSTRRET_CLUSTER0_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRUN_CLUSTER0_0_QCH, PPC_INSTRRUN_CLUSTER0_0_QCH, "GATE_PPC_INSTRRUN_CLUSTER0_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRUN_CLUSTER0_1_QCH, PPC_INSTRRUN_CLUSTER0_1_QCH, "GATE_PPC_INSTRRUN_CLUSTER0_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_g3d_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ADD_APBIF_G3D_QCH, ADD_APBIF_G3D_QCH, "GATE_ADD_APBIF_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADD_G3D_QCH, ADD_G3D_QCH, "GATE_ADD_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D0_G3D, ASB_G3D_QCH_LH_D0_G3D, "GATE_ASB_G3D_QCH_LH_D0_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D1_G3D, ASB_G3D_QCH_LH_D1_G3D, "GATE_ASB_G3D_QCH_LH_D1_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D2_G3D, ASB_G3D_QCH_LH_D2_G3D, "GATE_ASB_G3D_QCH_LH_D2_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D3_G3D, ASB_G3D_QCH_LH_D3_G3D, "GATE_ASB_G3D_QCH_LH_D3_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPMG3D_QCH, BUSIF_HPMG3D_QCH, "GATE_BUSIF_HPMG3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_STR_G3D_QCH, BUSIF_STR_G3D_QCH, "GATE_BUSIF_STR_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_STR_G3D_QCH_CORE, BUSIF_STR_G3D_QCH_CORE, "GATE_BUSIF_STR_G3D_QCH_CORE", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_G3D_QCH, D_TZPC_G3D_QCH, "GATE_D_TZPC_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_G3D_CMU_G3D_QCH, G3D_CMU_G3D_QCH, "GATE_G3D_CMU_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPU_QCH, GPU_QCH, "GATE_GPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_PCLK, HTU_G3D_QCH_PCLK, "GATE_HTU_G3D_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_CLK, HTU_G3D_QCH_CLK, "GATE_HTU_G3D_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_G3D_QCH, SYSREG_G3D_QCH, "GATE_SYSREG_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_G3D_QCH, VGEN_LITE_G3D_QCH, "GATE_VGEN_LITE_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_hsi0_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_BUS, MUX_CLKCMU_HSI0_BUS_USER, "UMUX_CLKCMU_HSI0_BUS", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_USB31DRD, MUX_CLKCMU_HSI0_USB31DRD_USER, "UMUX_CLKCMU_HSI0_USB31DRD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_USBDP_DEBUG, MUX_CLKCMU_HSI0_USBDP_DEBUG_USER, "UMUX_CLKCMU_HSI0_USBDP_DEBUG", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_DPGTC, MUX_CLKCMU_HSI0_DPGTC_USER, "UMUX_CLKCMU_HSI0_DPGTC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_DP_LINK_QCH_PCLK, DP_LINK_QCH_PCLK, "GATE_DP_LINK_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DP_LINK_QCH_GTC_CLK, DP_LINK_QCH_GTC_CLK, "GATE_DP_LINK_QCH_GTC_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_HSI0_QCH, D_TZPC_HSI0_QCH, "GATE_D_TZPC_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HSI0_CMU_HSI0_QCH, HSI0_CMU_HSI0_QCH, "GATE_HSI0_CMU_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_HSI0_BUS1_QCH, PPMU_HSI0_BUS1_QCH, "GATE_PPMU_HSI0_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_USB_QCH, SYSMMU_USB_QCH, "GATE_SYSMMU_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_HSI0_QCH, SYSREG_HSI0_QCH, "GATE_SYSREG_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_REF, USB31DRD_QCH_REF, "GATE_USB31DRD_QCH_REF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_SLV_CTRL, USB31DRD_QCH_SLV_CTRL, "GATE_USB31DRD_QCH_SLV_CTRL", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_SLV_LINK, USB31DRD_QCH_SLV_LINK, "GATE_USB31DRD_QCH_SLV_LINK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_APB, USB31DRD_QCH_APB, "GATE_USB31DRD_QCH_APB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_PCS, USB31DRD_QCH_PCS, "GATE_USB31DRD_QCH_PCS", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB31DRD_QCH_DBG, USB31DRD_QCH_DBG, "GATE_USB31DRD_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_HSI0_QCH, VGEN_LITE_HSI0_QCH, "GATE_VGEN_LITE_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_hsi1_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_BUS, MUX_CLKCMU_HSI1_BUS_USER, "UMUX_CLKCMU_HSI1_BUS", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_PCIE, MUX_CLKCMU_HSI1_PCIE_USER, "UMUX_CLKCMU_HSI1_PCIE", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_MMC_CARD, MUX_CLKCMU_HSI1_MMC_CARD_USER, "UMUX_CLKCMU_HSI1_MMC_CARD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_UFS_EMBD, MUX_CLKCMU_HSI1_UFS_EMBD_USER, "UMUX_CLKCMU_HSI1_UFS_EMBD", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_HSI1_QCH, D_TZPC_HSI1_QCH, "GATE_D_TZPC_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_HSI1_QCH, GPIO_HSI1_QCH, "GATE_GPIO_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HSI1_CMU_HSI1_QCH, HSI1_CMU_HSI1_QCH, "GATE_HSI1_CMU_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_MMC_CARD_QCH, MMC_CARD_QCH, "GATE_MMC_CARD_QCH", "UMUX_CLKCMU_HSI1_MMC_CARD", 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_MSTR, PCIE_GEN2_QCH_MSTR, "GATE_PCIE_GEN2_QCH_MSTR", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_PCS, PCIE_GEN2_QCH_PCS, "GATE_PCIE_GEN2_QCH_PCS", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_PHY, PCIE_GEN2_QCH_PHY, "GATE_PCIE_GEN2_QCH_PHY", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_DBI, PCIE_GEN2_QCH_DBI, "GATE_PCIE_GEN2_QCH_DBI", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_APB, PCIE_GEN2_QCH_APB, "GATE_PCIE_GEN2_QCH_APB", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_REF, PCIE_GEN2_QCH_REF, "GATE_PCIE_GEN2_QCH_REF", "UMUX_CLKCMU_HSI1_PCIE", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_APB, PCIE_GEN4_0_QCH_APB, "GATE_PCIE_GEN4_0_QCH_APB", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_DBI, PCIE_GEN4_0_QCH_DBI, "GATE_PCIE_GEN4_0_QCH_DBI", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_AXI, PCIE_GEN4_0_QCH_AXI, "GATE_PCIE_GEN4_0_QCH_AXI", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_PCS_APB, PCIE_GEN4_0_QCH_PCS_APB, "GATE_PCIE_GEN4_0_QCH_PCS_APB", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_REF, PCIE_GEN4_0_QCH_REF, "GATE_PCIE_GEN4_0_QCH_REF", "UMUX_CLKCMU_HSI1_PCIE", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_PMA_APB, PCIE_GEN4_0_QCH_PMA_APB, "GATE_PCIE_GEN4_0_QCH_PMA_APB", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN4_0_QCH_UDBG_APB, PCIE_GEN4_0_QCH_UDBG_APB, "GATE_PCIE_GEN4_0_QCH_UDBG_APB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_IA_GEN2_QCH, PCIE_IA_GEN2_QCH, "GATE_PCIE_IA_GEN2_QCH", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_IA_GEN4_0_QCH, PCIE_IA_GEN4_0_QCH, "GATE_PCIE_IA_GEN4_0_QCH", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_HSI1_QCH, PPMU_HSI1_QCH, "GATE_PPMU_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_HSI1_QCH, SYSMMU_HSI1_QCH, "GATE_SYSMMU_HSI1_QCH", "UMUX_CLKCMU_HSI1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_HSI1_QCH, SYSREG_HSI1_QCH, "GATE_SYSREG_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_HSI1_QCH, VGEN_LITE_HSI1_QCH, "GATE_VGEN_LITE_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", "UMUX_CLKCMU_HSI1_UFS_EMBD", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH, UFS_EMBD_QCH, "GATE_UFS_EMBD_QCH", "UMUX_CLKCMU_HSI1_UFS_EMBD", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_itp_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_ITP_BUS, MUX_CLKCMU_ITP_BUS_USER, "UMUX_CLKCMU_ITP_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_ITP_QCH, D_TZPC_ITP_QCH, "GATE_D_TZPC_ITP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ITP_QCH, ITP_QCH, "GATE_ITP_QCH", "UMUX_CLKCMU_ITP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ITP_CMU_ITP_QCH, ITP_CMU_ITP_QCH, "GATE_ITP_CMU_ITP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_ITP_QCH, SYSREG_ITP_QCH, "GATE_SYSREG_ITP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_lme_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_LME_BUS, MUX_CLKCMU_LME_BUS_USER, "UMUX_CLKCMU_LME_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_LME_QCH, D_TZPC_LME_QCH, "GATE_D_TZPC_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_QCH, LME_QCH, "GATE_LME_QCH", "UMUX_CLKCMU_LME_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_QCH_C2, LME_QCH_C2, "GATE_LME_QCH_C2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_CMU_LME_QCH, LME_CMU_LME_QCH, "GATE_LME_CMU_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_LME_QCH, PPMU_LME_QCH, "GATE_PPMU_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_LME_QCH_S2, SYSMMU_D_LME_QCH_S2, "GATE_SYSMMU_D_LME_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_LME_QCH_S1, SYSMMU_D_LME_QCH_S1, "GATE_SYSMMU_D_LME_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_LME_QCH, SYSREG_LME_QCH, "GATE_SYSREG_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_LME_QCH, VGEN_LITE_LME_QCH, "GATE_VGEN_LITE_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_m2m_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ASTC_QCH, ASTC_QCH, "GATE_ASTC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_M2M_QCH, D_TZPC_M2M_QCH, "GATE_D_TZPC_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_JPEG0_QCH, JPEG0_QCH, "GATE_JPEG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_JPEG1_QCH, JPEG1_QCH, "GATE_JPEG1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_JSQZ_QCH, JSQZ_QCH, "GATE_JSQZ_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH, M2M_QCH, "GATE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH_VOTF, M2M_QCH_VOTF, "GATE_M2M_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_CMU_M2M_QCH, M2M_CMU_M2M_QCH, "GATE_M2M_CMU_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D_M2M_QCH, PPMU_D_M2M_QCH, "GATE_PPMU_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ASTC_QCH, QE_ASTC_QCH, "GATE_QE_ASTC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JPEG0_QCH, QE_JPEG0_QCH, "GATE_QE_JPEG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JPEG1_QCH, QE_JPEG1_QCH, "GATE_QE_JPEG1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JSQZ_QCH, QE_JSQZ_QCH, "GATE_QE_JSQZ_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_M2M_QCH, QE_M2M_QCH, "GATE_QE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_QCH_S2, SYSMMU_D_M2M_QCH_S2, "GATE_SYSMMU_D_M2M_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_QCH_S1, SYSMMU_D_M2M_QCH_S1, "GATE_SYSMMU_D_M2M_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_M2M_QCH, SYSREG_M2M_QCH, "GATE_SYSREG_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_M2M_QCH, VGEN_LITE_M2M_QCH, "GATE_VGEN_LITE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mcfp0_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_MCFP0_BUS, MUX_CLKCMU_MCFP0_BUS_USER, "UMUX_CLKCMU_MCFP0_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MCFP0_QCH, D_TZPC_MCFP0_QCH, "GATE_D_TZPC_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP0_QCH, MCFP0_QCH, "GATE_MCFP0_QCH", "UMUX_CLKCMU_MCFP0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP0_CMU_MCFP0_QCH, MCFP0_CMU_MCFP0_QCH, "GATE_MCFP0_CMU_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_MCFP0_QCH, PPMU_D0_MCFP0_QCH, "GATE_PPMU_D0_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_MCFP0_QCH, PPMU_D1_MCFP0_QCH, "GATE_PPMU_D1_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D2_MCFP0_QCH, PPMU_D2_MCFP0_QCH, "GATE_PPMU_D2_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D3_MCFP0_QCH, PPMU_D3_MCFP0_QCH, "GATE_PPMU_D3_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D0_MCFP0_QCH, QE_D0_MCFP0_QCH, "GATE_QE_D0_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D1_MCFP0_QCH, QE_D1_MCFP0_QCH, "GATE_QE_D1_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D2_MCFP0_QCH, QE_D2_MCFP0_QCH, "GATE_QE_D2_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D3_MCFP0_QCH, QE_D3_MCFP0_QCH, "GATE_QE_D3_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCFP0_QCH_S1, SYSMMU_D0_MCFP0_QCH_S1, "GATE_SYSMMU_D0_MCFP0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCFP0_QCH_S2, SYSMMU_D0_MCFP0_QCH_S2, "GATE_SYSMMU_D0_MCFP0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCFP0_QCH_S1, SYSMMU_D1_MCFP0_QCH_S1, "GATE_SYSMMU_D1_MCFP0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCFP0_QCH_S2, SYSMMU_D1_MCFP0_QCH_S2, "GATE_SYSMMU_D1_MCFP0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCFP0_QCH_S1, SYSMMU_D2_MCFP0_QCH_S1, "GATE_SYSMMU_D2_MCFP0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCFP0_QCH_S2, SYSMMU_D2_MCFP0_QCH_S2, "GATE_SYSMMU_D2_MCFP0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_MCFP0_QCH_S1, SYSMMU_D3_MCFP0_QCH_S1, "GATE_SYSMMU_D3_MCFP0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_MCFP0_QCH_S2, SYSMMU_D3_MCFP0_QCH_S2, "GATE_SYSMMU_D3_MCFP0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCFP0_QCH, SYSREG_MCFP0_QCH, "GATE_SYSREG_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_MCFP0_QCH, VGEN_LITE_MCFP0_QCH, "GATE_VGEN_LITE_MCFP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mcfp1_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_MCFP1_MCFP1, MUX_CLKCMU_MCFP1_MCFP1_USER, "UMUX_CLKCMU_MCFP1_MCFP1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_MCFP1_ORBMCH, MUX_CLKCMU_MCFP1_ORBMCH_USER, "UMUX_CLKCMU_MCFP1_ORBMCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MCFP1_QCH, D_TZPC_MCFP1_QCH, "GATE_D_TZPC_MCFP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP1_QCH, MCFP1_QCH, "GATE_MCFP1_QCH", "UMUX_CLKCMU_MCFP1_MCFP1", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP1_CMU_MCFP1_QCH, MCFP1_CMU_MCFP1_QCH, "GATE_MCFP1_CMU_MCFP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH0_QCH_C2, ORBMCH0_QCH_C2, "GATE_ORBMCH0_QCH_C2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH0_QCH, ORBMCH0_QCH, "GATE_ORBMCH0_QCH", "UMUX_CLKCMU_MCFP1_ORBMCH", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH1_QCH_C2, ORBMCH1_QCH_C2, "GATE_ORBMCH1_QCH_C2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH1_QCH, ORBMCH1_QCH, "GATE_ORBMCH1_QCH", "UMUX_CLKCMU_MCFP1_ORBMCH", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_ORBMCH_QCH, PPMU_ORBMCH_QCH, "GATE_PPMU_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D0_ORBMCH_QCH, QE_D0_ORBMCH_QCH, "GATE_QE_D0_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D1_ORBMCH_QCH, QE_D1_ORBMCH_QCH, "GATE_QE_D1_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D2_ORBMCH_QCH, QE_D2_ORBMCH_QCH, "GATE_QE_D2_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D3_ORBMCH_QCH, QE_D3_ORBMCH_QCH, "GATE_QE_D3_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D4_ORBMCH_QCH, QE_D4_ORBMCH_QCH, "GATE_QE_D4_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D5_ORBMCH_QCH, QE_D5_ORBMCH_QCH, "GATE_QE_D5_ORBMCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_MCFP1_QCH_S2, SYSMMU_D_MCFP1_QCH_S2, "GATE_SYSMMU_D_MCFP1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_MCFP1_QCH_S1, SYSMMU_D_MCFP1_QCH_S1, "GATE_SYSMMU_D_MCFP1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCFP1_QCH, SYSREG_MCFP1_QCH, "GATE_SYSREG_MCFP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_MCFP1_QCH, VGEN_LITE_D0_MCFP1_QCH, "GATE_VGEN_LITE_D0_MCFP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_MCFP1_QCH, VGEN_LITE_D1_MCFP1_QCH, "GATE_VGEN_LITE_D1_MCFP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mcsc_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_MCSC_GDC, MUX_CLKCMU_MCSC_GDC_USER, "UMUX_CLKCMU_MCSC_GDC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_MCSC_BUS, MUX_CLKCMU_MCSC_BUS_USER, "UMUX_CLKCMU_MCSC_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_MCSC_QCH, ADD_MCSC_QCH, "GATE_ADD_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_MCSC_QCH, BUSIF_ADD_MCSC_QCH, "GATE_BUSIF_ADD_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_MCSC_QCH, BUSIF_HPM_MCSC_QCH, "GATE_BUSIF_HPM_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_MCSC_QCH, D_TZPC_MCSC_QCH, "GATE_D_TZPC_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GDC_QCH, GDC_QCH, "GATE_GDC_QCH", "UMUX_CLKCMU_MCSC_GDC", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GDC_QCH_C2_M, GDC_QCH_C2_M, "GATE_GDC_QCH_C2_M", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GDC_QCH_C2_S, GDC_QCH_C2_S, "GATE_GDC_QCH_C2_S", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH, MCSC_QCH, "GATE_MCSC_QCH", "UMUX_CLKCMU_MCSC_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH_C2_W, MCSC_QCH_C2_W, "GATE_MCSC_QCH_C2_W", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH_C2_R, MCSC_QCH_C2_R, "GATE_MCSC_QCH_C2_R", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_CMU_MCSC_QCH, MCSC_CMU_MCSC_QCH, "GATE_MCSC_CMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_MCSC_QCH, PPMU_D0_MCSC_QCH, "GATE_PPMU_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_MCSC_QCH, PPMU_D1_MCSC_QCH, "GATE_PPMU_D1_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D2_MCSC_QCH, PPMU_D2_MCSC_QCH, "GATE_PPMU_D2_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S1, SYSMMU_D0_MCSC_QCH_S1, "GATE_SYSMMU_D0_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S2, SYSMMU_D0_MCSC_QCH_S2, "GATE_SYSMMU_D0_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S1, SYSMMU_D1_MCSC_QCH_S1, "GATE_SYSMMU_D1_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S2, SYSMMU_D1_MCSC_QCH_S2, "GATE_SYSMMU_D1_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCSC_QCH_S1, SYSMMU_D2_MCSC_QCH_S1, "GATE_SYSMMU_D2_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCSC_QCH_S2, SYSMMU_D2_MCSC_QCH_S2, "GATE_SYSMMU_D2_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCSC_QCH, SYSREG_MCSC_QCH, "GATE_SYSREG_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_MCSC_QCH, VGEN_LITE_D0_MCSC_QCH, "GATE_VGEN_LITE_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_MCSC_QCH, VGEN_LITE_D1_MCSC_QCH, "GATE_VGEN_LITE_D1_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mfc0_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_MFC0_MFC0, MUX_CLKCMU_MFC0_MFC0_USER, "UMUX_CLKCMU_MFC0_MFC0", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_MFC0_WFD, MUX_CLKCMU_MFC0_WFD_USER, "UMUX_CLKCMU_MFC0_WFD", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MFC0_QCH, D_TZPC_MFC0_QCH, "GATE_D_TZPC_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ATB_MFC0_QCH_MI, LH_ATB_MFC0_QCH_MI, "GATE_LH_ATB_MFC0_QCH_MI", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ATB_MFC0_QCH_SI, LH_ATB_MFC0_QCH_SI, "GATE_LH_ATB_MFC0_QCH_SI", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_QCH, MFC0_QCH, "GATE_MFC0_QCH","UMUX_CLKCMU_MFC0_MFC0" , 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_QCH_VOTF, MFC0_QCH_VOTF, "GATE_MFC0_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_CMU_MFC0_QCH, MFC0_CMU_MFC0_QCH, "GATE_MFC0_CMU_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC0D0_QCH, PPMU_MFC0D0_QCH, "GATE_PPMU_MFC0D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC0D1_QCH, PPMU_MFC0D1_QCH, "GATE_PPMU_MFC0D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_WFD_QCH, PPMU_WFD_QCH, "GATE_PPMU_WFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D0_QCH_S1, SYSMMU_MFC0D0_QCH_S1, "GATE_SYSMMU_MFC0D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D0_QCH_S2, SYSMMU_MFC0D0_QCH_S2, "GATE_SYSMMU_MFC0D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D1_QCH_S1, SYSMMU_MFC0D1_QCH_S1, "GATE_SYSMMU_MFC0D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D1_QCH_S2, SYSMMU_MFC0D1_QCH_S2, "GATE_SYSMMU_MFC0D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MFC0_QCH, SYSREG_MFC0_QCH, "GATE_SYSREG_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_MFC0_QCH, VGEN_MFC0_QCH, "GATE_VGEN_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WFD_QCH, WFD_QCH, "GATE_WFD_QCH", "UMUX_CLKCMU_MFC0_WFD", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mfc1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ADM_APB_MFC0MFC1_QCH, ADM_APB_MFC0MFC1_QCH, "GATE_ADM_APB_MFC0MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_MFC1_QCH, D_TZPC_MFC1_QCH, "GATE_D_TZPC_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC1_QCH, MFC1_QCH, "GATE_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC1_CMU_MFC1_QCH, MFC1_CMU_MFC1_QCH, "GATE_MFC1_CMU_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC1D0_QCH, PPMU_MFC1D0_QCH, "GATE_PPMU_MFC1D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC1D1_QCH, PPMU_MFC1D1_QCH, "GATE_PPMU_MFC1D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D0_QCH_S2, SYSMMU_MFC1D0_QCH_S2, "GATE_SYSMMU_MFC1D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D0_QCH_S1, SYSMMU_MFC1D0_QCH_S1, "GATE_SYSMMU_MFC1D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D1_QCH_S2, SYSMMU_MFC1D1_QCH_S2, "GATE_SYSMMU_MFC1D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D1_QCH_S1, SYSMMU_MFC1D1_QCH_S1, "GATE_SYSMMU_MFC1D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MFC1_QCH, SYSREG_MFC1_QCH, "GATE_SYSREG_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_MFC1_QCH, VGEN_MFC1_QCH, "GATE_VGEN_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mif_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_MIF_DDRPHY2X, CLKMUX_MIF_DDRPHY2X, "UMUX_MIF_DDRPHY2X", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MIF_QCH, D_TZPC_MIF_QCH, "GATE_D_TZPC_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIF_CMU_MIF_QCH, MIF_CMU_MIF_QCH, "GATE_MIF_CMU_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QCH_ADAPTER_PPC_DEBUG_QCH, QCH_ADAPTER_PPC_DEBUG_QCH, "GATE_QCH_ADAPTER_PPC_DEBUG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MIF_QCH, SYSREG_MIF_QCH, "GATE_SYSREG_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NPU_BUS, MUX_CLKCMU_NPU_BUS_USER, "UMUX_CLKCMU_NPU_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_NPU_QCH, D_TZPC_NPU_QCH, "GATE_D_TZPC_NPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_PCLK, IP_NPUCORE_QCH_PCLK, "GATE_IP_NPUCORE_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_ACLK, IP_NPUCORE_QCH_ACLK, "GATE_IP_NPUCORE_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPU_CMU_NPU_QCH, NPU_CMU_NPU_QCH, "GATE_NPU_CMU_NPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPU_QCH, SYSREG_NPU_QCH, "GATE_SYSREG_NPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu01_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NPU01_BUS, MUX_CLKCMU_NPU01_BUS_USER, "UMUX_CLKCMU_NPU01_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_NPU01_QCH, D_TZPC_NPU01_QCH, "GATE_D_TZPC_NPU01_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPU01CORE_QCH_PCLK, IP_NPU01CORE_QCH_PCLK, "GATE_IP_NPU01CORE_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPU01CORE_QCH_ACLK, IP_NPU01CORE_QCH_ACLK, "GATE_IP_NPU01CORE_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPU01_CMU_NPU_QCH, NPU01_CMU_NPU_QCH, "GATE_NPU01_CMU_NPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPU01_QCH, SYSREG_NPU01_QCH, "GATE_SYSREG_NPU01_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu10_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NPU10_BUS, MUX_CLKCMU_NPU10_BUS_USER, "UMUX_CLKCMU_NPU10_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_NPU10_QCH, D_TZPC_NPU10_QCH, "GATE_D_TZPC_NPU10_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPU10CORE_QCH_PCLK, IP_NPU10CORE_QCH_PCLK, "GATE_IP_NPU10CORE_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPU10CORE_QCH_ACLK, IP_NPU10CORE_QCH_ACLK, "GATE_IP_NPU10CORE_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPU10_CMU_NPU_QCH, NPU10_CMU_NPU_QCH, "GATE_NPU10_CMU_NPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPU10_QCH, SYSREG_NPU10_QCH, "GATE_SYSREG_NPU10_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npus_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NPUS_BUS, MUX_CLKCMU_NPUS_BUS_USER, "UMUX_CLKCMU_NPUS_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_NPUS_QCH, ADD_NPUS_QCH, "GATE_ADD_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADM_DAP_NPUS_QCH, ADM_DAP_NPUS_QCH, "GATE_ADM_DAP_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_NPUS_QCH, BUSIF_ADD_NPUS_QCH, "GATE_BUSIF_ADD_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_NPUS_QCH, BUSIF_HPM_NPUS_QCH, "GATE_BUSIF_HPM_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_NPUS_QCH, D_TZPC_NPUS_QCH, "GATE_D_TZPC_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_NPUS_QCH_PCLK, HTU_NPUS_QCH_PCLK, "GATE_HTU_NPUS_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_NPUS_QCH_CLK, HTU_NPUS_QCH_CLK, "GATE_HTU_NPUS_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH, IP_NPUS_QCH, "GATE_IP_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_C2A0, IP_NPUS_QCH_C2A0, "GATE_IP_NPUS_QCH_C2A0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_CPU, IP_NPUS_QCH_CPU, "GATE_IP_NPUS_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_NEON, IP_NPUS_QCH_NEON, "GATE_IP_NPUS_QCH_NEON", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_C2A1, IP_NPUS_QCH_C2A1, "GATE_IP_NPUS_QCH_C2A1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPUS_CMU_NPUS_QCH, NPUS_CMU_NPUS_QCH, "GATE_NPUS_CMU_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_NPUS_0_QCH, PPMU_NPUS_0_QCH, "GATE_PPMU_NPUS_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_NPUS_1_QCH, PPMU_NPUS_1_QCH, "GATE_PPMU_NPUS_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_NPUS_2_QCH, PPMU_NPUS_2_QCH, "GATE_PPMU_NPUS_2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_NPUS_QCH_S2, SYSMMU_D0_NPUS_QCH_S2, "GATE_SYSMMU_D0_NPUS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_NPUS_QCH_S1, SYSMMU_D0_NPUS_QCH_S1, "GATE_SYSMMU_D0_NPUS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_NPUS_QCH_S2, SYSMMU_D1_NPUS_QCH_S2, "GATE_SYSMMU_D1_NPUS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_NPUS_QCH_S1, SYSMMU_D1_NPUS_QCH_S1, "GATE_SYSMMU_D1_NPUS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_NPUS_QCH_S2, SYSMMU_D2_NPUS_QCH_S2, "GATE_SYSMMU_D2_NPUS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_NPUS_QCH_S1, SYSMMU_D2_NPUS_QCH_S1, "GATE_SYSMMU_D2_NPUS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPUS_QCH, SYSREG_NPUS_QCH, "GATE_SYSREG_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_NPUS_QCH, VGEN_LITE_NPUS_QCH, "GATE_VGEN_LITE_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric0_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC0_QCH, D_TZPC_PERIC0_QCH, "GATE_D_TZPC_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC0_QCH, GPIO_PERIC0_QCH, "GATE_GPIO_PERIC0_QCH", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_CMU_PERIC0_QCH, PERIC0_CMU_PERIC0_QCH, "GATE_PERIC0_CMU_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_UART_DBG, PERIC0_TOP0_QCH_UART_DBG, "GATE_PERIC0_TOP0_QCH_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, "console-pclk0"),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI00_USI, PERIC0_TOP0_QCH_USI00_USI, "GATE_PERIC0_TOP0_QCH_USI00_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI00_I2C, PERIC0_TOP0_QCH_USI00_I2C, "GATE_PERIC0_TOP0_QCH_USI00_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI01_USI, PERIC0_TOP0_QCH_USI01_USI, "GATE_PERIC0_TOP0_QCH_USI01_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI01_I2C, PERIC0_TOP0_QCH_USI01_I2C, "GATE_PERIC0_TOP0_QCH_USI01_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI02_USI, PERIC0_TOP0_QCH_USI02_USI, "GATE_PERIC0_TOP0_QCH_USI02_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI02_I2C, PERIC0_TOP0_QCH_USI02_I2C, "GATE_PERIC0_TOP0_QCH_USI02_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI03_USI, PERIC0_TOP0_QCH_USI03_USI, "GATE_PERIC0_TOP0_QCH_USI03_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI03_I2C, PERIC0_TOP0_QCH_USI03_I2C, "GATE_PERIC0_TOP0_QCH_USI03_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI04_USI, PERIC0_TOP0_QCH_USI04_USI, "GATE_PERIC0_TOP0_QCH_USI04_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI04_I2C, PERIC0_TOP0_QCH_USI04_I2C, "GATE_PERIC0_TOP0_QCH_USI04_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP0_QCH_USI05_USI, PERIC0_TOP0_QCH_USI05_USI, "GATE_PERIC0_TOP0_QCH_USI05_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI05_I2C, PERIC0_TOP1_QCH_USI05_I2C, "GATE_PERIC0_TOP1_QCH_USI05_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI13_USI, PERIC0_TOP1_QCH_USI13_USI, "GATE_PERIC0_TOP1_QCH_USI13_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI13_I2C, PERIC0_TOP1_QCH_USI13_I2C, "GATE_PERIC0_TOP1_QCH_USI13_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI14_USI, PERIC0_TOP1_QCH_USI14_USI, "GATE_PERIC0_TOP1_QCH_USI14_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI14_I2C, PERIC0_TOP1_QCH_USI14_I2C, "GATE_PERIC0_TOP1_QCH_USI14_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI15_USI, PERIC0_TOP1_QCH_USI15_USI, "GATE_PERIC0_TOP1_QCH_USI15_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_USI15_I2C, PERIC0_TOP1_QCH_USI15_I2C, "GATE_PERIC0_TOP1_QCH_USI15_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_TOP1_QCH_PWM, PERIC0_TOP1_QCH_PWM, "GATE_PERIC0_TOP1_QCH_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC0_QCH, SYSREG_PERIC0_QCH, "GATE_SYSREG_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric1_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC1_QCH, D_TZPC_PERIC1_QCH, "GATE_D_TZPC_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC1_QCH, GPIO_PERIC1_QCH, "GATE_GPIO_PERIC1_QCH", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_CMU_PERIC1_QCH, PERIC1_CMU_PERIC1_QCH, "GATE_PERIC1_CMU_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP0_QCH_UART_BT, PERIC1_TOP0_QCH_UART_BT, "GATE_PERIC1_TOP0_QCH_UART_BT", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI11_USI, PERIC1_TOP1_QCH_USI11_USI, "GATE_PERIC1_TOP1_QCH_USI11_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI11_I2C, PERIC1_TOP1_QCH_USI11_I2C, "GATE_PERIC1_TOP1_QCH_USI11_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI16_USI, PERIC1_TOP1_QCH_USI16_USI, "GATE_PERIC1_TOP1_QCH_USI16_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI16_I2C, PERIC1_TOP1_QCH_USI16_I2C, "GATE_PERIC1_TOP1_QCH_USI16_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI17_USI, PERIC1_TOP1_QCH_USI17_USI, "GATE_PERIC1_TOP1_QCH_USI17_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI17_I2C, PERIC1_TOP1_QCH_USI17_I2C, "GATE_PERIC1_TOP1_QCH_USI17_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI12_USI, PERIC1_TOP1_QCH_USI12_USI, "GATE_PERIC1_TOP1_QCH_USI12_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI12_I2C, PERIC1_TOP1_QCH_USI12_I2C, "GATE_PERIC1_TOP1_QCH_USI12_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI18_USI, PERIC1_TOP1_QCH_USI18_USI, "GATE_PERIC1_TOP1_QCH_USI18_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_TOP1_QCH_USI18_I2C, PERIC1_TOP1_QCH_USI18_I2C, "GATE_PERIC1_TOP1_QCH_USI18_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC1_QCH, SYSREG_PERIC1_QCH, "GATE_SYSREG_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI16_I3C_QCH_P, USI16_I3C_QCH_P, "GATE_USI16_I3C_QCH_P", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI16_I3C_QCH_S, USI16_I3C_QCH_S, "GATE_USI16_I3C_QCH_S", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_USI17_I3C_QCH_P, USI17_I3C_QCH_P, "GATE_USI17_I3C_QCH_P", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI17_I3C_QCH_S, USI17_I3C_QCH_S, "GATE_USI17_I3C_QCH_S", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric2_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC2_BUS, MUX_CLKCMU_PERIC2_BUS_USER, "UMUX_CLKCMU_PERIC2_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC2_QCH, D_TZPC_PERIC2_QCH, "GATE_D_TZPC_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC2_QCH, GPIO_PERIC2_QCH, "GATE_GPIO_PERIC2_QCH", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_CMU_PERIC2_QCH, PERIC2_CMU_PERIC2_QCH, "GATE_PERIC2_CMU_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI06_USI, PERIC2_TOP0_QCH_USI06_USI, "GATE_PERIC2_TOP0_QCH_USI06_USI", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI07_USI, PERIC2_TOP0_QCH_USI07_USI, "GATE_PERIC2_TOP0_QCH_USI07_USI", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI08_USI, PERIC2_TOP0_QCH_USI08_USI, "GATE_PERIC2_TOP0_QCH_USI08_USI", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI08_I2C, PERIC2_TOP0_QCH_USI08_I2C, "GATE_PERIC2_TOP0_QCH_USI08_I2C", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI06_I2C, PERIC2_TOP0_QCH_USI06_I2C, "GATE_PERIC2_TOP0_QCH_USI06_I2C", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP0_QCH_USI07_I2C, PERIC2_TOP0_QCH_USI07_I2C, "GATE_PERIC2_TOP0_QCH_USI07_I2C", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP1_QCH_USI09_USI, PERIC2_TOP1_QCH_USI09_USI, "GATE_PERIC2_TOP1_QCH_USI09_USI", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP1_QCH_USI09_I2C, PERIC2_TOP1_QCH_USI09_I2C, "GATE_PERIC2_TOP1_QCH_USI09_I2C", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP1_QCH_USI10_USI, PERIC2_TOP1_QCH_USI10_USI, "GATE_PERIC2_TOP1_QCH_USI10_USI", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_TOP1_QCH_USI10_I2C, PERIC2_TOP1_QCH_USI10_I2C, "GATE_PERIC2_TOP1_QCH_USI10_I2C", "UMUX_CLKCMU_PERIC2_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC2_QCH, SYSREG_PERIC2_QCH, "GATE_SYSREG_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peris_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_BC_EMUL_QCH, BC_EMUL_QCH, "GATE_BC_EMUL_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_PERIS_QCH, D_TZPC_PERIS_QCH, "GATE_D_TZPC_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GIC_QCH, GIC_QCH, "GATE_GIC_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_QCH, OTP_QCH, "GATE_OTP_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_CON_BIRA_QCH, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_CON_BISR_QCH, OTP_CON_BISR_QCH, "GATE_OTP_CON_BISR_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_CON_TOP_QCH, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIS_CMU_PERIS_QCH, PERIS_CMU_PERIS_QCH, "GATE_PERIS_CMU_PERIS_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIS_QCH, SYSREG_PERIS_QCH, "GATE_SYSREG_PERIS_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TMU_SUB_QCH, TMU_SUB_QCH, "GATE_TMU_SUB_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TMU_TOP_QCH, TMU_TOP_QCH, "GATE_TMU_TOP_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT0_QCH, WDT0_QCH, "GATE_WDT0_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT1_QCH, WDT1_QCH, "GATE_WDT1_QCH", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_s2d_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_BIS_S2D_QCH, BIS_S2D_QCH, "GATE_BIS_S2D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_S2D_CMU_S2D_QCH, S2D_CMU_S2D_QCH, "GATE_S2D_CMU_S2D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_ssp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ADM_DAP_SSS_QCH, ADM_DAP_SSS_QCH, "GATE_ADM_DAP_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_SSS_QCH, BAAW_SSS_QCH, "GATE_BAAW_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_SSP_QCH, D_TZPC_SSP_QCH, "GATE_D_TZPC_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_SSP_QCH, PPMU_SSP_QCH, "GATE_PPMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_RTIC_QCH, QE_RTIC_QCH, "GATE_QE_RTIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_SSPCORE_QCH, QE_SSPCORE_QCH, "GATE_QE_SSPCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_SSS_QCH, QE_SSS_QCH, "GATE_QE_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RTIC_QCH, RTIC_QCH, "GATE_RTIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SSP_CMU_SSP_QCH, SSP_CMU_SSP_QCH, "GATE_SSP_CMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SSS_QCH, SSS_QCH, "GATE_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SWEEPER_D_SSP_QCH, SWEEPER_D_SSP_QCH, "GATE_SWEEPER_D_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_RTIC_QCH, SYSMMU_RTIC_QCH, "GATE_SYSMMU_RTIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_SSPCTRL_QCH, SYSREG_SSPCTRL_QCH, "GATE_SYSREG_SSPCTRL_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_RTIC_QCH, VGEN_LITE_RTIC_QCH, "GATE_VGEN_LITE_RTIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USS_SSPCORE_QCH, USS_SSPCORE_QCH, "GATE_USS_SSPCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_taa_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_TAA_BUS, MUX_CLKCMU_TAA_BUS_USER, "UMUX_CLKCMU_TAA_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_TAA_QCH, ADD_TAA_QCH, "GATE_ADD_TAA_QCH", "UMUX_CLKCMU_TAA_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_TAA_QCH, BUSIF_ADD_TAA_QCH, "GATE_BUSIF_ADD_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_TAA_QCH, BUSIF_HPM_TAA_QCH, "GATE_BUSIF_HPM_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_TAA_QCH, D_TZPC_TAA_QCH, "GATE_D_TZPC_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_TAA_QCH, PPMU_TAA_QCH, "GATE_PPMU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH, SIPU_TAA_QCH, "GATE_SIPU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH_C2_STAT, SIPU_TAA_QCH_C2_STAT, "GATE_SIPU_TAA_QCH_C2_STAT", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH_C2_YDS, SIPU_TAA_QCH_C2_YDS, "GATE_SIPU_TAA_QCH_C2_YDS", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_TAA_QCH_S1, SYSMMU_D_TAA_QCH_S1, "GATE_SYSMMU_D_TAA_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_TAA_QCH_S2, SYSMMU_D_TAA_QCH_S2, "GATE_SYSMMU_D_TAA_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_TAA_QCH, SYSREG_TAA_QCH, "GATE_SYSREG_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TAA_CMU_TAA_QCH, TAA_CMU_TAA_QCH, "GATE_TAA_CMU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_TAA0_QCH, VGEN_LITE_TAA0_QCH, "GATE_VGEN_LITE_TAA0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_TAA1_QCH, VGEN_LITE_TAA1_QCH, "GATE_VGEN_LITE_TAA1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vpc_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_VPC_BUS, MUX_CLKCMU_VPC_BUS_USER, "UMUX_CLKCMU_VPC_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_VPC_QCH, ADD_VPC_QCH, "GATE_ADD_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADM_DAP_VPC_QCH, ADM_DAP_VPC_QCH, "GATE_ADM_DAP_VPC_QCH", "UMUX_CLKCMU_VPC_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_VPC_QCH, BUSIF_ADD_VPC_QCH, "GATE_BUSIF_ADD_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_VPC_QCH, BUSIF_HPM_VPC_QCH, "GATE_BUSIF_HPM_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_VPC_QCH, D_TZPC_VPC_QCH, "GATE_D_TZPC_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_VPC_QCH_PCLK, HTU_VPC_QCH_PCLK, "GATE_HTU_VPC_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_VPC_QCH_CLK, HTU_VPC_QCH_CLK, "GATE_HTU_VPC_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_VPC_QCH, IP_VPC_QCH, "GATE_IP_VPC_QCH", "UMUX_CLKCMU_VPC_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_VPC0_QCH, PPMU_VPC0_QCH, "GATE_PPMU_VPC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_VPC1_QCH, PPMU_VPC1_QCH, "GATE_PPMU_VPC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_VPC2_QCH, PPMU_VPC2_QCH, "GATE_PPMU_VPC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC0_QCH_S1, SYSMMU_VPC0_QCH_S1, "GATE_SYSMMU_VPC0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC0_QCH_S2, SYSMMU_VPC0_QCH_S2, "GATE_SYSMMU_VPC0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC1_QCH_S1, SYSMMU_VPC1_QCH_S1, "GATE_SYSMMU_VPC1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC1_QCH_S2, SYSMMU_VPC1_QCH_S2, "GATE_SYSMMU_VPC1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC2_QCH_S1, SYSMMU_VPC2_QCH_S1, "GATE_SYSMMU_VPC2_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_VPC2_QCH_S2, SYSMMU_VPC2_QCH_S2, "GATE_SYSMMU_VPC2_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_VPC_QCH, SYSREG_VPC_QCH, "GATE_SYSREG_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_VPC_QCH, VGEN_LITE_VPC_QCH, "GATE_VGEN_LITE_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VPC_CMU_VPC_QCH, VPC_CMU_VPC_QCH, "GATE_VPC_CMU_VPC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vpd_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_VPD_BUS, MUX_CLKCMU_VPD_BUS_USER, "UMUX_CLKCMU_VPD_BUS", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_VPD_QCH, D_TZPC_VPD_QCH, "GATE_D_TZPC_VPD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_VPD_QCH, IP_VPD_QCH, "GATE_IP_VPD_QCH", "UMUX_CLKCMU_VPD_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_VPD_QCH, SYSREG_VPD_QCH, "GATE_SYSREG_VPD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VPD_CMU_VPD_QCH, VPD_CMU_VPD_QCH, "GATE_VPD_CMU_VPD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vts_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS_USER, "UMUX_CLKCMU_VTS_BUS", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKAUD_VTS_DMIC0, MUX_CLKAUD_VTS_DMIC0_USER, "UMUX_CLKAUD_VTS_DMIC0", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKAUD_VTS_DMIC1, MUX_CLKAUD_VTS_DMIC1_USER, "UMUX_CLKAUD_VTS_DMIC1", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_VTS_DMIC, MUX_CLKCMU_VTS_DMIC_USER, "UMUX_CLKCMU_VTS_DMIC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLK_RCO_VTS, MUX_CLK_RCO_VTS_USER, "UMUX_CLK_RCO_VTS", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLK_VTS_DMIC_AUD, MUX_CLK_VTS_DMIC_AUD, "UMUX_CLK_VTS_DMIC_AUD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLK_VTS_SERIAL_LIF, MUX_CLK_VTS_SERIAL_LIF, "UMUX_CLK_VTS_SERIAL_LIF", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLK_VTS_DMIC_IF, MUX_CLK_VTS_DMIC_IF, "UMUX_CLK_VTS_DMIC_IF", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_BAAW_C_VTS_QCH, BAAW_C_VTS_QCH, "GATE_BAAW_C_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_D_VTS_QCH, BAAW_D_VTS_QCH, "GATE_BAAW_D_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_VTS_QCH, BUSIF_HPM_VTS_QCH, "GATE_BUSIF_HPM_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CORTEXM4INTEGRATION_QCH_CPU, CORTEXM4INTEGRATION_QCH_CPU, "GATE_CORTEXM4INTEGRATION_QCH_CPU", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMAILBOX_TEST_QCH_ACLK, DMAILBOX_TEST_QCH_ACLK, "GATE_DMAILBOX_TEST_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMAILBOX_TEST_QCH_PCLK, DMAILBOX_TEST_QCH_PCLK, "GATE_DMAILBOX_TEST_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMAILBOX_TEST_QCH_LIF, DMAILBOX_TEST_QCH_LIF, "GATE_DMAILBOX_TEST_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB0_QCH_PCLK, DMIC_AHB0_QCH_PCLK, "GATE_DMIC_AHB0_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB1_QCH_PCLK, DMIC_AHB1_QCH_PCLK, "GATE_DMIC_AHB1_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB2_QCH_PCLK, DMIC_AHB2_QCH_PCLK, "GATE_DMIC_AHB2_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB3_QCH_PCLK, DMIC_AHB3_QCH_PCLK, "GATE_DMIC_AHB3_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB4_QCH_PCLK, DMIC_AHB4_QCH_PCLK, "GATE_DMIC_AHB4_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB5_QCH_PCLK, DMIC_AHB5_QCH_PCLK, "GATE_DMIC_AHB5_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD0_QCH_PCLK, DMIC_AUD0_QCH_PCLK, "GATE_DMIC_AUD0_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD0_QCH_DMIC, DMIC_AUD0_QCH_DMIC, "GATE_DMIC_AUD0_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD1_QCH_PCLK, DMIC_AUD1_QCH_PCLK, "GATE_DMIC_AUD1_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD1_QCH_DMIC, DMIC_AUD1_QCH_DMIC, "GATE_DMIC_AUD1_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD2_QCH_PCLK, DMIC_AUD2_QCH_PCLK, "GATE_DMIC_AUD2_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD2_QCH_DMIC, DMIC_AUD2_QCH_DMIC, "GATE_DMIC_AUD2_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF0_QCH_PCLK, DMIC_IF0_QCH_PCLK, "GATE_DMIC_IF0_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF0_QCH_DMIC, DMIC_IF0_QCH_DMIC, "GATE_DMIC_IF0_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF1_QCH_PCLK, DMIC_IF1_QCH_PCLK, "GATE_DMIC_IF1_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF1_QCH_DMIC, DMIC_IF1_QCH_DMIC, "GATE_DMIC_IF1_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF2_QCH_PCLK, DMIC_IF2_QCH_PCLK, "GATE_DMIC_IF2_QCH_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF2_QCH_DMIC, DMIC_IF2_QCH_DMIC, "GATE_DMIC_IF2_QCH_DMIC", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_VTS_QCH, D_TZPC_VTS_QCH, "GATE_D_TZPC_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_VTS_QCH, GPIO_VTS_QCH, "GATE_GPIO_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC0_QCH, HWACG_SYS_DMIC0_QCH, "GATE_HWACG_SYS_DMIC0_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC1_QCH, HWACG_SYS_DMIC1_QCH, "GATE_HWACG_SYS_DMIC1_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC2_QCH, HWACG_SYS_DMIC2_QCH, "GATE_HWACG_SYS_DMIC2_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC3_QCH, HWACG_SYS_DMIC3_QCH, "GATE_HWACG_SYS_DMIC3_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC4_QCH, HWACG_SYS_DMIC4_QCH, "GATE_HWACG_SYS_DMIC4_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC5_QCH, HWACG_SYS_DMIC5_QCH, "GATE_HWACG_SYS_DMIC5_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_SERIAL_LIF_QCH, HWACG_SYS_SERIAL_LIF_QCH, "GATE_HWACG_SYS_SERIAL_LIF_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_ABOX_VTS_QCH, MAILBOX_ABOX_VTS_QCH, "GATE_MAILBOX_ABOX_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_APM_VTS1_QCH, MAILBOX_APM_VTS1_QCH, "GATE_MAILBOX_APM_VTS1_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_AP_VTS_QCH, MAILBOX_AP_VTS_QCH, "GATE_MAILBOX_AP_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDMA_VTS_QCH, PDMA_VTS_QCH, "GATE_PDMA_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_PCLK, SERIAL_LIF_QCH_PCLK, "GATE_SERIAL_LIF_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_LIF, SERIAL_LIF_QCH_LIF, "GATE_SERIAL_LIF_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_HCLK, SERIAL_LIF_QCH_HCLK, "GATE_SERIAL_LIF_QCH_HCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_DEBUG_US_QCH_PCLK, SERIAL_LIF_DEBUG_US_QCH_PCLK, "GATE_SERIAL_LIF_DEBUG_US_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_DEBUG_US_QCH_LIF, SERIAL_LIF_DEBUG_US_QCH_LIF, "GATE_SERIAL_LIF_DEBUG_US_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_DEBUG_VT_QCH_PCLK, SERIAL_LIF_DEBUG_VT_QCH_PCLK, "GATE_SERIAL_LIF_DEBUG_VT_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_DEBUG_VT_QCH_LIF, SERIAL_LIF_DEBUG_VT_QCH_LIF, "GATE_SERIAL_LIF_DEBUG_VT_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, SS_VTS_GLUE_QCH_DMIC_IF_PAD0, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, SS_VTS_GLUE_QCH_DMIC_IF_PAD1, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2, SS_VTS_GLUE_QCH_DMIC_AUD_PAD2, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2, SS_VTS_GLUE_QCH_DMIC_IF_PAD2, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SWEEPER_D_VTS_QCH, SWEEPER_D_VTS_QCH, "GATE_SWEEPER_D_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_VTS_QCH, SYSREG_VTS_QCH, "GATE_SYSREG_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TIMER_QCH, TIMER_QCH, "GATE_TIMER_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TIMER1_QCH, TIMER1_QCH, "GATE_TIMER1_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TIMER2_QCH, TIMER2_QCH, "GATE_TIMER2_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_QCH, VGEN_LITE_QCH, "GATE_VGEN_LITE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VTS_CMU_VTS_QCH, VTS_CMU_VTS_QCH, "GATE_VTS_CMU_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_VTS_QCH, WDT_VTS_QCH, "GATE_WDT_VTS_QCH", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_yuvpp_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_YUVPP_BUS, MUX_CLKCMU_YUVPP_BUS_USER, "UMUX_CLKCMU_YUVPP_BUS", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_YUVPP_QCH, D_TZPC_YUVPP_QCH, "GATE_D_TZPC_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_FRC_MC_QCH, FRC_MC_QCH, "GATE_FRC_MC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_YUVPP_QCH, PPMU_YUVPP_QCH, "GATE_PPMU_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D0_YUVPP_QCH, QE_D0_YUVPP_QCH, "GATE_QE_D0_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D10_YUVPP_QCH, QE_D10_YUVPP_QCH, "GATE_QE_D10_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D11_YUVPP_QCH, QE_D11_YUVPP_QCH, "GATE_QE_D11_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D1_YUVPP_QCH, QE_D1_YUVPP_QCH, "GATE_QE_D1_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D2_YUVPP_QCH, QE_D2_YUVPP_QCH, "GATE_QE_D2_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D3_YUVPP_QCH, QE_D3_YUVPP_QCH, "GATE_QE_D3_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D4_YUVPP_QCH, QE_D4_YUVPP_QCH, "GATE_QE_D4_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D5_YUVPP_QCH, QE_D5_YUVPP_QCH, "GATE_QE_D5_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D6_YUVPP_QCH, QE_D6_YUVPP_QCH, "GATE_QE_D6_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D7_YUVPP_QCH, QE_D7_YUVPP_QCH, "GATE_QE_D7_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D8_YUVPP_QCH, QE_D8_YUVPP_QCH, "GATE_QE_D8_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D9_YUVPP_QCH, QE_D9_YUVPP_QCH, "GATE_QE_D9_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_YUVPP_QCH_S1, SYSMMU_D_YUVPP_QCH_S1, "GATE_SYSMMU_D_YUVPP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_YUVPP_QCH_S2, SYSMMU_D_YUVPP_QCH_S2, "GATE_SYSMMU_D_YUVPP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_YUVPP_QCH, SYSREG_YUVPP_QCH, "GATE_SYSREG_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_YUVPP0_QCH, VGEN_LITE_YUVPP0_QCH, "GATE_VGEN_LITE_YUVPP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_YUVPP1_QCH, VGEN_LITE_YUVPP1_QCH, "GATE_VGEN_LITE_YUVPP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_YUVPP2_QCH, VGEN_LITE_YUVPP2_QCH, "GATE_VGEN_LITE_YUVPP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YUVPP_CMU_YUVPP_QCH, YUVPP_CMU_YUVPP_QCH, "GATE_YUVPP_CMU_YUVPP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YUVPP_TOP_QCH, YUVPP_TOP_QCH, "GATE_YUVPP_TOP_QCH", "UMUX_CLKCMU_YUVPP_BUS", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YUVPP_TOP_QCH_C2COM, YUVPP_TOP_QCH_C2COM, "GATE_YUVPP_TOP_QCH_C2COM", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
|
|
/* Special VCLK */
|
|
struct init_vclk exynos2100_alive_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_VTS_BUS, CLKCMU_VTS_BUS, "DOUT_CLKCMU_VTS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_BUS, DIV_CLK_ALIVE_BUS, "DOUT_DIV_CLK_ALIVE_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CMGP_BUS, CLKCMU_CMGP_BUS, "DOUT_CLKCMU_CMGP_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_I3C_PMIC, DIV_CLK_ALIVE_I3C_PMIC, "DOUT_DIV_CLK_ALIVE_I3C_PMIC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CMGP_PERI, CLKCMU_CMGP_PERI, "DOUT_CLKCMU_CMGP_PERI", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CMGP_ADC, CLKCMU_CMGP_ADC, "DOUT_CLKCMU_CMGP_ADC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_DBGCORE_UART, DIV_CLK_ALIVE_DBGCORE_UART, "DOUT_DIV_CLK_ALIVE_DBGCORE_UART", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_aud_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU, DIV_CLK_AUD_CPU, "DOUT_DIV_CLK_AUD_CPU", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_DIV_CLK_AUD_AUDIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_PCLKDBG, DIV_CLK_AUD_CPU_PCLKDBG, "DOUT_DIV_CLK_AUD_CPU_PCLKDBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_DSIF, DIV_CLK_AUD_DSIF, "DOUT_DIV_CLK_AUD_DSIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_DIV_CLK_AUD_UAIF0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_DIV_CLK_AUD_UAIF1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_DIV_CLK_AUD_UAIF2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_DIV_CLK_AUD_UAIF3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_ACLK, DIV_CLK_AUD_CPU_ACLK, "DOUT_DIV_CLK_AUD_CPU_ACLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_BUS, DIV_CLK_AUD_BUS, "DOUT_DIV_CLK_AUD_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_BUSP, DIV_CLK_AUD_BUSP, "DOUT_DIV_CLK_AUD_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CNT, DIV_CLK_AUD_CNT, "DOUT_DIV_CLK_AUD_CNT", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF4, DIV_CLK_AUD_UAIF4, "DOUT_DIV_CLK_AUD_UAIF4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF5, DIV_CLK_AUD_UAIF5, "DOUT_DIV_CLK_AUD_UAIF5", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_SCLK, DIV_CLK_AUD_SCLK, "DOUT_DIV_CLK_AUD_SCLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_DMIC1, DIV_CLK_AUD_DMIC1, "DOUT_DIV_CLK_AUD_DMIC1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF6, DIV_CLK_AUD_UAIF6, "DOUT_DIV_CLK_AUD_UAIF6", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_VTS_DMIC0, CLKAUD_VTS_DMIC0, "DOUT_CLKAUD_VTS_DMIC0", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_HSI0_BUS, CLKAUD_HSI0_BUS, "DOUT_CLKAUD_HSI0_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_HSI0_USB31DRD, CLKAUD_HSI0_USB31DRD, "DOUT_CLKAUD_HSI0_USB31DRD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_PCMC, DIV_CLK_AUD_PCMC, "DOUT_DIV_CLK_AUD_PCMC", 0, 0, NULL),
|
|
VCLK(PLL_OUT_AUD0, PLL_AUD0, "PLL_OUT_AUD0", 0, 0, NULL),
|
|
VCLK(PLL_OUT_AUD1, PLL_AUD1, "PLL_OUT_AUD1", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_cmgp_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C0, DIV_CLK_CMGP_I2C0, "DOUT_DIV_CLK_CMGP_I2C0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI1, DIV_CLK_CMGP_USI1, "DOUT_DIV_CLK_CMGP_USI1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI0, DIV_CLK_CMGP_USI0, "DOUT_DIV_CLK_CMGP_USI0", 0, 0, NULL), //??VCLK?
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI2, DIV_CLK_CMGP_USI2, "DOUT_DIV_CLK_CMGP_USI2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI3, DIV_CLK_CMGP_USI3, "DOUT_DIV_CLK_CMGP_USI3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C1, DIV_CLK_CMGP_I2C1, "DOUT_DIV_CLK_CMGP_I2C1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C2, DIV_CLK_CMGP_I2C2, "DOUT_DIV_CLK_CMGP_I2C2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C3, DIV_CLK_CMGP_I2C3, "DOUT_DIV_CLK_CMGP_I2C3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I3C, DIV_CLK_CMGP_I3C, "DOUT_DIV_CLK_CMGP_I3C", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_top_vclks[] = {
|
|
VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
|
|
VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
|
|
VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
|
|
VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
|
|
VCLK(CIS_CLK4, CLKCMU_CIS_CLK4, "CIS_CLK4", 0, 0, NULL),
|
|
VCLK(CIS_CLK5, CLKCMU_CIS_CLK5, "CIS_CLK5", 0, 0, NULL),
|
|
VCLK(DOUT_CLK_TOP_HSI0_BUS, VCLK_DIV_CLK_TOP_HSI0_BUS, "DOUT_CLK_TOP_HSI0_BUS", 0, 0, NULL),
|
|
//PLL_MMC?
|
|
};
|
|
|
|
struct init_vclk exynos2100_hsi0_vclks[] = {
|
|
VCLK(USB31DRD, VCLK_IP_USB31DRD, "USB31DRD", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_hsi1_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_HSI1_MMC_CARD, CLKCMU_HSI1_MMC_CARD, "DOUT_CLKCMU_HSI1_MMC_CARD", 0, 0, NULL),
|
|
VCLK(UFS_EMBD, CLKCMU_HSI1_UFS_EMBD, "UFS_EMBD", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_lme_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_LME_BUSP, DIV_CLK_LME_BUSP, "DOUT_DIV_CLK_LME_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_m2m_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_M2M_BUSP, DIV_CLK_M2M_BUSP, "DOUT_DIV_CLK_M2M_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mcfp0_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_MCFP0_BUSP, DIV_CLK_MCFP0_BUSP, "DOUT_DIV_CLK_MCFP0_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_mcfp1_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_MCFP1_BUSP, DIV_CLK_MCFP1_BUSP, "DOUT_DIV_CLK_MCFP1_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_NPU_BUSP, DIV_CLK_NPU_BUSP, "DOUT_DIV_CLK_NPU_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu01_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_NPU01_BUSP, DIV_CLK_NPU01_BUSP, "DOUT_DIV_CLK_NPU01_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npu10_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_NPU10_BUSP, DIV_CLK_NPU10_BUSP, "DOUT_DIV_CLK_NPU10_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_npus_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_NPUS_BUSP, DIV_CLK_NPUS_BUSP, "DOUT_DIV_CLK_NPUS_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric0_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI00_USI, DIV_CLK_PERIC0_USI00_USI, "DOUT_DIV_CLK_PERIC0_USI00_USI", 0, 0, NULL),//??VCLK
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI01_USI, DIV_CLK_PERIC0_USI01_USI, "DOUT_DIV_CLK_PERIC0_USI01_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI02_USI, DIV_CLK_PERIC0_USI02_USI, "DOUT_DIV_CLK_PERIC0_USI02_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI03_USI, DIV_CLK_PERIC0_USI03_USI, "DOUT_DIV_CLK_PERIC0_USI03_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI04_USI, DIV_CLK_PERIC0_USI04_USI, "DOUT_DIV_CLK_PERIC0_USI04_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI05_USI, DIV_CLK_PERIC0_USI05_USI, "DOUT_DIV_CLK_PERIC0_USI05_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI_I2C, DIV_CLK_PERIC0_USI_I2C, "DOUT_DIV_CLK_PERIC0_USI_I2C", 0, 0, NULL),
|
|
VCLK(UART_DBG, DIV_CLK_PERIC0_UART_DBG, "UART_DBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI13_USI, DIV_CLK_PERIC0_USI13_USI, "DOUT_DIV_CLK_PERIC0_USI13_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI14_USI, DIV_CLK_PERIC0_USI14_USI, "DOUT_DIV_CLK_PERIC0_USI14_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI15_USI, DIV_CLK_PERIC0_USI15_USI, "DOUT_DIV_CLK_PERIC0_USI15_USI", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric1_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_PERIC1_UART_BT, DIV_CLK_PERIC1_UART_BT, "DOUT_DIV_CLK_PERIC1_UART_BT", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI_I2C, DIV_CLK_PERIC1_USI_I2C, "DOUT_DIV_CLK_PERIC1_USI_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI18_USI, DIV_CLK_PERIC1_USI18_USI, "DOUT_DIV_CLK_PERIC1_USI18_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI12_USI, DIV_CLK_PERIC1_USI12_USI, "DOUT_DIV_CLK_PERIC1_USI12_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI11_USI, DIV_CLK_PERIC1_USI11_USI, "DOUT_DIV_CLK_PERIC1_USI11_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI16_USI, DIV_CLK_PERIC1_USI16_USI, "DOUT_DIV_CLK_PERIC1_USI16_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI17_USI, DIV_CLK_PERIC1_USI17_USI, "DOUT_DIV_CLK_PERIC1_USI17_USI", 0, 0, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk exynos2100_peric2_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI08_USI, DIV_CLK_PERIC2_USI08_USI, "DOUT_DIV_CLK_PERIC2_USI08_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI_I2C, DIV_CLK_PERIC2_USI_I2C, "DOUT_DIV_CLK_PERIC2_USI_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI06_USI, DIV_CLK_PERIC2_USI06_USI, "DOUT_DIV_CLK_PERIC2_USI06_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI07_USI, DIV_CLK_PERIC2_USI07_USI, "DOUT_DIV_CLK_PERIC2_USI07_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI09_USI, DIV_CLK_PERIC2_USI09_USI, "DOUT_DIV_CLK_PERIC2_USI09_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI10_USI, DIV_CLK_PERIC2_USI10_USI, "DOUT_DIV_CLK_PERIC2_USI10_USI", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_taa_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_TAA_BUSP, DIV_CLK_TAA_BUSP, "DOUT_DIV_CLK_TAA_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vpc_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_VPC_BUSP, DIV_CLK_VPC_BUSP, "DOUT_DIV_CLK_VPC_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VPC_BUS, DIV_CLK_VPC_BUS, "DOUT_DIV_CLK_VPC_BUS", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vpd_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_VPD_BUSP, DIV_CLK_VPD_BUSP, "DOUT_DIV_CLK_VPD_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VPD_BUS, DIV_CLK_VPD_BUS, "DOUT_DIV_CLK_VPD_BUS", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_vts_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_IF, DIV_CLK_VTS_DMIC_IF, "DOUT_DIV_CLK_VTS_DMIC_IF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF_DIV2, "DOUT_DIV_CLK_VTS_DMIC_IF_DIV2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_BUS, DIV_CLK_VTS_BUS, "DOUT_DIV_CLK_VTS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_AUD, DIV_CLK_VTS_DMIC_AUD, "DOUT_DIV_CLK_VTS_DMIC_AUD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_AUD_DIV2, DIV_CLK_VTS_DMIC_AUD_DIV2, "DOUT_DIV_CLK_VTS_DMIC_AUD_DIV2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_SERIAL_LIF, DIV_CLK_VTS_SERIAL_LIF, "DOUT_DIV_CLK_VTS_SERIAL_LIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_AHB, DIV_CLK_VTS_DMIC_AHB, "DOUT_DIV_CLK_VTS_DMIC_AHB", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE, DIV_CLK_VTS_SERIAL_LIF_CORE, "DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk exynos2100_yuvpp_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_YUVPP_BUSP, DIV_CLK_YUVPP_BUSP, "DOUT_DIV_CLK_YUVPP_BUSP", 0, 0, NULL),
|
|
};
|
|
|
|
static struct init_vclk exynos2100_clkout_vclks[] = {
|
|
VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
|
|
VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
|
|
};
|
|
|
|
static struct of_device_id ext_clk_match[] = {
|
|
{.compatible = "samsung,exynos2100-oscclk", .data = (void *)0},
|
|
{},
|
|
};
|
|
|
|
void exynos2100_vclk_init(void)
|
|
{
|
|
/* Common clock init */
|
|
}
|
|
|
|
/* register exynos2100 clocks */
|
|
static int exynos2100_clock_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
void __iomem *reg_base;
|
|
|
|
if (np) {
|
|
reg_base = of_iomap(np, 0);
|
|
if (!reg_base)
|
|
panic("%s: failed to map registers\n", __func__);
|
|
} else {
|
|
panic("%s: unable to determine soc\n", __func__);
|
|
}
|
|
|
|
exynos2100_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
|
if (!exynos2100_clk_provider)
|
|
panic("%s: unable to allocate context.\n", __func__);
|
|
|
|
samsung_register_of_fixed_ext(exynos2100_clk_provider, exynos2100_fixed_rate_ext_clks,
|
|
ARRAY_SIZE(exynos2100_fixed_rate_ext_clks),
|
|
ext_clk_match);
|
|
|
|
/* register HWACG vclk */
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_alive_hwacg_vclks, ARRAY_SIZE(exynos2100_alive_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_aud_hwacg_vclks, ARRAY_SIZE(exynos2100_aud_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_bus0_hwacg_vclks, ARRAY_SIZE(exynos2100_bus0_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_bus1_hwacg_vclks, ARRAY_SIZE(exynos2100_bus1_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_bus2_hwacg_vclks, ARRAY_SIZE(exynos2100_bus2_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_cmgp_hwacg_vclks, ARRAY_SIZE(exynos2100_cmgp_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_top_hwacg_vclks, ARRAY_SIZE(exynos2100_top_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_core_hwacg_vclks, ARRAY_SIZE(exynos2100_core_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_csis_hwacg_vclks, ARRAY_SIZE(exynos2100_csis_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_dns_hwacg_vclks, ARRAY_SIZE(exynos2100_dns_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_dpub_hwacg_vclks, ARRAY_SIZE(exynos2100_dpub_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_dpuf0_hwacg_vclks, ARRAY_SIZE(exynos2100_dpuf0_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_dpuf1_hwacg_vclks, ARRAY_SIZE(exynos2100_dpuf1_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_dsu_hwacg_vclks, ARRAY_SIZE(exynos2100_dsu_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_g3d_hwacg_vclks, ARRAY_SIZE(exynos2100_g3d_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_hsi0_hwacg_vclks, ARRAY_SIZE(exynos2100_hsi0_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_hsi1_hwacg_vclks, ARRAY_SIZE(exynos2100_hsi1_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_itp_hwacg_vclks, ARRAY_SIZE(exynos2100_itp_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_lme_hwacg_vclks, ARRAY_SIZE(exynos2100_lme_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_m2m_hwacg_vclks, ARRAY_SIZE(exynos2100_m2m_hwacg_vclks));
|
|
samsung_register_vclk(exynos2100_clk_provider, exynos2100_mcfp0_hwacg_vclks, ARRAY_SIZE(exynos2100_mcfp0_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mcfp1_hwacg_vclks, ARRAY_SIZE(exynos2100_mcfp1_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mcsc_hwacg_vclks, ARRAY_SIZE(exynos2100_mcsc_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mfc0_hwacg_vclks, ARRAY_SIZE(exynos2100_mfc0_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mfc1_hwacg_vclks, ARRAY_SIZE(exynos2100_mfc1_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mif_hwacg_vclks, ARRAY_SIZE(exynos2100_mif_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npu_hwacg_vclks, ARRAY_SIZE(exynos2100_npu_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npus_hwacg_vclks, ARRAY_SIZE(exynos2100_npus_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric0_hwacg_vclks, ARRAY_SIZE(exynos2100_peric0_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric1_hwacg_vclks, ARRAY_SIZE(exynos2100_peric1_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric2_hwacg_vclks, ARRAY_SIZE(exynos2100_peric2_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peris_hwacg_vclks, ARRAY_SIZE(exynos2100_peris_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_s2d_hwacg_vclks, ARRAY_SIZE(exynos2100_s2d_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_ssp_hwacg_vclks, ARRAY_SIZE(exynos2100_ssp_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_taa_hwacg_vclks, ARRAY_SIZE(exynos2100_taa_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vpc_hwacg_vclks, ARRAY_SIZE(exynos2100_vpc_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vpd_hwacg_vclks, ARRAY_SIZE(exynos2100_vpd_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vts_hwacg_vclks, ARRAY_SIZE(exynos2100_vts_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_yuvpp_hwacg_vclks, ARRAY_SIZE(exynos2100_yuvpp_hwacg_vclks));
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/* register special vclk */
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_alive_vclks, ARRAY_SIZE(exynos2100_alive_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_aud_vclks, ARRAY_SIZE(exynos2100_aud_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_cmgp_vclks, ARRAY_SIZE(exynos2100_cmgp_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_top_vclks, ARRAY_SIZE(exynos2100_top_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_hsi0_vclks, ARRAY_SIZE(exynos2100_hsi0_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_hsi1_vclks, ARRAY_SIZE(exynos2100_hsi1_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_lme_vclks, ARRAY_SIZE(exynos2100_lme_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_m2m_vclks, ARRAY_SIZE(exynos2100_m2m_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mcfp0_vclks, ARRAY_SIZE(exynos2100_mcfp0_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_mcfp1_vclks, ARRAY_SIZE(exynos2100_mcfp1_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npu_vclks, ARRAY_SIZE(exynos2100_npu_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npu01_hwacg_vclks, ARRAY_SIZE(exynos2100_npu01_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npu10_hwacg_vclks, ARRAY_SIZE(exynos2100_npu10_hwacg_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_npus_vclks, ARRAY_SIZE(exynos2100_npus_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric0_vclks, ARRAY_SIZE(exynos2100_peric0_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric1_vclks, ARRAY_SIZE(exynos2100_peric1_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_peric2_vclks, ARRAY_SIZE(exynos2100_peric2_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_taa_vclks, ARRAY_SIZE(exynos2100_taa_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vpc_vclks, ARRAY_SIZE(exynos2100_vpc_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vpd_vclks, ARRAY_SIZE(exynos2100_vpd_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_vts_vclks, ARRAY_SIZE(exynos2100_vts_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_yuvpp_vclks, ARRAY_SIZE(exynos2100_yuvpp_vclks));
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samsung_register_vclk(exynos2100_clk_provider, exynos2100_clkout_vclks, ARRAY_SIZE(exynos2100_clkout_vclks));
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|
|
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clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
|
|
|
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samsung_clk_of_add_provider(np, exynos2100_clk_provider);
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|
|
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exynos2100_vclk_init();
|
|
|
|
pr_info("EXYNOS2100: Clock setup completed\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_exynos_clock_match[] = {
|
|
{ .compatible = "samsung,exynos2100-clock", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_exynos_clock_match);
|
|
|
|
static const struct platform_device_id exynos_clock_ids[] = {
|
|
{ "exynos2100-clock", },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver exynos2100_clock_driver = {
|
|
.driver = {
|
|
.name = "exynos2100_clock",
|
|
.of_match_table = of_exynos_clock_match,
|
|
},
|
|
.probe = exynos2100_clock_probe,
|
|
.id_table = exynos_clock_ids,
|
|
};
|
|
|
|
static int exynos2100_clock_init(void)
|
|
{
|
|
return platform_driver_register(&exynos2100_clock_driver);
|
|
}
|
|
arch_initcall(exynos2100_clock_init);
|
|
|
|
static void exynos2100_clock_exit(void)
|
|
{
|
|
return platform_driver_unregister(&exynos2100_clock_driver);
|
|
}
|
|
module_exit(exynos2100_clock_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|