16815 lines
949 KiB
C
Executable file
16815 lines
949 KiB
C
Executable file
#ifndef __CMUCAL_SFR_H__
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#define __CMUCAL_SFR_H__
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#include "../../cmucal.h"
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enum sfr_block_id {
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CMU_AUD = SFR_BLOCK_TYPE,
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CMU_TOP,
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CMU_CPUCL0,
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CMU_CPUCL1,
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CMU_CPUCL2,
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CMU_DSU,
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CMU_G3DCORE,
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CMU_MIF,
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CMU_S2D,
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CMU_ALIVE,
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CMU_CHUB,
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CMU_CHUBVTS,
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CMU_CMGP,
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CMU_CSIS,
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CMU_DNC,
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CMU_DSP,
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CMU_GNPU,
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CMU_HSI0,
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CMU_NOCL0,
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CMU_NOCL1A,
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CMU_NOCL1B,
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CMU_NOCL1C,
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CMU_PERIC0,
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CMU_PERIC1,
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CMU_PERIC2,
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CMU_SDMA,
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CMU_UFD,
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CMU_VTS,
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CMU_BRP,
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CMU_CPUCL0_GLB,
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CMU_CSTAT,
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CMU_DBGCORE,
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CMU_DPUB,
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CMU_DPUF,
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CMU_DPUF1,
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CMU_DRCP,
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CMU_G3D,
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CMU_HSI1,
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CMU_LME,
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CMU_M2M,
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CMU_MCSC,
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CMU_MFC0,
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CMU_MFC1,
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CMU_PERIS,
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CMU_SSP,
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CMU_UFS,
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CMU_YUVP,
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CMU_ALLCSIS,
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CMU_GNSS,
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CMU_STRONG,
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end_of_sfr_block,
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num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE,
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};
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enum sfr_id {
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PLL_LOCKTIME_PLL_AUD = SFR_TYPE,
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PLL_CON3_PLL_AUD,
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PLL_CON8_PLL_AUD,
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PLL_LOCKTIME_PLL_MMC,
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PLL_CON3_PLL_MMC,
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PLL_CON8_PLL_MMC,
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PLL_LOCKTIME_PLL_SHARED0,
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PLL_CON3_PLL_SHARED0,
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PLL_CON8_PLL_SHARED0,
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PLL_LOCKTIME_PLL_SHARED1,
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PLL_CON3_PLL_SHARED1,
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PLL_CON8_PLL_SHARED1,
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PLL_LOCKTIME_PLL_SHARED2,
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PLL_CON3_PLL_SHARED2,
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PLL_CON8_PLL_SHARED2,
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PLL_LOCKTIME_PLL_SHARED3,
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PLL_CON3_PLL_SHARED3,
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PLL_CON8_PLL_SHARED3,
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PLL_LOCKTIME_PLL_SHARED4,
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PLL_CON3_PLL_SHARED4,
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PLL_CON8_PLL_SHARED4,
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PLL_LOCKTIME_PLL_SHARED_MIF,
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PLL_CON3_PLL_SHARED_MIF,
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PLL_CON8_PLL_SHARED_MIF,
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PLL_LOCKTIME_PLL_CPUCL0,
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PLL_CON3_PLL_CPUCL0,
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PLL_CON8_PLL_CPUCL0,
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PLL_LOCKTIME_PLL_CPUCL1,
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PLL_CON3_PLL_CPUCL1,
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PLL_CON8_PLL_CPUCL1,
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PLL_LOCKTIME_PLL_CPUCL2,
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PLL_CON3_PLL_CPUCL2,
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PLL_CON8_PLL_CPUCL2,
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PLL_LOCKTIME_PLL_DSU,
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PLL_CON3_PLL_DSU,
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PLL_CON8_PLL_DSU,
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PLL_LOCKTIME_PLL_G3D,
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PLL_CON3_PLL_G3D,
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PLL_CON8_PLL_G3D,
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PLL_LOCKTIME_PLL_G3D1,
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PLL_CON3_PLL_G3D1,
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PLL_CON8_PLL_G3D1,
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PLL_LOCKTIME_PLL_MIF_MAIN,
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PLL_CON3_PLL_MIF_MAIN,
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PLL_LOCKTIME_PLL_MIF_SUB,
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PLL_CON3_PLL_MIF_SUB,
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PLL_LOCKTIME_PLL_MIF_S2D,
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PLL_CON3_PLL_MIF_S2D,
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CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC,
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CLK_CON_MUX_MUX_CLK_ALIVE_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI,
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CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI,
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CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC,
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CLK_CON_MUX_MUX_CLK_ALIVE_TIMER,
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CLK_CON_MUX_MUX_CLK_ALIVE_SPMI,
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CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART,
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CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC,
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CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB,
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CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC,
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CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
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CLK_CON_MUX_MUX_CLK_AUD_CPU,
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CLK_CON_MUX_MUX_CLK_AUD_DSIF,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
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CLK_CON_MUX_MUX_CLK_AUD_NOC,
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CLK_CON_MUX_MUX_CLK_AUD_PCMC,
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CLK_CON_MUX_MUX_CLK_AUD_AUDIF,
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CLK_CON_MUX_MUX_CLK_AUD_SCLK,
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CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF,
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CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE,
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CLK_CON_MUX_MUX_CHUB_TIMER,
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CLK_CON_MUX_MUX_CLK_CHUB_USI0,
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CLK_CON_MUX_MUX_CLK_CHUB_USI1,
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CLK_CON_MUX_MUX_CLK_CHUB_USI3,
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CLK_CON_MUX_MUX_CLK_CHUB_I2C,
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CLK_CON_MUX_MUX_CLK_CHUB_USI2,
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CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL,
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CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0,
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CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1,
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CLK_CON_MUX_MUX_CLK_CHUB_NOC,
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CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK,
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CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC,
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CLK_CON_MUX_MUX_CLK_CMGP_USI4,
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CLK_CON_MUX_MUX_CLK_CMGP_USI0,
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CLK_CON_MUX_MUX_CLK_CMGP_USI1,
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CLK_CON_MUX_MUX_CLK_CMGP_USI2,
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CLK_CON_MUX_MUX_CLK_CMGP_USI3,
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CLK_CON_MUX_MUX_CLK_CMGP_USI5,
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CLK_CON_MUX_MUX_CLK_CMGP_USI6,
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CLK_CON_MUX_MUX_CLK_CMGP_I2C,
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CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL,
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CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0,
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CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC,
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CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
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CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
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CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_BRP_NOC,
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CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC,
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CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
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CLK_CON_MUX_MUX_CMU_CMUREF,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
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CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
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CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
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CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
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CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
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CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
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CLK_CON_MUX_CLKCMU_DPUF_NOC,
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CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
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CLK_CON_MUX_MUX_CLKCMU_DPUF,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC,
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CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
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CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
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CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT,
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CLK_CON_MUX_CLKCMU_DPUB_NOC,
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CLK_CON_MUX_MUX_CLKCMU_DPUB,
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CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1,
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CLK_CON_MUX_MUX_CLKCMU_LME_NOC,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
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CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY,
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CLK_CON_MUX_MUX_CP_HISPEEDY_CLK,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
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CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
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CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP,
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CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
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CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC,
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CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
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CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
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CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC,
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CLK_CON_MUX_MUX_CP_SHARED0_CLK,
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CLK_CON_MUX_MUX_CP_SHARED1_CLK,
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CLK_CON_MUX_MUX_CP_SHARED2_CLK,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM,
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CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC,
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CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0,
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CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1,
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CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
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CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0,
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CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC,
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CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1,
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CLK_CON_MUX_MUX_CLKCMU_LME_LME,
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CLK_CON_MUX_MUX_CLKCMU_M2M_FRC,
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CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
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CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD,
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CLK_CON_MUX_MUX_CLKCMU_UFS_NOC,
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CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD,
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CLK_CON_MUX_CLKCMU_AUD_CPU,
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CLK_CON_MUX_CLKCMU_AUD_AUDIF0,
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CLK_CON_MUX_CLKCMU_AUD_AUDIF1,
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CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH,
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CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH,
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CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH,
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CLK_CON_MUX_CLKCMU_DSU_SWITCH,
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CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC,
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CLK_CON_MUX_CLKCMU_DNC_NOC,
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CLK_CON_MUX_CLKCMU_SDMA_NOC,
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CLK_CON_MUX_CLKCMU_DSP_NOC,
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CLK_CON_MUX_CLKCMU_G3D_SWITCH,
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CLK_CON_MUX_CLKCMU_GNPU_NOC,
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CLK_CON_MUX_CLKCMU_M2M_NOC,
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CLK_CON_MUX_CLKCMU_M2M_FRC,
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CLK_CON_MUX_CLKCMU_MCSC_NOC,
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CLK_CON_MUX_CLKCMU_MCSC_MCSC,
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CLK_CON_MUX_CLKCMU_NOCL0_NOC,
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CLK_CON_MUX_CLKCMU_NOCL1A_NOC,
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CLK_CON_MUX_CLKCMU_NOCL1B_NOC0,
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CLK_CON_MUX_CLKCMU_NOCL1C_NOC,
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CLK_CON_MUX_CP_SHARED0_CLK,
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CLK_CON_MUX_CP_SHARED2_CLK,
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CLK_CON_MUX_CP_HISPEEDY_CLK,
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CLK_CON_MUX_CLKCMU_UFS_MMC_CARD,
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CLK_CON_MUX_MUX_CPUCL0_CMUREF,
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CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN,
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CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX,
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CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN,
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CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP,
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CLK_CON_MUX_MUX_CLK_CPUCL0_DDD,
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CLK_CON_MUX_MUX_CLK_CPUCL0_HTU,
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CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0,
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CLK_CON_MUX_MUX_CPUCL1_CMUREF,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0,
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CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0,
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CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1,
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CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2,
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CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2,
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CLK_CON_MUX_MUX_CLK_CPUCL1_HTU,
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CLK_CON_MUX_MUX_CPUCL2_CMUREF,
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CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN,
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CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN,
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CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX,
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CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP,
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CLK_CON_MUX_MUX_CLK_CPUCL2_DDD,
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CLK_CON_MUX_MUX_CLK_CPUCL2_HTU,
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CLK_CON_MUX_MUX_CLK_CSIS_NOC,
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CLK_CON_MUX_MUX_CLK_CSIS_DCPHY,
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CLK_CON_MUX_MUX_CLK_DNC_NOC,
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CLK_CON_MUX_MUX_CLK_DSP_NOC,
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CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN,
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CLK_CON_MUX_MUX_DSU_CMUREF,
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CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN,
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CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX,
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CLK_CON_MUX_MUX_CLK_DSU_POWERIP,
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CLK_CON_MUX_MUX_CLK_DSU_DDD,
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CLK_CON_MUX_MUX_CLK_DSU_HTU,
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CLK_CON_MUX_MUX_CLK_G3D_CORE,
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CLK_CON_MUX_MUX_CLK_G3D_DDD,
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CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN,
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CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX,
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CLK_CON_MUX_MUX_CLK_G3D_PLL,
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CLK_CON_MUX_MUX_CLK_GNPU_NOC,
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CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD,
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CLK_CON_MUX_MUX_CLK_HSI0_NOC,
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CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK,
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CLK_CON_MUX_MUX_MIF_CMUREF,
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CLK_CON_MUX_MUX_NOCL0_CMUREF,
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CLK_CON_MUX_MUX_NOCL1A_CMUREF,
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CLK_CON_MUX_MUX_NOCL1B_CMUREF,
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CLK_CON_MUX_MUX_NOCL1C_CMUREF,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI04,
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CLK_CON_MUX_MUX_CLK_PERIC0_I2C,
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CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT,
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CLK_CON_MUX_MUX_CLK_PERIC1_I2C,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI07,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI08,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI09,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI10,
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CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_I2C,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI02,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI03,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI05,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI11,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE,
|
|
CLK_CON_MUX_MUX_CLK_SDMA_NOC,
|
|
CLK_CON_MUX_MUX_CLK_UFD_NOC,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD,
|
|
CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1,
|
|
CLK_CON_MUX_MUX_CLK_VTS_NOC,
|
|
PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER,
|
|
PLL_CON0_MUX_CLK_RCO_ALIVE_USER,
|
|
PLL_CON1_MUX_CLK_RCO_ALIVE_USER,
|
|
PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
|
|
PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
|
|
PLL_CON1_MUX_CLKCMU_AUD_CPU_USER,
|
|
PLL_CON0_MUX_CLKCMU_AUD_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_AUD_NOC_USER,
|
|
PLL_CON0_MUX_CP_PCMC_CLK_USER,
|
|
PLL_CON1_MUX_CP_PCMC_CLK_USER,
|
|
PLL_CON0_MUX_CLK_AUD_RCO_USER,
|
|
PLL_CON1_MUX_CLK_AUD_RCO_USER,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER,
|
|
PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER,
|
|
PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER,
|
|
PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER,
|
|
PLL_CON0_MUX_CLKCMU_BRP_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_BRP_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_USER,
|
|
PLL_CON1_MUX_CP_MPLL_CLK_USER,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_D2_USER,
|
|
PLL_CON1_MUX_CP_MPLL_CLK_D2_USER,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER,
|
|
PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DNC_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DNC_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER,
|
|
PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER,
|
|
PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DSP_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_DSP_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER,
|
|
PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER,
|
|
PLL_CON0_MUX_CLKCMU_LME_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_LME_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_LME_LME_USER,
|
|
PLL_CON1_MUX_CLKCMU_LME_LME_USER,
|
|
PLL_CON0_MUX_CLKCMU_M2M_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_M2M_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_M2M_FRC_USER,
|
|
PLL_CON1_MUX_CLKCMU_M2M_FRC_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER,
|
|
PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER,
|
|
PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X,
|
|
PLL_CON1_CLKMUX_MIF_DDRPHY2X,
|
|
PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER,
|
|
PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D,
|
|
PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D,
|
|
PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER,
|
|
PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_SSP_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_SSP_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER,
|
|
PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER,
|
|
PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER,
|
|
PLL_CON0_MUX_CLKCMU_UFS_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_UFS_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER,
|
|
PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER,
|
|
PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER,
|
|
PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER,
|
|
PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER,
|
|
PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER,
|
|
PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER,
|
|
PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER,
|
|
PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX,
|
|
CLK_CON_MUX_MUX_CLK_DBGCORE_NOC,
|
|
CLK_CON_MUX_MUX_OSCCLK_DBGCORE,
|
|
CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE,
|
|
CLK_CON_MUX_MUX_CLK_DSU_STRMUX,
|
|
CLK_CON_MUX_MUX_CLK_G3D_STRMUX,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC,
|
|
CLK_CON_DIV_CLKALIVE_UFD_NOC,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_NOC,
|
|
CLK_CON_DIV_CLKALIVE_CMGP_NOC,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_SPMI,
|
|
CLK_CON_DIV_CLKALIVE_CMGP_PERI,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART,
|
|
CLK_CON_DIV_CLKALIVE_CHUB_PERI,
|
|
CLK_CON_DIV_CLKALIVE_DBGCORE_NOC,
|
|
CLK_CON_DIV_CLKALIVE_DNC_NOC,
|
|
CLK_CON_DIV_CLKALIVE_GNPU_NOC,
|
|
CLK_CON_DIV_CLKALIVE_SDMA_NOC,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB,
|
|
CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC,
|
|
CLK_CON_DIV_CLKALIVE_CSIS_NOC,
|
|
CLK_CON_DIV_CLKALIVE_DSP_NOC,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOC,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
|
|
CLK_CON_DIV_CLKAUD_HSI0_NOC,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE,
|
|
CLK_CON_DIV_CLK_AUD_MCLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOCP,
|
|
CLK_CON_DIV_CLK_BRP_ADD_CH_CLK,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_NOC,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI0,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI1,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI3,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI2,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI4,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI5,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI6,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_NOC,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPOSC,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_NOC,
|
|
CLK_CON_DIV_CLKCMU_PERIS_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM,
|
|
CLK_CON_DIV_CLKCMU_BRP_NOC,
|
|
CLK_CON_DIV_CLKCMU_YUVP_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD,
|
|
CLK_CON_DIV_CLKCMU_MIF_NOCP,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM,
|
|
CLK_CON_DIV_CLKCMU_HSI0_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST,
|
|
CLK_CON_DIV_CLKCMU_CSIS_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM,
|
|
CLK_CON_DIV_CLKCMU_HSI1_NOC,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1,
|
|
CLK_CON_DIV_CLKCMU_LME_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB32DRD,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
|
|
CLK_CON_DIV_CLKCMU_AUD_NOC,
|
|
CLK_CON_DIV_CLKCMU_CSIS_DCPHY,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM,
|
|
CLK_CON_DIV_CP_SHARED1_CLK,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1,
|
|
CLK_CON_DIV_CLKCMU_SSP_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_NOC,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_NOCP,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM,
|
|
CLK_CON_DIV_CLKCMU_G3D_NOCP,
|
|
CLK_CON_DIV_CLKCMU_CSTAT_NOC,
|
|
CLK_CON_DIV_CLKCMU_DPUB_DSIM,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM,
|
|
CLK_CON_DIV_CLKCMU_VTS_DMIC,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM,
|
|
CLK_CON_DIV_CLKCMU_PERIS_GIC,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7,
|
|
CLK_CON_DIV_CLKCMU_NOCL1B_NOC1,
|
|
CLK_CON_DIV_CLKCMU_LME_LME,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM,
|
|
CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM,
|
|
CLK_CON_DIV_CLKCMU_UFS_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
|
|
CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_0,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_1,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_2,
|
|
CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_DCPHY,
|
|
CLK_CON_DIV_DIV_CLK_CSTAT_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOCP,
|
|
CLK_CON_DIV_CLK_DNC_ADD_CH_CLK,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_DPUF_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK,
|
|
CLK_CON_DIV_CLK_DSU_DDD,
|
|
CLK_CON_DIV_CLK_DSU_STR_DEM_CLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_G3D_DDD,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_EUSB,
|
|
CLK_CON_DIV_DIV_CLK_LME_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_M2M_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_NOCL0_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI02,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI03,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI05,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI11,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_SSP_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2,
|
|
CLK_CON_DIV_DIV_CLK_VTS_NOC,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE,
|
|
CLK_CON_DIV_DIV_CLK_VTS_CPU,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOCP,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOC,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOC,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOC,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOC,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER,
|
|
CLK_CON_DIV_DIV_CLK_G3D_CORE,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOC,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOC,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_MCSC,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOC,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOC,
|
|
CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLKALIVE_GNSS_NOC,
|
|
CLK_CON_GAT_CLKALIVE_UFD_RCO,
|
|
CLK_CON_GAT_CLKALIVE_DNC_RCO,
|
|
CLK_CON_GAT_CLKALIVE_GNPU_RCO,
|
|
CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC,
|
|
CLK_CON_GAT_CLKALIVE_SDMA_RCO,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC,
|
|
CLK_CON_GAT_CLKALIVE_CSIS_RCO,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC,
|
|
CLK_CON_GAT_CLKALIVE_DSP_RCO,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_BRP_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_LME,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CPUCL0_CPM,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CPUCL1_CPM0,
|
|
CLK_CON_GAT_CPUCL1_CPM1,
|
|
CLK_CON_GAT_CPUCL1_CPM2,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CPUCL2_CPM,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK,
|
|
CLK_CON_GAT_DSU_CPM,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0,
|
|
CLK_CON_GAT_G3DCORE_CPM,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK,
|
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CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1,
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CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM,
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CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM,
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CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M,
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CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S,
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CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM,
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CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1,
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CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF,
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CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1,
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CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM,
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CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC1,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC0,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_CLKCMU_HSI1_PCIE,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL,
|
|
CLK_CON_DIV_CLK_DSU_DDD_CTRL,
|
|
CLK_CON_DIV_CLK_G3D_DDD_CTRL,
|
|
CLK_CON_DIV_DIV_CLK_MIF_NOCD,
|
|
CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL,
|
|
CLK_CON_DIV_CLKCMU_OTP,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL,
|
|
CLK_CON_DIV_CLK_MIF_NOCD_S2D,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH,
|
|
QCH_CON_APM_DMA_QCH_APB,
|
|
QCH_CON_CHUB_RTC_QCH,
|
|
QCH_CON_CLKMON_QCH,
|
|
QCH_CON_DBGCORE_UART_QCH,
|
|
QCH_CON_DTZPC_ALIVE_QCH,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH,
|
|
QCH_CON_INTMEM_QCH,
|
|
QCH_CON_LH_AXI_SI_D_APM_QCH,
|
|
QCH_CON_MAILBOX_APM_AP_QCH,
|
|
QCH_CON_MAILBOX_APM_AUD_QCH,
|
|
QCH_CON_MAILBOX_APM_CHUB_QCH,
|
|
QCH_CON_MAILBOX_APM_CP_QCH,
|
|
QCH_CON_MAILBOX_APM_CP_1_QCH,
|
|
QCH_CON_MAILBOX_APM_GNSS_QCH,
|
|
QCH_CON_MAILBOX_APM_VTS_QCH,
|
|
QCH_CON_MAILBOX_AP_CHUB_QCH,
|
|
QCH_CON_MAILBOX_AP_CP_QCH,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH,
|
|
QCH_CON_MAILBOX_AP_GNSS_QCH,
|
|
QCH_CON_MAILBOX_CP_CHUB_QCH,
|
|
QCH_CON_MAILBOX_CP_GNSS_QCH,
|
|
QCH_CON_MAILBOX_GNSS_CHUB_QCH,
|
|
QCH_CON_MAILBOX_SHARED_SRAM_QCH,
|
|
QCH_CON_MCT_ALIVE_QCH,
|
|
QCH_CON_PMU_QCH_PMU,
|
|
QCH_CON_PMU_QCH_PMLINK,
|
|
QCH_CON_PMU_INTR_GEN_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH,
|
|
QCH_CON_RTC_QCH,
|
|
QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_GNSS_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_MODEM_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_APM_QCH,
|
|
QCH_CON_SLH_AXI_SI_IP_APM_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGP_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_PPU_QCH,
|
|
QCH_CON_SPC_ALIVE_QCH,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_P,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_S,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH,
|
|
QCH_CON_SYSREG_ALIVE_QCH,
|
|
QCH_CON_TOP_RTC_QCH,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH,
|
|
QCH_CON_WDT_ALIVE_QCH,
|
|
QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF0,
|
|
QCH_CON_CSIS_PDP_QCH_DMA,
|
|
QCH_CON_CSIS_PDP_QCH_MCB,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF1,
|
|
QCH_CON_CSIS_PDP_QCH_PDP,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_VOTF,
|
|
QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH,
|
|
QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH,
|
|
QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_CSIS_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_CSIS_QCH,
|
|
QCH_CON_LH_AXI_SI_D2_CSIS_QCH,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH,
|
|
QCH_CON_OIS_MCU_TOP_QCH,
|
|
QCH_CON_PPMU_D0_QCH,
|
|
QCH_CON_PPMU_D1_QCH,
|
|
QCH_CON_PPMU_D2_QCH,
|
|
QCH_CON_QE_CSIS_WDMA0_QCH,
|
|
QCH_CON_QE_CSIS_WDMA1_QCH,
|
|
QCH_CON_QE_CSIS_WDMA2_QCH,
|
|
QCH_CON_QE_CSIS_WDMA3_QCH,
|
|
QCH_CON_QE_CSIS_WDMA4_QCH,
|
|
QCH_CON_QE_PDP_D0_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH,
|
|
QCH_CON_SIU_G_PPMU_CSIS_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_CSIS_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2,
|
|
QCH_CON_VGEN_LITE_D0_QCH,
|
|
QCH_CON_VGEN_LITE_D1_QCH,
|
|
QCH_CON_ABOX_QCH_ACLK,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF,
|
|
QCH_CON_ABOX_QCH_BCLK0,
|
|
QCH_CON_ABOX_QCH_BCLK1,
|
|
QCH_CON_ABOX_QCH_BCLK2,
|
|
QCH_CON_ABOX_QCH_BCLK3,
|
|
DMYQCH_CON_ABOX_QCH_CPU,
|
|
QCH_CON_ABOX_QCH_BCLK4,
|
|
QCH_CON_ABOX_QCH_CNT,
|
|
QCH_CON_ABOX_QCH_BCLK5,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB,
|
|
QCH_CON_ABOX_QCH_BCLK6,
|
|
QCH_CON_ABOX_QCH_XCLK0,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK,
|
|
QCH_CON_ABOX_QCH_C2A0,
|
|
QCH_CON_ABOX_QCH_C2A1,
|
|
QCH_CON_ABOX_QCH_XCLK1,
|
|
QCH_CON_ABOX_QCH_XCLK2,
|
|
QCH_CON_ABOX_QCH_CPU0,
|
|
QCH_CON_ABOX_QCH_CPU1,
|
|
QCH_CON_ABOX_QCH_CPU2,
|
|
QCH_CON_ABOX_QCH_NEON0,
|
|
QCH_CON_ABOX_QCH_NEON1,
|
|
QCH_CON_ABOX_QCH_NEON2,
|
|
QCH_CON_ABOX_QCH_L2,
|
|
QCH_CON_ABOX_QCH_CCLK_ACP,
|
|
QCH_CON_ABOX_QCH_ACLK_ACP,
|
|
QCH_CON_ABOX_QCH_ACLK_ASB,
|
|
QCH_CON_AUD_CMU_AUD_QCH,
|
|
QCH_CON_BAAW_D_AUDCHUBVTS_QCH,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH,
|
|
QCH_CON_DMAILBOX_AUD_QCH_PCLK,
|
|
QCH_CON_DMAILBOX_AUD_QCH_ACLK,
|
|
QCH_CON_DMAILBOX_AUD_QCH_CCLK,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC,
|
|
QCH_CON_D_TZPC_AUD_QCH,
|
|
QCH_CON_LH_AXI_MI_PERI_ASB_QCH,
|
|
QCH_CON_LH_AXI_SI_PERI_ASB_QCH,
|
|
QCH_CON_LH_QDI_SI_D_AUD_QCH,
|
|
QCH_CON_MAILBOX_AUD0_QCH,
|
|
QCH_CON_MAILBOX_AUD1_QCH,
|
|
QCH_CON_MAILBOX_AUD2_QCH,
|
|
QCH_CON_MAILBOX_AUD3_QCH,
|
|
QCH_CON_PPMU_AUD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK,
|
|
QCH_CON_SERIAL_LIF_QCH_BCLK,
|
|
QCH_CON_SERIAL_LIF_QCH_ACLK,
|
|
QCH_CON_SERIAL_LIF_QCH_CCLK,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_AUD_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH,
|
|
QCH_CON_SMMU_AUD_QCH_S1,
|
|
QCH_CON_SMMU_AUD_QCH_S2,
|
|
QCH_CON_SYSREG_AUD_QCH,
|
|
QCH_CON_TREX_AUD_QCH,
|
|
QCH_CON_VGEN_LITE_AUD_QCH,
|
|
QCH_CON_WDT_AUD_QCH,
|
|
DMYQCH_CON_ADD_BRP_QCH,
|
|
QCH_CON_BRP_CMU_BRP_QCH,
|
|
QCH_CON_BUSIF_ADD_BRP_QCH,
|
|
QCH_CON_BYRP_QCH,
|
|
QCH_CON_BYRP_QCH_C2S_ZSL,
|
|
QCH_CON_BYRP_QCH_C2S_BYR,
|
|
QCH_CON_D_TZPC_BRP_QCH,
|
|
QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH,
|
|
QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH,
|
|
QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH,
|
|
QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_BRP_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_BRP_QCH,
|
|
QCH_CON_LH_AXI_SI_D2_BRP_QCH,
|
|
QCH_CON_L_SIU_BRP_QCH,
|
|
QCH_CON_PPMU_D0_BRP_QCH,
|
|
QCH_CON_PPMU_D1_BRP_QCH,
|
|
QCH_CON_PPMU_D2_BRP_QCH,
|
|
QCH_CON_RGBP_QCH,
|
|
QCH_CON_RGBP_QCH_VOTF0,
|
|
QCH_CON_RGBP_QCH_VOTF1,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_BRP_QCH,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S2,
|
|
QCH_CON_SYSREG_BRP_QCH,
|
|
QCH_CON_VGEN_LITE_BYRP_QCH,
|
|
QCH_CON_VGEN_LITE_RGBP_QCH,
|
|
QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH,
|
|
QCH_CON_APBIF_GPIO_CHUB_QCH,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH,
|
|
QCH_CON_CM4_CHUB_QCH_CPU,
|
|
QCH_CON_I2C_CHUB_QCH,
|
|
QCH_CON_I3C_CHUB_QCH_S,
|
|
QCH_CON_I3C_CHUB_QCH_P,
|
|
QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH,
|
|
QCH_CON_MAILBOX_CHUB_ABOX_QCH,
|
|
QCH_CON_MAILBOX_CHUB_DNC_QCH,
|
|
QCH_CON_PWM_CHUB_QCH,
|
|
QCH_CON_SPI_I2C_CHUB0_QCH,
|
|
QCH_CON_SPI_I2C_CHUB1_QCH,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH,
|
|
QCH_CON_SYSREG_CHUB_QCH,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH,
|
|
QCH_CON_TIMER_CHUB_QCH,
|
|
QCH_CON_USI_CHUB0_QCH,
|
|
QCH_CON_USI_CHUB1_QCH,
|
|
QCH_CON_USI_CHUB2_QCH,
|
|
QCH_CON_USI_CHUB3_QCH,
|
|
QCH_CON_WDT_CHUB_QCH,
|
|
QCH_CON_APBIF_UPMU_CHUB_QCH,
|
|
QCH_CON_APB_SEMA_DMAILBOX_QCH,
|
|
QCH_CON_APB_SEMA_PDMA_QCH,
|
|
QCH_CON_BAAW_CHUB_QCH,
|
|
QCH_CON_BAAW_LD_CHUBVTS_QCH,
|
|
QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH,
|
|
QCH_CON_CHUB_ALV_QCH_PMU,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK,
|
|
QCH_CON_D_TZPC_CHUBVTS_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH,
|
|
QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH,
|
|
QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH,
|
|
QCH_CON_MAILBOX_VTS_CHUB_QCH,
|
|
QCH_CON_PDMA_CHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH,
|
|
QCH_CON_SWEEPER_LD_CHUBVTS_QCH,
|
|
QCH_CON_SYSREG_CHUBVTS_QCH,
|
|
QCH_CON_VGEN_LITE_CHUBVTS_QCH,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH,
|
|
QCH_CON_CMGP_I2C_QCH,
|
|
QCH_CON_D_TZPC_CMGP_QCH,
|
|
QCH_CON_I2C_CMGP2_QCH,
|
|
QCH_CON_I2C_CMGP3_QCH,
|
|
QCH_CON_I2C_CMGP4_QCH,
|
|
QCH_CON_I2C_CMGP5_QCH,
|
|
QCH_CON_I2C_CMGP6_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGP_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH,
|
|
QCH_CON_SPI_I2C_CMGP0_QCH,
|
|
QCH_CON_SPI_I2C_CMGP1_QCH,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH,
|
|
QCH_CON_USI_CMGP0_QCH,
|
|
QCH_CON_USI_CMGP1_QCH,
|
|
QCH_CON_USI_CMGP2_QCH,
|
|
QCH_CON_USI_CMGP3_QCH,
|
|
QCH_CON_USI_CMGP4_QCH,
|
|
QCH_CON_USI_CMGP5_QCH,
|
|
QCH_CON_USI_CMGP6_QCH,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH,
|
|
QCH_CON_CPUCL0_QCH_CORE0,
|
|
QCH_CON_CPUCL0_QCH_CORE1,
|
|
QCH_CON_CPUCL0_QCH_CORE2,
|
|
QCH_CON_CPUCL0_QCH_CORE3,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX0,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX1,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH,
|
|
QCH_CON_HTU_CPUCL0_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL0_QCH_CLK,
|
|
QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH,
|
|
DMYQCH_CON_STR_CPUCL0_0_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH,
|
|
QCH_CON_BPS_CPUCL0_QCH,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_1_QCH,
|
|
QCH_CON_CFM_CPUCL0_QCH,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH,
|
|
QCH_CON_CSSYS_QCH,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH,
|
|
QCH_CON_LH_ATB_MI_T_BDU_QCH,
|
|
QCH_CON_LH_ATB_MI_T_DDCG3D_QCH,
|
|
QCH_CON_LH_AXI_SI_G_CSSYS_QCH,
|
|
QCH_CON_PMU_PCSM_PM_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH,
|
|
QCH_CON_SECJTAG_QCH,
|
|
QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH,
|
|
QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH,
|
|
QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH,
|
|
QCH_CON_SLH_AXI_MI_IG_ETR_QCH,
|
|
QCH_CON_SLH_AXI_MI_IG_STM_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH,
|
|
QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH,
|
|
QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH,
|
|
QCH_CON_SLH_AXI_SI_IG_ETR_QCH,
|
|
QCH_CON_SLH_AXI_SI_IG_STM_QCH,
|
|
QCH_CON_SYSREG_CPUCL0_QCH,
|
|
QCH_CON_TREX_CPUCL0_QCH,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH,
|
|
QCH_CON_CPUCL1_QCH_CORE4,
|
|
QCH_CON_CPUCL1_QCH_CORE5,
|
|
QCH_CON_CPUCL1_QCH_CORE6,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_CLK,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_CLK,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_CLK,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_PCLK,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH,
|
|
DMYQCH_CON_STR_CPUCL0_1_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH,
|
|
QCH_CON_CPUCL2_QCH_CORE7,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK,
|
|
QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH,
|
|
DMYQCH_CON_STR_CPUCL0_2_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH,
|
|
QCH_CON_D_TZPC_CSIS_QCH,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD,
|
|
QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH,
|
|
QCH_CON_SYSREG_CSIS_QCH,
|
|
QCH_CON_CSTAT_CMU_CSTAT_QCH,
|
|
QCH_CON_D_TZPC_CSTAT_QCH,
|
|
QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH,
|
|
QCH_CON_LH_AXI_SI_D_CSTAT_QCH,
|
|
QCH_CON_PPMU_CSTAT_QCH,
|
|
QCH_CON_SIPU_CSTAT_QCH,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2RD,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2DS,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_CSTAT_QCH,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S1,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S2,
|
|
QCH_CON_SYSREG_CSTAT_QCH,
|
|
QCH_CON_VGEN_LITE_CSTAT0_QCH,
|
|
QCH_CON_VGEN_LITE_CSTAT1_QCH,
|
|
QCH_CON_APBIF_S2D_DBGCORE_QCH,
|
|
QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH,
|
|
QCH_CON_DBGCORE_CMU_DBGCORE_QCH,
|
|
QCH_CON_D_TZPC_DBGCORE_QCH,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE,
|
|
QCH_CON_MDIS_DBGCORE_QCH,
|
|
QCH_CON_MDIS_DBGCORE_QCH_OSC,
|
|
QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH,
|
|
QCH_CON_SLH_AXI_MI_IP_APM_QCH,
|
|
QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH,
|
|
QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH,
|
|
QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH,
|
|
QCH_CON_SYSREG_DBGCORE_QCH,
|
|
QCH_CON_SYSREG_DBGCORE_CORE_QCH,
|
|
QCH_CON_WDT_DBGCORE_QCH,
|
|
DMYQCH_CON_ADD_DNC_QCH,
|
|
DMYQCH_CON_ADM_DAP_DNC_QCH,
|
|
QCH_CON_BAAW_DNCCHUBVTS_QCH,
|
|
QCH_CON_BUSIF_ADD_DNC_QCH,
|
|
QCH_CON_BUSIF_DDD_DNC_QCH,
|
|
QCH_CON_DNC_CMU_DNC_QCH,
|
|
QCH_CON_D_TZPC_DNC_QCH,
|
|
QCH_CON_HTU_DNC_QCH_PCLK,
|
|
QCH_CON_HTU_DNC_QCH_CLK,
|
|
QCH_CON_IP_DNC_QCH,
|
|
QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH,
|
|
QCH_CON_LH_AXI_MI_LP_IPDNC_QCH,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH,
|
|
QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH,
|
|
QCH_CON_LH_AXI_SI_LP_IPDNC_QCH,
|
|
QCH_CON_PPMU_IPDNC_QCH,
|
|
QCH_CON_PPMU_SDMA0_QCH,
|
|
QCH_CON_PPMU_SDMA1_QCH,
|
|
QCH_CON_PPMU_SDMA2_QCH,
|
|
QCH_CON_PPMU_SDMA3_QCH,
|
|
QCH_CON_SIU_G_PPMU_DNC_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_DNC_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_DSP0_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_SDMA_QCH,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S1,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S2,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S1,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S2,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S1,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S2,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S1,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S2,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S1,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S2,
|
|
QCH_CON_SYSREG_DNC_QCH,
|
|
QCH_CON_TREX_D_DNC_QCH,
|
|
QCH_CON_VGEN_DNC_QCH,
|
|
QCH_CON_VGEN_LITE_DNC_QCH,
|
|
QCH_CON_DPUB_QCH_DECON,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM0,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM1,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM2,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM0,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM1,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM2,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH,
|
|
QCH_CON_D_TZPC_DPUB_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_DPUB_QCH,
|
|
QCH_CON_SYSREG_DPUB_QCH,
|
|
QCH_CON_UPI_M0_QCH,
|
|
QCH_CON_DPUF_QCH_DPUF0,
|
|
QCH_CON_DPUF_QCH_VOTF0,
|
|
QCH_CON_DPUF_QCH_DPUF1,
|
|
QCH_CON_DPUF_QCH_VOTF1,
|
|
QCH_CON_DPUF_QCH_SRAMC,
|
|
QCH_CON_DPUF_CMU_DPUF_QCH,
|
|
QCH_CON_D_TZPC_DPUF_QCH,
|
|
QCH_CON_D_TZPC_DPUF1_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF_QCH,
|
|
QCH_CON_PPMU_D0_DPUF0_QCH,
|
|
QCH_CON_PPMU_D0_DPUF1_QCH,
|
|
QCH_CON_PPMU_D1_DPUF0_QCH,
|
|
QCH_CON_PPMU_D1_DPUF1_QCH,
|
|
QCH_CON_SIU_DPUF_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF_QCH,
|
|
QCH_CON_SLH_AXI_SI_D0_DPUF_QCH,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S2,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S2,
|
|
QCH_CON_SYSREG_DPUF_QCH,
|
|
QCH_CON_DPUF1_QCH_DPUF,
|
|
QCH_CON_DPUF1_QCH_VOTF,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH,
|
|
QCH_CON_PPMU_DPUF1D0_QCH,
|
|
QCH_CON_PPMU_DPUF1D1_QCH,
|
|
QCH_CON_SIU_DPUF1_QCH,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF1_QCH,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2,
|
|
QCH_CON_SYSREG_DPUF1_QCH,
|
|
QCH_CON_DRCP_QCH,
|
|
QCH_CON_DRCP_CMU_DRCP_QCH,
|
|
QCH_CON_D_TZPC_DRCP_QCH,
|
|
QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH,
|
|
QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D_DRCP_QCH,
|
|
QCH_CON_PPMU_D_DRCP_QCH,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_DRCP_QCH,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S2,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S1,
|
|
QCH_CON_SYSREG_DRCP_QCH,
|
|
QCH_CON_VGEN_LITE_D_DRCP_QCH,
|
|
QCH_CON_DSP_CMU_DSP_QCH,
|
|
QCH_CON_D_TZPC_DSP_QCH,
|
|
QCH_CON_IP_DSP_QCH,
|
|
QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_DSP_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH,
|
|
QCH_CON_SYSREG_DSP_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE,
|
|
QCH_CON_CLUSTER0_QCH_SCLK,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK,
|
|
QCH_CON_CLUSTER0_QCH_PCLK,
|
|
QCH_CON_CLUSTER0_QCH_PERIPHCLK,
|
|
QCH_CON_CLUSTER0_QCH_PPUCLK,
|
|
QCH_CON_CLUSTER0_QCH_GIC,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH,
|
|
QCH_CON_DSU_CMU_DSU_QCH,
|
|
QCH_CON_HTU_DSU_QCH_PCLK,
|
|
QCH_CON_HTU_DSU_QCH_CLK,
|
|
QCH_CON_LH_ACEL_MI_D0_ACP_QCH,
|
|
QCH_CON_LH_ACEL_MI_D1_ACP_QCH,
|
|
QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH,
|
|
QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH,
|
|
QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH,
|
|
QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH,
|
|
QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH,
|
|
QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH,
|
|
QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_PPU_QCH,
|
|
QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH,
|
|
DMYQCH_CON_STR_CPUCL0_3_QCH,
|
|
QCH_CON_U_DDD_CTRL_CORE__DSU_QCH,
|
|
DMYQCH_CON_BG3D_PWRCTL_QCH,
|
|
QCH_CON_CFM_G3D_QCH,
|
|
QCH_CON_D_TZPC_G3D_QCH,
|
|
QCH_CON_G3D_CMU_G3D_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_G3D_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH,
|
|
QCH_CON_SYSREG_G3D_QCH,
|
|
QCH_CON_ADD_APBIF_G3D_QCH,
|
|
DMYQCH_CON_ADD_G3D_QCH,
|
|
DMYQCH_CON_ADM_DAP_G_G3D_QCH,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D,
|
|
QCH_CON_ASB_G3D_QCH_S_LH_P_G3D,
|
|
QCH_CON_BUSIF_DDC_G3D_QCH,
|
|
QCH_CON_G3DCORE_CMU_G3DCORE_QCH,
|
|
DMYQCH_CON_GPU_QCH_CLK,
|
|
DMYQCH_CON_GPU_QCH_PCLK,
|
|
QCH_CON_HTU_G3D_QCH_PCLK,
|
|
QCH_CON_HTU_G3D_QCH_CLK,
|
|
QCH_CON_LH_ATB_SI_T_DDCG3D_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH,
|
|
QCH_CON_STR_MUX_G3D_QCH_PCLK,
|
|
QCH_CON_STR_MUX_G3D_QCH_CORE,
|
|
QCH_CON_U_DDD_CTRL_CORE__G3D_QCH,
|
|
QCH_CON_D_TZPC_GNPU_QCH,
|
|
QCH_CON_GNPU_CMU_GNPU_QCH,
|
|
QCH_CON_IP_NPUCORE_QCH_CORE,
|
|
QCH_CON_IP_NPUCORE_QCH_SRAM,
|
|
QCH_CON_LH_AXI_MI_LD0_GNPU_QCH,
|
|
QCH_CON_LH_AXI_MI_LD1_GNPU_QCH,
|
|
QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_GNPU_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH,
|
|
QCH_CON_SYSREG_GNPU_QCH,
|
|
QCH_CON_GNSS_CMU_GNSS_QCH,
|
|
QCH_CON_DP_LINK_QCH_OSC_CLK,
|
|
QCH_CON_DP_LINK_QCH_PCLK,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK,
|
|
QCH_CON_D_TZPC_HSI0_QCH,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH,
|
|
QCH_CON_SLH_ACEL_SI_D_HSI0_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH,
|
|
QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_HSI0_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH,
|
|
QCH_CON_SPC_HSI0_QCH,
|
|
QCH_CON_SYSMMU_D_HSI0_QCH,
|
|
QCH_CON_SYSREG_HSI0_QCH,
|
|
QCH_CON_USB32DRD_QCH_S_SUBCTRL,
|
|
QCH_CON_USB32DRD_QCH_S_LINK,
|
|
QCH_CON_USB32DRD_QCH_S_CTRL,
|
|
QCH_CON_USB32DRD_QCH_S_TCA,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBCTL,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBPHY,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH,
|
|
QCH_CON_D_TZPC_HSI1_QCH,
|
|
QCH_CON_GPIO_HSI1_QCH,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH,
|
|
QCH_CON_LH_ACEL_SI_D_HSI1_QCH,
|
|
QCH_CON_PCIE_GEN2_QCH_AXI,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_APB,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI,
|
|
QCH_CON_PCIE_GEN2_QCH_APB,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF,
|
|
QCH_CON_PCIE_GEN2_QCH_PMA_APB,
|
|
QCH_CON_PCIE_GEN2_QCH_UDBG_APB,
|
|
QCH_CON_PCIE_GEN3_QCH_APB,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI,
|
|
QCH_CON_PCIE_GEN3_QCH_AXI,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_APB,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_REF,
|
|
QCH_CON_PCIE_GEN3_QCH_UDBG_APB,
|
|
QCH_CON_PCIE_GEN3_QCH_PMA_APB,
|
|
QCH_CON_PCIE_IA_GEN2_QCH,
|
|
QCH_CON_PCIE_IA_GEN3_QCH,
|
|
QCH_CON_PPMU_HSI1_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_HSI1_QCH,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S1,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S2,
|
|
QCH_CON_SYSREG_HSI1_QCH,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH,
|
|
QCH_CON_D_TZPC_LME_QCH,
|
|
QCH_CON_GDC_QCH,
|
|
QCH_CON_GDC_QCH_C2_M,
|
|
QCH_CON_GDC_QCH_C2_S,
|
|
QCH_CON_LH_ACEL_SI_D_LME_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_LME_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_LME_QCH,
|
|
QCH_CON_LME_QCH_0,
|
|
QCH_CON_LME_CMU_LME_QCH,
|
|
QCH_CON_PPMU_D_LME_QCH,
|
|
QCH_CON_QE_D1_LME_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_LME_QCH,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2,
|
|
QCH_CON_SYSREG_LME_QCH,
|
|
QCH_CON_VGEN_LITE_D_GDC_QCH,
|
|
QCH_CON_VGEN_LITE_D_LME_QCH,
|
|
QCH_CON_D_TZPC_M2M_QCH,
|
|
QCH_CON_FRC_MC_QCH,
|
|
QCH_CON_JPEG0_QCH,
|
|
QCH_CON_JPEG1_QCH,
|
|
QCH_CON_JSQZ_QCH,
|
|
QCH_CON_LH_ACEL_SI_D_M2M_QCH,
|
|
QCH_CON_LH_AXI_MI_FRC_MC_QCH,
|
|
QCH_CON_LH_AXI_SI_FRC_MC_QCH,
|
|
QCH_CON_M2M_QCH,
|
|
QCH_CON_M2M_QCH_VOTF,
|
|
QCH_CON_M2M_CMU_M2M_QCH,
|
|
QCH_CON_PPMU_D_M2M_QCH,
|
|
QCH_CON_QE_FRC_MC_QCH,
|
|
QCH_CON_QE_JPEG0_QCH,
|
|
QCH_CON_QE_JPEG1_QCH,
|
|
QCH_CON_QE_JSQZ_QCH,
|
|
QCH_CON_QE_M2M_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_M2M_QCH,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S2,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S1,
|
|
QCH_CON_SYSREG_M2M_QCH,
|
|
QCH_CON_VGEN_LITE_M2M_QCH,
|
|
QCH_CON_D_TZPC_MCSC_QCH,
|
|
QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH,
|
|
QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH,
|
|
QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH,
|
|
QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC0_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC1_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC2_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC3_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC4_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC5_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC6_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_MCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D2_MCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D3_MCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D4_MCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC0_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC1_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC2_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC3_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC4_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC5_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC6_QCH,
|
|
QCH_CON_MCFP_QCH,
|
|
QCH_CON_MCSC_QCH,
|
|
QCH_CON_MCSC_QCH_C2R,
|
|
QCH_CON_MCSC_QCH_C2W,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH,
|
|
QCH_CON_PPMU_D0_MCSC_QCH,
|
|
QCH_CON_PPMU_D1_MCSC_QCH,
|
|
QCH_CON_PPMU_D2_MCSC_QCH,
|
|
QCH_CON_PPMU_D3_MCSC_QCH,
|
|
QCH_CON_PPMU_D4_MCSC_QCH,
|
|
QCH_CON_SIU_G_PPMU_MCSC_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_MCSC_QCH,
|
|
QCH_CON_SLH_AXI_SI_D0_MCSC_QCH,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S2,
|
|
QCH_CON_SYSREG_MCSC_QCH,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH,
|
|
QCH_CON_VGEN_LITE_D2_MCSC_QCH,
|
|
QCH_CON_D_TZPC_MFC0_QCH,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI,
|
|
QCH_CON_LH_AXI_MI_ID_MFC0_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_MFC0_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_MFC0_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_MFC0_QCH,
|
|
QCH_CON_MFC0_QCH,
|
|
QCH_CON_MFC0_QCH_VOTF,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH,
|
|
QCH_CON_PPMU_MFC0D0_QCH,
|
|
QCH_CON_PPMU_MFC0D1_QCH,
|
|
QCH_CON_PPMU_WFD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH,
|
|
QCH_CON_SIU_G_PPMU_MFC0_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_MFC0_QCH,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2,
|
|
QCH_CON_SYSREG_MFC0_QCH,
|
|
QCH_CON_VGEN_LITE_MFC0_QCH,
|
|
QCH_CON_WFD_QCH,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH,
|
|
QCH_CON_D_TZPC_MFC1_QCH,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_MFC1_QCH,
|
|
QCH_CON_LH_AXI_SI_D1_MFC1_QCH,
|
|
QCH_CON_MFC1_QCH,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH,
|
|
QCH_CON_PPMU_MFC1D0_QCH,
|
|
QCH_CON_PPMU_MFC1D1_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH,
|
|
QCH_CON_SIU_G_PPMU_MFC1_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_MFC1_QCH,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2,
|
|
QCH_CON_SYSREG_MFC1_QCH,
|
|
QCH_CON_VGEN_MFC1_QCH,
|
|
QCH_CON_BUSIF_DDD_MIF_QCH,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH,
|
|
QCH_CON_DMC_QCH,
|
|
QCH_CON_D_TZPC_MIF_QCH,
|
|
QCH_CON_MIF_CMU_MIF_QCH,
|
|
QCH_CON_QCH_ADAPTER_DDRPHY_QCH,
|
|
QCH_CON_QCH_ADAPTER_DMC_QCH,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_MIF_QCH,
|
|
QCH_CON_SPC_MIF_QCH,
|
|
QCH_CON_SYSREG_MIF_QCH,
|
|
QCH_CON_SYSREG_PRIVATE_MIF_QCH,
|
|
QCH_CON_BAAW_CP_QCH,
|
|
QCH_CON_BAAW_P_GNSS_QCH,
|
|
QCH_CON_BDU_QCH,
|
|
QCH_CON_CACHEAID_NOCL0_QCH,
|
|
DMYQCH_CON_CCI_QCH,
|
|
QCH_CON_CCI_QCH_S,
|
|
DMYQCH_CON_CMU_NOCL0_CMUREF_QCH,
|
|
QCH_CON_D_TZPC_NOCL0_QCH,
|
|
QCH_CON_LH_ACEL_MI_D0_G3D_QCH,
|
|
QCH_CON_LH_ACEL_MI_D1_G3D_QCH,
|
|
QCH_CON_LH_ACEL_MI_D2_G3D_QCH,
|
|
QCH_CON_LH_ACEL_MI_D3_G3D_QCH,
|
|
QCH_CON_LH_ACEL_SI_D0_ACP_QCH,
|
|
QCH_CON_LH_ACEL_SI_D1_ACP_QCH,
|
|
QCH_CON_LH_AST_MI_G_NOCL1A_QCH,
|
|
QCH_CON_LH_AST_MI_G_NOCL1B_QCH,
|
|
QCH_CON_LH_AST_MI_G_NOCL1C_QCH,
|
|
QCH_CON_LH_ATB_SI_T_BDU_QCH,
|
|
QCH_CON_LH_AXI_MI_D_APM_QCH,
|
|
QCH_CON_LH_AXI_MI_G_CSSYS_QCH,
|
|
QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH,
|
|
QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH,
|
|
QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH,
|
|
QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH,
|
|
QCH_CON_LH_QDI_MI_D_AUD_QCH,
|
|
QCH_CON_NOCIF_CMUTOPC_QCH,
|
|
QCH_CON_NOCL0_CMU_NOCL0_QCH,
|
|
QCH_CON_PBHA_GEN_D0_MODEM_QCH,
|
|
QCH_CON_PBHA_GEN_D1_MODEM_QCH,
|
|
QCH_CON_PPC_SCI_QCH,
|
|
QCH_CON_PPMU_APM_QCH,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH,
|
|
QCH_CON_PPMU_G3D0_QCH,
|
|
QCH_CON_PPMU_G3D1_QCH,
|
|
QCH_CON_PPMU_G3D2_QCH,
|
|
QCH_CON_PPMU_G3D3_QCH,
|
|
DMYQCH_CON_PPMU_SYNC_GEN_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH,
|
|
QCH_CON_SIU_G0_PPMU_NOCL0_QCH,
|
|
QCH_CON_SIU_G1_PPMU_NOCL0_QCH,
|
|
QCH_CON_SIU_G2_PPMU_NOCL0_QCH,
|
|
QCH_CON_SIU_G3_PPMU_NOCL0_QCH,
|
|
QCH_CON_SIU_G4_PPMU_NOCL0_QCH,
|
|
QCH_CON_SIU_G5_PPMU_NOCL0_QCH,
|
|
QCH_CON_SLH_ACEL_MI_D_SSP_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH,
|
|
QCH_CON_SLH_AXI_MI_D0_MODEM_QCH,
|
|
QCH_CON_SLH_AXI_MI_D1_MODEM_QCH,
|
|
QCH_CON_SLH_AXI_MI_D2_MODEM_QCH,
|
|
QCH_CON_SLH_AXI_MI_D_UFD_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_APM_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_AUD_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_G3D_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_GNSS_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MCW_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MIF0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MIF1_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MIF2_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MIF3_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MODEM_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC1_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_PERIS_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_SSP_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_UFD_QCH,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S1,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S2,
|
|
QCH_CON_SYSMMU_S2_APM_QCH,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S0,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S1,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S2,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S3,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S4,
|
|
QCH_CON_SYSREG_NOCL0_QCH,
|
|
QCH_CON_TREX_D0_ACP_QCH,
|
|
QCH_CON_TREX_D1_ACP_QCH,
|
|
QCH_CON_TREX_D_NOCL0_QCH,
|
|
QCH_CON_TREX_P_NOCL0_QCH,
|
|
QCH_CON_VGEN_D0_G3D_QCH,
|
|
QCH_CON_VGEN_D1_G3D_QCH,
|
|
QCH_CON_VGEN_D2_G3D_QCH,
|
|
QCH_CON_VGEN_D3_G3D_QCH,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH,
|
|
QCH_CON_WOW_DVFS_D0_CPUCL0_QCH,
|
|
QCH_CON_WOW_DVFS_D0_G3D_QCH,
|
|
QCH_CON_WOW_DVFS_D0_MIF_QCH,
|
|
QCH_CON_WOW_DVFS_D1_CPUCL0_QCH,
|
|
QCH_CON_WOW_DVFS_D1_MIF_QCH,
|
|
QCH_CON_WOW_DVFS_D2_MIF_QCH,
|
|
QCH_CON_WOW_DVFS_D3_MIF_QCH,
|
|
QCH_CON_WOW_DVFS_IRPS0_QCH,
|
|
QCH_CON_WOW_DVFS_IRPS1_QCH,
|
|
QCH_CON_WOW_DVFS_IRPS2_QCH,
|
|
QCH_CON_WOW_DVFS_IRPS3_QCH,
|
|
QCH_CON_WOW_DVFS_NOCL0_QCH,
|
|
QCH_CON_BAAW_P_DNC_QCH,
|
|
DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH,
|
|
QCH_CON_D_TZPC_NOCL1A_QCH,
|
|
QCH_CON_LH_ACEL_MI_D_HSI1_QCH,
|
|
QCH_CON_LH_ACEL_MI_D_LME_QCH,
|
|
QCH_CON_LH_ACEL_MI_D_M2M_QCH,
|
|
QCH_CON_LH_AST_SI_G_NOCL1A_QCH,
|
|
QCH_CON_LH_AXI_MI_D0_MFC0_QCH,
|
|
QCH_CON_LH_AXI_MI_D0_MFC1_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_DPUF_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_MFC0_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_MFC1_QCH,
|
|
QCH_CON_NOCL1A_CMU_NOCL1A_QCH,
|
|
QCH_CON_SIU_2X1_P0_NOCL1A_QCH,
|
|
QCH_CON_SIU_4X1_P0_NOCL1A_QCH,
|
|
QCH_CON_SIU_8X1_P0_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH,
|
|
QCH_CON_SLH_AXI_MI_D0_DPUF_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_DNC_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_DPUB_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_DPUF_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_HSI1_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_LME_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_M2M_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MFC0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MFC1_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC2_QCH,
|
|
QCH_CON_SYSREG_NOCL1A_QCH,
|
|
QCH_CON_TREX_D_NOCL1A_QCH,
|
|
QCH_CON_TREX_P_NOCL1A_QCH,
|
|
DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH,
|
|
QCH_CON_DIT_QCH,
|
|
QCH_CON_D_TZPC_NOCL1B_QCH,
|
|
QCH_CON_LH_ACEL_MI_D_UFS_QCH,
|
|
QCH_CON_LH_ACEL_MI_ID_DIT_QCH,
|
|
QCH_CON_LH_ACEL_SI_ID_DIT_QCH,
|
|
QCH_CON_LH_AST_SI_G_NOCL1B_QCH,
|
|
QCH_CON_LH_AXI_MI_ID_TT_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_TT_QCH,
|
|
QCH_CON_NOCL1B_CMU_NOCL1B_QCH,
|
|
QCH_CON_PDMA_QCH,
|
|
QCH_CON_PPMU_DIT_QCH,
|
|
QCH_CON_PPMU_D_TT_QCH,
|
|
QCH_CON_QE_PDMA_QCH,
|
|
QCH_CON_QE_SPDMA_QCH,
|
|
QCH_CON_SIU_8X1_P0_NOCL1B_QCH,
|
|
QCH_CON_SLH_ACEL_MI_D_HSI0_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_HSI0_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_UFS_QCH,
|
|
QCH_CON_SPDMA_QCH,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH,
|
|
QCH_CON_SYSMMU_S2_TT_QCH,
|
|
QCH_CON_SYSREG_NOCL1B_QCH,
|
|
QCH_CON_TREX_D_NOCL1B_QCH,
|
|
QCH_CON_TREX_P_NOCL1B_QCH,
|
|
QCH_CON_VGEN_LITE_NOCL1B_QCH,
|
|
QCH_CON_VGEN_PDMA_QCH,
|
|
QCH_CON_VGEN_SPDMA_QCH,
|
|
DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH,
|
|
QCH_CON_D_TZPC_NOCL1C_QCH,
|
|
QCH_CON_LH_AST_SI_G_NOCL1C_QCH,
|
|
QCH_CON_LH_AXI_MI_D0_BRP_QCH,
|
|
QCH_CON_LH_AXI_MI_D0_CSIS_QCH,
|
|
QCH_CON_LH_AXI_MI_D0_YUVP_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_BRP_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_CSIS_QCH,
|
|
QCH_CON_LH_AXI_MI_D1_MCSC_QCH,
|
|
QCH_CON_LH_AXI_MI_D2_BRP_QCH,
|
|
QCH_CON_LH_AXI_MI_D2_CSIS_QCH,
|
|
QCH_CON_LH_AXI_MI_D2_MCSC_QCH,
|
|
QCH_CON_LH_AXI_MI_D3_MCSC_QCH,
|
|
QCH_CON_LH_AXI_MI_D4_MCSC_QCH,
|
|
QCH_CON_LH_AXI_MI_D_CSTAT_QCH,
|
|
QCH_CON_NOCL1C_CMU_NOCL1C_QCH,
|
|
QCH_CON_SIU_8X1_P0_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH,
|
|
QCH_CON_SLH_AXI_MI_D0_MCSC_QCH,
|
|
QCH_CON_SLH_AXI_MI_D1_YUVP_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_BRP_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_CSIS_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_CSTAT_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_MCSC_QCH,
|
|
QCH_CON_SLH_AXI_SI_P_YUVP_QCH,
|
|
QCH_CON_SYSREG_NOCL1C_QCH,
|
|
QCH_CON_TREX_D_NOCL1C_QCH,
|
|
QCH_CON_TREX_P_NOCL1C_QCH,
|
|
QCH_CON_D_TZPC_PERIC0_QCH,
|
|
QCH_CON_GPIO_PERIC0_QCH,
|
|
QCH_CON_I3C00_QCH_S,
|
|
QCH_CON_I3C00_QCH_P,
|
|
QCH_CON_I3C01_QCH_S,
|
|
QCH_CON_I3C01_QCH_P,
|
|
QCH_CON_I3C02_QCH_S,
|
|
QCH_CON_I3C02_QCH_P,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC0_QCH,
|
|
QCH_CON_SYSREG_PERIC0_QCH,
|
|
QCH_CON_USI04_I2C_QCH,
|
|
QCH_CON_USI04_USI_QCH,
|
|
QCH_CON_BT_UART_QCH,
|
|
QCH_CON_D_TZPC_PERIC1_QCH,
|
|
QCH_CON_GPIO_PERIC1_QCH,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC1_QCH,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH,
|
|
QCH_CON_SYSREG_PERIC1_QCH,
|
|
QCH_CON_USI07_SPI_I2C_QCH,
|
|
QCH_CON_USI07_USI_QCH,
|
|
QCH_CON_USI08_SPI_I2C_QCH,
|
|
QCH_CON_USI08_USI_QCH,
|
|
QCH_CON_USI09_I2C_QCH,
|
|
QCH_CON_USI09_USI_QCH,
|
|
QCH_CON_USI10_I2C_QCH,
|
|
QCH_CON_USI10_USI_QCH,
|
|
QCH_CON_DBG_UART_QCH,
|
|
QCH_CON_D_TZPC_PERIC2_QCH,
|
|
QCH_CON_GPIO_PERIC2_QCH,
|
|
QCH_CON_I3C03_OIS_QCH_S,
|
|
QCH_CON_I3C03_OIS_QCH_P,
|
|
QCH_CON_I3C04_QCH_S,
|
|
QCH_CON_I3C04_QCH_P,
|
|
QCH_CON_I3C05_QCH_S,
|
|
QCH_CON_I3C05_QCH_P,
|
|
QCH_CON_I3C06_QCH_S,
|
|
QCH_CON_I3C06_QCH_P,
|
|
QCH_CON_I3C07_QCH_S,
|
|
QCH_CON_I3C07_QCH_P,
|
|
QCH_CON_I3C08_QCH_S,
|
|
QCH_CON_I3C08_QCH_P,
|
|
QCH_CON_I3C09_QCH_S,
|
|
QCH_CON_I3C09_QCH_P,
|
|
QCH_CON_I3C10_QCH_S,
|
|
QCH_CON_I3C10_QCH_P,
|
|
QCH_CON_I3C11_QCH_S,
|
|
QCH_CON_I3C11_QCH_P,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH,
|
|
QCH_CON_PWM_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC2_QCH,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH,
|
|
QCH_CON_SYSREG_PERIC2_QCH,
|
|
QCH_CON_USI00_SPI_I2C_QCH,
|
|
QCH_CON_USI00_USI_QCH,
|
|
QCH_CON_USI01_SPI_I2C_QCH,
|
|
QCH_CON_USI01_USI_QCH,
|
|
QCH_CON_USI02_I2C_QCH,
|
|
QCH_CON_USI02_USI_QCH,
|
|
QCH_CON_USI03_I2C_QCH,
|
|
QCH_CON_USI03_USI_QCH,
|
|
QCH_CON_USI05_I2C_QCH,
|
|
QCH_CON_USI05_USI_OIS_QCH,
|
|
QCH_CON_USI06_I2C_QCH,
|
|
QCH_CON_USI06_USI_OIS_QCH,
|
|
QCH_CON_USI11_I2C_QCH,
|
|
QCH_CON_USI11_USI_QCH,
|
|
QCH_CON_BUSIF_DDD_PERIS_QCH,
|
|
DMYQCH_CON_DFTMUX_PERIS_QCH,
|
|
QCH_CON_D_TZPC_PERIS_QCH,
|
|
QCH_CON_GIC_QCH,
|
|
QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH,
|
|
QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH,
|
|
QCH_CON_MCT_QCH,
|
|
QCH_CON_OTP_CON_BIRA_QCH,
|
|
QCH_CON_OTP_CON_TOP_QCH,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_PERIS_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH,
|
|
QCH_CON_SYSREG_PERIS_QCH,
|
|
QCH_CON_TMU_SUB_QCH,
|
|
QCH_CON_TMU_TOP_QCH,
|
|
QCH_CON_WDT0_QCH,
|
|
QCH_CON_WDT1_QCH,
|
|
DMYQCH_CON_BIS_S2D_QCH,
|
|
QCH_CON_S2D_CMU_S2D_QCH,
|
|
QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH,
|
|
QCH_CON_D_TZPC_SDMA_QCH,
|
|
QCH_CON_IP_SDMA_QCH,
|
|
QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH,
|
|
QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH,
|
|
QCH_CON_SDMA_CMU_SDMA_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_SDMA_QCH,
|
|
QCH_CON_SYSREG_SDMA_QCH,
|
|
QCH_CON_BAAW_SSS_QCH,
|
|
QCH_CON_D_TZPC_SSP_QCH,
|
|
QCH_CON_HW_APBSEMA_MEC_QCH,
|
|
QCH_CON_LH_AXI_MI_L_STRONG_QCH,
|
|
QCH_CON_PPMU_SSP_QCH,
|
|
QCH_CON_QE_SSS_QCH,
|
|
QCH_CON_QE_STRONG_QCH,
|
|
QCH_CON_SLH_ACEL_SI_D_SSP_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_SSP_QCH,
|
|
QCH_CON_SSP_CMU_SSP_QCH,
|
|
QCH_CON_SSS_QCH,
|
|
QCH_CON_SYSMMU_SSP_QCH,
|
|
QCH_CON_SYSREG_SSP_QCH,
|
|
QCH_CON_VGEN_LITE_SSP_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH,
|
|
QCH_CON_STRONG_CMU_STRONG_QCH,
|
|
QCH_CON_BAAW_D_UFDDNC_QCH,
|
|
QCH_CON_D_TZPC_UFD_QCH,
|
|
QCH_CON_I3C_UFD_QCH_PCLK,
|
|
QCH_CON_I3C_UFD_QCH_SCLK,
|
|
QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH,
|
|
QCH_CON_PDMA_UFD_QCH,
|
|
QCH_CON_PPMU_D_UFD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH,
|
|
QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_UFD_QCH,
|
|
QCH_CON_SLH_AXI_SI_D_UFD_QCH,
|
|
QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH,
|
|
QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH,
|
|
QCH_CON_SRAM_MIU_UFD_QCH,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S1,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S2,
|
|
QCH_CON_SYSREG_UFD_QCH,
|
|
QCH_CON_SYSREG_UFD_SECURE_QCH,
|
|
QCH_CON_UFD_CMU_UFD_QCH,
|
|
QCH_CON_VGEN_LITE_D_UFD_QCH,
|
|
QCH_CON_UFD_QCH,
|
|
QCH_CON_D_TZPC_UFS_QCH,
|
|
QCH_CON_GPIO_HSI1UFS_QCH,
|
|
QCH_CON_GPIO_UFS_QCH,
|
|
QCH_CON_LH_ACEL_SI_D_UFS_QCH,
|
|
QCH_CON_MMC_CARD_QCH,
|
|
QCH_CON_PPMU_UFS_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_UFS_QCH,
|
|
QCH_CON_SPC_UFS_QCH,
|
|
QCH_CON_SYSMMU_UFS_QCH_S2,
|
|
QCH_CON_SYSREG_UFS_QCH,
|
|
QCH_CON_UFS_CMU_UFS_QCH,
|
|
QCH_CON_UFS_EMBD_QCH_FMP,
|
|
QCH_CON_UFS_EMBD_QCH,
|
|
QCH_CON_VGEN_LITE_UFS_QCH,
|
|
QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT,
|
|
QCH_CON_BAAW_VTS_QCH,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC,
|
|
QCH_CON_GPIO_VTS_QCH,
|
|
QCH_CON_INTMEM_CODE_QCH,
|
|
QCH_CON_INTMEM_DATA0_QCH,
|
|
QCH_CON_INTMEM_DATA1_QCH,
|
|
QCH_CON_INTMEM_PCM_QCH,
|
|
QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH,
|
|
QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH,
|
|
QCH_CON_MAILBOX_DNC_VTS_QCH,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_PCLK,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_CCLK,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_ACLK,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_BCLK,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK,
|
|
QCH_CON_SYSREG_VTS_QCH,
|
|
QCH_CON_TIMER_QCH,
|
|
QCH_CON_TIMER1_QCH,
|
|
QCH_CON_TIMER2_QCH,
|
|
QCH_CON_VTS_CMU_VTS_QCH,
|
|
QCH_CON_WDT_VTS_QCH,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK,
|
|
QCH_CON_BUSIF_DDD_YUVP_QCH,
|
|
QCH_CON_D_TZPC_YUVP_QCH,
|
|
QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH,
|
|
QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH,
|
|
QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH,
|
|
QCH_CON_LH_AXI_SI_D0_YUVP_QCH,
|
|
QCH_CON_PPMU_D0_YUVP_QCH,
|
|
QCH_CON_PPMU_D1_YUVP_QCH,
|
|
QCH_CON_SIU_G_PPMU_YUVP_QCH,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH,
|
|
QCH_CON_SLH_AXI_MI_P_YUVP_QCH,
|
|
QCH_CON_SLH_AXI_SI_D1_YUVP_QCH,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S2,
|
|
QCH_CON_SYSREG_YUVP_QCH,
|
|
QCH_CON_VGEN_LITE_D0_YUVP_QCH,
|
|
QCH_CON_VGEN_LITE_D1_YUVP_QCH,
|
|
QCH_CON_YUVP_QCH,
|
|
QCH_CON_YUVP_QCH_VOTF0,
|
|
QCH_CON_YUVP_QCH_VOTF1,
|
|
QCH_CON_YUVP_CMU_YUVP_QCH,
|
|
ALIVE_CMU_ALIVE_CONTROLLER_OPTION,
|
|
ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION,
|
|
AUD_CMU_AUD_CONTROLLER_OPTION,
|
|
BRP_CMU_BRP_CONTROLLER_OPTION,
|
|
CHUB_CMU_CHUB_CONTROLLER_OPTION,
|
|
CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION,
|
|
CSTAT_CMU_CSTAT_CONTROLLER_OPTION,
|
|
DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION,
|
|
DNC_CMU_DNC_CONTROLLER_OPTION,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION,
|
|
DPUF_CMU_DPUF_CONTROLLER_OPTION,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION,
|
|
DRCP_CMU_DRCP_CONTROLLER_OPTION,
|
|
DSP_CMU_DSP_CONTROLLER_OPTION,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION,
|
|
G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION,
|
|
GNPU_CMU_GNPU_CONTROLLER_OPTION,
|
|
GNSS_CMU_GNSS_CONTROLLER_OPTION,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION,
|
|
LME_CMU_LME_CONTROLLER_OPTION,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION,
|
|
NOCL0_CMU_NOCL0_CONTROLLER_OPTION,
|
|
NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION,
|
|
NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION,
|
|
NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION,
|
|
SDMA_CMU_SDMA_CONTROLLER_OPTION,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION,
|
|
STRONG_CMU_STRONG_CONTROLLER_OPTION,
|
|
UFD_CMU_UFD_CONTROLLER_OPTION,
|
|
UFS_CMU_UFS_CONTROLLER_OPTION,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION,
|
|
YUVP_CMU_YUVP_CONTROLLER_OPTION,
|
|
end_of_sfr,
|
|
num_of_sfr = end_of_sfr - SFR_TYPE,
|
|
};
|
|
|
|
enum sfr_access_id {
|
|
PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME = SFR_ACCESS_TYPE,
|
|
PLL_CON3_PLL_AUD_ENABLE,
|
|
PLL_CON3_PLL_AUD_STABLE,
|
|
PLL_CON3_PLL_AUD_DIV_P,
|
|
PLL_CON3_PLL_AUD_DIV_M,
|
|
PLL_CON3_PLL_AUD_DIV_S,
|
|
PLL_CON8_PLL_AUD_F,
|
|
PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MMC_ENABLE,
|
|
PLL_CON3_PLL_MMC_STABLE,
|
|
PLL_CON3_PLL_MMC_DIV_P,
|
|
PLL_CON3_PLL_MMC_DIV_M,
|
|
PLL_CON3_PLL_MMC_DIV_S,
|
|
PLL_CON8_PLL_MMC_F,
|
|
PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED0_ENABLE,
|
|
PLL_CON3_PLL_SHARED0_STABLE,
|
|
PLL_CON3_PLL_SHARED0_DIV_P,
|
|
PLL_CON3_PLL_SHARED0_DIV_M,
|
|
PLL_CON3_PLL_SHARED0_DIV_S,
|
|
PLL_CON8_PLL_SHARED0_F,
|
|
PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED1_ENABLE,
|
|
PLL_CON3_PLL_SHARED1_STABLE,
|
|
PLL_CON3_PLL_SHARED1_DIV_P,
|
|
PLL_CON3_PLL_SHARED1_DIV_M,
|
|
PLL_CON3_PLL_SHARED1_DIV_S,
|
|
PLL_CON8_PLL_SHARED1_F,
|
|
PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED2_ENABLE,
|
|
PLL_CON3_PLL_SHARED2_STABLE,
|
|
PLL_CON3_PLL_SHARED2_DIV_P,
|
|
PLL_CON3_PLL_SHARED2_DIV_M,
|
|
PLL_CON3_PLL_SHARED2_DIV_S,
|
|
PLL_CON8_PLL_SHARED2_F,
|
|
PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED3_ENABLE,
|
|
PLL_CON3_PLL_SHARED3_STABLE,
|
|
PLL_CON3_PLL_SHARED3_DIV_P,
|
|
PLL_CON3_PLL_SHARED3_DIV_M,
|
|
PLL_CON3_PLL_SHARED3_DIV_S,
|
|
PLL_CON8_PLL_SHARED3_F,
|
|
PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED4_ENABLE,
|
|
PLL_CON3_PLL_SHARED4_STABLE,
|
|
PLL_CON3_PLL_SHARED4_DIV_P,
|
|
PLL_CON3_PLL_SHARED4_DIV_M,
|
|
PLL_CON3_PLL_SHARED4_DIV_S,
|
|
PLL_CON8_PLL_SHARED4_F,
|
|
PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED_MIF_ENABLE,
|
|
PLL_CON3_PLL_SHARED_MIF_STABLE,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_P,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_M,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_S,
|
|
PLL_CON8_PLL_SHARED_MIF_F,
|
|
PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL0_ENABLE,
|
|
PLL_CON3_PLL_CPUCL0_STABLE,
|
|
PLL_CON3_PLL_CPUCL0_DIV_P,
|
|
PLL_CON3_PLL_CPUCL0_DIV_M,
|
|
PLL_CON3_PLL_CPUCL0_DIV_S,
|
|
PLL_CON8_PLL_CPUCL0_F,
|
|
PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL1_ENABLE,
|
|
PLL_CON3_PLL_CPUCL1_STABLE,
|
|
PLL_CON3_PLL_CPUCL1_DIV_P,
|
|
PLL_CON3_PLL_CPUCL1_DIV_M,
|
|
PLL_CON3_PLL_CPUCL1_DIV_S,
|
|
PLL_CON8_PLL_CPUCL1_F,
|
|
PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL2_ENABLE,
|
|
PLL_CON3_PLL_CPUCL2_STABLE,
|
|
PLL_CON3_PLL_CPUCL2_DIV_P,
|
|
PLL_CON3_PLL_CPUCL2_DIV_M,
|
|
PLL_CON3_PLL_CPUCL2_DIV_S,
|
|
PLL_CON8_PLL_CPUCL2_F,
|
|
PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_DSU_ENABLE,
|
|
PLL_CON3_PLL_DSU_STABLE,
|
|
PLL_CON3_PLL_DSU_DIV_P,
|
|
PLL_CON3_PLL_DSU_DIV_M,
|
|
PLL_CON3_PLL_DSU_DIV_S,
|
|
PLL_CON8_PLL_DSU_F,
|
|
PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_G3D_ENABLE,
|
|
PLL_CON3_PLL_G3D_STABLE,
|
|
PLL_CON3_PLL_G3D_DIV_P,
|
|
PLL_CON3_PLL_G3D_DIV_M,
|
|
PLL_CON3_PLL_G3D_DIV_S,
|
|
PLL_CON8_PLL_G3D_F,
|
|
PLL_LOCKTIME_PLL_G3D1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_G3D1_ENABLE,
|
|
PLL_CON3_PLL_G3D1_STABLE,
|
|
PLL_CON3_PLL_G3D1_DIV_P,
|
|
PLL_CON3_PLL_G3D1_DIV_M,
|
|
PLL_CON3_PLL_G3D1_DIV_S,
|
|
PLL_CON8_PLL_G3D1_F,
|
|
PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_MAIN_ENABLE,
|
|
PLL_CON3_PLL_MIF_MAIN_STABLE,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_P,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_M,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_S,
|
|
PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_SUB_ENABLE,
|
|
PLL_CON3_PLL_MIF_SUB_STABLE,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_P,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_M,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_S,
|
|
PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_S2D_ENABLE,
|
|
PLL_CON3_PLL_MIF_S2D_STABLE,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_P,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_M,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_S,
|
|
CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_AUDIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_AUDIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SCLK_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SCLK_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CHUB_TIMER_SELECT,
|
|
CLK_CON_MUX_MUX_CHUB_TIMER_BUSY,
|
|
CLK_CON_MUX_MUX_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI5_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI5_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI6_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI6_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPUF_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DPUF_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPUF_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPUB_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DPUB_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPUB_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_SHARED0_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_SHARED0_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_SHARED1_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_SHARED1_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_SHARED2_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_SHARED2_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_LME_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_LME_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_AUD_CPU_SELECT,
|
|
CLK_CON_MUX_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF0_SELECT,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF0_BUSY,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF1_SELECT,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF1_BUSY,
|
|
CLK_CON_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_SELECT,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_SELECT,
|
|
CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_SELECT,
|
|
CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_BUSY,
|
|
CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DSU_SWITCH_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DSU_SWITCH_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DNC_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DNC_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_SDMA_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_SDMA_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DSP_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DSP_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_G3D_SWITCH_SELECT,
|
|
CLK_CON_MUX_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_GNPU_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_GNPU_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_M2M_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_M2M_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_M2M_FRC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_M2M_FRC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_MCSC_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_MCSC_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_MCSC_MCSC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_MCSC_MCSC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_NOCL0_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_NOCL0_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_NOCL1A_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_NOCL1A_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_SELECT,
|
|
CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_BUSY,
|
|
CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_NOCL1C_NOC_SELECT,
|
|
CLK_CON_MUX_CLKCMU_NOCL1C_NOC_BUSY,
|
|
CLK_CON_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CP_SHARED0_CLK_SELECT,
|
|
CLK_CON_MUX_CP_SHARED0_CLK_BUSY,
|
|
CLK_CON_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CP_SHARED2_CLK_SELECT,
|
|
CLK_CON_MUX_CP_SHARED2_CLK_BUSY,
|
|
CLK_CON_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CP_HISPEEDY_CLK_SELECT,
|
|
CLK_CON_MUX_CP_HISPEEDY_CLK_BUSY,
|
|
CLK_CON_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_SELECT,
|
|
CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_BUSY,
|
|
CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DNC_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DNC_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSP_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSP_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_POWERIP_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_POWERIP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_POWERIP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DDD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DDD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_HTU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_HTU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DDD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DDD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_PLL_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_PLL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_PLL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_GNPU_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_GNPU_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_NOCL1C_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_NOCL1C_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_NOCL1C_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI02_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI02_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI03_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI03_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI05_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI05_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI11_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI11_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_SDMA_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_SDMA_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_UFD_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_UFD_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_NOC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_NOC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY,
|
|
PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_BUSY,
|
|
PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY,
|
|
PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLK_AUD_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLK_AUD_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLK_AUD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_BRP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_USER_BUSY,
|
|
PLL_CON1_MUX_CP_MPLL_CLK_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_BUSY,
|
|
PLL_CON1_MUX_CP_MPLL_CLK_D2_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_BUSY,
|
|
PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_LME_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_LME_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_LME_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_LME_LME_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_LME_LME_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_LME_LME_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_M2M_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_M2M_FRC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY,
|
|
PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY,
|
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PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_BUSY,
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|
PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL,
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PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY,
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|
PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_BUSY,
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|
PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_MUX_SEL,
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PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_BUSY,
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PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_BUSY,
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|
PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_SSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_BUSY,
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PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_MUX_SEL,
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PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_BUSY,
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PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_UFS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_BUSY,
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PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING,
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PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_BUSY,
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|
PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL,
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|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY,
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|
PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_MUX_SEL,
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|
PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_BUSY,
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|
PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_MUX_SEL,
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PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_BUSY,
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|
PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY,
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|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_BUSY,
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CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_BUSY,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_BUSY,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_BUSY,
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|
CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_BUSY,
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|
CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_BUSY,
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|
CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_OSCCLK_DBGCORE_BUSY,
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|
CLK_CON_MUX_MUX_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_BUSY,
|
|
CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_DSU_STRMUX_BUSY,
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|
CLK_CON_MUX_MUX_CLK_DSU_STRMUX_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_G3D_STRMUX_BUSY,
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|
CLK_CON_MUX_MUX_CLK_G3D_STRMUX_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY,
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|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_UFD_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_UFD_NOC_BUSY,
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|
CLK_CON_DIV_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_NOC_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_NOC_BUSY,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_CMGP_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_CMGP_NOC_BUSY,
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|
CLK_CON_DIV_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_BUSY,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_CMGP_PERI_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_CMGP_PERI_BUSY,
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|
CLK_CON_DIV_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_CHUB_PERI_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_CHUB_PERI_BUSY,
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|
CLK_CON_DIV_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_BUSY,
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|
CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_DNC_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_DNC_NOC_BUSY,
|
|
CLK_CON_DIV_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKALIVE_GNPU_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_GNPU_NOC_BUSY,
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|
CLK_CON_DIV_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_SDMA_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_SDMA_NOC_BUSY,
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|
CLK_CON_DIV_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_BUSY,
|
|
CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKALIVE_CSIS_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_CSIS_NOC_BUSY,
|
|
CLK_CON_DIV_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKALIVE_DSP_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKALIVE_DSP_NOC_BUSY,
|
|
CLK_CON_DIV_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKAUD_HSI0_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKAUD_HSI0_NOC_BUSY,
|
|
CLK_CON_DIV_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_AUD_MCLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_AUD_MCLK_BUSY,
|
|
CLK_CON_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI5_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI5_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI6_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI6_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPOSC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPOSC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIS_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIS_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_BUSY,
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|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BRP_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_BRP_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_YUVP_NOC_DIVRATIO,
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|
CLK_CON_DIV_CLKCMU_YUVP_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_BUSY,
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|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_DIVRATIO,
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|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_LME_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_LME_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_AUD_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_AUD_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_DCPHY_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_DCPHY_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_BUSY,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_SSP_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_SSP_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G3D_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_G3D_NOCP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSTAT_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSTAT_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DPUB_DSIM_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_DPUB_DSIM_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VTS_DMIC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_VTS_DMIC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIS_GIC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIS_GIC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_LME_LME_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_LME_LME_BUSY,
|
|
CLK_CON_DIV_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_UFS_NOC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_UFS_NOC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_BUSY,
|
|
CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_BUSY,
|
|
CLK_CON_DIV_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_BUSY,
|
|
CLK_CON_DIV_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_0_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_0_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_1_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_1_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_2_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_2_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD_DIVRATIO,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD_BUSY,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUF_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUF_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUF_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_DSU_DDD_DIVRATIO,
|
|
CLK_CON_DIV_CLK_DSU_DDD_BUSY,
|
|
CLK_CON_DIV_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_G3D_DDD_DIVRATIO,
|
|
CLK_CON_DIV_CLK_G3D_DDD_BUSY,
|
|
CLK_CON_DIV_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_EUSB_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_EUSB_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_EUSB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_LME_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_LME_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_LME_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_M2M_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_M2M_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_M2M_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI02_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI02_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI03_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI03_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI05_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI05_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI11_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI11_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_SSP_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_SSP_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_SSP_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_NOC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_CPU_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_CPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_BUSY,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_BUSY,
|
|
CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOCP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOCP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DRCP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_MCSC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_GNSS_NOC_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_GNSS_NOC_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_UFD_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_UFD_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_UFD_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_DNC_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_DNC_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_DNC_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_GNPU_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_GNPU_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_GNPU_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_SDMA_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_SDMA_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_SDMA_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_CSIS_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_CSIS_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_CSIS_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKALIVE_DSP_RCO_CG_VAL,
|
|
CLK_CON_GAT_CLKALIVE_DSP_RCO_MANUAL,
|
|
CLK_CON_GAT_CLKALIVE_DSP_RCO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_CG_VAL,
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CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_MANUAL,
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CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_LME_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_LME_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CPUCL0_CPM_CG_VAL,
|
|
CLK_CON_GAT_CPUCL0_CPM_MANUAL,
|
|
CLK_CON_GAT_CPUCL0_CPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CPUCL1_CPM0_CG_VAL,
|
|
CLK_CON_GAT_CPUCL1_CPM0_MANUAL,
|
|
CLK_CON_GAT_CPUCL1_CPM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CPUCL1_CPM1_CG_VAL,
|
|
CLK_CON_GAT_CPUCL1_CPM1_MANUAL,
|
|
CLK_CON_GAT_CPUCL1_CPM1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CPUCL1_CPM2_CG_VAL,
|
|
CLK_CON_GAT_CPUCL1_CPM2_MANUAL,
|
|
CLK_CON_GAT_CPUCL1_CPM2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CPUCL2_CPM_CG_VAL,
|
|
CLK_CON_GAT_CPUCL2_CPM_MANUAL,
|
|
CLK_CON_GAT_CPUCL2_CPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_CG_VAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_MANUAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_CG_VAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_MANUAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_CG_VAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_MANUAL,
|
|
CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_DSU_CPM_CG_VAL,
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CLK_CON_GAT_DSU_CPM_MANUAL,
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CLK_CON_GAT_DSU_CPM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_G3DCORE_CPM_CG_VAL,
|
|
CLK_CON_GAT_G3DCORE_CPM_MANUAL,
|
|
CLK_CON_GAT_G3DCORE_CPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC1_CG_VAL,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC1_MANUAL,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC0_CG_VAL,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC0_MANUAL,
|
|
CLK_CON_GAT_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_DSU_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_G3D_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APM_DMA_QCH_APB_ENABLE,
|
|
QCH_CON_APM_DMA_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_APM_DMA_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CHUB_RTC_QCH_ENABLE,
|
|
QCH_CON_CHUB_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLKMON_QCH_ENABLE,
|
|
QCH_CON_CLKMON_QCH_CLOCK_REQ,
|
|
QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DBGCORE_UART_QCH_ENABLE,
|
|
QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ,
|
|
QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DTZPC_ALIVE_QCH_ENABLE,
|
|
QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_QCH_ENABLE,
|
|
QCH_CON_INTMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_AUD_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_CP_1_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_CP_1_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_CP_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCT_ALIVE_QCH_ENABLE,
|
|
QCH_CON_MCT_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_MCT_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_QCH_PMU_ENABLE,
|
|
QCH_CON_PMU_QCH_PMU_CLOCK_REQ,
|
|
QCH_CON_PMU_QCH_PMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_QCH_PMLINK_ENABLE,
|
|
QCH_CON_PMU_QCH_PMLINK_CLOCK_REQ,
|
|
QCH_CON_PMU_QCH_PMLINK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_INTR_GEN_QCH_ENABLE,
|
|
QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ,
|
|
QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RTC_QCH_ENABLE,
|
|
QCH_CON_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IP_APM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IP_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IP_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_PPU_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_PPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_PPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPC_ALIVE_QCH_ENABLE,
|
|
QCH_CON_SPC_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_SPC_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_P_ENABLE,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_P_CLOCK_REQ,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_S_ENABLE,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_S_CLOCK_REQ,
|
|
QCH_CON_SPMI_MASTER_PMIC_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ALIVE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TOP_RTC_QCH_ENABLE,
|
|
QCH_CON_TOP_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_TOP_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_ALIVE_QCH_ENABLE,
|
|
QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_ENABLE,
|
|
QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_DMA_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_MCB_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_VOTF_ENABLE,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_VOTF_CLOCK_REQ,
|
|
QCH_CON_CSIS_PDP_QCH_PDP_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OIS_MCU_TOP_QCH_ENABLE,
|
|
QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_WDMA0_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_WDMA0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_WDMA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_WDMA1_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_WDMA1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_WDMA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_WDMA2_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_WDMA2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_WDMA2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_WDMA3_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_WDMA3_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_WDMA3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_WDMA4_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_WDMA4_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_WDMA4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_D0_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_D0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_CSIS_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_ACLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK0_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK1_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK2_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK3_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ABOX_QCH_CPU_ENABLE,
|
|
DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ,
|
|
DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK4_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CNT_ENABLE,
|
|
QCH_CON_ABOX_QCH_CNT_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK5_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK6_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_XCLK0_ENABLE,
|
|
QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_C2A0_ENABLE,
|
|
QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_C2A1_ENABLE,
|
|
QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_XCLK1_ENABLE,
|
|
QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_XCLK2_ENABLE,
|
|
QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CPU0_ENABLE,
|
|
QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CPU1_ENABLE,
|
|
QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CPU2_ENABLE,
|
|
QCH_CON_ABOX_QCH_CPU2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CPU2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_NEON0_ENABLE,
|
|
QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_NEON1_ENABLE,
|
|
QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_NEON2_ENABLE,
|
|
QCH_CON_ABOX_QCH_NEON2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_NEON2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_L2_ENABLE,
|
|
QCH_CON_ABOX_QCH_L2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE,
|
|
QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_ACLK_ACP_ENABLE,
|
|
QCH_CON_ABOX_QCH_ACLK_ACP_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_ACLK_ACP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_ACLK_ASB_ENABLE,
|
|
QCH_CON_ABOX_QCH_ACLK_ASB_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_ACLK_ASB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_AUD_CMU_AUD_QCH_ENABLE,
|
|
QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_D_AUDCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_D_AUDCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_D_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_AUD_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMAILBOX_AUD_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_AUD_QCH_ACLK_ENABLE,
|
|
QCH_CON_DMAILBOX_AUD_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_AUD_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_AUD_QCH_CCLK_ENABLE,
|
|
QCH_CON_DMAILBOX_AUD_QCH_CCLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_AUD_QCH_CCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_AUD_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_PERI_ASB_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_PERI_ASB_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_PERI_ASB_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_PERI_ASB_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_QDI_SI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LH_QDI_SI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_QDI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD0_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD1_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD2_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD3_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_AUD_QCH_ENABLE,
|
|
QCH_CON_PPMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_QCH_BCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_QCH_BCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_QCH_BCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_QCH_ACLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_QCH_CCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_QCH_CCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_QCH_CCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SMMU_AUD_QCH_S1_ENABLE,
|
|
QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SMMU_AUD_QCH_S2_ENABLE,
|
|
QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_AUD_QCH_ENABLE,
|
|
QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_AUD_QCH_ENABLE,
|
|
QCH_CON_TREX_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_AUD_QCH_ENABLE,
|
|
QCH_CON_WDT_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_BRP_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_BRP_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BRP_CMU_BRP_QCH_ENABLE,
|
|
QCH_CON_BRP_CMU_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_BRP_CMU_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_BRP_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BYRP_QCH_ENABLE,
|
|
QCH_CON_BYRP_QCH_CLOCK_REQ,
|
|
QCH_CON_BYRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BYRP_QCH_C2S_ZSL_ENABLE,
|
|
QCH_CON_BYRP_QCH_C2S_ZSL_CLOCK_REQ,
|
|
QCH_CON_BYRP_QCH_C2S_ZSL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BYRP_QCH_C2S_BYR_ENABLE,
|
|
QCH_CON_BYRP_QCH_C2S_BYR_CLOCK_REQ,
|
|
QCH_CON_BYRP_QCH_C2S_BYR_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_BRP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D2_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D2_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D2_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_L_SIU_BRP_QCH_ENABLE,
|
|
QCH_CON_L_SIU_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_L_SIU_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_BRP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_BRP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_BRP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RGBP_QCH_ENABLE,
|
|
QCH_CON_RGBP_QCH_CLOCK_REQ,
|
|
QCH_CON_RGBP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RGBP_QCH_VOTF0_ENABLE,
|
|
QCH_CON_RGBP_QCH_VOTF0_CLOCK_REQ,
|
|
QCH_CON_RGBP_QCH_VOTF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RGBP_QCH_VOTF1_ENABLE,
|
|
QCH_CON_RGBP_QCH_VOTF1_CLOCK_REQ,
|
|
QCH_CON_RGBP_QCH_VOTF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_BRP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_BRP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_BRP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_BRP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BRP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_BYRP_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_BYRP_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_BYRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_RGBP_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_RGBP_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_RGBP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE,
|
|
QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE,
|
|
QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CM4_CHUB_QCH_CPU_ENABLE,
|
|
QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ,
|
|
QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CHUB_QCH_ENABLE,
|
|
QCH_CON_I2C_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_CHUB_QCH_S_ENABLE,
|
|
QCH_CON_I3C_CHUB_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C_CHUB_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_CHUB_QCH_P_ENABLE,
|
|
QCH_CON_I3C_CHUB_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C_CHUB_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_CHUB_ABOX_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_CHUB_ABOX_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_CHUB_ABOX_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_CHUB_DNC_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_CHUB_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_CHUB_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PWM_CHUB_QCH_ENABLE,
|
|
QCH_CON_PWM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_I2C_CHUB0_QCH_ENABLE,
|
|
QCH_CON_SPI_I2C_CHUB0_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_I2C_CHUB0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_I2C_CHUB1_QCH_ENABLE,
|
|
QCH_CON_SPI_I2C_CHUB1_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_ENABLE,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CHUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER_CHUB_QCH_ENABLE,
|
|
QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB0_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB0_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB1_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB1_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB2_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB2_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB3_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB3_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_CHUB_QCH_ENABLE,
|
|
QCH_CON_WDT_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_UPMU_CHUB_QCH_ENABLE,
|
|
QCH_CON_APBIF_UPMU_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_UPMU_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APB_SEMA_DMAILBOX_QCH_ENABLE,
|
|
QCH_CON_APB_SEMA_DMAILBOX_QCH_CLOCK_REQ,
|
|
QCH_CON_APB_SEMA_DMAILBOX_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APB_SEMA_PDMA_QCH_ENABLE,
|
|
QCH_CON_APB_SEMA_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_APB_SEMA_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_CHUB_QCH_ENABLE,
|
|
QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_LD_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_LD_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CHUB_ALV_QCH_PMU_ENABLE,
|
|
QCH_CON_CHUB_ALV_QCH_PMU_CLOCK_REQ,
|
|
QCH_CON_CHUB_ALV_QCH_PMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_ENABLE,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_ENABLE,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_PDMA_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_LD_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_LD_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMGP_I2C_QCH_ENABLE,
|
|
QCH_CON_CMGP_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_CMGP_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CMGP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP2_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP3_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP4_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP5_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP5_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP6_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP6_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP6_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_I2C_CMGP0_QCH_ENABLE,
|
|
QCH_CON_SPI_I2C_CMGP0_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_I2C_CMGP1_QCH_ENABLE,
|
|
QCH_CON_SPI_I2C_CMGP1_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_ENABLE,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP0_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP0_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP1_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP1_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP2_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP2_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP3_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP3_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP4_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP4_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP5_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP5_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP6_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP6_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP6_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_CORE0_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_CORE0_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_CORE0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_CORE1_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_CORE1_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_CORE1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_CORE2_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_CORE2_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_CORE2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_CORE3_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_CORE3_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_CORE3_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX0_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX0_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX1_ENABLE,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX1_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_QCH_COMPLEX1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_STR_CPUCL0_0_QCH_ENABLE,
|
|
DMYQCH_CON_STR_CPUCL0_0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BPS_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CFM_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_CFM_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_CFM_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSSYS_QCH_ENABLE,
|
|
QCH_CON_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_PCSM_PM_QCH_ENABLE,
|
|
QCH_CON_PMU_PCSM_PM_QCH_CLOCK_REQ,
|
|
QCH_CON_PMU_PCSM_PM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SECJTAG_QCH_ENABLE,
|
|
QCH_CON_SECJTAG_QCH_CLOCK_REQ,
|
|
QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IG_ETR_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IG_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IG_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IG_STM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IG_STM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IG_ETR_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IG_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IG_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IG_STM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IG_STM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_QCH_CORE4_ENABLE,
|
|
QCH_CON_CPUCL1_QCH_CORE4_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_QCH_CORE4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_QCH_CORE5_ENABLE,
|
|
QCH_CON_CPUCL1_QCH_CORE5_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_QCH_CORE5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_QCH_CORE6_ENABLE,
|
|
QCH_CON_CPUCL1_QCH_CORE6_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_QCH_CORE6_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_0_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_1_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_STR_CPUCL0_1_QCH_ENABLE,
|
|
DMYQCH_CON_STR_CPUCL0_1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL2_QCH_CORE7_ENABLE,
|
|
QCH_CON_CPUCL2_QCH_CORE7_CLOCK_REQ,
|
|
QCH_CON_CPUCL2_QCH_CORE7_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_STR_CPUCL0_2_QCH_ENABLE,
|
|
DMYQCH_CON_STR_CPUCL0_2_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CSIS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CSIS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSTAT_CMU_CSTAT_QCH_ENABLE,
|
|
QCH_CON_CSTAT_CMU_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_CSTAT_CMU_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CSTAT_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D_CSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CSTAT_QCH_ENABLE,
|
|
QCH_CON_PPMU_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SIPU_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SIPU_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2RD_ENABLE,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2RD_CLOCK_REQ,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2RD_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2DS_ENABLE,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2DS_CLOCK_REQ,
|
|
QCH_CON_SIPU_CSTAT_QCH_C2DS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_CSTAT_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_CSTAT0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_CSTAT0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_CSTAT0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_CSTAT1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_CSTAT1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_CSTAT1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_S2D_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_APBIF_S2D_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_S2D_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DBGCORE_CMU_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_DBGCORE_CMU_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_DBGCORE_CMU_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MDIS_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_MDIS_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_MDIS_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MDIS_DBGCORE_QCH_OSC_ENABLE,
|
|
QCH_CON_MDIS_DBGCORE_QCH_OSC_CLOCK_REQ,
|
|
QCH_CON_MDIS_DBGCORE_QCH_OSC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IP_APM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IP_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IP_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DBGCORE_CORE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DBGCORE_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DBGCORE_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_WDT_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_DNC_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_DNC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_DAP_DNC_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_DNC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_DNCCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_DNCCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_DNC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDD_DNC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDD_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDD_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNC_CMU_DNC_QCH_ENABLE,
|
|
QCH_CON_DNC_CMU_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_DNC_CMU_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DNC_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_DNC_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_DNC_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_DNC_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_DNC_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_DNC_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_DNC_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_DNC_QCH_ENABLE,
|
|
QCH_CON_IP_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_IPDNC_QCH_ENABLE,
|
|
QCH_CON_PPMU_IPDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_IPDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SDMA0_QCH_ENABLE,
|
|
QCH_CON_PPMU_SDMA0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SDMA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SDMA1_QCH_ENABLE,
|
|
QCH_CON_PPMU_SDMA1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SDMA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SDMA2_QCH_ENABLE,
|
|
QCH_CON_PPMU_SDMA2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SDMA2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SDMA3_QCH_ENABLE,
|
|
QCH_CON_PPMU_SDMA3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SDMA3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_DNC_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_DNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_IPDNC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA2_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SDMA3_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DNC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_DNC_QCH_ENABLE,
|
|
QCH_CON_TREX_D_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_DNC_QCH_ENABLE,
|
|
QCH_CON_VGEN_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_DNC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_DECON_ENABLE,
|
|
QCH_CON_DPUB_QCH_DECON_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_DECON_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM0_ENABLE,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM0_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM1_ENABLE,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM1_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM2_ENABLE,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM2_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_ALV_DSIM2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM0_ENABLE,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM0_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM1_ENABLE,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM1_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM2_ENABLE,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM2_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_OSC_DSIM2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUB_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_DPUB_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UPI_M0_QCH_ENABLE,
|
|
QCH_CON_UPI_M0_QCH_CLOCK_REQ,
|
|
QCH_CON_UPI_M0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_QCH_DPUF0_ENABLE,
|
|
QCH_CON_DPUF_QCH_DPUF0_CLOCK_REQ,
|
|
QCH_CON_DPUF_QCH_DPUF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_QCH_VOTF0_ENABLE,
|
|
QCH_CON_DPUF_QCH_VOTF0_CLOCK_REQ,
|
|
QCH_CON_DPUF_QCH_VOTF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_QCH_DPUF1_ENABLE,
|
|
QCH_CON_DPUF_QCH_DPUF1_CLOCK_REQ,
|
|
QCH_CON_DPUF_QCH_DPUF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_QCH_VOTF1_ENABLE,
|
|
QCH_CON_DPUF_QCH_VOTF1_CLOCK_REQ,
|
|
QCH_CON_DPUF_QCH_VOTF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_QCH_SRAMC_ENABLE,
|
|
QCH_CON_DPUF_QCH_SRAMC_CLOCK_REQ,
|
|
QCH_CON_DPUF_QCH_SRAMC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF_CMU_DPUF_QCH_ENABLE,
|
|
QCH_CON_DPUF_CMU_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUF_CMU_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUF_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_DPUF0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_DPUF1_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_DPUF0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_DPUF1_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_DPUF_QCH_ENABLE,
|
|
QCH_CON_SIU_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUF_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_QCH_DPUF_ENABLE,
|
|
QCH_CON_DPUF1_QCH_DPUF_CLOCK_REQ,
|
|
QCH_CON_DPUF1_QCH_DPUF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_QCH_VOTF_ENABLE,
|
|
QCH_CON_DPUF1_QCH_VOTF_CLOCK_REQ,
|
|
QCH_CON_DPUF1_QCH_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_DPUF1_QCH_ENABLE,
|
|
QCH_CON_SIU_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_ENABLE,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUF1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DRCP_QCH_ENABLE,
|
|
QCH_CON_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DRCP_CMU_DRCP_QCH_ENABLE,
|
|
QCH_CON_DRCP_CMU_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_DRCP_CMU_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DRCP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D_DRCP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_DRCP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_ENABLE,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_DRCP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_DRCP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DRCP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D_DRCP_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D_DRCP_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D_DRCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DSP_CMU_DSP_QCH_ENABLE,
|
|
QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ,
|
|
QCH_CON_DSP_CMU_DSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DSP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DSP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_DSP_QCH_ENABLE,
|
|
QCH_CON_IP_DSP_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_DSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_DSP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_DSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_DSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DSP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PPUCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PPUCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PPUCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_GIC_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DSU_CMU_DSU_QCH_ENABLE,
|
|
QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ,
|
|
QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_DSU_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_DSU_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D0_ACP_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D0_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D0_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D1_ACP_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D1_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D1_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_PPU_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_PPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_PPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_STR_CPUCL0_3_QCH_ENABLE,
|
|
DMYQCH_CON_STR_CPUCL0_3_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_BG3D_PWRCTL_QCH_ENABLE,
|
|
DMYQCH_CON_BG3D_PWRCTL_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_BG3D_PWRCTL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CFM_G3D_QCH_ENABLE,
|
|
QCH_CON_CFM_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_CFM_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_G3D_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G3D_CMU_G3D_QCH_ENABLE,
|
|
QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_G3D_QCH_ENABLE,
|
|
QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_ENABLE,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_G3D_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_DAP_G_G3D_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_G_G3D_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_G_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDC_G3D_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDC_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDC_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G3DCORE_CMU_G3DCORE_QCH_ENABLE,
|
|
QCH_CON_G3DCORE_CMU_G3DCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_G3DCORE_CMU_G3DCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_GPU_QCH_CLK_ENABLE,
|
|
DMYQCH_CON_GPU_QCH_CLK_CLOCK_REQ,
|
|
DMYQCH_CON_GPU_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_GPU_QCH_PCLK_ENABLE,
|
|
DMYQCH_CON_GPU_QCH_PCLK_CLOCK_REQ,
|
|
DMYQCH_CON_GPU_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_G3D_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_STR_MUX_G3D_QCH_PCLK_ENABLE,
|
|
QCH_CON_STR_MUX_G3D_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_STR_MUX_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_STR_MUX_G3D_QCH_CORE_ENABLE,
|
|
QCH_CON_STR_MUX_G3D_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_STR_MUX_G3D_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_ENABLE,
|
|
QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_GNPU_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GNPU_CMU_GNPU_QCH_ENABLE,
|
|
QCH_CON_GNPU_CMU_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_GNPU_CMU_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUCORE_QCH_CORE_ENABLE,
|
|
QCH_CON_IP_NPUCORE_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_IP_NPUCORE_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUCORE_QCH_SRAM_ENABLE,
|
|
QCH_CON_IP_NPUCORE_QCH_SRAM_CLOCK_REQ,
|
|
QCH_CON_IP_NPUCORE_QCH_SRAM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_GNPU_QCH_ENABLE,
|
|
QCH_CON_SYSREG_GNPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_GNPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE,
|
|
QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_OSC_CLK_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_OSC_CLK_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_OSC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_PCLK_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_HSI0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPC_HSI0_QCH_ENABLE,
|
|
QCH_CON_SPC_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SPC_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_HSI0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_D_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_HSI0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_SUBCTRL_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_SUBCTRL_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_SUBCTRL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_LINK_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_LINK_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_LINK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_CTRL_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_CTRL_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_CTRL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_TCA_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_TCA_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_TCA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBCTL_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBCTL_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBCTL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBPHY_ENABLE,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBPHY_CLOCK_REQ,
|
|
QCH_CON_USB32DRD_QCH_S_EUSBPHY_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_HSI1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_HSI1_QCH_ENABLE,
|
|
QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_AXI_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_AXI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_AXI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PMA_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PMA_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PMA_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_UDBG_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_UDBG_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_UDBG_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_AXI_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_AXI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_AXI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_REF_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_REF_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_REF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_UDBG_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_UDBG_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_UDBG_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_PMA_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_PMA_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_PMA_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_HSI1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_LME_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_ENABLE,
|
|
QCH_CON_GDC_QCH_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_C2_M_ENABLE,
|
|
QCH_CON_GDC_QCH_C2_M_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_C2_S_ENABLE,
|
|
QCH_CON_GDC_QCH_C2_S_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D_LME_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_LME_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_LME_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LME_QCH_0_ENABLE,
|
|
QCH_CON_LME_QCH_0_CLOCK_REQ,
|
|
QCH_CON_LME_QCH_0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LME_CMU_LME_QCH_ENABLE,
|
|
QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_LME_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D1_LME_QCH_ENABLE,
|
|
QCH_CON_QE_D1_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D1_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_LME_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_LME_QCH_ENABLE,
|
|
QCH_CON_SYSREG_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D_GDC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D_GDC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D_GDC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D_LME_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_M2M_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_FRC_MC_QCH_ENABLE,
|
|
QCH_CON_FRC_MC_QCH_CLOCK_REQ,
|
|
QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JPEG0_QCH_ENABLE,
|
|
QCH_CON_JPEG0_QCH_CLOCK_REQ,
|
|
QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JPEG1_QCH_ENABLE,
|
|
QCH_CON_JPEG1_QCH_CLOCK_REQ,
|
|
QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JSQZ_QCH_ENABLE,
|
|
QCH_CON_JSQZ_QCH_CLOCK_REQ,
|
|
QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D_M2M_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_FRC_MC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_FRC_MC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_FRC_MC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_FRC_MC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_FRC_MC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_FRC_MC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_QCH_ENABLE,
|
|
QCH_CON_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_QCH_VOTF_ENABLE,
|
|
QCH_CON_M2M_QCH_VOTF_CLOCK_REQ,
|
|
QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_CMU_M2M_QCH_ENABLE,
|
|
QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_M2M_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_FRC_MC_QCH_ENABLE,
|
|
QCH_CON_QE_FRC_MC_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_FRC_MC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JPEG0_QCH_ENABLE,
|
|
QCH_CON_QE_JPEG0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JPEG1_QCH_ENABLE,
|
|
QCH_CON_QE_JPEG1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JSQZ_QCH_ENABLE,
|
|
QCH_CON_QE_JSQZ_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_M2M_QCH_ENABLE,
|
|
QCH_CON_QE_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_M2M_QCH_ENABLE,
|
|
QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MCSC_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D3_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D3_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D4_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D4_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCFP_QCH_ENABLE,
|
|
QCH_CON_MCFP_QCH_CLOCK_REQ,
|
|
QCH_CON_MCFP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_ENABLE,
|
|
QCH_CON_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_C2R_ENABLE,
|
|
QCH_CON_MCSC_QCH_C2R_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_C2R_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_C2W_ENABLE,
|
|
QCH_CON_MCSC_QCH_C2W_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_C2W_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D3_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D3_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D3_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D4_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D4_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D4_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_MCSC_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D4_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MCSC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MFC0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_QCH_ENABLE,
|
|
QCH_CON_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_QCH_VOTF_ENABLE,
|
|
QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ,
|
|
QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC0D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC0D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_WFD_QCH_ENABLE,
|
|
QCH_CON_PPMU_WFD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_MFC0_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_MFC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MFC0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_MFC0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WFD_QCH_ENABLE,
|
|
QCH_CON_WFD_QCH_CLOCK_REQ,
|
|
QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MFC1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D1_MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D1_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC1_QCH_ENABLE,
|
|
QCH_CON_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC1D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC1D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_MFC1_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_MFC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MFC1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_MFC1_QCH_ENABLE,
|
|
QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDD_MIF_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDD_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDD_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMC_QCH_ENABLE,
|
|
QCH_CON_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MIF_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIF_CMU_MIF_QCH_ENABLE,
|
|
QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_DDRPHY_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_DDRPHY_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_DDRPHY_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_DMC_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPC_MIF_QCH_ENABLE,
|
|
QCH_CON_SPC_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SPC_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MIF_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PRIVATE_MIF_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PRIVATE_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PRIVATE_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_CP_QCH_ENABLE,
|
|
QCH_CON_BAAW_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_GNSS_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BDU_QCH_ENABLE,
|
|
QCH_CON_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CACHEAID_NOCL0_QCH_ENABLE,
|
|
QCH_CON_CACHEAID_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_CACHEAID_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CCI_QCH_ENABLE,
|
|
DMYQCH_CON_CCI_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CCI_QCH_S_ENABLE,
|
|
QCH_CON_CCI_QCH_S_CLOCK_REQ,
|
|
QCH_CON_CCI_QCH_S_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NOCL0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D0_ACP_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D0_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D0_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D1_ACP_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D1_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D1_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_G_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_G_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_QDI_MI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LH_QDI_MI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_QDI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NOCIF_CMUTOPC_QCH_ENABLE,
|
|
QCH_CON_NOCIF_CMUTOPC_QCH_CLOCK_REQ,
|
|
QCH_CON_NOCIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PBHA_GEN_D0_MODEM_QCH_ENABLE,
|
|
QCH_CON_PBHA_GEN_D0_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_PBHA_GEN_D0_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PBHA_GEN_D1_MODEM_QCH_ENABLE,
|
|
QCH_CON_PBHA_GEN_D1_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_PBHA_GEN_D1_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_SCI_QCH_ENABLE,
|
|
QCH_CON_PPC_SCI_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_SCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_APM_QCH_ENABLE,
|
|
QCH_CON_PPMU_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D2_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D3_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PPMU_SYNC_GEN_QCH_ENABLE,
|
|
DMYQCH_CON_PPMU_SYNC_GEN_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_PPMU_SYNC_GEN_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G0_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G0_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G0_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G1_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G1_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G1_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G2_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G2_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G2_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G3_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G3_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G3_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G4_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G4_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G4_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G5_PPMU_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SIU_G5_PPMU_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G5_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ACEL_MI_D_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_ACEL_MI_D_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ACEL_MI_D_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MODEM_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_APM_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S0_ENABLE,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S0_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S3_ENABLE,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S3_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S3_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S4_ENABLE,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S4_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_G3D_QCH_S4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NOCL0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D0_ACP_QCH_ENABLE,
|
|
QCH_CON_TREX_D0_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D0_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D1_ACP_QCH_ENABLE,
|
|
QCH_CON_TREX_D1_ACP_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D1_ACP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_NOCL0_QCH_ENABLE,
|
|
QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_NOCL0_QCH_ENABLE,
|
|
QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_VGEN_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_D1_G3D_QCH_ENABLE,
|
|
QCH_CON_VGEN_D1_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_D1_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_D2_G3D_QCH_ENABLE,
|
|
QCH_CON_VGEN_D2_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_D2_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_D3_G3D_QCH_ENABLE,
|
|
QCH_CON_VGEN_D3_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_D3_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D0_MIF_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D0_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D0_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D1_MIF_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D1_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D1_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D2_MIF_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D2_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D2_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_D3_MIF_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_D3_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_D3_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_IRPS0_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_IRPS0_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_IRPS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_IRPS1_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_IRPS1_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_IRPS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_IRPS2_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_IRPS2_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_IRPS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_IRPS3_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_IRPS3_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_IRPS3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WOW_DVFS_NOCL0_QCH_ENABLE,
|
|
QCH_CON_WOW_DVFS_NOCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_WOW_DVFS_NOCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_DNC_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D_LME_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D_M2M_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D0_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D0_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D0_MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D0_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_DPUF_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_MFC0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_MFC1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_2X1_P0_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SIU_2X1_P0_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_2X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_4X1_P0_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SIU_4X1_P0_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_4X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_8X1_P0_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SIU_8X1_P0_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_8X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_DNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_DNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_DNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_DPUB_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_DPUF_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_DPUF_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_DPUF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_LME_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MFC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MFC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_NOCL1A_QCH_ENABLE,
|
|
QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DIT_QCH_ENABLE,
|
|
QCH_CON_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_D_UFS_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_D_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_D_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_MI_ID_DIT_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_MI_ID_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_MI_ID_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_ID_DIT_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_ID_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_ID_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_ID_TT_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_ID_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_ID_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_TT_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_QCH_ENABLE,
|
|
QCH_CON_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DIT_QCH_ENABLE,
|
|
QCH_CON_PPMU_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_TT_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDMA_QCH_ENABLE,
|
|
QCH_CON_QE_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_SPDMA_QCH_ENABLE,
|
|
QCH_CON_QE_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_8X1_P0_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SIU_8X1_P0_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_8X1_P0_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_UFS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPDMA_QCH_ENABLE,
|
|
QCH_CON_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_TT_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_TT_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_TT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_NOCL1B_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_NOCL1B_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_NOCL1B_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_PDMA_QCH_ENABLE,
|
|
QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_SPDMA_QCH_ENABLE,
|
|
QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_G_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_G_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D0_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D0_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D0_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D0_YUVP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D0_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D2_BRP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D2_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D2_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D3_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D3_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D4_MCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D4_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_D_CSTAT_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_D_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NOCL1C_CMU_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_NOCL1C_CMU_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_NOCL1C_CMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_8X1_P0_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SIU_8X1_P0_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_8X1_P0_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_BRP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_BRP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_BRP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_P_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_P_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_P_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_TREX_D_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_NOCL1C_QCH_ENABLE,
|
|
QCH_CON_TREX_P_NOCL1C_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_NOCL1C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC0_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C00_QCH_S_ENABLE,
|
|
QCH_CON_I3C00_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C00_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C00_QCH_P_ENABLE,
|
|
QCH_CON_I3C00_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C00_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C01_QCH_S_ENABLE,
|
|
QCH_CON_I3C01_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C01_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C01_QCH_P_ENABLE,
|
|
QCH_CON_I3C01_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C01_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C02_QCH_S_ENABLE,
|
|
QCH_CON_I3C02_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C02_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C02_QCH_P_ENABLE,
|
|
QCH_CON_I3C02_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C02_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI04_I2C_QCH_ENABLE,
|
|
QCH_CON_USI04_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI04_USI_QCH_ENABLE,
|
|
QCH_CON_USI04_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BT_UART_QCH_ENABLE,
|
|
QCH_CON_BT_UART_QCH_CLOCK_REQ,
|
|
QCH_CON_BT_UART_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC1_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI07_SPI_I2C_QCH_ENABLE,
|
|
QCH_CON_USI07_SPI_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI07_SPI_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI07_USI_QCH_ENABLE,
|
|
QCH_CON_USI07_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI08_SPI_I2C_QCH_ENABLE,
|
|
QCH_CON_USI08_SPI_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI08_SPI_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI08_USI_QCH_ENABLE,
|
|
QCH_CON_USI08_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI09_I2C_QCH_ENABLE,
|
|
QCH_CON_USI09_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI09_USI_QCH_ENABLE,
|
|
QCH_CON_USI09_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI10_I2C_QCH_ENABLE,
|
|
QCH_CON_USI10_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI10_USI_QCH_ENABLE,
|
|
QCH_CON_USI10_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DBG_UART_QCH_ENABLE,
|
|
QCH_CON_DBG_UART_QCH_CLOCK_REQ,
|
|
QCH_CON_DBG_UART_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC2_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C03_OIS_QCH_S_ENABLE,
|
|
QCH_CON_I3C03_OIS_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C03_OIS_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C03_OIS_QCH_P_ENABLE,
|
|
QCH_CON_I3C03_OIS_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C03_OIS_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C04_QCH_S_ENABLE,
|
|
QCH_CON_I3C04_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C04_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C04_QCH_P_ENABLE,
|
|
QCH_CON_I3C04_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C04_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C05_QCH_S_ENABLE,
|
|
QCH_CON_I3C05_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C05_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C05_QCH_P_ENABLE,
|
|
QCH_CON_I3C05_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C05_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C06_QCH_S_ENABLE,
|
|
QCH_CON_I3C06_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C06_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C06_QCH_P_ENABLE,
|
|
QCH_CON_I3C06_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C06_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C07_QCH_S_ENABLE,
|
|
QCH_CON_I3C07_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C07_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C07_QCH_P_ENABLE,
|
|
QCH_CON_I3C07_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C07_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C08_QCH_S_ENABLE,
|
|
QCH_CON_I3C08_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C08_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C08_QCH_P_ENABLE,
|
|
QCH_CON_I3C08_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C08_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C09_QCH_S_ENABLE,
|
|
QCH_CON_I3C09_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C09_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C09_QCH_P_ENABLE,
|
|
QCH_CON_I3C09_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C09_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C10_QCH_S_ENABLE,
|
|
QCH_CON_I3C10_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C10_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C10_QCH_P_ENABLE,
|
|
QCH_CON_I3C10_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C10_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C11_QCH_S_ENABLE,
|
|
QCH_CON_I3C11_QCH_S_CLOCK_REQ,
|
|
QCH_CON_I3C11_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C11_QCH_P_ENABLE,
|
|
QCH_CON_I3C11_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C11_QCH_P_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PWM_QCH_ENABLE,
|
|
QCH_CON_PWM_QCH_CLOCK_REQ,
|
|
QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_ENABLE,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC2_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI00_SPI_I2C_QCH_ENABLE,
|
|
QCH_CON_USI00_SPI_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI00_SPI_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI00_USI_QCH_ENABLE,
|
|
QCH_CON_USI00_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI01_SPI_I2C_QCH_ENABLE,
|
|
QCH_CON_USI01_SPI_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI01_SPI_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI01_USI_QCH_ENABLE,
|
|
QCH_CON_USI01_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI02_I2C_QCH_ENABLE,
|
|
QCH_CON_USI02_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI02_USI_QCH_ENABLE,
|
|
QCH_CON_USI02_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI03_I2C_QCH_ENABLE,
|
|
QCH_CON_USI03_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI03_USI_QCH_ENABLE,
|
|
QCH_CON_USI03_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI05_I2C_QCH_ENABLE,
|
|
QCH_CON_USI05_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI05_USI_OIS_QCH_ENABLE,
|
|
QCH_CON_USI05_USI_OIS_QCH_CLOCK_REQ,
|
|
QCH_CON_USI05_USI_OIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI06_I2C_QCH_ENABLE,
|
|
QCH_CON_USI06_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI06_USI_OIS_QCH_ENABLE,
|
|
QCH_CON_USI06_USI_OIS_QCH_CLOCK_REQ,
|
|
QCH_CON_USI06_USI_OIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI11_I2C_QCH_ENABLE,
|
|
QCH_CON_USI11_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI11_USI_QCH_ENABLE,
|
|
QCH_CON_USI11_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDD_PERIS_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDD_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDD_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_PERIS_QCH_ENABLE,
|
|
DMYQCH_CON_DFTMUX_PERIS_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GIC_QCH_ENABLE,
|
|
QCH_CON_GIC_QCH_CLOCK_REQ,
|
|
QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCT_QCH_ENABLE,
|
|
QCH_CON_MCT_QCH_CLOCK_REQ,
|
|
QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_BIRA_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_TOP_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TMU_SUB_QCH_ENABLE,
|
|
QCH_CON_TMU_SUB_QCH_CLOCK_REQ,
|
|
QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TMU_TOP_QCH_ENABLE,
|
|
QCH_CON_TMU_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT0_QCH_ENABLE,
|
|
QCH_CON_WDT0_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT1_QCH_ENABLE,
|
|
QCH_CON_WDT1_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_BIS_S2D_QCH_ENABLE,
|
|
DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_S2D_CMU_S2D_QCH_ENABLE,
|
|
QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ,
|
|
QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_SDMA_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_SDMA_QCH_ENABLE,
|
|
QCH_CON_IP_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SDMA_CMU_SDMA_QCH_ENABLE,
|
|
QCH_CON_SDMA_CMU_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SDMA_CMU_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_SDMA_QCH_ENABLE,
|
|
QCH_CON_SYSREG_SDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_SDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_SSS_QCH_ENABLE,
|
|
QCH_CON_BAAW_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_SSP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE,
|
|
QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ,
|
|
QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_L_STRONG_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_L_STRONG_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_L_STRONG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SSP_QCH_ENABLE,
|
|
QCH_CON_PPMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_SSS_QCH_ENABLE,
|
|
QCH_CON_QE_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_STRONG_QCH_ENABLE,
|
|
QCH_CON_QE_STRONG_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_STRONG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_ACEL_SI_D_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_ACEL_SI_D_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_ACEL_SI_D_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_SSP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SSP_CMU_SSP_QCH_ENABLE,
|
|
QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SSS_QCH_ENABLE,
|
|
QCH_CON_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_SSP_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_SSP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_SSP_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_STRONG_CMU_STRONG_QCH_ENABLE,
|
|
QCH_CON_STRONG_CMU_STRONG_QCH_CLOCK_REQ,
|
|
QCH_CON_STRONG_CMU_STRONG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_D_UFDDNC_QCH_ENABLE,
|
|
QCH_CON_BAAW_D_UFDDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_D_UFDDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_UFD_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_UFD_QCH_PCLK_ENABLE,
|
|
QCH_CON_I3C_UFD_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_I3C_UFD_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_UFD_QCH_SCLK_ENABLE,
|
|
QCH_CON_I3C_UFD_QCH_SCLK_CLOCK_REQ,
|
|
QCH_CON_I3C_UFD_QCH_SCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_UFD_QCH_ENABLE,
|
|
QCH_CON_PDMA_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_UFD_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_D_UFD_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_D_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_D_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SRAM_MIU_UFD_QCH_ENABLE,
|
|
QCH_CON_SRAM_MIU_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SRAM_MIU_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_UFD_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_UFD_QCH_ENABLE,
|
|
QCH_CON_SYSREG_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_UFD_SECURE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_UFD_SECURE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_UFD_SECURE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFD_CMU_UFD_QCH_ENABLE,
|
|
QCH_CON_UFD_CMU_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFD_CMU_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D_UFD_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFD_QCH_ENABLE,
|
|
QCH_CON_UFD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_UFS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_HSI1UFS_QCH_ENABLE,
|
|
QCH_CON_GPIO_HSI1UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_HSI1UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_UFS_QCH_ENABLE,
|
|
QCH_CON_GPIO_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ACEL_SI_D_UFS_QCH_ENABLE,
|
|
QCH_CON_LH_ACEL_SI_D_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_ACEL_SI_D_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MMC_CARD_QCH_ENABLE,
|
|
QCH_CON_MMC_CARD_QCH_CLOCK_REQ,
|
|
QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_UFS_QCH_ENABLE,
|
|
QCH_CON_PPMU_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_UFS_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPC_UFS_QCH_ENABLE,
|
|
QCH_CON_SPC_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SPC_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_UFS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_UFS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_UFS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_UFS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_CMU_UFS_QCH_ENABLE,
|
|
QCH_CON_UFS_CMU_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_UFS_CMU_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_UFS_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_UFS_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_UFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_ENABLE,
|
|
QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_CLOCK_REQ,
|
|
QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_VTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_VTS_QCH_ENABLE,
|
|
QCH_CON_GPIO_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_CODE_QCH_ENABLE,
|
|
QCH_CON_INTMEM_CODE_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_CODE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_DATA0_QCH_ENABLE,
|
|
QCH_CON_INTMEM_DATA0_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_DATA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_DATA1_QCH_ENABLE,
|
|
QCH_CON_INTMEM_DATA1_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_DATA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_PCM_QCH_ENABLE,
|
|
QCH_CON_INTMEM_PCM_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_PCM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_DNC_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_DNC_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_DNC_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_PCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_CCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_CCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_CCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_ACLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_BCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_BCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_VT_QCH_BCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_VTS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER_QCH_ENABLE,
|
|
QCH_CON_TIMER_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER1_QCH_ENABLE,
|
|
QCH_CON_TIMER1_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER2_QCH_ENABLE,
|
|
QCH_CON_TIMER2_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VTS_CMU_VTS_QCH_ENABLE,
|
|
QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_VTS_QCH_ENABLE,
|
|
QCH_CON_WDT_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_ENABLE,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_CLOCK_REQ,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_ENABLE,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_CLOCK_REQ,
|
|
QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_DDD_YUVP_QCH_ENABLE,
|
|
QCH_CON_BUSIF_DDD_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_DDD_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_YUVP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_ENABLE,
|
|
QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_ENABLE,
|
|
QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_AXI_SI_D0_YUVP_QCH_ENABLE,
|
|
QCH_CON_LH_AXI_SI_D0_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_LH_AXI_SI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_YUVP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_YUVP_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIU_G_PPMU_YUVP_QCH_ENABLE,
|
|
QCH_CON_SIU_G_PPMU_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SIU_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_MI_P_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_MI_P_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_MI_P_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_ENABLE,
|
|
QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_YUVP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_YUVP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_YUVP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_YUVP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_YUVP_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_YUVP_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_YUVP_QCH_IGNORE_FORCE_PM_EN,
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QCH_CON_VGEN_LITE_D1_YUVP_QCH_ENABLE,
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|
QCH_CON_VGEN_LITE_D1_YUVP_QCH_CLOCK_REQ,
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|
QCH_CON_VGEN_LITE_D1_YUVP_QCH_IGNORE_FORCE_PM_EN,
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QCH_CON_YUVP_QCH_ENABLE,
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|
QCH_CON_YUVP_QCH_CLOCK_REQ,
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QCH_CON_YUVP_QCH_IGNORE_FORCE_PM_EN,
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QCH_CON_YUVP_QCH_VOTF0_ENABLE,
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QCH_CON_YUVP_QCH_VOTF0_CLOCK_REQ,
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QCH_CON_YUVP_QCH_VOTF0_IGNORE_FORCE_PM_EN,
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QCH_CON_YUVP_QCH_VOTF1_ENABLE,
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QCH_CON_YUVP_QCH_VOTF1_CLOCK_REQ,
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|
QCH_CON_YUVP_QCH_VOTF1_IGNORE_FORCE_PM_EN,
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QCH_CON_YUVP_CMU_YUVP_QCH_ENABLE,
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QCH_CON_YUVP_CMU_YUVP_QCH_CLOCK_REQ,
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QCH_CON_YUVP_CMU_YUVP_QCH_IGNORE_FORCE_PM_EN,
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ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
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ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
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ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
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|
ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
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|
AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
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AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
end_of_sfr_access,
|
|
num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE,
|
|
};
|
|
|
|
#endif
|