708 lines
17 KiB
C
Executable file
708 lines
17 KiB
C
Executable file
#ifndef __CMUCAL_VCLK_H__
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#define __CMUCAL_VCLK_H__
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#include "../../cmucal.h"
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enum vclk_id {
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/* DVFS VCLK*/
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VCLK_VDD_MIF = DFS_VCLK_TYPE,
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VCLK_VDD_CPUCL0,
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VCLK_VDD_ALIVE,
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VCLK_VDDI,
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VCLK_VDD_CPUCL1,
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VCLK_VDD_AUD,
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end_of_dfs_vclk,
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num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE,
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/* SPECIAL VCLK*/
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VCLK_MUX_CLK_ALIVE_I3C_PMIC = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE,
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VCLK_CLKCMU_ALIVE_BUS,
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VCLK_DIV_CLK_AUD_PCMC,
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VCLK_MUX_BUSC_CMUREF,
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VCLK_MUX_CLKCMU_CMU_BOOST,
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VCLK_MUX_CLK_CHUB_TIMER,
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VCLK_MUX_CMU_CMUREF,
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VCLK_MUX_CORE_CMUREF,
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VCLK_MUX_CPUCL0_CMUREF,
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VCLK_MUX_DSU_CMUREF,
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VCLK_MUX_MIF_CMUREF,
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VCLK_MUX_CLK_USB_USB20DRD,
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VCLK_CLKCMU_USB_USB20DRD,
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VCLK_CLKCMU_DPU_DSIM,
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VCLK_MUX_CLKCMU_PERI_MMC_CARD,
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VCLK_DIV_CLK_ALIVE_DBGCORE_UART,
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VCLK_DIV_CLK_ALIVE_USI0,
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VCLK_DIV_CLK_ALIVE_I2C,
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VCLK_MUX_CLKCMU_AUD_CPU,
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VCLK_DIV_CLK_AUD_MCLK,
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VCLK_DIV_CLK_CHUB_USI0,
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VCLK_CLKCMU_CHUB_PERI,
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VCLK_DIV_CLK_CHUB_USI1,
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VCLK_DIV_CLK_CHUB_USI2,
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VCLK_DIV_CLK_CHUB_USI3,
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VCLK_DIV_CLK_CMGP_USI0,
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VCLK_CLKCMU_CMGP_PERI,
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VCLK_DIV_CLK_CMGP_USI4,
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VCLK_DIV_CLK_CMGP_I3C,
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VCLK_DIV_CLK_CMGP_USI1,
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VCLK_DIV_CLK_CMGP_USI2,
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VCLK_DIV_CLK_CMGP_USI3,
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VCLK_CLKCMU_CIS_CLK0,
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VCLK_CLKCMU_CIS_CLK1,
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VCLK_CLKCMU_CIS_CLK2,
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VCLK_CLKCMU_CIS_CLK3,
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VCLK_CLKCMU_CIS_CLK4,
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VCLK_CLKCMU_CIS_CLK5,
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VCLK_DIV_CLK_CPUCL0_SHORTSTOP,
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VCLK_DIV_CLK_CPUCL1_SHORTSTOP,
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VCLK_DIV_CLK_CPUCL1_HTU,
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VCLK_DIV_CLK_DSU_SHORTSTOP,
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VCLK_DIV_CLK_CLUSTER0_ATCLK,
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VCLK_DIV_CLK_PERI_USI00_USI,
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VCLK_MUX_CLKCMU_PERI_IP,
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VCLK_DIV_CLK_PERI_USI01_USI,
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VCLK_DIV_CLK_PERI_USI02_USI,
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VCLK_DIV_CLK_PERI_USI03_USI,
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VCLK_DIV_CLK_PERI_USI04_USI,
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VCLK_DIV_CLK_PERI_USI05_USI,
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VCLK_DIV_CLK_PERI_UART_DBG,
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VCLK_DIV_CLK_PERI_USI06_USI,
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VCLK_DIV_VTS_SERIAL_LIF_CORE,
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VCLK_CLKCMU_CHUBVTS_BUS,
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VCLK_MUX_CLKCMU_AP2GNSS,
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end_of_vclk,
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num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE),
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/* COMMON VCLK*/
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VCLK_BLK_CMU = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE,
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VCLK_BLK_S2D,
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VCLK_BLK_ALIVE,
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VCLK_BLK_AUD,
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VCLK_BLK_CHUB,
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VCLK_BLK_CHUBVTS,
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VCLK_BLK_CMGP,
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VCLK_BLK_CORE,
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VCLK_BLK_CPUCL0,
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VCLK_BLK_CPUCL1,
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VCLK_BLK_DSU,
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VCLK_BLK_USB,
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VCLK_BLK_VTS,
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VCLK_BLK_BUSC,
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VCLK_BLK_CPUCL0_GLB,
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VCLK_BLK_CSIS,
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VCLK_BLK_DPU,
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VCLK_BLK_G3D,
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VCLK_BLK_ISP,
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VCLK_BLK_M2M,
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VCLK_BLK_MCSC,
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VCLK_BLK_MFC,
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VCLK_BLK_NPU0,
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VCLK_BLK_NPUS,
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VCLK_BLK_PERI,
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VCLK_BLK_TAA,
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VCLK_BLK_TNR,
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end_of_common_vclk,
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num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE),
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/* GATE VCLK*/
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VCLK_IP_SLH_AXI_SI_D_APM = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE,
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VCLK_IP_SLH_AXI_MI_P_APM,
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VCLK_IP_WDT_ALIVE,
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VCLK_IP_SYSREG_ALIVE,
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VCLK_IP_MAILBOX_APM_AP,
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VCLK_IP_APBIF_PMU_ALIVE,
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VCLK_IP_INTMEM,
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VCLK_IP_SLH_AXI_SI_G_SCAN2DRAM,
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VCLK_IP_PMU_INTR_GEN,
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VCLK_IP_XIU_DP_ALIVE,
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VCLK_IP_ALIVE_CMU_ALIVE,
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VCLK_IP_GREBEINTEGRATION,
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VCLK_IP_APBIF_GPIO_ALIVE,
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VCLK_IP_APBIF_TOP_RTC,
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VCLK_IP_SS_DBGCORE,
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VCLK_IP_D_TZPC_ALIVE,
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VCLK_IP_MAILBOX_APM_VTS,
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VCLK_IP_MAILBOX_AP_DBGCORE,
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VCLK_IP_SLH_AXI_SI_G_DBGCORE,
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VCLK_IP_APBIF_RTC,
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VCLK_IP_SLH_AXI_SI_C_CMGP,
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VCLK_IP_VGEN_LITE_ALIVE,
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VCLK_IP_DBGCORE_UART,
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VCLK_IP_ROM_CRC32_HOST,
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VCLK_IP_SLH_AXI_MI_C_GNSS,
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VCLK_IP_SLH_AXI_MI_C_MODEM,
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VCLK_IP_SLH_AXI_MI_C_CHUBVTS,
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VCLK_IP_SLH_AXI_MI_C_WLBT,
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VCLK_IP_SLH_AXI_SI_LP_CHUBVTS,
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VCLK_IP_MAILBOX_APM_CHUB,
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VCLK_IP_MAILBOX_WLBT_CHUB,
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VCLK_IP_MAILBOX_WLBT_ABOX,
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VCLK_IP_MAILBOX_AP_WLBT_WL,
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VCLK_IP_MAILBOX_APM_WLBT,
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VCLK_IP_MAILBOX_GNSS_WLBT,
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VCLK_IP_MAILBOX_GNSS_CHUB,
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VCLK_IP_MAILBOX_AP_GNSS,
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VCLK_IP_MAILBOX_APM_GNSS,
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VCLK_IP_MAILBOX_CP_GNSS,
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VCLK_IP_MAILBOX_CP_WLBT_WL,
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VCLK_IP_MAILBOX_CP_CHUB,
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VCLK_IP_MAILBOX_AP_CP_S,
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VCLK_IP_MAILBOX_AP_CP,
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VCLK_IP_MAILBOX_APM_CP,
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VCLK_IP_MAILBOX_VTS_CHUB,
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VCLK_IP_MAILBOX_AP_CHUB,
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VCLK_IP_I3C_APM_PMIC,
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VCLK_IP_APBIF_SYSREG_VGPIO2AP,
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VCLK_IP_APBIF_SYSREG_VGPIO2APM,
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VCLK_IP_APBIF_SYSREG_VGPIO2PMU,
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VCLK_IP_APBIF_CHUB_RTC,
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VCLK_IP_MAILBOX_AP_WLBT_BT,
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VCLK_IP_MAILBOX_CP_WLBT_BT,
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VCLK_IP_HW_SCANDUMP_CLKSTOP_CTRL,
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VCLK_IP_SWEEPER_P_ALIVE,
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VCLK_IP_I2C_ALIVE0,
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VCLK_IP_USI_ALIVE0,
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VCLK_IP_MAILBOX_SHARED_SRAM,
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VCLK_IP_AUD_CMU_AUD,
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VCLK_IP_LH_AXI_SI_D_AUD,
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VCLK_IP_PPMU_AUD,
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VCLK_IP_ABOX,
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VCLK_IP_SLH_AXI_MI_P_AUD,
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VCLK_IP_PERI_AXI_ASB,
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VCLK_IP_WDT_AUD,
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VCLK_IP_SYSMMU_AUD,
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VCLK_IP_AD_APB_SYSMMU_AUD_NS,
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VCLK_IP_AD_APB_SYSMMU_AUD_S,
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VCLK_IP_AD_APB_SYSMMU_AUD_S2,
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VCLK_IP_DFTMUX_AUD,
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VCLK_IP_MAILBOX_AUD0,
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VCLK_IP_MAILBOX_AUD1,
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VCLK_IP_D_TZPC_AUD,
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VCLK_IP_SLH_AXI_MI_D_USBAUD,
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VCLK_IP_VGEN_LITE_AUD,
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VCLK_IP_AD_APB_VGENLITE_AUD,
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VCLK_IP_SYSREG_AUD,
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VCLK_IP_BUSC_CMU_BUSC,
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VCLK_IP_AD_APB_PDMA,
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VCLK_IP_XIU_P_BUSC,
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VCLK_IP_XIU_D_BUSC,
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VCLK_IP_SLH_AXI_MI_D_PERI,
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VCLK_IP_SLH_AXI_MI_D_USB,
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VCLK_IP_LH_AXI_MI_D_MFC,
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VCLK_IP_SLH_AXI_MI_D_APM,
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VCLK_IP_PDMA_BUSC,
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VCLK_IP_SPDMA_BUSC,
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VCLK_IP_SYSMMU_AXI_D_BUSC,
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VCLK_IP_SYSREG_BUSC,
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VCLK_IP_TREX_D_BUSC,
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VCLK_IP_VGEN_PDMA,
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VCLK_IP_SLH_AXI_MI_P_BUSC,
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VCLK_IP_D_TZPC_BUSC,
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VCLK_IP_LH_AXI_MI_D_CHUBVTS,
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VCLK_IP_VGEN_SPDMA,
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VCLK_IP_APBIF_GPIO_CHUB,
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VCLK_IP_APBIF_CHUB_COMBINE_WAKEUP_SRC,
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VCLK_IP_CM4_CHUB,
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VCLK_IP_PWM_CHUB,
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VCLK_IP_SYSREG_CHUB,
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VCLK_IP_TIMER_CHUB,
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VCLK_IP_WDT_CHUB,
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VCLK_IP_I2C_CHUB1,
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VCLK_IP_USI_CHUB0,
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VCLK_IP_USI_CHUB1,
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VCLK_IP_USI_CHUB2,
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VCLK_IP_SYSREG_COMBINE_CHUB2AP,
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VCLK_IP_SYSREG_COMBINE_CHUB2APM,
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VCLK_IP_SYSREG_COMBINE_CHUB2WLBT,
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VCLK_IP_APBIF_GPIO_CHUBEINT,
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VCLK_IP_I2C_CHUB3,
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VCLK_IP_USI_CHUB3,
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VCLK_IP_AHB_BUSMATRIX_CHUB,
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VCLK_IP_SLH_AXI_SI_M_CHUB,
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VCLK_IP_SLH_AXI_MI_S_CHUB,
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VCLK_IP_CHUB_CMU_CHUB,
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VCLK_IP_CHUBVTS_CMU_CHUBVTS,
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VCLK_IP_BAAW_VTS,
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VCLK_IP_D_TZPC_CHUBVTS,
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VCLK_IP_LH_AXI_SI_D_CHUBVTS,
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VCLK_IP_SLH_AXI_MI_M_CHUB,
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VCLK_IP_SLH_AXI_MI_LP_CHUBVTS,
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VCLK_IP_SLH_AXI_MI_M_VTS,
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VCLK_IP_SLH_AXI_SI_C_CHUBVTS,
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VCLK_IP_SLH_AXI_SI_S_CHUB,
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VCLK_IP_SLH_AXI_SI_S_VTS,
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VCLK_IP_SWEEPER_C_CHUBVTS,
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VCLK_IP_SYSREG_CHUBVTS,
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VCLK_IP_VGEN_LITE_CHUBVTS,
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VCLK_IP_XIU_DP_CHUBVTS,
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VCLK_IP_BPS_LP_CHUBVTS,
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VCLK_IP_BAAW_CHUB,
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VCLK_IP_CMGP_CMU_CMGP,
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VCLK_IP_GPIO_CMGP,
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VCLK_IP_I2C_CMGP0,
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VCLK_IP_SYSREG_CMGP,
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VCLK_IP_USI_CMGP0,
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VCLK_IP_SYSREG_CMGP2PMU_AP,
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VCLK_IP_D_TZPC_CMGP,
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VCLK_IP_SLH_AXI_MI_C_CMGP,
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VCLK_IP_SYSREG_CMGP2APM,
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VCLK_IP_SYSREG_CMGP2CP,
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VCLK_IP_I3C_CMGP,
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VCLK_IP_SYSREG_CMGP2CHUB,
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VCLK_IP_SYSREG_CMGP2GNSS,
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VCLK_IP_SYSREG_CMGP2WLBT,
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VCLK_IP_I2C_CMGP4,
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VCLK_IP_USI_CMGP4,
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VCLK_IP_I2C_CMGP1,
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VCLK_IP_I2C_CMGP2,
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VCLK_IP_I2C_CMGP3,
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VCLK_IP_USI_CMGP1,
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VCLK_IP_USI_CMGP2,
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VCLK_IP_USI_CMGP3,
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VCLK_IP_CORE_CMU_CORE,
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VCLK_IP_SYSREG_CORE,
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VCLK_IP_SIREX,
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VCLK_IP_TREX_P_CORE,
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VCLK_IP_DIT,
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VCLK_IP_TREX_D_NRT,
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VCLK_IP_SLH_AXI_SI_P_G3D,
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VCLK_IP_SLH_AXI_SI_P_CPUCL0,
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VCLK_IP_SLH_AXI_SI_P_CSIS,
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VCLK_IP_SLH_AXI_MI_D_HSI,
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VCLK_IP_TREX_D_CORE,
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VCLK_IP_SLH_AXI_SI_P_APM,
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VCLK_IP_D_TZPC_CORE,
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VCLK_IP_SLH_AXI_MI_D_WLBT,
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VCLK_IP_SLH_AXI_SI_P_WLBT,
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VCLK_IP_SLH_AXI_MI_D0_MODEM,
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VCLK_IP_SLH_AXI_MI_D1_MODEM,
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VCLK_IP_SLH_AXI_MI_D_GNSS,
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VCLK_IP_LH_AXI_SI_D0_MIF_NRT,
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VCLK_IP_AD_APB_DIT,
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VCLK_IP_AD_AXI_GIC,
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VCLK_IP_SLH_AXI_SI_P_USB,
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VCLK_IP_SLH_AXI_SI_P_MODEM,
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VCLK_IP_SLH_AXI_SI_P_MIF0,
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VCLK_IP_SLH_AXI_SI_P_MIF1,
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VCLK_IP_SLH_AXI_SI_P_MFC,
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VCLK_IP_SLH_AXI_SI_P_GNSS,
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VCLK_IP_GIC,
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VCLK_IP_LH_AXI_MI_D_AUD,
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VCLK_IP_LH_AXI_SI_D1_MIF_CP,
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VCLK_IP_LH_AXI_SI_D1_MIF_NRT,
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VCLK_IP_SLH_AXI_SI_P_AUD,
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VCLK_IP_SLH_AXI_SI_P_DPU,
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VCLK_IP_SLH_AXI_SI_P_HSI,
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VCLK_IP_SLH_AXI_SI_P_TAA,
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VCLK_IP_BAAW_P_GNSS,
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VCLK_IP_BAAW_P_MODEM,
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VCLK_IP_BAAW_P_WLBT,
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VCLK_IP_SFR_APBIF_CMU_TOPC,
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VCLK_IP_SLH_AXI_SI_P_ISP,
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VCLK_IP_SLH_AXI_SI_P_MCSC,
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VCLK_IP_SLH_AXI_SI_P_TNR,
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VCLK_IP_SLH_AXI_SI_P_NPU0,
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VCLK_IP_SLH_AXI_SI_P_PERI,
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VCLK_IP_LH_AXI_MI_D_SSS,
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VCLK_IP_SYSMMU_ACEL_D_DIT,
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VCLK_IP_LH_AXI_SI_D_SSS,
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VCLK_IP_SLH_AXI_MI_G_CSSYS,
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VCLK_IP_LH_AXI_SI_D0_MIF_CP,
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VCLK_IP_SSS,
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VCLK_IP_PUF,
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VCLK_IP_AD_APB_PUF,
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VCLK_IP_SLH_AXI_SI_P_NPUS,
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VCLK_IP_LH_AXI_SI_D0_MIF_RT,
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VCLK_IP_LH_AXI_SI_D1_MIF_RT,
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VCLK_IP_SLH_AXI_SI_P_BUSC,
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VCLK_IP_SLH_AXI_SI_P_MCW,
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VCLK_IP_LH_AXI_MI_D_G3D,
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VCLK_IP_BAAW_D_SSS,
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VCLK_IP_BDU,
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VCLK_IP_XIU_G_BDU,
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VCLK_IP_PPC_DEBUG,
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VCLK_IP_LH_AXI_MI_D0_DPU,
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VCLK_IP_LH_AXI_MI_D0_NPUS,
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VCLK_IP_LH_AXI_MI_D1_NPUS,
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VCLK_IP_SYSMMU_ACEL_D2_MODEM,
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VCLK_IP_ADM_APB_G_BDU,
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VCLK_IP_LH_AXI_MI_D1_DPU,
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VCLK_IP_SLH_AXI_SI_P_M2M,
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VCLK_IP_LH_AST_MI_G_CPU,
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VCLK_IP_SLH_AXI_MI_P_CLUSTER0,
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VCLK_IP_VGEN_LITE_CORE,
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VCLK_IP_AD_APB_VGEN_LITE_CORE,
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VCLK_IP_LH_AXI_MI_D_M2M,
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VCLK_IP_HW_APBSEMA_MEC,
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VCLK_IP_HTU_CPUCL0,
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VCLK_IP_CPUCL0_CMU_CPUCL0,
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VCLK_IP_CPUCL0,
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VCLK_IP_CPUCL0_GLB_CMU_CPUCL0_GLB,
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VCLK_IP_APB_ASYNC_P_CSSYS_0,
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VCLK_IP_XIU_P_CPUCL0,
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VCLK_IP_BPS_CPUCL0,
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VCLK_IP_CSSYS,
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VCLK_IP_D_TZPC_CPUCL0,
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VCLK_IP_SLH_AXI_MI_G_DBGCORE,
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VCLK_IP_SLH_AXI_MI_G_INT_CSSYS,
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VCLK_IP_SLH_AXI_MI_G_INT_DBGCORE,
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VCLK_IP_SLH_AXI_MI_P_CPUCL0,
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VCLK_IP_SLH_AXI_SI_G_CSSYS,
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VCLK_IP_SLH_AXI_SI_G_INT_CSSYS,
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VCLK_IP_SLH_AXI_SI_G_INT_DBGCORE,
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VCLK_IP_SECJTAG,
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VCLK_IP_SYSREG_CPUCL0,
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VCLK_IP_XIU_DP_CSSYS,
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VCLK_IP_ADM_APB_G_CLUSTER0,
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VCLK_IP_CPUCL1_CMU_CPUCL1,
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VCLK_IP_CPUCL1,
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VCLK_IP_HTU_CPUCL1,
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VCLK_IP_CSIS_CMU_CSIS,
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VCLK_IP_LH_AXI_SI_D0_CSIS,
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VCLK_IP_LH_AXI_SI_D1_CSIS,
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VCLK_IP_D_TZPC_CSIS,
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VCLK_IP_CSIS_PDP,
|
|
VCLK_IP_PPMU_CSIS_D0,
|
|
VCLK_IP_PPMU_CSIS_D1,
|
|
VCLK_IP_SYSMMU_D0_CSIS,
|
|
VCLK_IP_SYSMMU_D1_CSIS,
|
|
VCLK_IP_SYSREG_CSIS,
|
|
VCLK_IP_SLH_AXI_MI_P_CSIS,
|
|
VCLK_IP_LH_AST_SI_OTF0_CSISTAA,
|
|
VCLK_IP_LH_AST_MI_ZOTF0_TAACSIS,
|
|
VCLK_IP_LH_AST_MI_ZOTF1_TAACSIS,
|
|
VCLK_IP_AD_APB_CSIS0,
|
|
VCLK_IP_XIU_D0_CSIS,
|
|
VCLK_IP_XIU_D1_CSIS,
|
|
VCLK_IP_LH_AST_SI_OTF1_CSISTAA,
|
|
VCLK_IP_LH_AST_MI_SOTF0_TAACSIS,
|
|
VCLK_IP_LH_AST_MI_SOTF1_TAACSIS,
|
|
VCLK_IP_PPMU_CSIS_D2,
|
|
VCLK_IP_QE_CSIS_DMA0,
|
|
VCLK_IP_QE_CSIS_DMA1,
|
|
VCLK_IP_QE_ZSL0,
|
|
VCLK_IP_QE_STRP0,
|
|
VCLK_IP_QE_PDP_STAT_IMG0,
|
|
VCLK_IP_MIPI_DCPHY_LINK_WRAP,
|
|
VCLK_IP_LH_AXI_SI_D2_CSIS,
|
|
VCLK_IP_QE_ZSL1,
|
|
VCLK_IP_QE_STRP1,
|
|
VCLK_IP_QE_PDP_STAT_IMG1,
|
|
VCLK_IP_QE_CSIS_DMA2,
|
|
VCLK_IP_QE_CSIS_DMA3,
|
|
VCLK_IP_QE_PDP_AF0,
|
|
VCLK_IP_QE_PDP_AF1,
|
|
VCLK_IP_XIU_D2_CSIS,
|
|
VCLK_IP_XIU_D3_CSIS,
|
|
VCLK_IP_SYSMMU_D2_CSIS,
|
|
VCLK_IP_XIU_D4_CSIS,
|
|
VCLK_IP_PPMU_CSIS_D3,
|
|
VCLK_IP_SYSMMU_D3_CSIS,
|
|
VCLK_IP_LH_AXI_SI_D3_CSIS,
|
|
VCLK_IP_QE_PDP_AF2,
|
|
VCLK_IP_QE_STRP2,
|
|
VCLK_IP_QE_ZSL2,
|
|
VCLK_IP_QE_PDP_STAT_IMG2,
|
|
VCLK_IP_LH_AST_SI_OTF2_CSISTAA,
|
|
VCLK_IP_LH_AST_MI_ZOTF2_TAACSIS,
|
|
VCLK_IP_LH_AST_MI_SOTF2_TAACSIS,
|
|
VCLK_IP_VGEN_LITE0_CSIS,
|
|
VCLK_IP_VGEN_LITE1_CSIS,
|
|
VCLK_IP_VGEN_LITE2_CSIS,
|
|
VCLK_IP_DPU_CMU_DPU,
|
|
VCLK_IP_SYSREG_DPU,
|
|
VCLK_IP_SYSMMU_AXI_D0_DPU,
|
|
VCLK_IP_SLH_AXI_MI_P_DPU,
|
|
VCLK_IP_PPMU_D0_DPU,
|
|
VCLK_IP_LH_AXI_SI_D0_DPU,
|
|
VCLK_IP_DPU,
|
|
VCLK_IP_D_TZPC_DPU,
|
|
VCLK_IP_AD_APB_DECON0,
|
|
VCLK_IP_LH_AXI_SI_D1_DPU,
|
|
VCLK_IP_PPMU_D1_DPU,
|
|
VCLK_IP_SYSMMU_AXI_D1_DPU,
|
|
VCLK_IP_SLH_AXI_SI_P_CLUSTER0,
|
|
VCLK_IP_XIU_D_CPUCL0,
|
|
VCLK_IP_DSU_CMU_DSU,
|
|
VCLK_IP_LH_AXI_SI_D0_MIF_CPU,
|
|
VCLK_IP_LH_AXI_SI_D1_MIF_CPU,
|
|
VCLK_IP_PPC_INSTRRUN_CLUSTER0_0,
|
|
VCLK_IP_PPC_INSTRRUN_CLUSTER0_1,
|
|
VCLK_IP_PPC_INSTRRET_CLUSTER0_0,
|
|
VCLK_IP_PPC_INSTRRET_CLUSTER0_1,
|
|
VCLK_IP_CLUSTER0,
|
|
VCLK_IP_HTU_DSU,
|
|
VCLK_IP_PPMU_CPUCL0,
|
|
VCLK_IP_PPMU_CPUCL1,
|
|
VCLK_IP_LH_AST_SI_G_CPU,
|
|
VCLK_IP_SLH_AXI_MI_P_G3D,
|
|
VCLK_IP_SYSREG_G3D,
|
|
VCLK_IP_G3D_CMU_G3D,
|
|
VCLK_IP_GPU,
|
|
VCLK_IP_D_TZPC_G3D,
|
|
VCLK_IP_LHS_AXI_P_INT_G3D,
|
|
VCLK_IP_LHM_AXI_P_INT_G3D,
|
|
VCLK_IP_LH_AXI_SI_D_G3D,
|
|
VCLK_IP_HTU_G3D,
|
|
VCLK_IP_PPMU_D_G3D,
|
|
VCLK_IP_AS_APB_SYSMMU_D_G3D,
|
|
VCLK_IP_SYSMMU_D_G3D,
|
|
VCLK_IP_GRAY2BIN_G3D,
|
|
VCLK_IP_XIU_D0_G3D,
|
|
VCLK_IP_AS_APB_VGENLITE_G3D,
|
|
VCLK_IP_VGEN_LITE_G3D,
|
|
VCLK_IP_GNSS_CMU_GNSS,
|
|
VCLK_IP_VGEN_LITE_HSI,
|
|
VCLK_IP_HSI_CMU_HSI,
|
|
VCLK_IP_SYSREG_HSI,
|
|
VCLK_IP_GPIO_HSI,
|
|
VCLK_IP_SLH_AXI_SI_D_HSI,
|
|
VCLK_IP_SLH_AXI_MI_P_HSI,
|
|
VCLK_IP_PPMU_HSI,
|
|
VCLK_IP_D_TZPC_HSI,
|
|
VCLK_IP_UFS_EMBD,
|
|
VCLK_IP_S2MPU_D_HSI,
|
|
VCLK_IP_GPIO_HSI_UFS,
|
|
VCLK_IP_SYSREG_ISP,
|
|
VCLK_IP_ISP_CMU_ISP,
|
|
VCLK_IP_D_TZPC_ISP,
|
|
VCLK_IP_PPMU_ISP,
|
|
VCLK_IP_LH_AXI_SI_D_ISP,
|
|
VCLK_IP_AD_APB_ITP,
|
|
VCLK_IP_ITP_DNS,
|
|
VCLK_IP_SYSMMU_D_ISP,
|
|
VCLK_IP_LH_AST_MI_OTF_TAAISP,
|
|
VCLK_IP_LH_AST_SI_OTF_ISPMCSC,
|
|
VCLK_IP_LH_AST_MI_OTF0_TNRISP,
|
|
VCLK_IP_LH_AST_MI_OTF1_TNRISP,
|
|
VCLK_IP_XIU_D_ISP,
|
|
VCLK_IP_AD_APB_VGEN_LITE_ISP,
|
|
VCLK_IP_VGEN_LITE_ISP,
|
|
VCLK_IP_SLH_AXI_MI_P_ISP,
|
|
VCLK_IP_M2M,
|
|
VCLK_IP_M2M_CMU_M2M,
|
|
VCLK_IP_SYSREG_M2M,
|
|
VCLK_IP_SLH_AXI_MI_P_M2M,
|
|
VCLK_IP_SYSMMU_D_M2M,
|
|
VCLK_IP_PPMU_D_M2M,
|
|
VCLK_IP_XIU_D_M2M,
|
|
VCLK_IP_AS_APB_JPEG0,
|
|
VCLK_IP_JPEG0,
|
|
VCLK_IP_D_TZPC_M2M,
|
|
VCLK_IP_LH_AXI_SI_D_M2M,
|
|
VCLK_IP_AS_APB_VGEN_LITE_M2M,
|
|
VCLK_IP_VGEN_LITE_M2M,
|
|
VCLK_IP_MCSC_CMU_MCSC,
|
|
VCLK_IP_SLH_AXI_MI_P_MCSC,
|
|
VCLK_IP_SYSREG_MCSC,
|
|
VCLK_IP_PPMU_MCSC,
|
|
VCLK_IP_D_TZPC_MCSC,
|
|
VCLK_IP_AD_APB_GDC,
|
|
VCLK_IP_PPMU_GDC,
|
|
VCLK_IP_SYSMMU_D1_MCSC,
|
|
VCLK_IP_GDC,
|
|
VCLK_IP_MCSC,
|
|
VCLK_IP_AD_AXI_MCSC,
|
|
VCLK_IP_AD_AXI_GDC,
|
|
VCLK_IP_TREX_D_CAM,
|
|
VCLK_IP_LH_AXI_MI_D0_CSIS,
|
|
VCLK_IP_LH_AXI_MI_D0_TNR,
|
|
VCLK_IP_LH_AXI_MI_D1_CSIS,
|
|
VCLK_IP_LH_AXI_MI_D1_TNR,
|
|
VCLK_IP_LH_AXI_MI_D2_CSIS,
|
|
VCLK_IP_LH_AXI_MI_D3_CSIS,
|
|
VCLK_IP_LH_AXI_MI_D_ISP,
|
|
VCLK_IP_LH_AXI_MI_D_TAA,
|
|
VCLK_IP_LH_AST_MI_OTF_ISPMCSC,
|
|
VCLK_IP_AD_APB_MCSC,
|
|
VCLK_IP_SYSMMU_D0_MCSC,
|
|
VCLK_IP_XIU_D_MCSC,
|
|
VCLK_IP_ORBMCH,
|
|
VCLK_IP_AD_APB_SYSMMU_D0_MCSC_NS,
|
|
VCLK_IP_VGEN_LITE_MCSC,
|
|
VCLK_IP_VGEN_LITE_GDC,
|
|
VCLK_IP_MFC_CMU_MFC,
|
|
VCLK_IP_AS_APB_MFC,
|
|
VCLK_IP_SYSREG_MFC,
|
|
VCLK_IP_LH_AXI_SI_D_MFC,
|
|
VCLK_IP_SLH_AXI_MI_P_MFC,
|
|
VCLK_IP_SYSMMU_MFC,
|
|
VCLK_IP_PPMU_MFC,
|
|
VCLK_IP_MFC,
|
|
VCLK_IP_D_TZPC_MFC,
|
|
VCLK_IP_VGEN_LITE_MFC,
|
|
VCLK_IP_MIF_CMU_MIF,
|
|
VCLK_IP_SFRAPB_BRIDGE_DDRPHY,
|
|
VCLK_IP_SYSREG_MIF,
|
|
VCLK_IP_SLH_AXI_MI_P_MIF,
|
|
VCLK_IP_DMC,
|
|
VCLK_IP_DDRPHY,
|
|
VCLK_IP_SFRAPB_BRIDGE_DMC,
|
|
VCLK_IP_D_TZPC_MIF,
|
|
VCLK_IP_QE_DMC_CPU,
|
|
VCLK_IP_PPMU_DMC_CPU,
|
|
VCLK_IP_SFRAPB_BRIDGE_DMC_PF,
|
|
VCLK_IP_SFRAPB_BRIDGE_DMC_SECURE,
|
|
VCLK_IP_SFRAPB_BRIDGE_DMC_PPMPU,
|
|
VCLK_IP_LH_AXI_MI_D_MIF_CPU,
|
|
VCLK_IP_LH_AXI_MI_D_MIF_RT,
|
|
VCLK_IP_LH_AXI_MI_D_MIF_NRT,
|
|
VCLK_IP_LH_AXI_MI_D_MIF_CP,
|
|
VCLK_IP_MODEM_CMU_MODEM,
|
|
VCLK_IP_NPU0_CMU_NPU0,
|
|
VCLK_IP_D_TZPC_NPU0,
|
|
VCLK_IP_SYSREG_NPU0,
|
|
VCLK_IP_SLH_AXI_MI_P_NPU0,
|
|
VCLK_IP_IP_NPUCORE,
|
|
VCLK_IP_LH_AXI_MI_D_CTRL_NPU0,
|
|
VCLK_IP_LH_AXI_MI_D0_NPU0,
|
|
VCLK_IP_LH_AXI_SI_D_RQ_NPU0,
|
|
VCLK_IP_LH_AXI_SI_D_CMDQ_NPU0,
|
|
VCLK_IP_LH_AXI_MI_D1_NPU0,
|
|
VCLK_IP_VGEN_LITE_NPUS,
|
|
VCLK_IP_LH_AXI_MI_D_RQ_NPU0,
|
|
VCLK_IP_LH_AXI_SI_D_CTRL_NPU0,
|
|
VCLK_IP_LH_AXI_SI_D0_NPU0,
|
|
VCLK_IP_LH_AXI_SI_D0_NPUS,
|
|
VCLK_IP_LH_AXI_SI_D1_NPUS,
|
|
VCLK_IP_SYSMMU_D0_NPUS,
|
|
VCLK_IP_IP_NPUS,
|
|
VCLK_IP_PPMU_NPUS_0,
|
|
VCLK_IP_HTU_NPUS,
|
|
VCLK_IP_LH_AXI_MI_D_CMDQ_NPU0,
|
|
VCLK_IP_SYSMMU_D1_NPUS,
|
|
VCLK_IP_LH_AXI_SI_D1_NPU0,
|
|
VCLK_IP_PPMU_NPUS_1,
|
|
VCLK_IP_DS_256_128_0,
|
|
VCLK_IP_DS_256_128_1,
|
|
VCLK_IP_D_TZPC_NPUS,
|
|
VCLK_IP_SLH_AXI_MI_P_INT_NPUS,
|
|
VCLK_IP_SLH_AXI_SI_P_INT_NPUS,
|
|
VCLK_IP_AD_APB_SYSMMU_D0_NPUS_NS,
|
|
VCLK_IP_SYSREG_NPUS,
|
|
VCLK_IP_SLH_AXI_MI_P_NPUS,
|
|
VCLK_IP_ADM_DAP_NPUS,
|
|
VCLK_IP_NPUS_CMU_NPUS,
|
|
VCLK_IP_GPIO_PERI,
|
|
VCLK_IP_SYSREG_PERI,
|
|
VCLK_IP_PERI_CMU_PERI,
|
|
VCLK_IP_SLH_AXI_MI_P_PERI,
|
|
VCLK_IP_D_TZPC_PERI,
|
|
VCLK_IP_XIU_P_PERI,
|
|
VCLK_IP_MCT,
|
|
VCLK_IP_OTP_CON_TOP,
|
|
VCLK_IP_WDT0,
|
|
VCLK_IP_WDT1,
|
|
VCLK_IP_TMU,
|
|
VCLK_IP_PWM,
|
|
VCLK_IP_UART_DBG,
|
|
VCLK_IP_USI00_USI,
|
|
VCLK_IP_USI00_I2C,
|
|
VCLK_IP_USI01_USI,
|
|
VCLK_IP_USI01_I2C,
|
|
VCLK_IP_USI02_USI,
|
|
VCLK_IP_USI02_I2C,
|
|
VCLK_IP_USI03_USI,
|
|
VCLK_IP_USI03_I2C,
|
|
VCLK_IP_USI04_USI,
|
|
VCLK_IP_USI04_I2C,
|
|
VCLK_IP_USI05_USI,
|
|
VCLK_IP_USI05_I2C,
|
|
VCLK_IP_VGEN_LITE_PERI,
|
|
VCLK_IP_S2MPU_D_PERI,
|
|
VCLK_IP_MMC_CARD,
|
|
VCLK_IP_PPMU_PERI,
|
|
VCLK_IP_SLH_AXI_SI_D_PERI,
|
|
VCLK_IP_GPIO_PERIMMC,
|
|
VCLK_IP_USI06_USI,
|
|
VCLK_IP_USI06_I2C,
|
|
VCLK_IP_USI07_I2C,
|
|
VCLK_IP_S2D_CMU_S2D,
|
|
VCLK_IP_BIS_S2D,
|
|
VCLK_IP_SLH_AXI_MI_G_SCAN2DRAM,
|
|
VCLK_IP_LH_AXI_SI_D_TAA,
|
|
VCLK_IP_SLH_AXI_MI_P_TAA,
|
|
VCLK_IP_SYSREG_TAA,
|
|
VCLK_IP_TAA_CMU_TAA,
|
|
VCLK_IP_LH_AST_SI_OTF_TAAISP,
|
|
VCLK_IP_D_TZPC_TAA,
|
|
VCLK_IP_LH_AST_MI_OTF0_CSISTAA,
|
|
VCLK_IP_SIPU_TAA,
|
|
VCLK_IP_LH_AST_SI_ZOTF0_TAACSIS,
|
|
VCLK_IP_LH_AST_SI_ZOTF1_TAACSIS,
|
|
VCLK_IP_PPMU_TAA,
|
|
VCLK_IP_LH_AST_MI_OTF1_CSISTAA,
|
|
VCLK_IP_LH_AST_SI_SOTF0_TAACSIS,
|
|
VCLK_IP_LH_AST_SI_SOTF1_TAACSIS,
|
|
VCLK_IP_AD_APB_TAA,
|
|
VCLK_IP_SYSMMU_TAA,
|
|
VCLK_IP_XIU_D_TAA,
|
|
VCLK_IP_LH_AST_MI_OTF2_CSISTAA,
|
|
VCLK_IP_LH_AST_SI_ZOTF2_TAACSIS,
|
|
VCLK_IP_LH_AST_SI_SOTF2_TAACSIS,
|
|
VCLK_IP_VGEN_LITE0_TAA,
|
|
VCLK_IP_VGEN_LITE1_TAA,
|
|
VCLK_IP_TNR_CMU_TNR,
|
|
VCLK_IP_SLH_AXI_MI_P_TNR,
|
|
VCLK_IP_APB_ASYNC_TNR_0,
|
|
VCLK_IP_LH_AXI_SI_D0_TNR,
|
|
VCLK_IP_LH_AXI_SI_D1_TNR,
|
|
VCLK_IP_SYSREG_TNR,
|
|
VCLK_IP_D_TZPC_TNR,
|
|
VCLK_IP_XIU_D1_TNR,
|
|
VCLK_IP_PPMU_D0_TNR,
|
|
VCLK_IP_PPMU_D1_TNR,
|
|
VCLK_IP_SYSMMU_D0_TNR,
|
|
VCLK_IP_SYSMMU_D1_TNR,
|
|
VCLK_IP_TNR,
|
|
VCLK_IP_LH_AST_SI_OTF0_TNRISP,
|
|
VCLK_IP_XIU_D0_TNR,
|
|
VCLK_IP_LH_AST_SI_OTF1_TNRISP,
|
|
VCLK_IP_VGEN_LITE_D_TNR,
|
|
VCLK_IP_USB20DRD_TOP,
|
|
VCLK_IP_PPMU_USB,
|
|
VCLK_IP_SLH_AXI_SI_D_USB,
|
|
VCLK_IP_VGEN_LITE_USB,
|
|
VCLK_IP_D_TZPC_USB,
|
|
VCLK_IP_SLH_AXI_MI_P_USB,
|
|
VCLK_IP_S2MPU_D_USB,
|
|
VCLK_IP_SYSREG_USB,
|
|
VCLK_IP_USB_CMU_USB,
|
|
VCLK_IP_XIU_D_USB,
|
|
VCLK_IP_SLH_AXI_SI_D_USBAUD,
|
|
VCLK_IP_URAM,
|
|
VCLK_IP_AHB_BUSMATRIX_VTS,
|
|
VCLK_IP_DMIC_IF0,
|
|
VCLK_IP_SYSREG_VTS,
|
|
VCLK_IP_VTS_CMU_VTS,
|
|
VCLK_IP_GPIO_VTS,
|
|
VCLK_IP_WDT_VTS,
|
|
VCLK_IP_DMIC_AHB0,
|
|
VCLK_IP_ASYNCINTERRUPT_VTS,
|
|
VCLK_IP_SS_VTS_GLUE,
|
|
VCLK_IP_CM4_VTS,
|
|
VCLK_IP_MAILBOX_ABOX_VTS,
|
|
VCLK_IP_DMIC_AHB2,
|
|
VCLK_IP_MAILBOX_AP_VTS,
|
|
VCLK_IP_TIMER_VTS,
|
|
VCLK_IP_DMIC_IF1,
|
|
VCLK_IP_SLH_AXI_MI_S_VTS,
|
|
VCLK_IP_SLH_AXI_SI_M_VTS,
|
|
VCLK_IP_HWACG_SYS_DMIC0,
|
|
VCLK_IP_HWACG_SYS_DMIC2,
|
|
VCLK_IP_U_DMIC_CLK_SCAN_MUX,
|
|
VCLK_IP_AXI2AHB_VTS,
|
|
VCLK_IP_AHB2AXI_VTS,
|
|
VCLK_IP_SERIAL_LIF_AUD,
|
|
VCLK_IP_DMIC_AUD0,
|
|
VCLK_IP_DMIC_AUD1,
|
|
VCLK_IP_HWACG_SYS_SERIAL_LIF,
|
|
end_of_gate_vclk,
|
|
num_of_gate_vclk = end_of_gate_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE),
|
|
|
|
};
|
|
#endif
|