686 lines
124 KiB
C
Executable file
686 lines
124 KiB
C
Executable file
#include "../../cmucal.h"
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#include "cmucal-sfr.h"
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#include "cmucal-qch.h"
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unsigned int cmucal_qch_size = 644;
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struct cmucal_qch cmucal_qch_list[] = {
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CLK_QCH(ALIVE_CMU_ALIVE_QCH, QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_CHUB_RTC_QCH, QCH_CON_APBIF_CHUB_RTC_QCH_ENABLE, QCH_CON_APBIF_CHUB_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_CHUB_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2AP_QCH, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2APM_QCH, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_SYSREG_VGPIO2PMU_QCH, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_TOP_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DBGCORE_UART_QCH, QCH_CON_DBGCORE_UART_QCH_ENABLE, QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL, QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_ALIVE_QCH, QCH_CON_D_TZPC_ALIVE_QCH_ENABLE, QCH_CON_D_TZPC_ALIVE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ALIVE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(HW_SCANDUMP_CLKSTOP_CTRL_QCH, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_ALIVE0_QCH, QCH_CON_I2C_ALIVE0_QCH_ENABLE, QCH_CON_I2C_ALIVE0_QCH_CLOCK_REQ, QCH_CON_I2C_ALIVE0_QCH_EXPIRE_VAL, QCH_CON_I2C_ALIVE0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_APM_PMIC_QCH_P, QCH_CON_I3C_APM_PMIC_QCH_P_ENABLE, QCH_CON_I3C_APM_PMIC_QCH_P_CLOCK_REQ, QCH_CON_I3C_APM_PMIC_QCH_P_EXPIRE_VAL, QCH_CON_I3C_APM_PMIC_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_APM_PMIC_QCH_S, QCH_CON_I3C_APM_PMIC_QCH_S_ENABLE, QCH_CON_I3C_APM_PMIC_QCH_S_CLOCK_REQ, QCH_CON_I3C_APM_PMIC_QCH_S_EXPIRE_VAL, QCH_CON_I3C_APM_PMIC_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CHUB_QCH, QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CP_QCH, QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_GNSS_QCH, QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_VTS_QCH, QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_WLBT_QCH, QCH_CON_MAILBOX_APM_WLBT_QCH_ENABLE, QCH_CON_MAILBOX_APM_WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CHUB_QCH, QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_QCH, QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_S_QCH, QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_GNSS_QCH, QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_WLBT_BT_QCH, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_ENABLE, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_WLBT_WL_QCH, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_ENABLE, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_CHUB_QCH, QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_GNSS_QCH, QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_WLBT_BT_QCH, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_ENABLE, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_WLBT_WL_QCH, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_ENABLE, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_GNSS_CHUB_QCH, QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_GNSS_WLBT_QCH, QCH_CON_MAILBOX_GNSS_WLBT_QCH_ENABLE, QCH_CON_MAILBOX_GNSS_WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS_WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_SHARED_SRAM_QCH, QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE, QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHARED_SRAM_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_VTS_CHUB_QCH, QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_WLBT_ABOX_QCH, QCH_CON_MAILBOX_WLBT_ABOX_QCH_ENABLE, QCH_CON_MAILBOX_WLBT_ABOX_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT_ABOX_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_WLBT_CHUB_QCH, QCH_CON_MAILBOX_WLBT_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_WLBT_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ROM_CRC32_HOST_QCH, QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_ALIVE_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_C_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_C_GNSS_QCH, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_C_MODEM_QCH, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_C_WLBT_QCH, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_APM_QCH, QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_C_CMGP_QCH, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_D_APM_QCH, QCH_CON_SLH_AXI_SI_D_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_G_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_LP_CHUBVTS_QCH, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_DBGCORE_QCH_GREBE, QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_DBGCORE_QCH_DBG, QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ALIVE_QCH, QCH_CON_SYSREG_ALIVE_QCH_ENABLE, QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_ALIVE0_QCH, QCH_CON_USI_ALIVE0_QCH_ENABLE, QCH_CON_USI_ALIVE0_QCH_CLOCK_REQ, QCH_CON_USI_ALIVE0_QCH_EXPIRE_VAL, QCH_CON_USI_ALIVE0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_ALIVE_QCH, QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_ALIVE_QCH, QCH_CON_WDT_ALIVE_QCH_ENABLE, QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL, QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK4, QCH_CON_ABOX_QCH_BCLK4_ENABLE, QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CNT, QCH_CON_ABOX_QCH_CNT_ENABLE, QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK5, QCH_CON_ABOX_QCH_BCLK5_ENABLE, QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK6, QCH_CON_ABOX_QCH_BCLK6_ENABLE, QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CPU, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_PCMC_CLK, QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_C2A0, QCH_CON_ABOX_QCH_C2A0_ENABLE, QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_C2A1, QCH_CON_ABOX_QCH_C2A1_ENABLE, QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_XCLK0, QCH_CON_ABOX_QCH_XCLK0_ENABLE, QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_XCLK1, QCH_CON_ABOX_QCH_XCLK1_ENABLE, QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_XCLK2, QCH_CON_ABOX_QCH_XCLK2_ENABLE, QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CPU0, QCH_CON_ABOX_QCH_CPU0_ENABLE, QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU0_EXPIRE_VAL, QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CPU1, QCH_CON_ABOX_QCH_CPU1_ENABLE, QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU1_EXPIRE_VAL, QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_NEON0, QCH_CON_ABOX_QCH_NEON0_ENABLE, QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON0_EXPIRE_VAL, QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_NEON1, QCH_CON_ABOX_QCH_NEON1_ENABLE, QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON1_EXPIRE_VAL, QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_L2, QCH_CON_ABOX_QCH_L2_ENABLE, QCH_CON_ABOX_QCH_L2_CLOCK_REQ, QCH_CON_ABOX_QCH_L2_EXPIRE_VAL, QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CCLK_ACP, QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE, QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ACP_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN),
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CLK_QCH(AUD_CMU_AUD_QCH, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_AUD_QCH, DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_AUD_QCH, QCH_CON_D_TZPC_AUD_QCH_ENABLE, QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_AUD_QCH, QCH_CON_LH_AXI_SI_D_AUD_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD0_QCH, QCH_CON_MAILBOX_AUD0_QCH_ENABLE, QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AUD1_QCH, QCH_CON_MAILBOX_AUD1_QCH_ENABLE, QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_AUD_QCH, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_USBAUD_QCH, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_AUD_QCH, QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AUD_QCH_S1, QCH_CON_SYSMMU_AUD_QCH_S1_ENABLE, QCH_CON_SYSMMU_AUD_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AUD_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AUD_QCH_S2, QCH_CON_SYSMMU_AUD_QCH_S2_ENABLE, QCH_CON_SYSMMU_AUD_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AUD_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_AUD_QCH, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_AUD_QCH, QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSC_CMU_BUSC_QCH, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_BUSC_CMUREF_QCH, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_BUSC_QCH, QCH_CON_D_TZPC_BUSC_QCH_ENABLE, QCH_CON_D_TZPC_BUSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_CHUBVTS_QCH, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_MFC_QCH, QCH_CON_LH_AXI_MI_D_MFC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_BUSC_QCH, QCH_CON_PDMA_BUSC_QCH_ENABLE, QCH_CON_PDMA_BUSC_QCH_CLOCK_REQ, QCH_CON_PDMA_BUSC_QCH_EXPIRE_VAL, QCH_CON_PDMA_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_APM_QCH, QCH_CON_SLH_AXI_MI_D_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_PERI_QCH, QCH_CON_SLH_AXI_MI_D_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_USB_QCH, QCH_CON_SLH_AXI_MI_D_USB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_BUSC_QCH, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPDMA_BUSC_QCH, QCH_CON_SPDMA_BUSC_QCH_ENABLE, QCH_CON_SPDMA_BUSC_QCH_CLOCK_REQ, QCH_CON_SPDMA_BUSC_QCH_EXPIRE_VAL, QCH_CON_SPDMA_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AXI_D_BUSC_QCH, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_ENABLE, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUSC_QCH, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_BUSC_QCH, QCH_CON_TREX_D_BUSC_QCH_ENABLE, QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_PDMA_QCH, QCH_CON_VGEN_PDMA_QCH_ENABLE, QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL, QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_SPDMA_QCH, QCH_CON_VGEN_SPDMA_QCH_ENABLE, QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_SPDMA_QCH_EXPIRE_VAL, QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_EXPIRE_VAL, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_GPIO_CHUB_QCH, QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE, QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CHUB_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_GPIO_CHUBEINT_QCH, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_ENABLE, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CHUB_CMU_CHUB_QCH, QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL, QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CM4_CHUB_QCH_CPU, QCH_CON_CM4_CHUB_QCH_CPU_ENABLE, QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ, QCH_CON_CM4_CHUB_QCH_CPU_EXPIRE_VAL, QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CHUB1_QCH, QCH_CON_I2C_CHUB1_QCH_ENABLE, QCH_CON_I2C_CHUB1_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB1_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CHUB3_QCH, QCH_CON_I2C_CHUB3_QCH_ENABLE, QCH_CON_I2C_CHUB3_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB3_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PWM_CHUB_QCH, QCH_CON_PWM_CHUB_QCH_ENABLE, QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL, QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_S_CHUB_QCH, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_M_CHUB_QCH, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CHUB_QCH, QCH_CON_SYSREG_CHUB_QCH_ENABLE, QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_COMBINE_CHUB2AP_QCH, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_COMBINE_CHUB2APM_QCH, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_COMBINE_CHUB2WLBT_QCH, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER_CHUB_QCH, QCH_CON_TIMER_CHUB_QCH_ENABLE, QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL, QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB0_QCH, QCH_CON_USI_CHUB0_QCH_ENABLE, QCH_CON_USI_CHUB0_QCH_CLOCK_REQ, QCH_CON_USI_CHUB0_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB1_QCH, QCH_CON_USI_CHUB1_QCH_ENABLE, QCH_CON_USI_CHUB1_QCH_CLOCK_REQ, QCH_CON_USI_CHUB1_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB2_QCH, QCH_CON_USI_CHUB2_QCH_ENABLE, QCH_CON_USI_CHUB2_QCH_CLOCK_REQ, QCH_CON_USI_CHUB2_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB3_QCH, QCH_CON_USI_CHUB3_QCH_ENABLE, QCH_CON_USI_CHUB3_QCH_CLOCK_REQ, QCH_CON_USI_CHUB3_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CHUB_QCH, QCH_CON_WDT_CHUB_QCH_ENABLE, QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL, QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_CHUB_QCH, QCH_CON_BAAW_CHUB_QCH_ENABLE, QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_VTS_QCH, QCH_CON_BAAW_VTS_QCH_ENABLE, QCH_CON_BAAW_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CHUBVTS_CMU_CHUBVTS_QCH, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CHUBVTS_QCH, QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE, QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_CHUBVTS_QCH, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_LP_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_M_CHUB_QCH, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_M_VTS_QCH, QCH_CON_SLH_AXI_MI_M_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_M_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_M_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_M_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_C_CHUBVTS_QCH, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_S_CHUB_QCH, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_S_VTS_QCH, QCH_CON_SLH_AXI_SI_S_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_S_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_S_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_S_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_C_CHUBVTS_QCH, QCH_CON_SWEEPER_C_CHUBVTS_QCH_ENABLE, QCH_CON_SWEEPER_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SWEEPER_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CHUBVTS_QCH, QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE, QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_CHUBVTS_QCH, QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE, QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CMGP_QCH, QCH_CON_D_TZPC_CMGP_QCH_ENABLE, QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP0_QCH, QCH_CON_I2C_CMGP0_QCH_ENABLE, QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP1_QCH, QCH_CON_I2C_CMGP1_QCH_ENABLE, QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP2_QCH, QCH_CON_I2C_CMGP2_QCH_ENABLE, QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP3_QCH, QCH_CON_I2C_CMGP3_QCH_ENABLE, QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP4_QCH, QCH_CON_I2C_CMGP4_QCH_ENABLE, QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP4_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_CMGP_QCH_P, QCH_CON_I3C_CMGP_QCH_P_ENABLE, QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ, QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL, QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(I3C_CMGP_QCH_S, QCH_CON_I3C_CMGP_QCH_S_ENABLE, QCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ, QCH_CON_I3C_CMGP_QCH_S_EXPIRE_VAL, QCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_C_CMGP_QCH, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2APM_QCH, QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CHUB_QCH, QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2WLBT_QCH, QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP0_QCH, QCH_CON_USI_CMGP0_QCH_ENABLE, QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP1_QCH, QCH_CON_USI_CMGP1_QCH_ENABLE, QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP2_QCH, QCH_CON_USI_CMGP2_QCH_ENABLE, QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP3_QCH, QCH_CON_USI_CMGP3_QCH_ENABLE, QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP4_QCH, QCH_CON_USI_CMGP4_QCH_ENABLE, QCH_CON_USI_CMGP4_QCH_CLOCK_REQ, QCH_CON_USI_CMGP4_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CMU_CMUREF_QCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK5, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_APB_G_BDU_QCH, DMYQCH_CON_ADM_APB_G_BDU_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_BDU_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_G_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_D_SSS_QCH, QCH_CON_BAAW_D_SSS_QCH_ENABLE, QCH_CON_BAAW_D_SSS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_SSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_MODEM_QCH, QCH_CON_BAAW_P_MODEM_QCH_ENABLE, QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_WLBT_QCH, QCH_CON_BAAW_P_WLBT_QCH_ENABLE, QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CORE_CMUREF_QCH, DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CORE_QCH, QCH_CON_D_TZPC_CORE_QCH_ENABLE, QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HW_APBSEMA_MEC_QCH, QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE, QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ, QCH_CON_HW_APBSEMA_MEC_QCH_EXPIRE_VAL, QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_G_CPU_QCH, QCH_CON_LH_AST_MI_G_CPU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D0_DPU_QCH, QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D0_NPUS_QCH, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D1_DPU_QCH, QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D1_NPUS_QCH, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_AUD_QCH, QCH_CON_LH_AXI_MI_D_AUD_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_G3D_QCH, QCH_CON_LH_AXI_MI_D_G3D_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_M2M_QCH, QCH_CON_LH_AXI_MI_D_M2M_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_SSS_QCH, QCH_CON_LH_AXI_MI_D_SSS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_MIF_CP_QCH, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_MIF_NRT_QCH, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_MIF_RT_QCH, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_MIF_CP_QCH, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_MIF_NRT_QCH, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_MIF_RT_QCH, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_SSS_QCH, QCH_CON_LH_AXI_SI_D_SSS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PUF_QCH, DMYQCH_CON_PUF_QCH_ENABLE, DMYQCH_CON_PUF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_I_ARESETN_SSS_QCH, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_ENABLE, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFR_APBIF_CMU_TOPC_QCH, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIREX_QCH, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D0_MODEM_QCH, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D1_MODEM_QCH, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_GNSS_QCH, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_HSI_QCH, QCH_CON_SLH_AXI_MI_D_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_D_WLBT_QCH, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_G_CSSYS_QCH, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_CLUSTER0_QCH, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_APM_QCH, QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_AUD_QCH, QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_BUSC_QCH, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_CSIS_QCH, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_DPU_QCH, QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_G3D_QCH, QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_GNSS_QCH, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_HSI_QCH, QCH_CON_SLH_AXI_SI_P_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_ISP_QCH, QCH_CON_SLH_AXI_SI_P_ISP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_ISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_M2M_QCH, QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MCSC_QCH, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MCW_QCH, QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCW_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MFC_QCH, QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MIF0_QCH, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MIF1_QCH, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_MODEM_QCH, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_NPU0_QCH, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_NPUS_QCH, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_PERI_QCH, QCH_CON_SLH_AXI_SI_P_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_TAA_QCH, QCH_CON_SLH_AXI_SI_P_TAA_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TAA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_TNR_QCH, QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_USB_QCH, QCH_CON_SLH_AXI_SI_P_USB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_WLBT_QCH, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_ACEL_D2_MODEM_QCH, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_ENABLE, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_CLOCK_REQ, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_ACEL_D_DIT_QCH, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_ENABLE, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_CLOCK_REQ, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_NRT_QCH, QCH_CON_TREX_D_NRT_QCH_ENABLE, QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_CORE_QCH, QCH_CON_TREX_P_CORE_QCH_ENABLE, QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_CORE_QCH, QCH_CON_VGEN_LITE_CORE_QCH_ENABLE, QCH_CON_VGEN_LITE_CORE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CORE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_QCH, DMYQCH_CON_CPUCL0_QCH_ENABLE, DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL0_QCH_PCLK, QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL0_QCH_CLK, QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(BPS_CPUCL0_QCH, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSSYS_QCH, DMYQCH_CON_CSSYS_QCH_ENABLE, DMYQCH_CON_CSSYS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CPUCL0_QCH, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_G_INT_CSSYS_QCH, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_G_INT_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_G_CSSYS_QCH, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_G_INT_CSSYS_QCH, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_G_INT_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_BIG, DMYQCH_CON_CPUCL1_QCH_BIG_ENABLE, DMYQCH_CON_CPUCL1_QCH_BIG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_BIG_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_DDD_HC0, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_QCH_DDD_HC1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL1_QCH_PCLK, QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_CPUCL1_QCH_CLK, QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_CMU_CSIS_QCH, QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_VOTF0, QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF0_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_DMA, QCH_CON_CSIS_PDP_QCH_DMA_ENABLE, QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_DMA_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_PDP_TOP, QCH_CON_CSIS_PDP_QCH_PDP_TOP_ENABLE, QCH_CON_CSIS_PDP_QCH_PDP_TOP_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_PDP_TOP_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_MCB, QCH_CON_CSIS_PDP_QCH_MCB_ENABLE, QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_MCB_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_VOTF1, QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF1_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_C2_PDP, QCH_CON_CSIS_PDP_QCH_C2_PDP_ENABLE, QCH_CON_CSIS_PDP_QCH_C2_PDP_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_C2_PDP_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_C2_PDP_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_CSIS_QCH, QCH_CON_D_TZPC_CSIS_QCH_ENABLE, QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_SOTF0_TAACSIS_QCH, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_SOTF1_TAACSIS_QCH, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_SOTF2_TAACSIS_QCH, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_ZOTF0_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_ZOTF1_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_ZOTF2_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF0_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF1_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF2_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_CSIS_QCH, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_CSIS_QCH, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D2_CSIS_QCH, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D3_CSIS_QCH, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS0, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS2, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS3, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS4, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIPI_DCPHY_LINK_WRAP_QCH_CSIS5, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CSIS_D0_QCH, QCH_CON_PPMU_CSIS_D0_QCH_ENABLE, QCH_CON_PPMU_CSIS_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CSIS_D1_QCH, QCH_CON_PPMU_CSIS_D1_QCH_ENABLE, QCH_CON_PPMU_CSIS_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CSIS_D2_QCH, QCH_CON_PPMU_CSIS_D2_QCH_ENABLE, QCH_CON_PPMU_CSIS_D2_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D2_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CSIS_D3_QCH, QCH_CON_PPMU_CSIS_D3_QCH_ENABLE, QCH_CON_PPMU_CSIS_D3_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D3_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA0_QCH, QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA1_QCH, QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA2_QCH, QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_CSIS_DMA3_QCH, QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_AF0_QCH, QCH_CON_QE_PDP_AF0_QCH_ENABLE, QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_AF1_QCH, QCH_CON_QE_PDP_AF1_QCH_ENABLE, QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_AF2_QCH, QCH_CON_QE_PDP_AF2_QCH_ENABLE, QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG0_QCH, QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG1_QCH, QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_PDP_STAT_IMG2_QCH, QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP0_QCH, QCH_CON_QE_STRP0_QCH_ENABLE, QCH_CON_QE_STRP0_QCH_CLOCK_REQ, QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP1_QCH, QCH_CON_QE_STRP1_QCH_ENABLE, QCH_CON_QE_STRP1_QCH_CLOCK_REQ, QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_STRP2_QCH, QCH_CON_QE_STRP2_QCH_ENABLE, QCH_CON_QE_STRP2_QCH_CLOCK_REQ, QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL0_QCH, QCH_CON_QE_ZSL0_QCH_ENABLE, QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL1_QCH, QCH_CON_QE_ZSL1_QCH_ENABLE, QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ZSL2_QCH, QCH_CON_QE_ZSL2_QCH_ENABLE, QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_CSIS_QCH, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_CSIS_QCH_S1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_CSIS_QCH_S2, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_CSIS_QCH_S1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_CSIS_QCH_S2, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_CSIS_QCH_S1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D2_CSIS_QCH_S2, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_CSIS_QCH_S2, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D3_CSIS_QCH_S1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CSIS_QCH, QCH_CON_SYSREG_CSIS_QCH_ENABLE, QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE0_CSIS_QCH, QCH_CON_VGEN_LITE0_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE0_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE0_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE1_CSIS_QCH, QCH_CON_VGEN_LITE1_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE1_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE1_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE2_CSIS_QCH, QCH_CON_VGEN_LITE2_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE2_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE2_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU, QCH_CON_DPU_QCH_DPU_ENABLE, QCH_CON_DPU_QCH_DPU_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_DMA, QCH_CON_DPU_QCH_DPU_DMA_ENABLE, QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_DPP, QCH_CON_DPU_QCH_DPU_DPP_ENABLE, QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_C2SERV, QCH_CON_DPU_QCH_DPU_C2SERV_ENABLE, QCH_CON_DPU_QCH_DPU_C2SERV_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_C2SERV_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_C2SERV_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH, DMYQCH_CON_DPU_QCH_ENABLE, DMYQCH_CON_DPU_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_CMU_DPU_QCH, QCH_CON_DPU_CMU_DPU_QCH_ENABLE, QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_DPU_QCH, QCH_CON_D_TZPC_DPU_QCH_ENABLE, QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_DPU_QCH, QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_DPU_QCH, QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_DPU_QCH, QCH_CON_PPMU_D0_DPU_QCH_ENABLE, QCH_CON_PPMU_D0_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_DPU_QCH, QCH_CON_PPMU_D1_DPU_QCH_ENABLE, QCH_CON_PPMU_D1_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_DPU_QCH, QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AXI_D0_DPU_QCH_S1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_ENABLE, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AXI_D0_DPU_QCH_S2, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_ENABLE, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AXI_D1_DPU_QCH_S1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_ENABLE, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AXI_D1_DPU_QCH_S2, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_ENABLE, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DPU_QCH, QCH_CON_SYSREG_DPU_QCH_ENABLE, QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_GIC, QCH_CON_CLUSTER0_QCH_GIC_ENABLE, QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_DBG_PD, QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PCLK, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PERIPHCLK, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PDBGCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_DSU_CMUREF_QCH, DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_DSU_SHORTSTOP_QCH, QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DSU_CMU_DSU_QCH, QCH_CON_DSU_CMU_DSU_QCH_ENABLE, QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL, QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_DSU_QCH_PCLK, QCH_CON_HTU_DSU_QCH_PCLK_ENABLE, QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_DSU_QCH_CLK, QCH_CON_HTU_DSU_QCH_CLK_ENABLE, QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_G_CPU_QCH, QCH_CON_LH_AST_SI_G_CPU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_MIF_CPU_QCH, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_MIF_CPU_QCH, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRET_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRET_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRUN_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPC_INSTRRUN_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL0_QCH, QCH_CON_PPMU_CPUCL0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL1_QCH, QCH_CON_PPMU_CPUCL1_QCH_ENABLE, QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_CLUSTER0_QCH, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_G3D_QCH, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPU_QCH, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_G3D_QCH_CLK, QCH_CON_HTU_G3D_QCH_CLK_ENABLE, QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_G3D_QCH_PCLK, QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_INT_G3D_QCH, QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_INT_G3D_QCH, QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_G3D_QCH, QCH_CON_LH_AXI_SI_D_G3D_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D_G3D_QCH, QCH_CON_PPMU_D_G3D_QCH_ENABLE, QCH_CON_PPMU_D_G3D_QCH_CLOCK_REQ, QCH_CON_PPMU_D_G3D_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_G3D_QCH, QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_G3D_QCH, QCH_CON_SYSMMU_D_G3D_QCH_ENABLE, QCH_CON_SYSMMU_D_G3D_QCH_CLOCK_REQ, QCH_CON_SYSMMU_D_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_G3D_QCH, QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GNSS_CMU_GNSS_QCH, QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE, QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ, QCH_CON_GNSS_CMU_GNSS_QCH_EXPIRE_VAL, QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_HSI_QCH, QCH_CON_D_TZPC_HSI_QCH_ENABLE, QCH_CON_D_TZPC_HSI_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_HSI_QCH, QCH_CON_GPIO_HSI_QCH_ENABLE, QCH_CON_GPIO_HSI_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_HSI_UFS_QCH, QCH_CON_GPIO_HSI_UFS_QCH_ENABLE, QCH_CON_GPIO_HSI_UFS_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI_UFS_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI_UFS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HSI_CMU_HSI_QCH, QCH_CON_HSI_CMU_HSI_QCH_ENABLE, QCH_CON_HSI_CMU_HSI_QCH_CLOCK_REQ, QCH_CON_HSI_CMU_HSI_QCH_EXPIRE_VAL, QCH_CON_HSI_CMU_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_HSI_QCH, QCH_CON_PPMU_HSI_QCH_ENABLE, QCH_CON_PPMU_HSI_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2MPU_D_HSI_QCH_S2, QCH_CON_S2MPU_D_HSI_QCH_S2_ENABLE, QCH_CON_S2MPU_D_HSI_QCH_S2_CLOCK_REQ, QCH_CON_S2MPU_D_HSI_QCH_S2_EXPIRE_VAL, QCH_CON_S2MPU_D_HSI_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_HSI_QCH, QCH_CON_SLH_AXI_MI_P_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_D_HSI_QCH, QCH_CON_SLH_AXI_SI_D_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_HSI_QCH, QCH_CON_SYSREG_HSI_QCH_ENABLE, QCH_CON_SYSREG_HSI_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_HSI_QCH, QCH_CON_VGEN_LITE_HSI_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_HSI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_ISP_QCH, QCH_CON_D_TZPC_ISP_QCH_ENABLE, QCH_CON_D_TZPC_ISP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ISP_CMU_ISP_QCH, QCH_CON_ISP_CMU_ISP_QCH_ENABLE, QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ITP_DNS_QCH_S00, QCH_CON_ITP_DNS_QCH_S00_ENABLE, QCH_CON_ITP_DNS_QCH_S00_CLOCK_REQ, QCH_CON_ITP_DNS_QCH_S00_EXPIRE_VAL, QCH_CON_ITP_DNS_QCH_S00_IGNORE_FORCE_PM_EN),
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CLK_QCH(ITP_DNS_QCH_S01, QCH_CON_ITP_DNS_QCH_S01_ENABLE, QCH_CON_ITP_DNS_QCH_S01_CLOCK_REQ, QCH_CON_ITP_DNS_QCH_S01_EXPIRE_VAL, QCH_CON_ITP_DNS_QCH_S01_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF0_TNRISP_QCH, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF1_TNRISP_QCH, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF_TAAISP_QCH, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF_ISPMCSC_QCH, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_ISP_QCH, QCH_CON_LH_AXI_SI_D_ISP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_ISP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_ISP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_ISP_QCH, QCH_CON_PPMU_ISP_QCH_ENABLE, QCH_CON_PPMU_ISP_QCH_CLOCK_REQ, QCH_CON_PPMU_ISP_QCH_EXPIRE_VAL, QCH_CON_PPMU_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_ISP_QCH, QCH_CON_SLH_AXI_MI_P_ISP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_ISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_ISP_QCH_S1, QCH_CON_SYSMMU_D_ISP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_ISP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_ISP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_ISP_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_ISP_QCH_S2, QCH_CON_SYSMMU_D_ISP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_ISP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_ISP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_ISP_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ISP_QCH, QCH_CON_SYSREG_ISP_QCH_ENABLE, QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_ISP_QCH, QCH_CON_VGEN_LITE_ISP_QCH_ENABLE, QCH_CON_VGEN_LITE_ISP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ISP_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_M2M_QCH, QCH_CON_D_TZPC_M2M_QCH_ENABLE, QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JPEG0_QCH, QCH_CON_JPEG0_QCH_ENABLE, QCH_CON_JPEG0_QCH_CLOCK_REQ, QCH_CON_JPEG0_QCH_EXPIRE_VAL, QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_M2M_QCH, QCH_CON_LH_AXI_SI_D_M2M_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_QCH_S2, QCH_CON_M2M_QCH_S2_ENABLE, QCH_CON_M2M_QCH_S2_CLOCK_REQ, QCH_CON_M2M_QCH_S2_EXPIRE_VAL, QCH_CON_M2M_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_QCH_S1, QCH_CON_M2M_QCH_S1_ENABLE, QCH_CON_M2M_QCH_S1_CLOCK_REQ, QCH_CON_M2M_QCH_S1_EXPIRE_VAL, QCH_CON_M2M_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(M2M_CMU_M2M_QCH, QCH_CON_M2M_CMU_M2M_QCH_ENABLE, QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL, QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D_M2M_QCH, QCH_CON_PPMU_D_M2M_QCH_ENABLE, QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_M2M_QCH, QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_M2M_QCH_S1, QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D_M2M_QCH_S2, QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_M2M_QCH, QCH_CON_SYSREG_M2M_QCH_ENABLE, QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL, QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_M2M_QCH, QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MCSC_QCH, QCH_CON_D_TZPC_MCSC_QCH_ENABLE, QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GDC_QCH, QCH_CON_GDC_QCH_ENABLE, QCH_CON_GDC_QCH_CLOCK_REQ, QCH_CON_GDC_QCH_EXPIRE_VAL, QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF_ISPMCSC_QCH, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D0_CSIS_QCH, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D0_TNR_QCH, QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D1_CSIS_QCH, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D1_TNR_QCH, QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D2_CSIS_QCH, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D3_CSIS_QCH, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_ISP_QCH, QCH_CON_LH_AXI_MI_D_ISP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_ISP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_ISP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_TAA_QCH, QCH_CON_LH_AXI_MI_D_TAA_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_QCH, QCH_CON_MCSC_QCH_ENABLE, QCH_CON_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCSC_CMU_MCSC_QCH, QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH_QCH_ACLK, QCH_CON_ORBMCH_QCH_ACLK_ENABLE, QCH_CON_ORBMCH_QCH_ACLK_CLOCK_REQ, QCH_CON_ORBMCH_QCH_ACLK_EXPIRE_VAL, QCH_CON_ORBMCH_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ORBMCH_QCH_C2CLK, QCH_CON_ORBMCH_QCH_C2CLK_ENABLE, QCH_CON_ORBMCH_QCH_C2CLK_CLOCK_REQ, QCH_CON_ORBMCH_QCH_C2CLK_EXPIRE_VAL, QCH_CON_ORBMCH_QCH_C2CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_GDC_QCH, QCH_CON_PPMU_GDC_QCH_ENABLE, QCH_CON_PPMU_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_GDC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MCSC_QCH, QCH_CON_PPMU_MCSC_QCH_ENABLE, QCH_CON_PPMU_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_MCSC_QCH, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCSC_QCH_S1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_MCSC_QCH_S2, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCSC_QCH_S1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_MCSC_QCH_S2, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MCSC_QCH, QCH_CON_SYSREG_MCSC_QCH_ENABLE, QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_CAM_QCH, QCH_CON_TREX_D_CAM_QCH_ENABLE, QCH_CON_TREX_D_CAM_QCH_CLOCK_REQ, QCH_CON_TREX_D_CAM_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_GDC_QCH, QCH_CON_VGEN_LITE_GDC_QCH_ENABLE, QCH_CON_VGEN_LITE_GDC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_GDC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_GDC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_MCSC_QCH, QCH_CON_VGEN_LITE_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MCSC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MCSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MFC_QCH, QCH_CON_D_TZPC_MFC_QCH_ENABLE, QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_MFC_QCH, QCH_CON_LH_AXI_SI_D_MFC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFC_QCH, QCH_CON_PPMU_MFC_QCH_ENABLE, QCH_CON_PPMU_MFC_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_MFC_QCH, QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC_QCH_S1, QCH_CON_SYSMMU_MFC_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFC_QCH_S2, QCH_CON_SYSMMU_MFC_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_MFC_QCH, QCH_CON_VGEN_LITE_MFC_QCH_ENABLE, QCH_CON_VGEN_LITE_MFC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MFC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_MIF_QCH, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_MIF_CP_QCH, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_MIF_CPU_QCH, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_MIF_NRT_QCH, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_MIF_RT_QCH, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DMC_CPU_QCH, QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_DMC_CPU_QCH, QCH_CON_QE_DMC_CPU_QCH_ENABLE, QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DDRPHY_QCH, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_PF_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_PPMPU_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_SECURE_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_MIF_QCH, QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MODEM_CMU_MODEM_QCH, QCH_CON_MODEM_CMU_MODEM_QCH_ENABLE, QCH_CON_MODEM_CMU_MODEM_QCH_CLOCK_REQ, QCH_CON_MODEM_CMU_MODEM_QCH_EXPIRE_VAL, QCH_CON_MODEM_CMU_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPU0_QCH, QCH_CON_D_TZPC_NPU0_QCH_ENABLE, QCH_CON_D_TZPC_NPU0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUCORE_QCH_ACLK, QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUCORE_QCH_PCLK, QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D0_NPU0_QCH, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D1_NPU0_QCH, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_CTRL_NPU0_QCH, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_CMDQ_NPU0_QCH, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_RQ_NPU0_QCH, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPU0_CMU_NPU0_QCH, QCH_CON_NPU0_CMU_NPU0_QCH_ENABLE, QCH_CON_NPU0_CMU_NPU0_QCH_CLOCK_REQ, QCH_CON_NPU0_CMU_NPU0_QCH_EXPIRE_VAL, QCH_CON_NPU0_CMU_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_NPU0_QCH, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPU0_QCH, QCH_CON_SYSREG_NPU0_QCH_ENABLE, QCH_CON_SYSREG_NPU0_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_DAP_NPUS_QCH, DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE, DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_NPUS_QCH, QCH_CON_D_TZPC_NPUS_QCH_ENABLE, QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_NPUS_QCH_PCLK, QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE, QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(HTU_NPUS_QCH_CLK, QCH_CON_HTU_NPUS_QCH_CLK_ENABLE, QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH, QCH_CON_IP_NPUS_QCH_ENABLE, QCH_CON_IP_NPUS_QCH_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_C2A0CLK, QCH_CON_IP_NPUS_QCH_C2A0CLK_ENABLE, QCH_CON_IP_NPUS_QCH_C2A0CLK_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A0CLK_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A0CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_C2A1CLK, QCH_CON_IP_NPUS_QCH_C2A1CLK_ENABLE, QCH_CON_IP_NPUS_QCH_C2A1CLK_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A1CLK_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A1CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_CPU, QCH_CON_IP_NPUS_QCH_CPU_ENABLE, QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IP_NPUS_QCH_NEON, QCH_CON_IP_NPUS_QCH_NEON_ENABLE, QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_CMDQ_NPU0_QCH, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_D_RQ_NPU0_QCH, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_NPU0_QCH, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_NPUS_QCH, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_NPU0_QCH, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_NPUS_QCH, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_CTRL_NPU0_QCH, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(NPUS_CMU_NPUS_QCH, QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE, QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ, QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL, QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_NPUS_0_QCH, QCH_CON_PPMU_NPUS_0_QCH_ENABLE, QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_NPUS_1_QCH, QCH_CON_PPMU_NPUS_1_QCH_ENABLE, QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_INT_NPUS_QCH, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_NPUS_QCH, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_P_INT_NPUS_QCH, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_NPUS_QCH_S1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_NPUS_QCH_S2, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_NPUS_QCH_S1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_NPUS_QCH_S2, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_NPUS_QCH, QCH_CON_SYSREG_NPUS_QCH_ENABLE, QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_NPUS_QCH, QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE, QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_PERI_QCH, QCH_CON_D_TZPC_PERI_QCH_ENABLE, QCH_CON_D_TZPC_PERI_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERI_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERI_QCH, QCH_CON_GPIO_PERI_QCH_ENABLE, QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERIMMC_QCH_GPIO, QCH_CON_GPIO_PERIMMC_QCH_GPIO_ENABLE, QCH_CON_GPIO_PERIMMC_QCH_GPIO_CLOCK_REQ, QCH_CON_GPIO_PERIMMC_QCH_GPIO_EXPIRE_VAL, QCH_CON_GPIO_PERIMMC_QCH_GPIO_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERI_CMU_PERI_QCH, QCH_CON_PERI_CMU_PERI_QCH_ENABLE, QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_PERI_QCH, QCH_CON_PPMU_PERI_QCH_ENABLE, QCH_CON_PPMU_PERI_QCH_CLOCK_REQ, QCH_CON_PPMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PPMU_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2MPU_D_PERI_QCH, QCH_CON_S2MPU_D_PERI_QCH_ENABLE, QCH_CON_S2MPU_D_PERI_QCH_CLOCK_REQ, QCH_CON_S2MPU_D_PERI_QCH_EXPIRE_VAL, QCH_CON_S2MPU_D_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_PERI_QCH, QCH_CON_SLH_AXI_MI_P_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_D_PERI_QCH, QCH_CON_SLH_AXI_SI_D_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERI_QCH, QCH_CON_SYSREG_PERI_QCH_ENABLE, QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TMU_QCH, QCH_CON_TMU_QCH_ENABLE, QCH_CON_TMU_QCH_CLOCK_REQ, QCH_CON_TMU_QCH_EXPIRE_VAL, QCH_CON_TMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UART_DBG_QCH, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL, QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI00_I2C_QCH, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI00_USI_QCH, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI01_I2C_QCH, QCH_CON_USI01_I2C_QCH_ENABLE, QCH_CON_USI01_I2C_QCH_CLOCK_REQ, QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI01_USI_QCH, QCH_CON_USI01_USI_QCH_ENABLE, QCH_CON_USI01_USI_QCH_CLOCK_REQ, QCH_CON_USI01_USI_QCH_EXPIRE_VAL, QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI02_I2C_QCH, QCH_CON_USI02_I2C_QCH_ENABLE, QCH_CON_USI02_I2C_QCH_CLOCK_REQ, QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI02_USI_QCH, QCH_CON_USI02_USI_QCH_ENABLE, QCH_CON_USI02_USI_QCH_CLOCK_REQ, QCH_CON_USI02_USI_QCH_EXPIRE_VAL, QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI03_I2C_QCH, QCH_CON_USI03_I2C_QCH_ENABLE, QCH_CON_USI03_I2C_QCH_CLOCK_REQ, QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI03_USI_QCH, QCH_CON_USI03_USI_QCH_ENABLE, QCH_CON_USI03_USI_QCH_CLOCK_REQ, QCH_CON_USI03_USI_QCH_EXPIRE_VAL, QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI04_I2C_QCH, QCH_CON_USI04_I2C_QCH_ENABLE, QCH_CON_USI04_I2C_QCH_CLOCK_REQ, QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI04_USI_QCH, QCH_CON_USI04_USI_QCH_ENABLE, QCH_CON_USI04_USI_QCH_CLOCK_REQ, QCH_CON_USI04_USI_QCH_EXPIRE_VAL, QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI05_I2C_QCH, QCH_CON_USI05_I2C_QCH_ENABLE, QCH_CON_USI05_I2C_QCH_CLOCK_REQ, QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI05_USI_QCH, QCH_CON_USI05_USI_QCH_ENABLE, QCH_CON_USI05_USI_QCH_CLOCK_REQ, QCH_CON_USI05_USI_QCH_EXPIRE_VAL, QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI06_I2C_QCH, QCH_CON_USI06_I2C_QCH_ENABLE, QCH_CON_USI06_I2C_QCH_CLOCK_REQ, QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI06_USI_QCH, QCH_CON_USI06_USI_QCH_ENABLE, QCH_CON_USI06_USI_QCH_CLOCK_REQ, QCH_CON_USI06_USI_QCH_EXPIRE_VAL, QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI07_I2C_QCH, QCH_CON_USI07_I2C_QCH_ENABLE, QCH_CON_USI07_I2C_QCH_CLOCK_REQ, QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_PERI_QCH, QCH_CON_VGEN_LITE_PERI_QCH_ENABLE, QCH_CON_VGEN_LITE_PERI_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_PERI_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT0_QCH, QCH_CON_WDT0_QCH_ENABLE, QCH_CON_WDT0_QCH_CLOCK_REQ, QCH_CON_WDT0_QCH_EXPIRE_VAL, QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT1_QCH, QCH_CON_WDT1_QCH_ENABLE, QCH_CON_WDT1_QCH_CLOCK_REQ, QCH_CON_WDT1_QCH_EXPIRE_VAL, QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_G_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_TAA_QCH, QCH_CON_D_TZPC_TAA_QCH_ENABLE, QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF0_CSISTAA_QCH, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF1_CSISTAA_QCH, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF2_CSISTAA_QCH, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF_TAAISP_QCH, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_SOTF0_TAACSIS_QCH, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_SOTF1_TAACSIS_QCH, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_SOTF2_TAACSIS_QCH, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_ZOTF0_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_ZOTF1_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_ZOTF2_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_TAA_QCH, QCH_CON_LH_AXI_SI_D_TAA_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_TAA_QCH, QCH_CON_PPMU_TAA_QCH_ENABLE, QCH_CON_PPMU_TAA_QCH_CLOCK_REQ, QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL, QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH, QCH_CON_SIPU_TAA_QCH_ENABLE, QCH_CON_SIPU_TAA_QCH_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH_C2_STAT, QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIPU_TAA_QCH_C2_YDS, QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_TAA_QCH, QCH_CON_SLH_AXI_MI_P_TAA_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TAA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_TAA_QCH_S1, QCH_CON_SYSMMU_TAA_QCH_S1_ENABLE, QCH_CON_SYSMMU_TAA_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_TAA_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_TAA_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_TAA_QCH_S2, QCH_CON_SYSMMU_TAA_QCH_S2_ENABLE, QCH_CON_SYSMMU_TAA_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_TAA_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_TAA_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_TAA_QCH, QCH_CON_SYSREG_TAA_QCH_ENABLE, QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ, QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TAA_CMU_TAA_QCH, QCH_CON_TAA_CMU_TAA_QCH_ENABLE, QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ, QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL, QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE0_TAA_QCH, QCH_CON_VGEN_LITE0_TAA_QCH_ENABLE, QCH_CON_VGEN_LITE0_TAA_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE0_TAA_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE0_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE1_TAA_QCH, QCH_CON_VGEN_LITE1_TAA_QCH_ENABLE, QCH_CON_VGEN_LITE1_TAA_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE1_TAA_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE1_TAA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_TNR_QCH, QCH_CON_D_TZPC_TNR_QCH_ENABLE, QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF0_TNRISP_QCH, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF1_TNRISP_QCH, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_TNR_QCH, QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_TNR_QCH, QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D0_TNR_QCH, QCH_CON_PPMU_D0_TNR_QCH_ENABLE, QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D1_TNR_QCH, QCH_CON_PPMU_D1_TNR_QCH_ENABLE, QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_TNR_QCH, QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_TNR_QCH_S1, QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D0_TNR_QCH_S2, QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_TNR_QCH_S1, QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_D1_TNR_QCH_S2, QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_TNR_QCH, QCH_CON_SYSREG_TNR_QCH_ENABLE, QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TNR_QCH_MCFP0, QCH_CON_TNR_QCH_MCFP0_ENABLE, QCH_CON_TNR_QCH_MCFP0_CLOCK_REQ, QCH_CON_TNR_QCH_MCFP0_EXPIRE_VAL, QCH_CON_TNR_QCH_MCFP0_IGNORE_FORCE_PM_EN),
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CLK_QCH(TNR_QCH_MCFP1, QCH_CON_TNR_QCH_MCFP1_ENABLE, QCH_CON_TNR_QCH_MCFP1_CLOCK_REQ, QCH_CON_TNR_QCH_MCFP1_EXPIRE_VAL, QCH_CON_TNR_QCH_MCFP1_IGNORE_FORCE_PM_EN),
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CLK_QCH(TNR_CMU_TNR_QCH, QCH_CON_TNR_CMU_TNR_QCH_ENABLE, QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_D_TNR_QCH, QCH_CON_VGEN_LITE_D_TNR_QCH_ENABLE, QCH_CON_VGEN_LITE_D_TNR_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_TNR_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D_TNR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(D_TZPC_USB_QCH, QCH_CON_D_TZPC_USB_QCH_ENABLE, QCH_CON_D_TZPC_USB_QCH_CLOCK_REQ, QCH_CON_D_TZPC_USB_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_USB_QCH, QCH_CON_PPMU_USB_QCH_ENABLE, QCH_CON_PPMU_USB_QCH_CLOCK_REQ, QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2MPU_D_USB_QCH, QCH_CON_S2MPU_D_USB_QCH_ENABLE, QCH_CON_S2MPU_D_USB_QCH_CLOCK_REQ, QCH_CON_S2MPU_D_USB_QCH_EXPIRE_VAL, QCH_CON_S2MPU_D_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_USB_QCH, QCH_CON_SLH_AXI_MI_P_USB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_D_USB_QCH, QCH_CON_SLH_AXI_SI_D_USB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_D_USBAUD_QCH, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_USB_QCH, QCH_CON_SYSREG_USB_QCH_ENABLE, QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB20DRD_TOP_QCH_SLV_CTRL, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_ENABLE, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_CLOCK_REQ, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_EXPIRE_VAL, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB20DRD_TOP_QCH_SLV_LINK, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_ENABLE, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_CLOCK_REQ, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_EXPIRE_VAL, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB_CMU_USB_QCH, QCH_CON_USB_CMU_USB_QCH_ENABLE, QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_USB_QCH, QCH_CON_VGEN_LITE_USB_QCH_ENABLE, QCH_CON_VGEN_LITE_USB_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_USB_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CM4_VTS_QCH_CPU, QCH_CON_CM4_VTS_QCH_CPU_ENABLE, QCH_CON_CM4_VTS_QCH_CPU_CLOCK_REQ, QCH_CON_CM4_VTS_QCH_CPU_EXPIRE_VAL, QCH_CON_CM4_VTS_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB0_QCH_PCLK, QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB2_QCH_PCLK, QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD0_QCH_PCLK, QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD0_QCH_DMIC, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD1_QCH_PCLK, QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AUD1_QCH_DMIC, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF0_QCH_PCLK, QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF0_QCH_DMIC, DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF1_QCH_PCLK, QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_IF1_QCH_DMIC, DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC0_QCH, QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_DMIC2_QCH, QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(HWACG_SYS_SERIAL_LIF_QCH, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_ABOX_VTS_QCH, QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_VTS_QCH, QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_AUD_QCH_PCLK, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_EXPIRE_VAL, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_AUD_QCH_AHB, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_ENABLE, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_IGNORE_FORCE_PM_EN),
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CLK_QCH(SERIAL_LIF_AUD_QCH_LIF, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_ENABLE, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_S_VTS_QCH, QCH_CON_SLH_AXI_MI_S_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_S_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_S_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_S_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_M_VTS_QCH, QCH_CON_SLH_AXI_SI_M_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_M_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_M_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_M_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN),
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CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER_VTS_QCH, QCH_CON_TIMER_VTS_QCH_ENABLE, QCH_CON_TIMER_VTS_QCH_CLOCK_REQ, QCH_CON_TIMER_VTS_QCH_EXPIRE_VAL, QCH_CON_TIMER_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN),
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};
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unsigned int cmucal_option_size = 31;
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struct cmucal_option cmucal_option_list[] = {
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CLK_OPTION(CTRL_OPTION_CMU_ALIVE, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_AUD, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_BUSC, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CHUB, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CHUBVTS, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CMGP, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TOP, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CORE, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL0_GLB, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CSIS, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DPU, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DSU, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_GNSS, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_HSI, HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_ISP, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_M2M, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MCSC, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MFC, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MODEM, MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPU0, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_NPUS, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERI, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_S2D, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TAA, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TNR, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_USB, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VTS, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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};
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