1429 lines
58 KiB
C
Executable file
1429 lines
58 KiB
C
Executable file
#ifndef __CMUCAL_NODE_H__
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#define __CMUCAL_NODE_H__
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#include "../../cmucal.h"
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enum clk_id {
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OSCCLK_RCO_ALIVE = FIXED_RATE_TYPE,
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CLK_RCO_ALIVE,
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CLK_RCO_I3C_PMIC,
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RTCCLK_ALIVE,
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OSCCLK_ALIVE,
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OSCCLK_AUD,
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IOCLK_AUDIOCDCLK0,
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IOCLK_AUDIOCDCLK1,
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IOCLK_AUDIOCDCLK2,
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IOCLK_AUDIOCDCLK3,
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IOCLK_AUDIOCDCLK4,
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TICK_USB,
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IOCLK_AUDIOCDCLK5,
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IOCLK_AUDIOCDCLK6,
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CLKIO_AUD_DSIF,
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OSCCLK_BUSC,
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OSCCLK_RCO_CHUB,
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RTCCLK_CHUB,
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OSCCLK_RCO_CHUBVTS,
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OSCCLK_RCO_CMGP,
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OSCCLK_CMU,
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OSCCLK_CORE,
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OSCCLK_CPUCL0,
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OSCCLK_CPUCL1,
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OSCCLK_CSIS,
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OSCCLK_DPU,
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OSCCLK_DSU,
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OSCCLK_G3D,
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OSCCLK_HSI,
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OSCCLK_ISP,
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OSCCLK_M2M,
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OSCCLK_MCSC,
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OSCCLK_MFC,
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OSCCLK_MIF,
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PCMC_CLK,
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OSCCLK_NPU0,
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OSCCLK_NPUS,
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OSCCLK_PERI,
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OSCCLK_S2D,
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I_SCLK_S2D,
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OSCCLK_TAA,
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OSCCLK_TNR,
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OSCCLK_USB,
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OSCCLK_RCO_VTS,
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RCO_400,
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end_of_fixed_rate,
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num_of_fixed_rate = (end_of_fixed_rate - FIXED_RATE_TYPE) & MASK_OF_ID,
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CLKCMU_OTP = FIXED_FACTOR_TYPE,
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DIV_CLK_MIF_BUSD,
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CLK_MIF_BUSD_S2D,
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PLL_SHARED0_D1,
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PLL_SHARED1_D1,
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PLL_SHARED2_D1,
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PLL_SHARED0_D2,
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PLL_SHARED1_D2,
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PLL_SHARED2_D2,
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PLL_SHARED0_D3,
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PLL_SHARED1_D3,
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PLL_SHARED2_D3,
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PLL_SHARED0_D4,
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PLL_SHARED1_D4,
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PLL_SHARED2_D4,
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PLL_AUD_D1,
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PLL_AUD_D2,
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PLL_AUD_D3,
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PLL_AUD_D4,
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PLL_MMC_D2,
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end_of_fixed_factor,
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num_of_fixed_factor = (end_of_fixed_factor - FIXED_FACTOR_TYPE) & MASK_OF_ID,
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PLL_AUD = PLL_TYPE,
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PLL_SHARED1,
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PLL_SHARED0,
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PLL_G3D,
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PLL_MMC,
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PLL_SHARED2,
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PLL_CPUCL0,
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PLL_CPUCL1,
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PLL_DSU,
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PLL_MIF,
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PLL_MIF_S2D,
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end_of_pll,
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num_of_pll = (end_of_pll - PLL_TYPE) & MASK_OF_ID,
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MUX_CLKCMU_CMGP_BUS = MUX_TYPE,
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MUX_CLK_ALIVE_BUS,
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MUX_CLKCMU_CMGP_PERI,
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MUX_CLK_ALIVE_I3C_PMIC,
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MUX_CLKCMU_CHUBVTS_BUS,
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MUX_CLK_ALIVE_DBGCORE_UART,
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MUX_CLKCMU_AP2GNSS,
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MUX_CLKCMU_CHUB_PERI,
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MUX_CLK_ALIVE_USI0,
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MUX_CLK_ALIVE_I2C,
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MUX_CLK_AUD_UAIF3,
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MUX_CLK_AUD_UAIF2,
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MUX_CLK_AUD_UAIF1,
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MUX_CLK_AUD_UAIF0,
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MUX_CLK_AUD_CPU,
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MUX_CLK_AUD_FM,
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MUX_CLK_AUD_UAIF4,
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MUX_CLK_AUD_UAIF5,
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MUX_CLK_AUD_UAIF6,
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MUX_CLK_AUD_DSIF,
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MUX_CLK_AUD_CPU_PLL,
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MUX_CLK_AUD_BUS,
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MUX_CLK_AUD_PCMC,
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MUX_BUSC_CMUREF,
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MUX_CLK_CHUB_TIMER,
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MUX_CLK_CHUB_USI0,
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MUX_CLK_CHUB_USI1,
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MUX_CLK_CHUB_USI2,
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MUX_CLK_CHUB_I2C,
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MUX_CLK_CHUB_USI3,
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MUX_CLK_CHUB_BUS,
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MUX_CLK_CHUBVTS_BUS,
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MUX_CLK_CMGP_I2C,
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MUX_CLK_CMGP_USI0,
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MUX_CLK_CMGP_USI4,
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MUX_CLK_CMGP_I3C,
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MUX_CLK_CMGP_BUS,
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MUX_CLK_CMGP_USI1,
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MUX_CLK_CMGP_USI2,
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MUX_CLK_CMGP_USI3,
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MUX_CLKCMU_MFC_MFC,
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MUX_CLKCMU_CORE_BUS,
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MUX_CLKCMU_CPUCL0_SWITCH,
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MUX_CLKCMU_MIF_SWITCH,
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MUX_CLKCMU_TAA_BUS,
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MUX_CLKCMU_ISP_BUS,
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MUX_CLKCMU_AUD_CPU,
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MUX_CLKCMU_M2M_MSCL,
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MUX_CLKCMU_CPUCL0_DBG_BUS,
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MUX_CLKCMU_CIS_CLK0,
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MUX_CLKCMU_CIS_CLK1,
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MUX_CLKCMU_CIS_CLK2,
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MUX_CLKCMU_HSI_UFS_EMBD,
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MUX_CMU_CMUREF,
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MUX_CLKCMU_PERI_BUS,
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MUX_CLKCMU_NPU0_BUS,
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MUX_CLKCMU_ALIVE_BUS,
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MUX_CLKCMU_HSI_BUS,
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MUX_CLKCMU_MIF_BUSP,
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MUX_CLKCMU_PERI_IP,
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MUX_CLKCMU_DPU_BUS,
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MUX_CLKCMU_CPUCL1_SWITCH,
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MUX_CLKCMU_USB_BUS,
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MUX_CLKCMU_TNR_BUS,
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MUX_CLKCMU_PERI_MMC_CARD,
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MUX_CLKCMU_CMU_BOOST,
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MUX_CLKCMU_CORE_G3D,
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MUX_CLKCMU_CSIS_BUS,
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MUX_CLKCMU_MCSC_BUS,
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MUX_CLKCMU_MCSC_GDC,
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MUX_CLKCMU_USB_USB20DRD,
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MUX_CLKCMU_NPUS_BUS,
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MUX_CLKCMU_G3D_SWITCH,
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MUX_CLKCMU_CORE_SSS,
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MUX_CLKCMU_BUSC_BUS,
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MUX_CLKCMU_CIS_CLK3,
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MUX_CLKCMU_CIS_CLK4,
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CLKCMU_G3D_BUS,
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MUX_CLKCMU_CIS_CLK5,
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MUX_CLKCMU_DSU_SWITCH,
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MUX_CLKCMU_CPUCL0_BUSP,
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MUX_CLKCMU_DPU_DSIM,
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MUX_CLKCMU_MCSC_MCSC,
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MUX_CLKCMU_AUD_BUS,
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MUX_CORE_CMUREF,
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MUX_CLK_CORE_GIC,
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MUX_CLK_CPUCL0_PLL,
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MUX_CPUCL0_CMUREF,
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MUX_CLK_CPUCL1_PLL,
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MUX_CPUCL1_CMUREF,
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MUX_DSU_CMUREF,
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MUX_CLK_DSU_PLL,
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MUX_MIF_CMUREF,
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MUX_CLK_S2D_CORE,
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MUX_CLK_USB_BUS,
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MUX_CLK_USB_USB20DRD,
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MUX_CLK_VTS_BUS,
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MUX_VTS_DMIC_AUD,
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MUX_VTS_SERIAL_LIF,
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MUX_CLK_VTS_DMIC_IF,
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ALIVE_CMU_ALIVE_CLKOUT0,
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AUD_CMU_AUD_CLKOUT0,
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BUSC_CMU_BUSC_CLKOUT0,
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CHUB_CMU_CHUB_CLKOUT0,
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CHUBVTS_CMU_CHUBVTS_CLKOUT0,
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CMGP_CMU_CMGP_CLKOUT0,
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CMU_CMU_TOP_CLKOUT0,
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CORE_CMU_CORE_CLKOUT0,
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CPUCL0_CMU_CPUCL0_CLKOUT0,
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CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT0,
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CPUCL1_CMU_CPUCL1_CLKOUT0,
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CSIS_CMU_CSIS_CLKOUT0,
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DPU_CMU_DPU_CLKOUT0,
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DSU_CMU_DSU_CLKOUT0,
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G3D_CMU_G3D_CLKOUT0,
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HSI_CMU_HSI_CLKOUT0,
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ISP_CMU_ISP_CLKOUT0,
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M2M_CMU_M2M_CLKOUT0,
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MCSC_CMU_MCSC_CLKOUT0,
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MFC_CMU_MFC_CLKOUT0,
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MIF_CMU_MIF_CLKOUT0,
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NPU0_CMU_NPU0_CLKOUT0,
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NPUS_CMU_NPUS_CLKOUT0,
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PERI_CMU_PERI_CLKOUT0,
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TAA_CMU_TAA_CLKOUT0,
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TNR_CMU_TNR_CLKOUT0,
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USB_CMU_USB_CLKOUT0,
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VTS_CMU_VTS_CLKOUT0,
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MUX_CLKCMU_ALIVE_BUS_USER = ((MASK_OF_ID & VTS_CMU_VTS_CLKOUT0) | USER_MUX_TYPE) + 1,
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MUX_CLK_RCO_ALIVE_USER,
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MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
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MUX_CLK_ALIVE_TIMER,
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MUX_CLKCMU_AUD_CPU_USER,
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MUX_CLKCMU_AUD_BUS_USER,
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MUX_CP_PCMC_CLK_USER,
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MUX_CLKCMU_BUSC_BUS_USER,
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MUX_CLK_CHUB_BUS_USER,
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MUX_CLKCMU_CHUB_PERI_USER,
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MUX_CLKCMU_CHUB_RCO_USER,
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MUX_CLKCMU_CHUBVTS_BUS_USER,
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MUX_CLKCMU_CHUBVTS_RCO_USER,
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MUX_CLKCMU_CMGP_BUS_USER,
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MUX_CLKCMU_CMGP_PERI_USER,
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MUX_CLKCMU_CMGP_RCO_USER,
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MUX_CLKCMU_CORE_BUS_USER,
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MUX_CLKCMU_CORE_G3D_USER,
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MUX_CLKCMU_CORE_SSS_USER,
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MUX_CLKCMU_CPUCL0_SWITCH_USER,
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MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
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MUX_CLKCMU_CPUCL0_BUSP_USER,
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MUX_CLKCMU_CPUCL1_SWITCH_USER,
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MUX_CLKCMU_CSIS_BUS_USER,
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MUX_CLKCMU_DPU_BUS_USER,
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MUX_CLKCMU_DPU_DSIM_USER,
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MUX_CLKCMU_DSU_SWITCH_USER,
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MUX_CLKCMU_G3D_BUS_USER,
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MUX_CLKCMU_HSI_BUS_USER,
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MUX_CLKCMU_HSI_UFS_EMBD_USER,
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MUX_CLKCMU_ISP_BUS_USER,
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MUX_CLKCMU_M2M_MSCL_USER,
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MUX_CLKCMU_MCSC_BUS_USER,
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MUX_CLKCMU_MCSC_GDC_USER,
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MUX_CLKCMU_MCSC_MCSC_USER,
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MUX_CLKCMU_MFC_MFC_USER,
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MUX_CLKCMU_MIF_BUSP_USER,
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CLKMUX_MIF_DDRPHY2X,
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MUX_CLKCMU_NPU0_BUS_USER,
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MUX_CLKCMU_NPUS_BUS_USER,
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MUX_CLKCMU_PERI_BUS_USER,
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MUX_CLKCMU_PERI_USI00_USI_USER,
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MUX_CLKCMU_PERI_USI01_USI_USER,
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MUX_CLKCMU_PERI_USI02_USI_USER,
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MUX_CLKCMU_PERI_USI03_USI_USER,
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MUX_CLKCMU_PERI_USI04_USI_USER,
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MUX_CLKCMU_PERI_USI05_USI_USER,
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MUX_CLKCMU_PERI_USI_I2C_USER,
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MUX_CLKCMU_PERI_UART_DBG,
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MUX_CLKCMU_PERI_MMC_CARD_USER,
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MUX_CLKCMU_PERI_USI06_USI_USER,
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CLKCMU_MIF_DDRPHY2X_S2D,
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MUX_CLKCMU_TAA_BUS_USER,
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MUX_CLKCMU_TNR_BUS_USER,
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MUX_CLKCMU_USB_BUS_USER,
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MUX_CLKCMU_USB_USB20DRD_USER,
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MUX_CLKAUD_USB_BUS_USER,
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MUX_CLKAUD_USB_USB20DRD_USER,
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MUX_CLKCMU_VTS_BUS_USER,
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MUX_CLKCMU_VTS_RCO_USER,
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MUX_CLK_AUD_DMIC_BUS_USER,
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MUX_HCHGEN_CLK_AUD_CPU,
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end_of_mux,
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num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,
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CLKCMU_CMGP_PERI = DIV_TYPE,
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DIV_CLK_ALIVE_BUS,
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CLKCMU_CMGP_BUS,
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DIV_CLK_ALIVE_I3C_PMIC,
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DIV_CLK_ALIVE_DBGCORE_UART,
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CLKCMU_CHUBVTS_BUS,
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CLKCMU_CHUB_PERI,
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DIV_CLK_ALIVE_USI0,
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DIV_CLK_ALIVE_I2C,
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DIV_CLK_AUD_CPU_PCLKDBG,
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DIV_CLK_AUD_FM_SPDY,
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DIV_CLK_AUD_UAIF0,
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DIV_CLK_AUD_UAIF1,
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DIV_CLK_AUD_UAIF2,
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DIV_CLK_AUD_UAIF3,
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DIV_CLK_AUD_CPU_ACLK,
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DIV_CLK_AUD_BUSP,
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DIV_CLK_AUD_CNT,
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DIV_CLK_AUD_UAIF4,
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DIV_CLK_AUD_DSIF,
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DIV_CLK_AUD_FM,
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DIV_CLK_AUD_UAIF5,
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DIV_CLK_AUD_UAIF6,
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DIV_CLK_AUD_MCLK,
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DIV_CLK_AUD_AUDIF,
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DIV_CLK_AUD_BUSD,
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DIV_CLK_AUD_PCMC,
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CLKAUD_USB_BUS,
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CLKAUD_USB_USB20DRD,
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DIV_CLK_AUD_CPU,
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DIV_CLK_AUD_CPU_ACP,
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CLK_AUD_DMIC,
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DIV_CLK_BUSC_BUSP,
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DIV_CLK_CHUB_USI0,
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DIV_CLK_CHUB_USI1,
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DIV_CLK_CHUB_USI2,
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DIV_CLK_CHUB_I2C,
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DIV_CLK_CHUB_USI3,
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DIV_CLK_CHUB_BUS,
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DIV_CLK_CHUBVTS_BUS,
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DIV_CLK_CMGP_I2C,
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DIV_CLK_CMGP_USI0,
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DIV_CLK_CMGP_USI4,
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DIV_CLK_CMGP_I3C,
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DIV_CLK_CMGP_USI1,
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DIV_CLK_CMGP_USI2,
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DIV_CLK_CMGP_USI3,
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CLKCMU_ALIVE_BUS,
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CLKCMU_G3D_SWITCH,
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CLKCMU_PERI_BUS,
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CLKCMU_DPU_BUS,
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CLKCMU_MFC_MFC,
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CLKCMU_CORE_BUS,
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CLKCMU_CPUCL0_SWITCH,
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CLKCMU_TAA_BUS,
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CLKCMU_ISP_BUS,
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CLKCMU_AUD_CPU,
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CLKCMU_M2M_MSCL,
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CLKCMU_CPUCL0_DBG_BUS,
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CLKCMU_CIS_CLK0,
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CLKCMU_CIS_CLK1,
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CLKCMU_CIS_CLK2,
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CLKCMU_HSI_UFS_EMBD,
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CLKCMU_NPU0_BUS,
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CLKCMU_MIF_BUSP,
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CLKCMU_PERI_IP,
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CLKCMU_CPUCL1_SWITCH,
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CLKCMU_USB_BUS,
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CLKCMU_TNR_BUS,
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CLKCMU_CMU_BOOST,
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CLKCMU_CORE_G3D,
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CLKCMU_CSIS_BUS,
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CLKCMU_MCSC_BUS,
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CLKCMU_HSI_BUS,
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CLKCMU_PERI_MMC_CARD,
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CLKCMU_MCSC_GDC,
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CLKCMU_USB_USB20DRD,
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CLKCMU_NPUS_BUS,
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CLKCMU_CORE_SSS,
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CLKCMU_BUSC_BUS,
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CLKCMU_CIS_CLK3,
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CLKCMU_CIS_CLK4,
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CLKCMU_CIS_CLK5,
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CLKCMU_DSU_SWITCH,
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CLKCMU_CPUCL0_BUSP,
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CLKCMU_DPU_DSIM,
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CLKCMU_MCSC_MCSC,
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CLKCMU_AUD_BUS,
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DIV_CLK_CORE_BUSP,
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DIV_CLK_CPUCL0_SHORTSTOP,
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DIV_CLK_CPUCL0_DBG_PCLKDBG,
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DIV_CLK_CPUCL1_SHORTSTOP,
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DIV_CLK_CPUCL1_HTU,
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DIV_CLK_CSIS_BUSP,
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DIV_CLK_DPU_BUSP,
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DIV_CLK_DSU_SHORTSTOP,
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DIV_CLK_CLUSTER0_ACLK,
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DIV_CLK_CLUSTER0_ATCLK,
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DIV_CLK_CLUSTER0_PCLK,
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DIV_CLK_CLUSTER0_PERIPHCLK,
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DIV_CLK_G3D_BUSP,
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DIV_CLK_ISP_BUSP,
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DIV_CLK_M2M_BUSP,
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DIV_CLK_MCSC_BUSP,
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DIV_CLK_MFC_BUSP,
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DIV_CLK_NPU0_BUSP,
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DIV_CLK_NPUS_BUSP,
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DIV_CLK_PERI_USI00_USI,
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DIV_CLK_PERI_USI01_USI,
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DIV_CLK_PERI_USI02_USI,
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DIV_CLK_PERI_USI03_USI,
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DIV_CLK_PERI_USI04_USI,
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DIV_CLK_PERI_USI05_USI,
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DIV_CLK_PERI_USI_I2C,
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DIV_CLK_PERI_UART_DBG,
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DIV_CLK_PERI_USI06_USI,
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DIV_CLK_TAA_BUSP,
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DIV_CLK_TNR_BUSP,
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DIV_CLK_VTS_DMIC_IF,
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DIV_CLK_VTS_DMIC_IF_DIV2,
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DIV_CLK_VTS_BUS,
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DIV_VTS_DMIC_AUD,
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DIV_VTS_DMIC_AUD_DIV2,
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DIV_VTS_SERIAL_LIF_CORE,
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DIV_VTS_SERIAL_LIF,
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DIV_CLK_CPUCL0_CPU = ((MASK_OF_ID & DIV_VTS_SERIAL_LIF) | CONST_DIV_TYPE) + 1,
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DIV_CLK_CPUCL1_CPU,
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DIV_CLK_DSU_CLUSTER,
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DIV_CLK_G3D_BUSD,
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DIV_CLK_NPU0_BUS,
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DIV_CLK_NPUS_BUS,
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end_of_div,
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num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,
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GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK = GATE_TYPE,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
|
|
GATE_CLKCMU_CMGP_PERI,
|
|
GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
|
|
GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK,
|
|
GATE_CLKCMU_CMGP_BUS,
|
|
GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK,
|
|
CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK,
|
|
CLKCMU_VTS_RCO,
|
|
GATE_CLKCMU_CHUB_BUS,
|
|
AP2GNSS_CLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK,
|
|
GATE_CLKCMU_CHUB_PERI,
|
|
GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK,
|
|
GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK,
|
|
CLKCMU_CHUB_RCO,
|
|
CLKCMU_CMGP_RCO,
|
|
GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK,
|
|
CLKCMU_CHUBVTS_RCO,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
|
GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
|
|
GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4,
|
|
GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
|
|
GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK,
|
|
GATE_CLKAUD_USB_BUS,
|
|
GATE_CLKAUD_USB_USB20DRD,
|
|
GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2,
|
|
GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY,
|
|
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY,
|
|
GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS,
|
|
GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0,
|
|
GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1,
|
|
GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK,
|
|
GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK,
|
|
GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0,
|
|
GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK,
|
|
GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK,
|
|
CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK,
|
|
CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK,
|
|
GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK,
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK,
|
|
GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK,
|
|
GATE_CLKCMU_ALIVE_BUS,
|
|
CLKCMU_MIF_SWITCH,
|
|
GATE_CLKCMU_MFC_MFC,
|
|
GATE_CLKCMU_HSI_BUS,
|
|
GATE_CLKCMU_PERI_MMC_CARD,
|
|
GATE_CLKCMU_DPU_BUS,
|
|
GATE_CLKCMU_G3D_SWITCH,
|
|
GATE_CLKCMU_PERI_BUS,
|
|
GATE_CLKCMU_CORE_BUS,
|
|
GATE_CLKCMU_CPUCL0_SWITCH,
|
|
GATE_CLKCMU_TAA_BUS,
|
|
GATE_CLKCMU_ISP_BUS,
|
|
GATE_CLKCMU_AUD_CPU,
|
|
GATE_CLKCMU_M2M_MSCL,
|
|
GATE_CLKCMU_CPUCL0_DBG_BUS,
|
|
GATE_CLKCMU_CIS_CLK0,
|
|
GATE_CLKCMU_CIS_CLK1,
|
|
GATE_CLKCMU_CIS_CLK2,
|
|
GATE_CLKCMU_HSI_UFS_EMBD,
|
|
GATE_CLKCMU_NPU0_BUS,
|
|
GATE_CLKCMU_MIF_BUSP,
|
|
GATE_CLKCMU_PERI_IP,
|
|
GATE_CLKCMU_CPUCL1_SWITCH,
|
|
GATE_CLKCMU_USB_BUS,
|
|
GATE_CLKCMU_TNR_BUS,
|
|
GATE_CLKCMU_CORE_G3D,
|
|
GATE_CLKCMU_CSIS_BUS,
|
|
GATE_CLKCMU_MCSC_BUS,
|
|
GATE_CLKCMU_MCSC_GDC,
|
|
GATE_CLKCMU_G3D_BUS,
|
|
GATE_CLKCMU_USB_USB20DRD,
|
|
AP2CP_SHARED0_CLK,
|
|
AP2CP_SHARED1_CLK,
|
|
GATE_CLKCMU_NPUS_BUS,
|
|
GATE_CLKCMU_CORE_SSS,
|
|
AP2CP_SHARED2_CLK,
|
|
AP2CP_HISPEEDY_CLK,
|
|
GATE_CLKCMU_BUSC_BUS,
|
|
GATE_CLKCMU_CIS_CLK3,
|
|
GATE_CLKCMU_CIS_CLK4,
|
|
GATE_CLKCMU_CIS_CLK5,
|
|
GATE_CLKCMU_DSU_SWITCH,
|
|
GATE_CLKCMU_CPUCL0_BUSP,
|
|
GATE_CLKCMU_DPU_DSIM,
|
|
GATE_CLKCMU_MCSC_MCSC,
|
|
GATE_CLKCMU_AUD_BUS,
|
|
CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE,
|
|
GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A,
|
|
GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS,
|
|
GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS,
|
|
GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK,
|
|
GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS,
|
|
GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN,
|
|
GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK,
|
|
CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
|
GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC,
|
|
GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK,
|
|
GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4,
|
|
GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5,
|
|
GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1,
|
|
GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK,
|
|
GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK,
|
|
GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON,
|
|
GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA,
|
|
GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP,
|
|
GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV,
|
|
GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2,
|
|
CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK,
|
|
GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK,
|
|
CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK,
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK,
|
|
CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK,
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
|
CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK,
|
|
GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK,
|
|
GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP,
|
|
GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS,
|
|
GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK,
|
|
GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK,
|
|
GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
|
GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
|
GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK,
|
|
CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK,
|
|
CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK,
|
|
CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK,
|
|
CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK,
|
|
CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK,
|
|
GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK,
|
|
GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK,
|
|
GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM,
|
|
CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK,
|
|
GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF,
|
|
CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK,
|
|
GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK,
|
|
GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK,
|
|
GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1,
|
|
GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK,
|
|
GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK,
|
|
CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM,
|
|
GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK,
|
|
GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK,
|
|
GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS,
|
|
GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK,
|
|
CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK,
|
|
CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK,
|
|
GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK,
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE,
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU,
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF,
|
|
GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK,
|
|
CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK,
|
|
CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK,
|
|
CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK,
|
|
GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK,
|
|
GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK,
|
|
CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS,
|
|
GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM,
|
|
CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM,
|
|
GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK,
|
|
CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK,
|
|
GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK,
|
|
CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
|
GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0,
|
|
GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
|
GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
|
GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK,
|
|
GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK,
|
|
GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK,
|
|
GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK,
|
|
GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
|
GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK,
|
|
CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK,
|
|
GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK,
|
|
CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT,
|
|
GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS,
|
|
GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK,
|
|
GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK,
|
|
CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM,
|
|
GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK,
|
|
GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1,
|
|
GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0,
|
|
GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK,
|
|
GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK,
|
|
GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1,
|
|
GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK,
|
|
GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK,
|
|
GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26,
|
|
GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK,
|
|
GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK,
|
|
GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2,
|
|
GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL,
|
|
GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY,
|
|
CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK,
|
|
GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK,
|
|
GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK,
|
|
GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK,
|
|
CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
|
|
GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
|
CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
|
|
GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS,
|
|
CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0,
|
|
GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS,
|
|
GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK,
|
|
GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
|
|
GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
|
|
end_of_gate,
|
|
num_of_gate = (end_of_gate - GATE_TYPE) & MASK_OF_ID,
|
|
|
|
};
|
|
#endif
|