1210 lines
29 KiB
C
Executable file
1210 lines
29 KiB
C
Executable file
#ifndef __CMUCAL_VCLK_H__
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#define __CMUCAL_VCLK_H__
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#include "../cmucal.h"
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enum vclk_id {
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/* DVFS VCLK*/
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VCLK_VDD_MIF = DFS_VCLK_TYPE,
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VCLK_VDD_CAM,
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VCLK_VDD_CPUCL2,
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VCLK_VDD_CPUCL0,
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VCLK_VDD_CPUCL1,
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VCLK_VDD_INT_CMU,
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end_of_dfs_vclk,
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num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE,
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/* SPECIAL VCLK*/
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VCLK_MUX_CLK_ALIVE_I3C_PMIC = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE,
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VCLK_CLKCMU_ALIVE_BUS,
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VCLK_MUX_CLK_AUD_DSIF,
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VCLK_MUX_BUS0_CMUREF,
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VCLK_MUX_CLKCMU_CMU_BOOST,
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VCLK_MUX_BUS1_CMUREF,
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VCLK_MUX_BUS2_CMUREF,
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VCLK_CLK_CMGP_ADC,
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VCLK_CLKCMU_CMGP_ADC,
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VCLK_MUX_CORE_CMUREF,
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VCLK_MUX_CPUCL0_CMUREF,
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VCLK_MUX_CLKCMU_CMU_BOOST_CPU,
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VCLK_MUX_CPUCL1_CMUREF,
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VCLK_MUX_CPUCL2_CMUREF,
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VCLK_MUX_DSU_CMUREF,
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VCLK_MUX_CLK_HSI0_USB31DRD,
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VCLK_MUX_MIF_CMUREF,
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VCLK_MUX_CLKCMU_CMU_BOOST_MIF,
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VCLK_CLKCMU_G3D_SHADER,
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VCLK_DIV_CLK_ALIVE_DBGCORE_UART,
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VCLK_DIV_CLK_CMGP_I2C0,
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VCLK_CLKCMU_CMGP_PERI,
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VCLK_DIV_CLK_CMGP_USI1,
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VCLK_DIV_CLK_CMGP_USI0,
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VCLK_DIV_CLK_CMGP_USI2,
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VCLK_DIV_CLK_CMGP_USI3,
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VCLK_DIV_CLK_CMGP_I2C1,
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VCLK_DIV_CLK_CMGP_I2C2,
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VCLK_DIV_CLK_CMGP_I2C3,
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VCLK_DIV_CLK_CMGP_I3C,
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VCLK_MUX_CLKCMU_HPM,
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VCLK_CLKCMU_CIS_CLK0,
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VCLK_CLKCMU_CIS_CLK1,
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VCLK_CLKCMU_CIS_CLK2,
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VCLK_CLKCMU_CIS_CLK3,
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VCLK_CLKCMU_CIS_CLK4,
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VCLK_CLKCMU_CIS_CLK5,
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VCLK_DIV_CLK_CPUCL0_SHORTSTOP_CORE,
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VCLK_DIV_CLK_CPUCL1_SHORTSTOP_CORE,
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VCLK_DIV_CLK_CPUCL1_HTU,
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VCLK_DIV_CLK_CPUCL2_SHORTSTOP_CORE,
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VCLK_DIV_CLK_CPUCL2_HTU,
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VCLK_DIV_CLK_DSU_SHORTSTOP_CLUSTER,
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VCLK_DIV_CLK_PERIC0_USI00_USI,
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VCLK_DIV_CLK_PERIC0_USI01_USI,
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VCLK_DIV_CLK_PERIC0_USI02_USI,
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VCLK_DIV_CLK_PERIC0_USI03_USI,
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VCLK_DIV_CLK_PERIC0_USI04_USI,
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VCLK_DIV_CLK_PERIC0_USI05_USI,
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VCLK_DIV_CLK_PERIC0_UART_DBG,
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VCLK_DIV_CLK_PERIC0_USI13_USI,
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VCLK_DIV_CLK_PERIC0_USI14_USI,
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VCLK_DIV_CLK_PERIC0_USI15_USI,
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VCLK_DIV_CLK_PERIC1_UART_BT,
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VCLK_DIV_CLK_PERIC1_USI11_USI,
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VCLK_DIV_CLK_PERIC1_USI12_USI,
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VCLK_DIV_CLK_PERIC1_USI16_USI,
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VCLK_DIV_CLK_PERIC1_USI17_USI,
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VCLK_DIV_CLK_PERIC1_USI18_USI,
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VCLK_DIV_CLK_PERIC2_USI06_USI,
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VCLK_DIV_CLK_PERIC2_USI07_USI,
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VCLK_DIV_CLK_PERIC2_USI08_USI,
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VCLK_DIV_CLK_PERIC2_USI09_USI,
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VCLK_DIV_CLK_PERIC2_USI10_USI,
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VCLK_DIV_CLK_TOP_HSI0_BUS,
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end_of_vclk,
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num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE),
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/* COMMON VCLK*/
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VCLK_BLK_AUD = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE,
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VCLK_BLK_CMU,
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VCLK_BLK_S2D,
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VCLK_BLK_ALIVE,
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VCLK_BLK_CPUCL0,
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VCLK_BLK_CPUCL1,
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VCLK_BLK_CPUCL2,
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VCLK_BLK_DSU,
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VCLK_BLK_G3D,
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VCLK_BLK_HSI0,
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VCLK_BLK_PERIC0,
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VCLK_BLK_PERIC1,
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VCLK_BLK_PERIC2,
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VCLK_BLK_VTS,
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VCLK_BLK_BUS0,
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VCLK_BLK_BUS1,
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VCLK_BLK_BUS2,
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VCLK_BLK_CORE,
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VCLK_BLK_CPUCL0_GLB,
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VCLK_BLK_CSIS,
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VCLK_BLK_DNS,
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VCLK_BLK_DPUB,
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VCLK_BLK_DPUF0,
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VCLK_BLK_DPUF1,
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VCLK_BLK_ITP,
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VCLK_BLK_LME,
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VCLK_BLK_M2M,
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VCLK_BLK_MCFP0,
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VCLK_BLK_MCFP1,
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VCLK_BLK_MCSC,
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VCLK_BLK_MFC0,
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VCLK_BLK_MFC1,
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VCLK_BLK_NPU,
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VCLK_BLK_NPU01,
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VCLK_BLK_NPU10,
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VCLK_BLK_NPUS,
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VCLK_BLK_PERIS,
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VCLK_BLK_SSP,
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VCLK_BLK_TAA,
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VCLK_BLK_VPC,
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VCLK_BLK_VPD,
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VCLK_BLK_YUVPP,
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end_of_common_vclk,
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num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE),
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/* GATE VCLK*/
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VCLK_IP_LHS_AXI_D_APM = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE,
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VCLK_IP_LHM_AXI_P_APM,
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VCLK_IP_WDT_ALIVE,
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VCLK_IP_SYSREG_ALIVE,
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VCLK_IP_MAILBOX_APM_AP,
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VCLK_IP_APBIF_PMU_ALIVE,
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VCLK_IP_INTMEM,
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VCLK_IP_LHS_AXI_G_SCAN2DRAM,
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VCLK_IP_PMU_INTR_GEN,
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VCLK_IP_PEM,
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VCLK_IP_XIU_DP_ALIVE,
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VCLK_IP_ALIVE_CMU_ALIVE,
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VCLK_IP_GREBEINTEGRATION,
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VCLK_IP_GPIO_ALIVE,
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VCLK_IP_APBIF_TOP_RTC,
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VCLK_IP_SS_DBGCORE,
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VCLK_IP_DTZPC_ALIVE,
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VCLK_IP_MAILBOX_AP_DBGCORE,
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VCLK_IP_LHS_AXI_LP_VTS,
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VCLK_IP_LHS_AXI_G_DBGCORE,
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VCLK_IP_APBIF_RTC,
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VCLK_IP_LHS_AXI_C_CMGP,
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VCLK_IP_VGEN_LITE_ALIVE,
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VCLK_IP_ROM_CRC32_HOST,
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VCLK_IP_I3C_PMIC,
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VCLK_IP_LHM_AXI_C_MODEM,
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VCLK_IP_MAILBOX_APM_CP,
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VCLK_IP_MAILBOX_AP_CP,
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VCLK_IP_MAILBOX_AP_CP_S,
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VCLK_IP_LHM_AXI_C_VTS,
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VCLK_IP_APBIF_SYSREG_VGPIO2AP,
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VCLK_IP_APBIF_SYSREG_VGPIO2APM,
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VCLK_IP_APBIF_SYSREG_VGPIO2PMU,
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VCLK_IP_SWEEPER_P_ALIVE,
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VCLK_IP_CLKMON,
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VCLK_IP_DBGCORE_UART,
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VCLK_IP_DOUBLE_IP_BATCHER,
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VCLK_IP_HW_SCANDUMP_CLKSTOP_CTRL,
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VCLK_IP_AUD_CMU_AUD,
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VCLK_IP_LHS_AXI_D_AUD,
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VCLK_IP_PPMU_AUD,
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VCLK_IP_SYSREG_AUD,
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VCLK_IP_ABOX,
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VCLK_IP_LHM_AXI_P_AUD,
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VCLK_IP_PERI_AXI_ASB,
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VCLK_IP_WDT_AUD,
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VCLK_IP_SMMU_AUD,
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VCLK_IP_AD_APB_SMMU_AUD,
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VCLK_IP_AD_APB_SMMU_AUD_S,
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VCLK_IP_VGEN_LITE_AUD,
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VCLK_IP_AD_APB_SMMU_AUD_NS1,
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VCLK_IP_MAILBOX_AUD0,
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VCLK_IP_MAILBOX_AUD1,
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VCLK_IP_D_TZPC_AUD,
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VCLK_IP_LHM_AXI_D_HSI0AUD,
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VCLK_IP_LHS_AXI_D_AUDHSI0,
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VCLK_IP_LHS_AXI_D_AUDVTS,
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VCLK_IP_AXI_US_32TO128,
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VCLK_IP_TREX_AUD,
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VCLK_IP_MAILBOX_AUD2,
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VCLK_IP_MAILBOX_AUD3,
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VCLK_IP_BAAW_D_AUDVTS,
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VCLK_IP_BUS0_CMU_BUS0,
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VCLK_IP_SYSREG_BUS0,
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VCLK_IP_TREX_D0_BUS0,
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VCLK_IP_LHS_AXI_P_MIF0,
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VCLK_IP_LHS_AXI_P_MIF1,
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VCLK_IP_LHS_AXI_P_MIF2,
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VCLK_IP_LHS_AXI_P_MIF3,
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VCLK_IP_LHS_AXI_P_NPU10,
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VCLK_IP_LHS_AXI_P_VPC,
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VCLK_IP_LHS_AXI_P_NPUS,
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VCLK_IP_LHS_AXI_P_NPU01,
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VCLK_IP_LHS_AXI_P_PERISGIC,
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VCLK_IP_LHS_AXI_P_NPU00,
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VCLK_IP_TREX_P_BUS0,
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VCLK_IP_TREX_D1_BUS0,
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VCLK_IP_LHM_ACEL_D1_VPC,
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VCLK_IP_LHM_ACEL_D2_VPC,
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VCLK_IP_LHM_AXI_D0_NPUS,
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VCLK_IP_D_TZPC_BUS0,
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VCLK_IP_LHS_DBG_G_BUS0,
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VCLK_IP_LHM_AXI_D2_NPUS,
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VCLK_IP_LHM_ACEL_D0_VPC,
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VCLK_IP_LHM_AXI_D1_NPUS,
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VCLK_IP_BUSIF_CMUTOPC,
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VCLK_IP_CACHEAID_BUS0,
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VCLK_IP_BAAW_P_VPC,
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VCLK_IP_LHS_AXI_P_PERIC0,
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VCLK_IP_LHS_AXI_P_PERIC2,
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VCLK_IP_ASYNCSFR_WR_SMC,
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VCLK_IP_BUS1_CMU_BUS1,
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VCLK_IP_AD_APB_DIT,
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VCLK_IP_D_TZPC_BUS1,
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VCLK_IP_DIT,
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VCLK_IP_LHS_AXI_P_DPUB,
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VCLK_IP_LHS_AXI_P_HSI0,
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VCLK_IP_LHS_AXI_P_VTS,
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VCLK_IP_LHS_DBG_G_BUS1,
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VCLK_IP_QE_PDMA,
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VCLK_IP_PDMA,
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VCLK_IP_QE_SPDMA,
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VCLK_IP_SPDMA,
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VCLK_IP_SYSREG_BUS1,
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VCLK_IP_TREX_D_BUS1,
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VCLK_IP_TREX_P_BUS1,
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VCLK_IP_TREX_RB_BUS1,
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VCLK_IP_XIU_D0_BUS1,
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VCLK_IP_LHM_AXI_D0_DPUF0,
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VCLK_IP_LHM_ACEL_D_HSI0,
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VCLK_IP_LHM_AXI_D1_DPUF0,
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VCLK_IP_LHM_AXI_D_APM,
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VCLK_IP_LHM_AXI_D_VTS,
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VCLK_IP_AD_APB_VGEN_PDMA,
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VCLK_IP_AD_APB_PDMA,
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VCLK_IP_AD_APB_SPDMA,
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VCLK_IP_AD_APB_SYSMMU_ACVPS,
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VCLK_IP_AD_APB_SYSMMU_DIT,
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VCLK_IP_AD_APB_SYSMMU_SBIC,
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VCLK_IP_VGEN_LITE_BUS1,
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VCLK_IP_BAAW_P_VTS,
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VCLK_IP_SYSMMU_S2_ACVPS,
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VCLK_IP_SYSMMU_S2_DIT,
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VCLK_IP_SYSMMU_S2_SBIC,
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VCLK_IP_LHS_AXI_P_DPUF0,
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VCLK_IP_VGEN_PDMA,
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VCLK_IP_LHM_AXI_D_SBIC,
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VCLK_IP_LHS_AXI_D_SBIC,
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VCLK_IP_AD_APB_SBIC,
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VCLK_IP_SBIC,
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VCLK_IP_LHM_AXI_D0_DPUF1,
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VCLK_IP_LHM_AXI_D1_DPUF1,
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VCLK_IP_LHS_AXI_P_DPUF1,
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VCLK_IP_BUS2_CMU_BUS2,
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VCLK_IP_LHS_AXI_P_ITP,
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VCLK_IP_LHM_AXI_D_LME,
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VCLK_IP_TREX_D_BUS2,
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VCLK_IP_LHM_AXI_D0_MCFP0,
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VCLK_IP_LHM_AXI_D_YUVPP,
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VCLK_IP_LHM_AXI_D0_DNS,
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VCLK_IP_LHS_AXI_P_MCFP0,
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VCLK_IP_LHS_AXI_P_MCSC,
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VCLK_IP_TREX_P_BUS2,
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VCLK_IP_LHM_AXI_D1_MCFP0,
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VCLK_IP_LHS_AXI_P_LME,
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VCLK_IP_LHM_AXI_D1_MCSC,
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VCLK_IP_LHS_DBG_G_BUS2,
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VCLK_IP_LHM_AXI_D_TAA,
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VCLK_IP_D_TZPC_BUS2,
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VCLK_IP_SYSREG_BUS2,
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VCLK_IP_LHS_AXI_P_CSIS,
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VCLK_IP_LHM_AXI_D1_CSIS,
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VCLK_IP_LHS_AXI_P_HSI1,
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VCLK_IP_LHM_ACEL_D0_MCSC,
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VCLK_IP_LHS_AXI_P_TAA,
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VCLK_IP_LHM_ACEL_D_HSI1,
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VCLK_IP_LHM_AXI_D0_CSIS,
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VCLK_IP_LHS_AXI_P_YUVPP,
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VCLK_IP_LHM_AXI_D2_CSIS,
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VCLK_IP_LHM_AXI_D_MCFP1,
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VCLK_IP_LHM_AXI_D1_DNS,
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VCLK_IP_LHM_AXI_D2_MCSC,
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VCLK_IP_LHM_AXI_D0_MFC0,
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VCLK_IP_LHM_AXI_D0_MFC1,
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VCLK_IP_LHM_AXI_D1_MFC0,
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VCLK_IP_LHM_AXI_D1_MFC1,
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VCLK_IP_LHM_AXI_D2_MCFP0,
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VCLK_IP_LHM_AXI_D3_CSIS,
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VCLK_IP_LHM_AXI_D3_MCFP0,
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VCLK_IP_LHS_AXI_P_M2M,
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VCLK_IP_LHS_AXI_P_MFC0,
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VCLK_IP_LHS_AXI_P_MFC1,
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VCLK_IP_LHS_AXI_P_SSP,
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VCLK_IP_LHM_ACEL_D_SSP,
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VCLK_IP_LHM_ACEL_D_M2M,
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VCLK_IP_LHS_AXI_P_PERIC1,
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VCLK_IP_CMGP_CMU_CMGP,
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VCLK_IP_ADC_CMGP,
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VCLK_IP_GPIO_CMGP,
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VCLK_IP_I2C_CMGP0,
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VCLK_IP_I2C_CMGP1,
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VCLK_IP_I2C_CMGP2,
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VCLK_IP_I2C_CMGP3,
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VCLK_IP_SYSREG_CMGP,
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VCLK_IP_USI_CMGP0,
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VCLK_IP_USI_CMGP1,
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VCLK_IP_USI_CMGP2,
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VCLK_IP_USI_CMGP3,
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VCLK_IP_SYSREG_CMGP2PMU_AP,
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VCLK_IP_D_TZPC_CMGP,
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VCLK_IP_LHM_AXI_C_CMGP,
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VCLK_IP_SYSREG_CMGP2APM,
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VCLK_IP_I3C_CMGP,
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VCLK_IP_SYSREG_CMGP2CP,
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VCLK_IP_APBIF_GPIO_CMGP,
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VCLK_IP_CORE_CMU_CORE,
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VCLK_IP_SYSREG_CORE,
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VCLK_IP_MPACE2AXI_0,
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VCLK_IP_MPACE2AXI_1,
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VCLK_IP_PPC_DEBUG_CCI,
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VCLK_IP_TREX_P0_CORE,
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VCLK_IP_LHS_ATB_T_BDU,
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VCLK_IP_BDU,
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VCLK_IP_TREX_P1_CORE,
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VCLK_IP_LHS_AXI_P_G3D,
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VCLK_IP_LHS_AXI_P_CPUCL0,
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VCLK_IP_LHM_ACE_D0_G3D,
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VCLK_IP_LHM_ACE_D1_G3D,
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VCLK_IP_LHM_ACE_D2_G3D,
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VCLK_IP_LHM_ACE_D3_G3D,
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VCLK_IP_TREX_D_CORE,
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VCLK_IP_PPCFW_G3D,
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VCLK_IP_LHS_AXI_P_APM,
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VCLK_IP_D_TZPC_CORE,
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VCLK_IP_PPC_G3D0,
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VCLK_IP_PPC_G3D1,
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VCLK_IP_PPC_G3D2,
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VCLK_IP_PPC_G3D3,
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VCLK_IP_PPC_IRPS0,
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VCLK_IP_PPC_IRPS1,
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VCLK_IP_MPACE_ASB_D0_MIF,
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VCLK_IP_MPACE_ASB_D1_MIF,
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VCLK_IP_MPACE_ASB_D2_MIF,
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VCLK_IP_MPACE_ASB_D3_MIF,
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VCLK_IP_AXI_ASB_CSSYS,
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VCLK_IP_LHM_AXI_G_CSSYS,
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VCLK_IP_CCI,
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VCLK_IP_PPMU_G3D0,
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VCLK_IP_PPMU_G3D1,
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VCLK_IP_PPMU_G3D2,
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VCLK_IP_PPMU_G3D3,
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VCLK_IP_SYSMMU_G3D0,
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VCLK_IP_SYSMMU_G3D1,
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VCLK_IP_SYSMMU_G3D2,
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VCLK_IP_SYSMMU_G3D3,
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VCLK_IP_XIU_D_CORE,
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VCLK_IP_APB_ASYNC_SYSMMU_G3D0,
|
|
VCLK_IP_ACE_SLICE_G3D0,
|
|
VCLK_IP_ACE_SLICE_G3D1,
|
|
VCLK_IP_ACE_SLICE_G3D2,
|
|
VCLK_IP_ACE_SLICE_G3D3,
|
|
VCLK_IP_LHM_AXI_D0_MODEM,
|
|
VCLK_IP_LHM_AXI_D1_MODEM,
|
|
VCLK_IP_LHM_ACEL_D2_MODEM,
|
|
VCLK_IP_LHM_AXI_D_AUD,
|
|
VCLK_IP_LHS_AXI_P_AUD,
|
|
VCLK_IP_LHS_AXI_P_MODEM,
|
|
VCLK_IP_PPC_IRPS2,
|
|
VCLK_IP_PPC_IRPS3,
|
|
VCLK_IP_PPC_CPUCL0_0,
|
|
VCLK_IP_PPC_CPUCL0_1,
|
|
VCLK_IP_PPMU_CPUCL0_0,
|
|
VCLK_IP_PPMU_CPUCL0_1,
|
|
VCLK_IP_LHM_ACE_D0_CLUSTER0,
|
|
VCLK_IP_LHM_ACE_D1_CLUSTER0,
|
|
VCLK_IP_BAAW_CP,
|
|
VCLK_IP_SYSMMU_MODEM,
|
|
VCLK_IP_LHS_AXI_P_PERIS,
|
|
VCLK_IP_PPMU_MIF0,
|
|
VCLK_IP_PPMU_MIF1,
|
|
VCLK_IP_PPMU_MIF2,
|
|
VCLK_IP_PPMU_MIF3,
|
|
VCLK_IP_VGEN_LITE_MODEM,
|
|
VCLK_IP_CPUCL0_CMU_CPUCL0,
|
|
VCLK_IP_ADD_CPUCL0_0,
|
|
VCLK_IP_BUSIF_ADD_CPUCL0_0,
|
|
VCLK_IP_BUSIF_DDD_CPUCL0_0,
|
|
VCLK_IP_BUSIF_STR_CPUCL0_0,
|
|
VCLK_IP_HTU_CPUCL0,
|
|
VCLK_IP_HWACG_BUSIF_DDD_CPUCL0_0,
|
|
VCLK_IP_DDD_CPUCL0_0,
|
|
VCLK_IP_ADM_APB_G_CLUSTER0,
|
|
VCLK_IP_LHM_AXI_G_INT_ETR,
|
|
VCLK_IP_LHS_AXI_G_CSSYS,
|
|
VCLK_IP_LHM_AXI_G_INT_STM,
|
|
VCLK_IP_LHM_AXI_P_CPUCL0,
|
|
VCLK_IP_TREX_CPUCL0,
|
|
VCLK_IP_SECJTAG,
|
|
VCLK_IP_BPS_CPUCL0,
|
|
VCLK_IP_LHM_AXI_G_INT_CSSYS,
|
|
VCLK_IP_LHM_ATB_T_BDU,
|
|
VCLK_IP_XIU_P_CPUCL0,
|
|
VCLK_IP_D_TZPC_CPUCL0,
|
|
VCLK_IP_SYSREG_CPUCL0,
|
|
VCLK_IP_LHM_AXI_G_DBGCORE,
|
|
VCLK_IP_BUSIF_HPM_CPUCL0,
|
|
VCLK_IP_XIU_DP_CSSYS,
|
|
VCLK_IP_LHS_AXI_G_INT_STM,
|
|
VCLK_IP_LHM_AXI_G_INT_DBGCORE,
|
|
VCLK_IP_APB_ASYNC_P_CSSYS_0,
|
|
VCLK_IP_CSSYS,
|
|
VCLK_IP_LHS_AXI_G_INT_CSSYS,
|
|
VCLK_IP_LHS_AXI_G_INT_ETR,
|
|
VCLK_IP_LHS_AXI_G_INT_DBGCORE,
|
|
VCLK_IP_CPUCL0_GLB_CMU_CPUCL0_GLB,
|
|
VCLK_IP_HPM_CPUCL0_0,
|
|
VCLK_IP_HPM_CPUCL0_1,
|
|
VCLK_IP_HPM_CPUCL0_2,
|
|
VCLK_IP_LHM_ATB_T0_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T1_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T2_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T3_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T4_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T5_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T6_CLUSTER0,
|
|
VCLK_IP_LHM_ATB_T7_CLUSTER0,
|
|
VCLK_IP_CPUCL1_CMU_CPUCL1,
|
|
VCLK_IP_ADD_CPUCL0_1,
|
|
VCLK_IP_BUSIF_ADD_CPUCL0_1,
|
|
VCLK_IP_BUSIF_DDD_CPUCL0_2,
|
|
VCLK_IP_BUSIF_DDD_CPUCL0_3,
|
|
VCLK_IP_BUSIF_DDD_CPUCL0_4,
|
|
VCLK_IP_BUSIF_STR_CPUCL0_1,
|
|
VCLK_IP_HTU_CPUCL1,
|
|
VCLK_IP_HWACG_BUSIF_DDD_CPUCL0_2,
|
|
VCLK_IP_HWACG_BUSIF_DDD_CPUCL0_4,
|
|
VCLK_IP_CPUCL1,
|
|
VCLK_IP_HWACG_BUSIF_DDD_CPUCL0_3,
|
|
VCLK_IP_CPUCL2_CMU_CPUCL2,
|
|
VCLK_IP_BUSIF_STR_CPUCL0_2,
|
|
VCLK_IP_ADD_CPUCL0_2,
|
|
VCLK_IP_BUSIF_ADD_CPUCL0_2,
|
|
VCLK_IP_BUSIF_DDD_CPUCL0_1,
|
|
VCLK_IP_HTU_CPUCL2,
|
|
VCLK_IP_HWACG_BUSIF_DDD_CPUCL0_1,
|
|
VCLK_IP_DDD_CPUCL0_1,
|
|
VCLK_IP_MIPI_PHY_LINK_WRAP,
|
|
VCLK_IP_PDP_TOP,
|
|
VCLK_IP_QE_PDP_STAT_IMG0,
|
|
VCLK_IP_QE_CSIS_DMA3,
|
|
VCLK_IP_QE_PDP_STAT_AF0,
|
|
VCLK_IP_QE_PDP_AF1,
|
|
VCLK_IP_QE_PDP_STAT_IMG1,
|
|
VCLK_IP_QE_STRP1,
|
|
VCLK_IP_QE_STRP2,
|
|
VCLK_IP_QE_ZSL1,
|
|
VCLK_IP_QE_ZSL2,
|
|
VCLK_IP_AD_APB_PDP_CORE,
|
|
VCLK_IP_VGEN_LITE_D1,
|
|
VCLK_IP_VGEN_LITE_D2,
|
|
VCLK_IP_LHS_AST_OTF0_CSISTAA,
|
|
VCLK_IP_LHS_AST_OTF1_CSISTAA,
|
|
VCLK_IP_LHS_AST_OTF2_CSISTAA,
|
|
VCLK_IP_LHS_AST_INT_VO_PDPCSIS,
|
|
VCLK_IP_CSIS_CMU_CSIS,
|
|
VCLK_IP_LHS_AXI_D0_CSIS,
|
|
VCLK_IP_LHS_AXI_D1_CSIS,
|
|
VCLK_IP_D_TZPC_CSIS,
|
|
VCLK_IP_CSISX6,
|
|
VCLK_IP_PPMU_D0,
|
|
VCLK_IP_PPMU_D1,
|
|
VCLK_IP_SYSMMU_D0_CSIS,
|
|
VCLK_IP_SYSMMU_D1_CSIS,
|
|
VCLK_IP_SYSREG_CSIS,
|
|
VCLK_IP_VGEN_LITE_D0,
|
|
VCLK_IP_LHM_AXI_P_CSIS,
|
|
VCLK_IP_LHM_AST_INT_VO_PDPCSIS,
|
|
VCLK_IP_LHM_AST_ZOTF0_TAACSIS,
|
|
VCLK_IP_LHM_AST_ZOTF1_TAACSIS,
|
|
VCLK_IP_LHM_AST_ZOTF2_TAACSIS,
|
|
VCLK_IP_AD_APB_CSIS0,
|
|
VCLK_IP_XIU_D0_CSIS,
|
|
VCLK_IP_XIU_D1_CSIS,
|
|
VCLK_IP_QE_CSIS_DMA1,
|
|
VCLK_IP_QE_ZSL0,
|
|
VCLK_IP_QE_STRP0,
|
|
VCLK_IP_LHM_AST_SOTF0_TAACSIS,
|
|
VCLK_IP_LHM_AST_SOTF1_TAACSIS,
|
|
VCLK_IP_LHM_AST_SOTF2_TAACSIS,
|
|
VCLK_IP_PPMU_D2,
|
|
VCLK_IP_OIS_MCU_TOP,
|
|
VCLK_IP_AD_AXI_OIS_MCU_TOP,
|
|
VCLK_IP_QE_CSIS_DMA0,
|
|
VCLK_IP_LHS_AXI_P_CSISPERIC1,
|
|
VCLK_IP_LHS_AST_OTF3_CSISTAA,
|
|
VCLK_IP_LHM_AST_ZOTF3_TAACSIS,
|
|
VCLK_IP_LHM_AST_SOTF3_TAACSIS,
|
|
VCLK_IP_LHM_AST_INT_VO_CSISPDP,
|
|
VCLK_IP_LHS_AST_INT_VO_CSISPDP,
|
|
VCLK_IP_XIU_D2_CSIS,
|
|
VCLK_IP_PPMU_D3,
|
|
VCLK_IP_SYSMMU_D2_CSIS,
|
|
VCLK_IP_SYSMMU_D3_CSIS,
|
|
VCLK_IP_QE_CSIS_DMA2,
|
|
VCLK_IP_LHS_AXI_D2_CSIS,
|
|
VCLK_IP_LHS_AXI_D3_CSIS,
|
|
VCLK_IP_QE_PDP_STAT_IMG2,
|
|
VCLK_IP_QE_PDP_AF2,
|
|
VCLK_IP_XIU_D4_CSIS,
|
|
VCLK_IP_XIU_D3_CSIS,
|
|
VCLK_IP_AD_AXI_STRP,
|
|
VCLK_IP_LHM_AST_INT_OTF0_CSISPDP,
|
|
VCLK_IP_LHM_AST_INT_OTF1_CSISPDP,
|
|
VCLK_IP_LHM_AST_INT_OTF2_CSISPDP,
|
|
VCLK_IP_LHM_AST_INT_OTF3_CSISPDP,
|
|
VCLK_IP_LHS_AST_INT_OTF0_CSISPDP,
|
|
VCLK_IP_LHS_AST_INT_OTF1_CSISPDP,
|
|
VCLK_IP_LHS_AST_INT_OTF2_CSISPDP,
|
|
VCLK_IP_LHS_AST_INT_OTF3_CSISPDP,
|
|
VCLK_IP_LHM_AST_INT_OTF0_PDPCSIS,
|
|
VCLK_IP_LHM_AST_INT_OTF1_PDPCSIS,
|
|
VCLK_IP_LHM_AST_INT_OTF2_PDPCSIS,
|
|
VCLK_IP_LHM_AST_INT_OTF3_PDPCSIS,
|
|
VCLK_IP_LHS_AST_INT_OTF0_PDPCSIS,
|
|
VCLK_IP_LHS_AST_INT_OTF1_PDPCSIS,
|
|
VCLK_IP_LHS_AST_INT_OTF2_PDPCSIS,
|
|
VCLK_IP_LHS_AST_INT_OTF3_PDPCSIS,
|
|
VCLK_IP_QE_STRP3,
|
|
VCLK_IP_QE_ZSL3,
|
|
VCLK_IP_DNS_CMU_DNS,
|
|
VCLK_IP_LHM_AST_OTF4_ITPDNS,
|
|
VCLK_IP_XIU_D0_DNS,
|
|
VCLK_IP_LHM_AST_OTF_TAADNS,
|
|
VCLK_IP_SYSMMU_D1_DNS,
|
|
VCLK_IP_LHM_AXI_P_ITPDNS,
|
|
VCLK_IP_LHM_AST_OTF3_ITPDNS,
|
|
VCLK_IP_D_TZPC_DNS,
|
|
VCLK_IP_LHM_AST_OTF_MCFP1DNS,
|
|
VCLK_IP_LHM_AST_OTF2_ITPDNS,
|
|
VCLK_IP_AD_APB_DNS0,
|
|
VCLK_IP_DNS,
|
|
VCLK_IP_LHM_AST_OTF0_ITPDNS,
|
|
VCLK_IP_LHM_AST_OTF1_ITPDNS,
|
|
VCLK_IP_XIU_D1_DNS,
|
|
VCLK_IP_LHS_AST_OTF9_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF8_DNSITP,
|
|
VCLK_IP_SYSREG_DNS,
|
|
VCLK_IP_LHS_AXI_D0_DNS,
|
|
VCLK_IP_PPMU_D0_DNS,
|
|
VCLK_IP_LHS_AST_OTF5_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF4_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF6_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF0_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF1_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF2_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF3_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF7_DNSITP,
|
|
VCLK_IP_LHS_AXI_D1_DNS,
|
|
VCLK_IP_LHM_AST_CTL_ITPDNS,
|
|
VCLK_IP_PPMU_D1_DNS,
|
|
VCLK_IP_SYSMMU_D0_DNS,
|
|
VCLK_IP_LHS_AST_CTL_DNSITP,
|
|
VCLK_IP_VGEN_LITE_D0_DNS,
|
|
VCLK_IP_VGEN_LITE_D1_DNS,
|
|
VCLK_IP_DPUB_CMU_DPUB,
|
|
VCLK_IP_LHM_AXI_P_DPUB,
|
|
VCLK_IP_D_TZPC_DPUB,
|
|
VCLK_IP_SYSREG_DPUB,
|
|
VCLK_IP_DPUB,
|
|
VCLK_IP_AD_APB_DECON_MAIN,
|
|
VCLK_IP_DPUF0_CMU_DPUF0,
|
|
VCLK_IP_SYSREG_DPUF0,
|
|
VCLK_IP_SYSMMU_DPUF0D0,
|
|
VCLK_IP_LHM_AXI_P_DPUF0,
|
|
VCLK_IP_LHS_AXI_D1_DPUF0,
|
|
VCLK_IP_AD_APB_DPUF0_DMA,
|
|
VCLK_IP_SYSMMU_DPUF0D1,
|
|
VCLK_IP_PPMU_DPUF0D0,
|
|
VCLK_IP_PPMU_DPUF0D1,
|
|
VCLK_IP_LHS_AXI_D0_DPUF0,
|
|
VCLK_IP_DPUF0,
|
|
VCLK_IP_D_TZPC_DPUF0,
|
|
VCLK_IP_LHM_AXI_D_DPUF1DPUF0,
|
|
VCLK_IP_DPUF1_CMU_DPUF1,
|
|
VCLK_IP_AD_APB_DPUF1_DMA,
|
|
VCLK_IP_LHS_AXI_D1_DPUF1,
|
|
VCLK_IP_DPUF1,
|
|
VCLK_IP_PPMU_DPUF1D0,
|
|
VCLK_IP_PPMU_DPUF1D1,
|
|
VCLK_IP_D_TZPC_DPUF1,
|
|
VCLK_IP_LHS_AXI_D0_DPUF1,
|
|
VCLK_IP_LHM_AXI_P_DPUF1,
|
|
VCLK_IP_SYSMMU_DPUF1D0,
|
|
VCLK_IP_SYSMMU_DPUF1D1,
|
|
VCLK_IP_SYSREG_DPUF1,
|
|
VCLK_IP_LHS_AXI_D_DPUF1DPUF0,
|
|
VCLK_IP_CLUSTER0,
|
|
VCLK_IP_DSU_CMU_DSU,
|
|
VCLK_IP_LHM_AST_IRI_GICCPU_CLUSTER0,
|
|
VCLK_IP_LHS_AST_ICC_CPUGIC_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T0_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T1_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T2_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T3_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T4_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T5_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T6_CLUSTER0,
|
|
VCLK_IP_LHS_ATB_T7_CLUSTER0,
|
|
VCLK_IP_BUSIF_STR_CPUCL0_3,
|
|
VCLK_IP_HTU_DSU,
|
|
VCLK_IP_PPC_INSTRRET_CLUSTER0_0,
|
|
VCLK_IP_PPC_INSTRRET_CLUSTER0_1,
|
|
VCLK_IP_PPC_INSTRRUN_CLUSTER0_0,
|
|
VCLK_IP_PPC_INSTRRUN_CLUSTER0_1,
|
|
VCLK_IP_ACE_US_128TO256_D0_CLUSTER0,
|
|
VCLK_IP_ACE_US_128TO256_D1_CLUSTER0,
|
|
VCLK_IP_LHS_ACE_D0_CLUSTER0,
|
|
VCLK_IP_LHS_ACE_D1_CLUSTER0,
|
|
VCLK_IP_LHM_AXI_P_G3D,
|
|
VCLK_IP_BUSIF_HPMG3D,
|
|
VCLK_IP_HPM_G3D,
|
|
VCLK_IP_SYSREG_G3D,
|
|
VCLK_IP_G3D_CMU_G3D,
|
|
VCLK_IP_LHS_AXI_P_INT_G3D,
|
|
VCLK_IP_VGEN_LITE_G3D,
|
|
VCLK_IP_LHM_AXI_P_INT_G3D,
|
|
VCLK_IP_GRAY2BIN_G3D,
|
|
VCLK_IP_D_TZPC_G3D,
|
|
VCLK_IP_ADD_APBIF_G3D,
|
|
VCLK_IP_ADD_G3D,
|
|
VCLK_IP_DDD_APBIF_G3D,
|
|
VCLK_IP_GPU,
|
|
VCLK_IP_BUSIF_STR_G3D,
|
|
VCLK_IP_DDD_G3D,
|
|
VCLK_IP_HTU_G3D,
|
|
VCLK_IP_USB31DRD,
|
|
VCLK_IP_DP_LINK,
|
|
VCLK_IP_PPMU_HSI0_BUS1,
|
|
VCLK_IP_LHS_ACEL_D_HSI0,
|
|
VCLK_IP_VGEN_LITE_HSI0,
|
|
VCLK_IP_D_TZPC_HSI0,
|
|
VCLK_IP_LHM_AXI_P_HSI0,
|
|
VCLK_IP_SYSMMU_USB,
|
|
VCLK_IP_SYSREG_HSI0,
|
|
VCLK_IP_HSI0_CMU_HSI0,
|
|
VCLK_IP_XIU_D1_HSI0,
|
|
VCLK_IP_LHM_AXI_D_AUDHSI0,
|
|
VCLK_IP_LHS_AXI_D_HSI0AUD,
|
|
VCLK_IP_XIU_D0_HSI0,
|
|
VCLK_IP_SYSMMU_HSI1,
|
|
VCLK_IP_HSI1_CMU_HSI1,
|
|
VCLK_IP_PCIE_GEN2,
|
|
VCLK_IP_SYSREG_HSI1,
|
|
VCLK_IP_GPIO_HSI1,
|
|
VCLK_IP_LHS_ACEL_D_HSI1,
|
|
VCLK_IP_LHM_AXI_P_HSI1,
|
|
VCLK_IP_XIU_D_HSI1,
|
|
VCLK_IP_XIU_P_HSI1,
|
|
VCLK_IP_PPMU_HSI1,
|
|
VCLK_IP_VGEN_LITE_HSI1,
|
|
VCLK_IP_PCIE_IA_GEN2,
|
|
VCLK_IP_D_TZPC_HSI1,
|
|
VCLK_IP_PCIE_GEN4_0,
|
|
VCLK_IP_PCIE_IA_GEN4_0,
|
|
VCLK_IP_UFS_EMBD,
|
|
VCLK_IP_MMC_CARD,
|
|
VCLK_IP_ITP_CMU_ITP,
|
|
VCLK_IP_SYSREG_ITP,
|
|
VCLK_IP_D_TZPC_ITP,
|
|
VCLK_IP_LHS_AST_CTL_ITPDNS,
|
|
VCLK_IP_ITP,
|
|
VCLK_IP_LHS_AST_OTF4_ITPDNS,
|
|
VCLK_IP_LHM_AST_CTL_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF4_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF3_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF5_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF6_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF7_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF8_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF9_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF2_DNSITP,
|
|
VCLK_IP_LHM_AXI_P_ITP,
|
|
VCLK_IP_LHM_AST_OTF0_DNSITP,
|
|
VCLK_IP_LHM_AST_OTF1_DNSITP,
|
|
VCLK_IP_LHS_AST_OTF1_ITPDNS,
|
|
VCLK_IP_LHS_AST_OTF2_ITPDNS,
|
|
VCLK_IP_LHS_AST_OTF3_ITPDNS,
|
|
VCLK_IP_AD_APB_ITP0,
|
|
VCLK_IP_LHS_AST_OTF0_ITPDNS,
|
|
VCLK_IP_LHS_AXI_P_ITPDNS,
|
|
VCLK_IP_LHM_AST_OTF_MCFP1ITP,
|
|
VCLK_IP_LHS_AST_OTF_ITPMCSC,
|
|
VCLK_IP_LME_CMU_LME,
|
|
VCLK_IP_SYSMMU_D_LME,
|
|
VCLK_IP_SYSREG_LME,
|
|
VCLK_IP_D_TZPC_LME,
|
|
VCLK_IP_LME,
|
|
VCLK_IP_PPMU_LME,
|
|
VCLK_IP_LHS_AXI_D_LME,
|
|
VCLK_IP_AD_APB_LME,
|
|
VCLK_IP_VGEN_LITE_LME,
|
|
VCLK_IP_LHM_AXI_P_LME,
|
|
VCLK_IP_XIU_D_LME,
|
|
VCLK_IP_M2M_CMU_M2M,
|
|
VCLK_IP_LHS_ACEL_D_M2M,
|
|
VCLK_IP_AS_APB_M2M,
|
|
VCLK_IP_SYSMMU_D_M2M,
|
|
VCLK_IP_XIU_D_M2M,
|
|
VCLK_IP_QE_JPEG0,
|
|
VCLK_IP_D_TZPC_M2M,
|
|
VCLK_IP_M2M,
|
|
VCLK_IP_QE_JSQZ,
|
|
VCLK_IP_QE_M2M,
|
|
VCLK_IP_LHM_AXI_P_M2M,
|
|
VCLK_IP_QE_ASTC,
|
|
VCLK_IP_VGEN_LITE_M2M,
|
|
VCLK_IP_PPMU_D_M2M,
|
|
VCLK_IP_SYSREG_M2M,
|
|
VCLK_IP_ASTC,
|
|
VCLK_IP_JPEG0,
|
|
VCLK_IP_JSQZ,
|
|
VCLK_IP_JPEG1,
|
|
VCLK_IP_QE_JPEG1,
|
|
VCLK_IP_MCFP0_CMU_MCFP0,
|
|
VCLK_IP_LHS_AXI_D0_MCFP0,
|
|
VCLK_IP_LHM_AXI_P_MCFP0,
|
|
VCLK_IP_LHS_AST_OTF0_MCFP0MCFP1,
|
|
VCLK_IP_LHS_AST_OTF1_MCFP0MCFP1,
|
|
VCLK_IP_LHM_AST_OTF0_MCFP1MCFP0,
|
|
VCLK_IP_SYSREG_MCFP0,
|
|
VCLK_IP_D_TZPC_MCFP0,
|
|
VCLK_IP_VGEN_LITE_MCFP0,
|
|
VCLK_IP_PPMU_D0_MCFP0,
|
|
VCLK_IP_SYSMMU_D0_MCFP0,
|
|
VCLK_IP_APB_ASYNC_MCFP0_0,
|
|
VCLK_IP_MCFP0,
|
|
VCLK_IP_LHS_AXI_D1_MCFP0,
|
|
VCLK_IP_LHM_AST_OTF1_MCFP1MCFP0,
|
|
VCLK_IP_PPMU_D1_MCFP0,
|
|
VCLK_IP_SYSMMU_D1_MCFP0,
|
|
VCLK_IP_LHS_AXI_P_MCFP0MCFP1,
|
|
VCLK_IP_LHM_AST_OTF2_MCFP1MCFP0,
|
|
VCLK_IP_LHM_AST_OTF3_MCFP1MCFP0,
|
|
VCLK_IP_QE_D0_MCFP0,
|
|
VCLK_IP_QE_D1_MCFP0,
|
|
VCLK_IP_QE_D2_MCFP0,
|
|
VCLK_IP_QE_D3_MCFP0,
|
|
VCLK_IP_XIU_D0_MCFP0,
|
|
VCLK_IP_PPMU_D2_MCFP0,
|
|
VCLK_IP_PPMU_D3_MCFP0,
|
|
VCLK_IP_SYSMMU_D2_MCFP0,
|
|
VCLK_IP_SYSMMU_D3_MCFP0,
|
|
VCLK_IP_LHS_AXI_D2_MCFP0,
|
|
VCLK_IP_LHS_AXI_D3_MCFP0,
|
|
VCLK_IP_LHM_AST_CTL_MCFP1MCFP0,
|
|
VCLK_IP_LHS_AST_CTL_MCFP0MCFP1,
|
|
VCLK_IP_MCFP1_CMU_MCFP1,
|
|
VCLK_IP_AD_APB_MCFP1_0,
|
|
VCLK_IP_QE_D2_ORBMCH,
|
|
VCLK_IP_VGEN_LITE_D0_MCFP1,
|
|
VCLK_IP_PPMU_ORBMCH,
|
|
VCLK_IP_QE_D0_ORBMCH,
|
|
VCLK_IP_LHM_AST_OTF1_MCFP0MCFP1,
|
|
VCLK_IP_LHM_AXI_P_MCFP0MCFP1,
|
|
VCLK_IP_MCFP1,
|
|
VCLK_IP_LHS_AXI_D_MCFP1,
|
|
VCLK_IP_LHS_AST_OTF_MCFP1ITP,
|
|
VCLK_IP_LHM_AST_VO_TAAMCFP1,
|
|
VCLK_IP_LHS_AST_OTF_MCFP1DNS,
|
|
VCLK_IP_ORBMCH0,
|
|
VCLK_IP_SYSREG_MCFP1,
|
|
VCLK_IP_LHS_AST_VO_MCFP1TAA,
|
|
VCLK_IP_SYSMMU_D_MCFP1,
|
|
VCLK_IP_D_TZPC_MCFP1,
|
|
VCLK_IP_XIU_D_MCFP1,
|
|
VCLK_IP_QE_D1_ORBMCH,
|
|
VCLK_IP_LHS_AST_OTF0_MCFP1MCFP0,
|
|
VCLK_IP_LHM_AST_OTF0_MCFP0MCFP1,
|
|
VCLK_IP_LHS_AST_OTF1_MCFP1MCFP0,
|
|
VCLK_IP_AD_APB_ORBMCH0,
|
|
VCLK_IP_LHS_AST_OTF2_MCFP1MCFP0,
|
|
VCLK_IP_LHS_AST_OTF3_MCFP1MCFP0,
|
|
VCLK_IP_QE_D3_ORBMCH,
|
|
VCLK_IP_LHM_AST_CTL_MCFP0MCFP1,
|
|
VCLK_IP_LHS_AST_CTL_MCFP1MCFP0,
|
|
VCLK_IP_ORBMCH1,
|
|
VCLK_IP_QE_D4_ORBMCH,
|
|
VCLK_IP_QE_D5_ORBMCH,
|
|
VCLK_IP_VGEN_LITE_D1_MCFP1,
|
|
VCLK_IP_MCSC_CMU_MCSC,
|
|
VCLK_IP_LHM_AXI_P_MCSC,
|
|
VCLK_IP_SYSREG_MCSC,
|
|
VCLK_IP_MCSC,
|
|
VCLK_IP_PPMU_D0_MCSC,
|
|
VCLK_IP_D_TZPC_MCSC,
|
|
VCLK_IP_VGEN_LITE_D0_MCSC,
|
|
VCLK_IP_AD_APB_MCSC_0,
|
|
VCLK_IP_PPMU_D1_MCSC,
|
|
VCLK_IP_GDC,
|
|
VCLK_IP_AD_APB_GDC,
|
|
VCLK_IP_PPMU_D2_MCSC,
|
|
VCLK_IP_SYSMMU_D2_MCSC,
|
|
VCLK_IP_SYSMMU_D0_MCSC,
|
|
VCLK_IP_LHS_AXI_D2_MCSC,
|
|
VCLK_IP_LHS_ACEL_D0_MCSC,
|
|
VCLK_IP_LHM_AST_OTF_YUVPPMCSC,
|
|
VCLK_IP_HPM_MCSC,
|
|
VCLK_IP_BUSIF_ADD_MCSC,
|
|
VCLK_IP_BUSIF_DDD_MCSC,
|
|
VCLK_IP_ADD_MCSC,
|
|
VCLK_IP_BUSIF_HPM_MCSC,
|
|
VCLK_IP_XIU_D2_MCSC,
|
|
VCLK_IP_VGEN_LITE_D1_MCSC,
|
|
VCLK_IP_XIU_D0_MCSC,
|
|
VCLK_IP_DDD_MCSC,
|
|
VCLK_IP_LHM_AXI_D_YUVPPMCSC,
|
|
VCLK_IP_XIU_D1_MCSC,
|
|
VCLK_IP_LHS_AXI_D1_MCSC,
|
|
VCLK_IP_SYSMMU_D1_MCSC,
|
|
VCLK_IP_LHM_AST_OTF_ITPMCSC,
|
|
VCLK_IP_MFC0_CMU_MFC0,
|
|
VCLK_IP_AS_APB_MFC0,
|
|
VCLK_IP_SYSREG_MFC0,
|
|
VCLK_IP_LHS_AXI_D0_MFC0,
|
|
VCLK_IP_LHS_AXI_D1_MFC0,
|
|
VCLK_IP_LHM_AXI_P_MFC0,
|
|
VCLK_IP_SYSMMU_MFC0D0,
|
|
VCLK_IP_SYSMMU_MFC0D1,
|
|
VCLK_IP_PPMU_MFC0D0,
|
|
VCLK_IP_PPMU_MFC0D1,
|
|
VCLK_IP_AS_AXI_WFD,
|
|
VCLK_IP_PPMU_WFD,
|
|
VCLK_IP_XIU_D_MFC0,
|
|
VCLK_IP_VGEN_MFC0,
|
|
VCLK_IP_MFC0,
|
|
VCLK_IP_WFD,
|
|
VCLK_IP_LH_ATB_MFC0,
|
|
VCLK_IP_D_TZPC_MFC0,
|
|
VCLK_IP_AS_APB_WFD_NS,
|
|
VCLK_IP_LHM_AST_OTF0_MFC1MFC0,
|
|
VCLK_IP_LHM_AST_OTF1_MFC1MFC0,
|
|
VCLK_IP_LHM_AST_OTF2_MFC1MFC0,
|
|
VCLK_IP_LHM_AST_OTF3_MFC1MFC0,
|
|
VCLK_IP_LHS_AST_OTF0_MFC0MFC1,
|
|
VCLK_IP_LHS_AST_OTF1_MFC0MFC1,
|
|
VCLK_IP_LHS_AST_OTF2_MFC0MFC1,
|
|
VCLK_IP_LHS_AST_OTF3_MFC0MFC1,
|
|
VCLK_IP_ADS_APB_MFC0MFC1,
|
|
VCLK_IP_MFC1_CMU_MFC1,
|
|
VCLK_IP_AS_APB_MFC1,
|
|
VCLK_IP_MFC1,
|
|
VCLK_IP_PPMU_MFC1D1,
|
|
VCLK_IP_PPMU_MFC1D0,
|
|
VCLK_IP_LHS_AXI_D0_MFC1,
|
|
VCLK_IP_VGEN_MFC1,
|
|
VCLK_IP_LHM_AXI_P_MFC1,
|
|
VCLK_IP_SYSMMU_MFC1D0,
|
|
VCLK_IP_SYSMMU_MFC1D1,
|
|
VCLK_IP_SYSREG_MFC1,
|
|
VCLK_IP_D_TZPC_MFC1,
|
|
VCLK_IP_LHS_AXI_D1_MFC1,
|
|
VCLK_IP_ADM_APB_MFC0MFC1,
|
|
VCLK_IP_LHM_AST_OTF0_MFC0MFC1,
|
|
VCLK_IP_LHM_AST_OTF1_MFC0MFC1,
|
|
VCLK_IP_LHM_AST_OTF2_MFC0MFC1,
|
|
VCLK_IP_LHM_AST_OTF3_MFC0MFC1,
|
|
VCLK_IP_LHS_AST_OTF0_MFC1MFC0,
|
|
VCLK_IP_LHS_AST_OTF1_MFC1MFC0,
|
|
VCLK_IP_LHS_AST_OTF2_MFC1MFC0,
|
|
VCLK_IP_LHS_AST_OTF3_MFC1MFC0,
|
|
VCLK_IP_MIF_CMU_MIF,
|
|
VCLK_IP_DDRPHY,
|
|
VCLK_IP_SYSREG_MIF,
|
|
VCLK_IP_LHM_AXI_P_MIF,
|
|
VCLK_IP_APBBR_DDRPHY,
|
|
VCLK_IP_APBBR_DMC,
|
|
VCLK_IP_DMC,
|
|
VCLK_IP_QCH_ADAPTER_PPC_DEBUG,
|
|
VCLK_IP_D_TZPC_MIF,
|
|
VCLK_IP_PPC_DEBUG,
|
|
VCLK_IP_NPU_CMU_NPU,
|
|
VCLK_IP_IP_NPUCORE,
|
|
VCLK_IP_LHM_AXI_D1_NPU,
|
|
VCLK_IP_LHS_AXI_D_RQ_NPU,
|
|
VCLK_IP_LHM_AXI_P_NPU,
|
|
VCLK_IP_LHM_AXI_D0_NPU,
|
|
VCLK_IP_D_TZPC_NPU,
|
|
VCLK_IP_LHS_AXI_D_CMDQ_NPU,
|
|
VCLK_IP_SYSREG_NPU,
|
|
VCLK_IP_LHM_AXI_D_CTRL_NPU,
|
|
VCLK_IP_NPU01_CMU_NPU,
|
|
VCLK_IP_IP_NPU01CORE,
|
|
VCLK_IP_LHM_AXI_D1_NPU01,
|
|
VCLK_IP_LHS_AXI_D_RQ_NPU01,
|
|
VCLK_IP_LHM_AXI_P_NPU01,
|
|
VCLK_IP_LHM_AXI_D0_NPU01,
|
|
VCLK_IP_D_TZPC_NPU01,
|
|
VCLK_IP_LHS_AXI_D_CMDQ_NPU01,
|
|
VCLK_IP_SYSREG_NPU01,
|
|
VCLK_IP_LHM_AXI_D_CTRL_NPU01,
|
|
VCLK_IP_NPU10_CMU_NPU,
|
|
VCLK_IP_IP_NPU10CORE,
|
|
VCLK_IP_LHM_AXI_D1_NPU10,
|
|
VCLK_IP_LHS_AXI_D_RQ_NPU10,
|
|
VCLK_IP_LHM_AXI_P_NPU10,
|
|
VCLK_IP_LHM_AXI_D0_NPU10,
|
|
VCLK_IP_D_TZPC_NPU10,
|
|
VCLK_IP_LHS_AXI_D_CMDQ_NPU10,
|
|
VCLK_IP_SYSREG_NPU10,
|
|
VCLK_IP_LHM_AXI_D_CTRL_NPU10,
|
|
VCLK_IP_NPUS_CMU_NPUS,
|
|
VCLK_IP_SYSMMU_D0_NPUS,
|
|
VCLK_IP_SYSMMU_D2_NPUS,
|
|
VCLK_IP_SYSMMU_D1_NPUS,
|
|
VCLK_IP_LHS_AXI_D0_NPU10,
|
|
VCLK_IP_LHS_AXI_D0_NPUS,
|
|
VCLK_IP_LHS_AXI_D_CTRL_NPU10,
|
|
VCLK_IP_LHS_AXI_D0_NPU01,
|
|
VCLK_IP_VGEN_LITE_NPUS,
|
|
VCLK_IP_LHS_AXI_D0_NPU00,
|
|
VCLK_IP_LHM_AXI_P_NPUS,
|
|
VCLK_IP_LHM_AXI_D_CMDQ_NPU01,
|
|
VCLK_IP_LHM_AXI_D_CMDQ_NPU00,
|
|
VCLK_IP_LHS_AXI_D_CTRL_NPU00,
|
|
VCLK_IP_LHS_AXI_D1_NPUS,
|
|
VCLK_IP_LHS_AXI_D_CTRL_NPU01,
|
|
VCLK_IP_LHM_AXI_D_RQ_NPU10,
|
|
VCLK_IP_LHS_AXI_D1_NPU00,
|
|
VCLK_IP_LHS_AXI_D1_NPU01,
|
|
VCLK_IP_LHM_AXI_D_CMDQ_NPU10,
|
|
VCLK_IP_SYSREG_NPUS,
|
|
VCLK_IP_D_TZPC_NPUS,
|
|
VCLK_IP_IP_NPUS,
|
|
VCLK_IP_LHS_AXI_D2_NPUS,
|
|
VCLK_IP_PPMU_NPUS_2,
|
|
VCLK_IP_PPMU_NPUS_1,
|
|
VCLK_IP_PPMU_NPUS_0,
|
|
VCLK_IP_LHM_AXI_D_RQ_NPU00,
|
|
VCLK_IP_LHM_AXI_D_RQ_NPU01,
|
|
VCLK_IP_LHS_AXI_D1_NPU10,
|
|
VCLK_IP_AD_APB_P0_NPUS,
|
|
VCLK_IP_LHS_AXI_P_INT_NPUS,
|
|
VCLK_IP_LHM_AXI_P_INT_NPUS,
|
|
VCLK_IP_HPM_NPUS,
|
|
VCLK_IP_ADD_NPUS,
|
|
VCLK_IP_BUSIF_HPM_NPUS,
|
|
VCLK_IP_BUSIF_ADD_NPUS,
|
|
VCLK_IP_BUSIF_DDD_NPUS,
|
|
VCLK_IP_HTU_NPUS,
|
|
VCLK_IP_DDD_NPUS,
|
|
VCLK_IP_ADM_DAP_NPUS,
|
|
VCLK_IP_GPIO_PERIC0,
|
|
VCLK_IP_SYSREG_PERIC0,
|
|
VCLK_IP_PERIC0_CMU_PERIC0,
|
|
VCLK_IP_LHM_AXI_P_PERIC0,
|
|
VCLK_IP_D_TZPC_PERIC0,
|
|
VCLK_IP_PERIC0_TOP0,
|
|
VCLK_IP_PERIC0_TOP1,
|
|
VCLK_IP_GPIO_PERIC1,
|
|
VCLK_IP_SYSREG_PERIC1,
|
|
VCLK_IP_PERIC1_CMU_PERIC1,
|
|
VCLK_IP_LHM_AXI_P_PERIC1,
|
|
VCLK_IP_D_TZPC_PERIC1,
|
|
VCLK_IP_PERIC1_TOP0,
|
|
VCLK_IP_PERIC1_TOP1,
|
|
VCLK_IP_LHM_AXI_P_CSISPERIC1,
|
|
VCLK_IP_XIU_P_PERIC1,
|
|
VCLK_IP_USI16_I3C,
|
|
VCLK_IP_USI17_I3C,
|
|
VCLK_IP_PERIC2_TOP0,
|
|
VCLK_IP_SYSREG_PERIC2,
|
|
VCLK_IP_D_TZPC_PERIC2,
|
|
VCLK_IP_LHM_AXI_P_PERIC2,
|
|
VCLK_IP_GPIO_PERIC2,
|
|
VCLK_IP_PERIC2_CMU_PERIC2,
|
|
VCLK_IP_PERIC2_TOP1,
|
|
VCLK_IP_SYSREG_PERIS,
|
|
VCLK_IP_WDT1,
|
|
VCLK_IP_WDT0,
|
|
VCLK_IP_PERIS_CMU_PERIS,
|
|
VCLK_IP_OTP_CON_BIRA,
|
|
VCLK_IP_GIC,
|
|
VCLK_IP_LHM_AXI_P_PERIS,
|
|
VCLK_IP_MCT,
|
|
VCLK_IP_OTP_CON_TOP,
|
|
VCLK_IP_D_TZPC_PERIS,
|
|
VCLK_IP_TMU_SUB,
|
|
VCLK_IP_TMU_TOP,
|
|
VCLK_IP_LHM_AXI_P_PERISGIC,
|
|
VCLK_IP_BC_EMUL,
|
|
VCLK_IP_LHM_AST_ICC_CPUGIC_CLUSTER0,
|
|
VCLK_IP_LHS_AST_IRI_GICCPU_CLUSTER0,
|
|
VCLK_IP_OTP_CON_BISR,
|
|
VCLK_IP_S2D_CMU_S2D,
|
|
VCLK_IP_BIS_S2D,
|
|
VCLK_IP_LHM_AXI_G_SCAN2DRAM,
|
|
VCLK_IP_AD_APB_SYSMMU_RTIC,
|
|
VCLK_IP_SYSMMU_RTIC,
|
|
VCLK_IP_RTIC,
|
|
VCLK_IP_XIU_D_SSP,
|
|
VCLK_IP_LHS_ACEL_D_SSP,
|
|
VCLK_IP_AD_APB_PUF,
|
|
VCLK_IP_PUF,
|
|
VCLK_IP_SSS,
|
|
VCLK_IP_LHM_AXI_P_SSP,
|
|
VCLK_IP_D_TZPC_SSP,
|
|
VCLK_IP_BAAW_SSS,
|
|
VCLK_IP_LHM_AXI_D_SSPCORE,
|
|
VCLK_IP_PPMU_SSP,
|
|
VCLK_IP_USS_SSPCORE,
|
|
VCLK_IP_QE_RTIC,
|
|
VCLK_IP_QE_SSPCORE,
|
|
VCLK_IP_QE_SSS,
|
|
VCLK_IP_VGEN_LITE_RTIC,
|
|
VCLK_IP_SYSREG_SSPCTRL,
|
|
VCLK_IP_SWEEPER_D_SSP,
|
|
VCLK_IP_BPS_AXI_P_SSP,
|
|
VCLK_IP_ADM_DAP_SSS,
|
|
VCLK_IP_SSP_CMU_SSP,
|
|
VCLK_IP_LHS_AXI_D_TAA,
|
|
VCLK_IP_LHM_AXI_P_TAA,
|
|
VCLK_IP_SYSREG_TAA,
|
|
VCLK_IP_TAA_CMU_TAA,
|
|
VCLK_IP_LHS_AST_OTF_TAADNS,
|
|
VCLK_IP_D_TZPC_TAA,
|
|
VCLK_IP_LHM_AST_OTF0_CSISTAA,
|
|
VCLK_IP_SIPU_TAA,
|
|
VCLK_IP_AD_APB_TAA,
|
|
VCLK_IP_LHS_AST_ZOTF0_TAACSIS,
|
|
VCLK_IP_LHS_AST_ZOTF1_TAACSIS,
|
|
VCLK_IP_LHS_AST_ZOTF2_TAACSIS,
|
|
VCLK_IP_PPMU_TAA,
|
|
VCLK_IP_SYSMMU_D_TAA,
|
|
VCLK_IP_VGEN_LITE_TAA0,
|
|
VCLK_IP_LHM_AST_OTF1_CSISTAA,
|
|
VCLK_IP_LHM_AST_OTF2_CSISTAA,
|
|
VCLK_IP_LHS_AST_SOTF0_TAACSIS,
|
|
VCLK_IP_LHS_AST_SOTF1_TAACSIS,
|
|
VCLK_IP_LHS_AST_SOTF2_TAACSIS,
|
|
VCLK_IP_LHM_AST_OTF3_CSISTAA,
|
|
VCLK_IP_LHS_AST_SOTF3_TAACSIS,
|
|
VCLK_IP_LHS_AST_ZOTF3_TAACSIS,
|
|
VCLK_IP_LHM_AST_VO_MCFP1TAA,
|
|
VCLK_IP_LHS_AST_VO_TAAMCFP1,
|
|
VCLK_IP_HPM_TAA,
|
|
VCLK_IP_BUSIF_HPM_TAA,
|
|
VCLK_IP_ADD_TAA,
|
|
VCLK_IP_BUSIF_ADD_TAA,
|
|
VCLK_IP_BUSIF_DDD_TAA,
|
|
VCLK_IP_VGEN_LITE_TAA1,
|
|
VCLK_IP_DDD_TAA,
|
|
VCLK_IP_XIU_D_TAA,
|
|
VCLK_IP_VPC_CMU_VPC,
|
|
VCLK_IP_D_TZPC_VPC,
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|
VCLK_IP_LHS_AXI_P_VPCVPD0,
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VCLK_IP_LHS_AXI_P_VPCVPD1,
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|
VCLK_IP_LHS_AXI_D_VPCVPD0_SFR,
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VCLK_IP_LHM_AXI_P_VPC,
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VCLK_IP_LHM_AXI_D_VPD0VPC_SFR,
|
|
VCLK_IP_LHM_AXI_D_VPD1VPC_SFR,
|
|
VCLK_IP_PPMU_VPC0,
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|
VCLK_IP_PPMU_VPC1,
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|
VCLK_IP_PPMU_VPC2,
|
|
VCLK_IP_IP_VPC,
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|
VCLK_IP_SYSREG_VPC,
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VCLK_IP_LHS_AXI_D_VPCVPD1_SFR,
|
|
VCLK_IP_LHS_AXI_P_VPC_200,
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|
VCLK_IP_LHM_AXI_P_VPC_800,
|
|
VCLK_IP_SYSMMU_VPC2,
|
|
VCLK_IP_LHS_ACEL_D2_VPC,
|
|
VCLK_IP_LHM_AXI_D_VPD1VPC_CACHE,
|
|
VCLK_IP_LHM_AXI_D_VPD0VPC_CACHE,
|
|
VCLK_IP_AD_APB_VPC0,
|
|
VCLK_IP_SYSMMU_VPC0,
|
|
VCLK_IP_SYSMMU_VPC1,
|
|
VCLK_IP_LHS_ACEL_D0_VPC,
|
|
VCLK_IP_LHS_ACEL_D1_VPC,
|
|
VCLK_IP_LHS_AXI_D_VPCVPD0_DMA,
|
|
VCLK_IP_LHS_AXI_D_VPCVPD1_DMA,
|
|
VCLK_IP_HPM_VPC,
|
|
VCLK_IP_ADD_VPC,
|
|
VCLK_IP_BUSIF_HPM_VPC,
|
|
VCLK_IP_BUSIF_ADD_VPC,
|
|
VCLK_IP_BUSIF_DDD_VPC,
|
|
VCLK_IP_ADM_DAP_VPC,
|
|
VCLK_IP_HTU_VPC,
|
|
VCLK_IP_DDD_VPC,
|
|
VCLK_IP_VGEN_LITE_VPC,
|
|
VCLK_IP_XIU_VPC_VOTF,
|
|
VCLK_IP_VPD_CMU_VPD,
|
|
VCLK_IP_SYSREG_VPD,
|
|
VCLK_IP_LHS_AXI_D_VPDVPC_SFR,
|
|
VCLK_IP_IP_VPD,
|
|
VCLK_IP_LHS_AXI_D_VPDVPC_CACHE,
|
|
VCLK_IP_LHM_AXI_P_VPCVPD,
|
|
VCLK_IP_LHM_AXI_D_VPCVPD_SFR,
|
|
VCLK_IP_D_TZPC_VPD,
|
|
VCLK_IP_LHM_AXI_D_VPCVPD_DMA,
|
|
VCLK_IP_AHB_BUSMATRIX,
|
|
VCLK_IP_DMIC_IF0,
|
|
VCLK_IP_SYSREG_VTS,
|
|
VCLK_IP_VTS_CMU_VTS,
|
|
VCLK_IP_LHM_AXI_P_VTS,
|
|
VCLK_IP_GPIO_VTS,
|
|
VCLK_IP_WDT_VTS,
|
|
VCLK_IP_DMIC_AHB0,
|
|
VCLK_IP_DMIC_AHB1,
|
|
VCLK_IP_ASYNCINTERRUPT,
|
|
VCLK_IP_SS_VTS_GLUE,
|
|
VCLK_IP_CORTEXM4INTEGRATION,
|
|
VCLK_IP_LHS_AXI_D_VTS,
|
|
VCLK_IP_D_TZPC_VTS,
|
|
VCLK_IP_VGEN_LITE,
|
|
VCLK_IP_BPS_LP_VTS,
|
|
VCLK_IP_BPS_P_VTS,
|
|
VCLK_IP_SWEEPER_D_VTS,
|
|
VCLK_IP_BAAW_D_VTS,
|
|
VCLK_IP_MAILBOX_ABOX_VTS,
|
|
VCLK_IP_DMIC_AHB2,
|
|
VCLK_IP_DMIC_AHB3,
|
|
VCLK_IP_DMIC_IF2,
|
|
VCLK_IP_MAILBOX_APM_VTS1,
|
|
VCLK_IP_TIMER,
|
|
VCLK_IP_PDMA_VTS,
|
|
VCLK_IP_DMIC_AHB4,
|
|
VCLK_IP_DMIC_AHB5,
|
|
VCLK_IP_DMIC_AUD0,
|
|
VCLK_IP_DMIC_IF1,
|
|
VCLK_IP_DMIC_AUD1,
|
|
VCLK_IP_DMIC_AUD2,
|
|
VCLK_IP_SERIAL_LIF,
|
|
VCLK_IP_TIMER1,
|
|
VCLK_IP_TIMER2,
|
|
VCLK_IP_SERIAL_LIF_DEBUG_VT,
|
|
VCLK_IP_SERIAL_LIF_DEBUG_US,
|
|
VCLK_IP_LHM_AXI_D_AUDVTS,
|
|
VCLK_IP_MAILBOX_AP_VTS,
|
|
VCLK_IP_BAAW_C_VTS,
|
|
VCLK_IP_LHS_AXI_C_VTS,
|
|
VCLK_IP_SWEEPER_C_VTS,
|
|
VCLK_IP_HWACG_SYS_DMIC0,
|
|
VCLK_IP_HWACG_SYS_DMIC1,
|
|
VCLK_IP_HWACG_SYS_DMIC2,
|
|
VCLK_IP_HWACG_SYS_DMIC3,
|
|
VCLK_IP_HWACG_SYS_DMIC4,
|
|
VCLK_IP_HWACG_SYS_DMIC5,
|
|
VCLK_IP_ASYNCAHB0,
|
|
VCLK_IP_ASYNCAHB1,
|
|
VCLK_IP_ASYNCAHB2,
|
|
VCLK_IP_ASYNCAHB3,
|
|
VCLK_IP_ASYNCAHB4,
|
|
VCLK_IP_ASYNCAHB5,
|
|
VCLK_IP_HPM_VTS,
|
|
VCLK_IP_ASYNC_APB_VTS,
|
|
VCLK_IP_BUSIF_HPM_VTS,
|
|
VCLK_IP_DMAILBOX_TEST,
|
|
VCLK_IP_HWACG_SYS_SERIAL_LIF,
|
|
VCLK_IP_LHM_AXI_LP_VTS,
|
|
VCLK_IP_YUVPP_CMU_YUVPP,
|
|
VCLK_IP_AD_APB_YUVPP0,
|
|
VCLK_IP_D_TZPC_YUVPP,
|
|
VCLK_IP_LHM_AXI_P_YUVPP,
|
|
VCLK_IP_SYSREG_YUVPP,
|
|
VCLK_IP_VGEN_LITE_YUVPP0,
|
|
VCLK_IP_SYSMMU_D_YUVPP,
|
|
VCLK_IP_QE_D0_YUVPP,
|
|
VCLK_IP_PPMU_YUVPP,
|
|
VCLK_IP_XIU_D0_YUVPP,
|
|
VCLK_IP_LHS_AXI_D_YUVPP,
|
|
VCLK_IP_QE_D1_YUVPP,
|
|
VCLK_IP_YUVPP_TOP,
|
|
VCLK_IP_QE_D2_YUVPP,
|
|
VCLK_IP_QE_D3_YUVPP,
|
|
VCLK_IP_QE_D4_YUVPP,
|
|
VCLK_IP_QE_D5_YUVPP,
|
|
VCLK_IP_LHS_AST_OTF_YUVPPMCSC,
|
|
VCLK_IP_FRC_MC,
|
|
VCLK_IP_VGEN_LITE_YUVPP1,
|
|
VCLK_IP_QE_D6_YUVPP,
|
|
VCLK_IP_QE_D7_YUVPP,
|
|
VCLK_IP_QE_D8_YUVPP,
|
|
VCLK_IP_QE_D9_YUVPP,
|
|
VCLK_IP_XIU_D1_YUVPP,
|
|
VCLK_IP_AD_APB_FRC_MC,
|
|
VCLK_IP_LHS_AXI_D_YUVPPMCSC,
|
|
VCLK_IP_AD_AXI_FRC_MC,
|
|
VCLK_IP_VGEN_LITE_YUVPP2,
|
|
VCLK_IP_QE_D10_YUVPP,
|
|
VCLK_IP_QE_D11_YUVPP,
|
|
end_of_gate_vclk,
|
|
num_of_gate_vclk = end_of_gate_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE),
|
|
|
|
};
|
|
#endif
|