15303 lines
833 KiB
C
Executable file
15303 lines
833 KiB
C
Executable file
#ifndef __CMUCAL_SFR_H__
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#define __CMUCAL_SFR_H__
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#include "../cmucal.h"
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enum sfr_block_id {
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CMU_AUD = SFR_BLOCK_TYPE,
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CMU_TOP,
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CMU_CPUCL0,
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CMU_CPUCL1,
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CMU_CPUCL2,
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CMU_DSU,
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CMU_MIF,
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CMU_S2D,
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CMU_ALIVE,
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CMU_BUS0,
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CMU_BUS1,
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CMU_BUS2,
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CMU_CMGP,
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CMU_CORE,
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CMU_G3D,
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CMU_HSI0,
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CMU_PERIC0,
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CMU_PERIC1,
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CMU_PERIC2,
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CMU_VTS,
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CMU_CPUCL0_GLB,
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CMU_CSIS,
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CMU_DNS,
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CMU_DPUB,
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CMU_DPUF0,
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CMU_DPUF1,
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CMU_HSI1,
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CMU_ITP,
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CMU_LME,
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CMU_M2M,
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CMU_MCFP0,
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CMU_MCFP1,
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CMU_MCSC,
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CMU_MFC0,
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CMU_MFC1,
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CMU_NPU,
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CMU_NPU01,
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CMU_NPU10,
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CMU_NPUS,
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CMU_PERIS,
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CMU_SSP,
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CMU_TAA,
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CMU_VPC,
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CMU_VPD,
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CMU_YUVPP,
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end_of_sfr_block,
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num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE,
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};
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enum sfr_id {
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OSC_LOCKTIME_RCO_400 = SFR_TYPE,
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OSC_CON0_RCO_400,
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OSC_CON1_RCO_400,
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OSC_CON2_RCO_400,
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OSC_CON3_RCO_400,
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OSC_CON4_RCO_400,
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PLL_LOCKTIME_PLL_AUD0,
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PLL_CON3_PLL_AUD0,
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PLL_CON8_PLL_AUD0,
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PLL_LOCKTIME_PLL_AUD1,
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PLL_CON3_PLL_AUD1,
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PLL_CON8_PLL_AUD1,
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PLL_LOCKTIME_PLL_G3D,
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PLL_CON3_PLL_G3D,
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PLL_LOCKTIME_PLL_MMC,
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PLL_CON3_PLL_MMC,
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PLL_CON8_PLL_MMC,
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PLL_LOCKTIME_PLL_SHARED0,
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PLL_CON3_PLL_SHARED0,
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PLL_LOCKTIME_PLL_SHARED1,
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PLL_CON3_PLL_SHARED1,
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PLL_LOCKTIME_PLL_SHARED2,
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PLL_CON3_PLL_SHARED2,
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PLL_LOCKTIME_PLL_SHARED3,
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PLL_CON3_PLL_SHARED3,
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PLL_LOCKTIME_PLL_SHARED4,
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PLL_CON3_PLL_SHARED4,
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PLL_LOCKTIME_PLL_SHARED_MIF,
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PLL_CON3_PLL_SHARED_MIF,
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PLL_LOCKTIME_PLL_CPUCL0,
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PLL_CON3_PLL_CPUCL0,
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PLL_LOCKTIME_PLL_CPUCL1,
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PLL_CON3_PLL_CPUCL1,
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PLL_LOCKTIME_PLL_CPUCL2,
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PLL_CON3_PLL_CPUCL2,
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PLL_LOCKTIME_PLL_DSU,
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PLL_CON3_PLL_DSU,
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PLL_LOCKTIME_PLL_MIF_MAIN,
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PLL_CON3_PLL_MIF_MAIN,
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PLL_LOCKTIME_PLL_MIF_SUB,
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PLL_CON3_PLL_MIF_SUB,
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PLL_LOCKTIME_PLL_MIF_S2D,
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PLL_CON3_PLL_MIF_S2D,
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CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS,
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CLK_CON_MUX_MUX_CLK_ALIVE_BUS,
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CLK_CON_MUX_MUX_CLKCMU_VTS_BUS,
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CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC,
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CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI,
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CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
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CLK_CON_MUX_MUX_CLK_AUD_CPU,
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CLK_CON_MUX_MUX_CLK_AUD_DSIF,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
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CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
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CLK_CON_MUX_MUX_CLK_AUD_CNT,
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CLK_CON_MUX_MUX_CLK_AUD_BUS,
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CLK_CON_MUX_MUX_CLK_AUD_PCMC,
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CLK_CON_MUX_MUX_BUS0_CMUREF,
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CLK_CON_MUX_MUX_BUS1_CMUREF,
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CLK_CON_MUX_MUX_BUS2_CMUREF,
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CLK_CON_MUX_MUX_CLK_CMGP_I2C0,
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CLK_CON_MUX_MUX_CLK_CMGP_USI0,
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CLK_CON_MUX_MUX_CLK_CMGP_USI1,
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CLK_CON_MUX_MUX_CLK_CMGP_USI2,
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CLK_CON_MUX_MUX_CLK_CMGP_USI3,
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CLK_CON_MUX_CLK_CMGP_ADC,
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CLK_CON_MUX_MUX_CLK_CMGP_I2C1,
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CLK_CON_MUX_MUX_CLK_CMGP_I2C2,
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CLK_CON_MUX_MUX_CLK_CMGP_I2C3,
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CLK_CON_MUX_MUX_CLK_CMGP_I3C,
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CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
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CLK_CON_MUX_MUX_CLKCMU_VPD_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_TAA_BUS,
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CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
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CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
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CLK_CON_MUX_MUX_CLKCMU_HPM,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
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CLK_CON_MUX_MUX_CMU_CMUREF,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
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CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
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CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
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CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
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CLK_CON_MUX_CLKCMU_DPUF0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
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CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
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CLK_CON_MUX_MUX_CLKCMU_DPUF0,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
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CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS,
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CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
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CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
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CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE,
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CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
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CLK_CON_MUX_MUX_CLKCMU_M2M_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT,
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CLK_CON_MUX_CLKCMU_DPUB_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPUB,
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CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1,
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CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC,
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CLK_CON_MUX_MUX_CLKCMU_LME_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1,
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CLK_CON_MUX_MUX_CLKCMU_VPC_BUS,
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CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG,
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CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
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CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH,
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CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP,
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CLK_CON_MUX_MUX_CP_UCPU_CLK,
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CLK_CON_MUX_MUX_CP_LCPU_CLK,
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CLK_CON_MUX_MUX_CP_HISPEEDY_CLK,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
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CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
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CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC,
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CLK_CON_MUX_MUX_CLKCMU_G3D_BUS,
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CLK_CON_MUX_CLKCMU_G3D_SHADER,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
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CLK_CON_MUX_MUX_CLKCMU_DPUF1,
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CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT,
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CLK_CON_MUX_CLKCMU_DPUF1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP,
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CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
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CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
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CLK_CON_MUX_MUX_CORE_CMUREF,
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CLK_CON_MUX_MUX_CPUCL0_CMUREF,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
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CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY,
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CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY,
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CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
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CLK_CON_MUX_MUX_CPUCL1_CMUREF,
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CLK_CON_MUX_MUX_CPUCL2_CMUREF,
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CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
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CLK_CON_MUX_MUX_CLK_DSU_CLUSTER,
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CLK_CON_MUX_MUX_DSU_CMUREF,
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CLK_CON_MUX_MUX_PLL_DSU_DELAY,
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CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY,
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CLK_CON_MUX_MUX_CLK_G3D_BUS,
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CLK_CON_MUX_MUX_CLK_HSI0_BUS,
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CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD,
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CLK_CON_MUX_MUX_MIF_CMUREF,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
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CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI,
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CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI,
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CLK_CON_MUX_MUX_CLK_S2D_CORE,
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CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF,
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CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD,
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CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF,
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CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB,
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CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE,
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PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER,
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PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER,
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PLL_CON0_MUX_CLK_RCO_ALIVE_USER,
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PLL_CON1_MUX_CLK_RCO_ALIVE_USER,
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PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
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PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
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PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
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PLL_CON1_MUX_CLKCMU_AUD_CPU_USER,
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PLL_CON0_MUX_CLKCMU_AUD_BUS_USER,
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PLL_CON1_MUX_CLKCMU_AUD_BUS_USER,
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PLL_CON0_MUX_CP_PCMC_CLK_USER,
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PLL_CON1_MUX_CP_PCMC_CLK_USER,
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PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER,
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PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER,
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PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER,
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PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER,
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PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER,
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PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER,
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PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER,
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PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER,
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PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER,
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PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER,
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PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER,
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PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER,
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PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER,
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PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER,
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PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
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PLL_CON1_MUX_CLKCMU_CORE_BUS_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
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PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
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PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER,
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PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
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PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
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PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER,
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PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER,
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PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER,
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PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER,
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PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER,
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PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER,
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PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER,
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PLL_CON0_MUX_CLKCMU_DNS_BUS_USER,
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PLL_CON1_MUX_CLKCMU_DNS_BUS_USER,
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PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER,
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PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER,
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PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER,
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PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER,
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PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER,
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PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER,
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PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER,
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PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER,
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PLL_CON0_MUX_CLKCMU_G3D_BUS_USER,
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PLL_CON1_MUX_CLKCMU_G3D_BUS_USER,
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PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER,
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PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER,
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PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER,
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PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER,
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PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER,
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PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER,
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PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
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PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER,
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PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
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PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER,
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PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
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PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
|
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PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER,
|
|
PLL_CON0_MUX_CLK_USB20PHY_USER,
|
|
PLL_CON1_MUX_CLK_USB20PHY_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER,
|
|
PLL_CON0_MUX_CLKCMU_ITP_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_ITP_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_LME_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_LME_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_M2M_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_M2M_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER,
|
|
PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER,
|
|
PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X,
|
|
PLL_CON1_CLKMUX_MIF_DDRPHY2X,
|
|
PLL_CON0_MUX_CLKCMU_NPU_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_NPU_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER,
|
|
PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D,
|
|
PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D,
|
|
PLL_CON0_MUX_CLKCMU_SSP_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_SSP_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER,
|
|
PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER,
|
|
PLL_CON0_MUX_CLKCMU_TAA_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_TAA_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_VPC_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_VPC_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_VPD_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_VPD_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_VTS_BUS_USER,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER,
|
|
PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER,
|
|
PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER,
|
|
PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER,
|
|
PLL_CON0_MUX_CLK_RCO_VTS_USER,
|
|
PLL_CON1_MUX_CLK_RCO_VTS_USER,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER,
|
|
PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER,
|
|
PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR,
|
|
CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_BUS,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC,
|
|
CLK_CON_DIV_CLKCMU_CMGP_PERI,
|
|
CLK_CON_DIV_CLKCMU_CMGP_ADC,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SCLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC1,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
|
|
CLK_CON_DIV_CLKAUD_VTS_DMIC0,
|
|
CLK_CON_DIV_CLKAUD_HSI0_BUS,
|
|
CLK_CON_DIV_CLKAUD_HSI0_USB31DRD,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC,
|
|
CLK_CON_DIV_DIV_CLK_BUS0_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_BUS1_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_BUS2_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C0,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C1,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C2,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C3,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I3C,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_BUS,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0,
|
|
CLK_CON_DIV_CLKCMU_VPD_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS,
|
|
CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS,
|
|
CLK_CON_DIV_CLKCMU_TAA_BUS,
|
|
CLK_CON_DIV_CLKCMU_ITP_BUS,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU,
|
|
CLK_CON_DIV_CLKCMU_HPM,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF,
|
|
CLK_CON_DIV_CLKCMU_NPU_BUS,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_HSI0_BUS,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_BUS,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK4,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS,
|
|
CLK_CON_DIV_CLKCMU_CSIS_CSIS,
|
|
CLK_CON_DIV_CLKCMU_MCFP0_BUS,
|
|
CLK_CON_DIV_CLKCMU_MCSC_BUS,
|
|
CLK_CON_DIV_CLKCMU_DNS_BUS,
|
|
CLK_CON_DIV_CLKCMU_NPUS_BUS,
|
|
CLK_CON_DIV_CLKCMU_HSI1_BUS,
|
|
CLK_CON_DIV_CLKCMU_MCSC_GDC,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
|
|
CLK_CON_DIV_CLKCMU_SSP_SSPCORE,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK5,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
|
|
CLK_CON_DIV_CLKCMU_M2M_BUS,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1,
|
|
CLK_CON_DIV_CLKCMU_BUS1_SBIC,
|
|
CLK_CON_DIV_CLKCMU_LME_BUS,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_MCFP1,
|
|
CLK_CON_DIV_CLKCMU_VPC_BUS,
|
|
CLK_CON_DIV_CLKCMU_BUS0_BUS,
|
|
CLK_CON_DIV_CLKCMU_BUS2_BUS,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
|
|
CLK_CON_DIV_CLKCMU_AUD_BUS,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH,
|
|
CLK_CON_DIV_CLKCMU_CSIS_PDP,
|
|
CLK_CON_DIV_CP_SHARED0_CLK,
|
|
CLK_CON_DIV_CP_SHARED1_CLK,
|
|
CLK_CON_DIV_CP_SHARED2_CLK,
|
|
CLK_CON_DIV_CP_HISPEEDY_CLK,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1,
|
|
CLK_CON_DIV_CLKCMU_SSP_BUS,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_FRC,
|
|
CLK_CON_DIV_CLKCMU_G3D_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_BUSP,
|
|
CLK_CON_DIV_CLKCMU_DSU_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
|
|
CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_HTU,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_HTU,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_DPUF0_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_M2M_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_SSP_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUSP,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_CSIS,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_PDP,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUS,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER,
|
|
CLK_CON_DIV_DIV_CLK_G3D_SHADER,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUS,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUS,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUS,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUS,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_GDC,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_MFC0,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_MFC1,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUS,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUS,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUS,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUS,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUS,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUS,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUS,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUS,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_FRC,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC,
|
|
CLK_CON_GAT_CLKCMU_VTS_DMIC,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLKAUD_VTS_DMIC1,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPD_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_TAA_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPC_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP,
|
|
CLK_CON_GAT_CP_UCPU_CLK,
|
|
CLK_CON_GAT_CP_LCPU_CLK,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK,
|
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CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS,
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CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK,
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CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK,
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|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1,
|
|
CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK,
|
|
CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK,
|
|
CLK_CON_DIV_CLKCMU_HSI1_PCIE,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD,
|
|
CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK,
|
|
CLK_CON_DIV_DIV_CLK_MIF_BUSD,
|
|
CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLKCMU_OTP,
|
|
CLK_CON_DIV_CLK_MIF_BUSD_S2D,
|
|
CLK_CON_DIV_CLK_TAA_ADD_CH_CLK,
|
|
CLK_CON_DIV_CLK_VPC_ADD_CH_CLK,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH,
|
|
QCH_CON_APBIF_RTC_QCH,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH,
|
|
QCH_CON_APBIF_TOP_RTC_QCH,
|
|
QCH_CON_CLKMON_QCH,
|
|
QCH_CON_DBGCORE_UART_QCH,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_APM,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA,
|
|
QCH_CON_DTZPC_ALIVE_QCH,
|
|
QCH_CON_GPIO_ALIVE_QCH,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH,
|
|
QCH_CON_I3C_PMIC_QCH_P,
|
|
DMYQCH_CON_I3C_PMIC_QCH_S,
|
|
QCH_CON_INTMEM_QCH,
|
|
QCH_CON_LHM_AXI_C_MODEM_QCH,
|
|
QCH_CON_LHM_AXI_C_VTS_QCH,
|
|
QCH_CON_LHM_AXI_P_APM_QCH,
|
|
QCH_CON_LHS_AXI_C_CMGP_QCH,
|
|
QCH_CON_LHS_AXI_D_APM_QCH,
|
|
QCH_CON_LHS_AXI_G_DBGCORE_QCH,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH,
|
|
QCH_CON_LHS_AXI_LP_VTS_QCH,
|
|
QCH_CON_MAILBOX_APM_AP_QCH,
|
|
QCH_CON_MAILBOX_APM_CP_QCH,
|
|
QCH_CON_MAILBOX_AP_CP_QCH,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH,
|
|
QCH_CON_PEM_QCH,
|
|
QCH_CON_PMU_INTR_GEN_QCH,
|
|
QCH_CON_ROM_CRC32_HOST_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH,
|
|
QCH_CON_SS_DBGCORE_QCH_GREBE,
|
|
QCH_CON_SS_DBGCORE_QCH_DBG,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH,
|
|
QCH_CON_SYSREG_ALIVE_QCH,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH,
|
|
QCH_CON_WDT_ALIVE_QCH,
|
|
QCH_CON_ABOX_QCH_ACLK,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF,
|
|
QCH_CON_ABOX_QCH_BCLK0,
|
|
QCH_CON_ABOX_QCH_BCLK1,
|
|
QCH_CON_ABOX_QCH_BCLK2,
|
|
QCH_CON_ABOX_QCH_BCLK3,
|
|
DMYQCH_CON_ABOX_QCH_CPU,
|
|
QCH_CON_ABOX_QCH_BCLK4,
|
|
QCH_CON_ABOX_QCH_CNT,
|
|
QCH_CON_ABOX_QCH_BCLK5,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB,
|
|
QCH_CON_ABOX_QCH_SCLK,
|
|
QCH_CON_ABOX_QCH_BCLK6,
|
|
QCH_CON_ABOX_QCH_XCLK,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK,
|
|
QCH_CON_ABOX_QCH_C2A0,
|
|
QCH_CON_ABOX_QCH_C2A1,
|
|
QCH_CON_AUD_CMU_AUD_QCH,
|
|
QCH_CON_BAAW_D_AUDVTS_QCH,
|
|
QCH_CON_D_TZPC_AUD_QCH,
|
|
QCH_CON_LHM_AXI_D_HSI0AUD_QCH,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH,
|
|
QCH_CON_LHS_AXI_D_AUDHSI0_QCH,
|
|
QCH_CON_LHS_AXI_D_AUDVTS_QCH,
|
|
QCH_CON_MAILBOX_AUD0_QCH,
|
|
QCH_CON_MAILBOX_AUD1_QCH,
|
|
QCH_CON_MAILBOX_AUD2_QCH,
|
|
QCH_CON_MAILBOX_AUD3_QCH,
|
|
QCH_CON_PPMU_AUD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH,
|
|
QCH_CON_SMMU_AUD_QCH_S1,
|
|
QCH_CON_SMMU_AUD_QCH_S2,
|
|
QCH_CON_SYSREG_AUD_QCH,
|
|
QCH_CON_TREX_AUD_QCH,
|
|
QCH_CON_VGEN_LITE_AUD_QCH,
|
|
QCH_CON_WDT_AUD_QCH,
|
|
QCH_CON_ASYNCSFR_WR_SMC_QCH,
|
|
QCH_CON_BAAW_P_VPC_QCH,
|
|
QCH_CON_BUS0_CMU_BUS0_QCH,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH,
|
|
QCH_CON_CACHEAID_BUS0_QCH,
|
|
DMYQCH_CON_CMU_BUS0_CMUREF_QCH,
|
|
QCH_CON_D_TZPC_BUS0_QCH,
|
|
QCH_CON_LHM_ACEL_D0_VPC_QCH,
|
|
QCH_CON_LHM_ACEL_D1_VPC_QCH,
|
|
QCH_CON_LHM_ACEL_D2_VPC_QCH,
|
|
QCH_CON_LHM_AXI_D0_NPUS_QCH,
|
|
QCH_CON_LHM_AXI_D1_NPUS_QCH,
|
|
QCH_CON_LHM_AXI_D2_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH,
|
|
QCH_CON_LHS_AXI_P_NPU00_QCH,
|
|
QCH_CON_LHS_AXI_P_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_P_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_P_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIC2_QCH,
|
|
QCH_CON_LHS_AXI_P_PERISGIC_QCH,
|
|
QCH_CON_LHS_AXI_P_VPC_QCH,
|
|
QCH_CON_SYSREG_BUS0_QCH,
|
|
QCH_CON_TREX_D0_BUS0_QCH,
|
|
QCH_CON_TREX_D1_BUS0_QCH,
|
|
QCH_CON_TREX_P_BUS0_QCH,
|
|
QCH_CON_BAAW_P_VTS_QCH,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH,
|
|
DMYQCH_CON_CMU_BUS1_CMUREF_QCH,
|
|
QCH_CON_DIT_QCH,
|
|
QCH_CON_D_TZPC_BUS1_QCH,
|
|
QCH_CON_LHM_ACEL_D_HSI0_QCH,
|
|
QCH_CON_LHM_AXI_D0_DPUF0_QCH,
|
|
QCH_CON_LHM_AXI_D0_DPUF1_QCH,
|
|
QCH_CON_LHM_AXI_D1_DPUF0_QCH,
|
|
QCH_CON_LHM_AXI_D1_DPUF1_QCH,
|
|
QCH_CON_LHM_AXI_D_APM_QCH,
|
|
QCH_CON_LHM_AXI_D_SBIC_QCH,
|
|
QCH_CON_LHM_AXI_D_VTS_QCH,
|
|
QCH_CON_LHS_AXI_D_SBIC_QCH,
|
|
QCH_CON_LHS_AXI_P_DPUB_QCH,
|
|
QCH_CON_LHS_AXI_P_DPUF0_QCH,
|
|
QCH_CON_LHS_AXI_P_DPUF1_QCH,
|
|
QCH_CON_LHS_AXI_P_HSI0_QCH,
|
|
QCH_CON_LHS_AXI_P_VTS_QCH,
|
|
QCH_CON_PDMA_QCH,
|
|
QCH_CON_QE_PDMA_QCH,
|
|
QCH_CON_QE_SPDMA_QCH,
|
|
QCH_CON_SBIC_QCH,
|
|
QCH_CON_SPDMA_QCH,
|
|
QCH_CON_SYSMMU_S2_ACVPS_QCH,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH,
|
|
QCH_CON_SYSMMU_S2_SBIC_QCH,
|
|
QCH_CON_SYSREG_BUS1_QCH,
|
|
QCH_CON_TREX_D_BUS1_QCH,
|
|
QCH_CON_TREX_P_BUS1_QCH,
|
|
QCH_CON_TREX_RB_BUS1_QCH,
|
|
QCH_CON_VGEN_LITE_BUS1_QCH,
|
|
QCH_CON_VGEN_PDMA_QCH,
|
|
QCH_CON_BUS2_CMU_BUS2_QCH,
|
|
DMYQCH_CON_CMU_BUS2_CMUREF_QCH,
|
|
QCH_CON_D_TZPC_BUS2_QCH,
|
|
QCH_CON_LHM_ACEL_D0_MCSC_QCH,
|
|
QCH_CON_LHM_ACEL_D_HSI1_QCH,
|
|
QCH_CON_LHM_ACEL_D_M2M_QCH,
|
|
QCH_CON_LHM_ACEL_D_SSP_QCH,
|
|
QCH_CON_LHM_AXI_D0_CSIS_QCH,
|
|
QCH_CON_LHM_AXI_D0_DNS_QCH,
|
|
QCH_CON_LHM_AXI_D0_MCFP0_QCH,
|
|
QCH_CON_LHM_AXI_D0_MFC0_QCH,
|
|
QCH_CON_LHM_AXI_D0_MFC1_QCH,
|
|
QCH_CON_LHM_AXI_D1_CSIS_QCH,
|
|
QCH_CON_LHM_AXI_D1_DNS_QCH,
|
|
QCH_CON_LHM_AXI_D1_MCFP0_QCH,
|
|
QCH_CON_LHM_AXI_D1_MCSC_QCH,
|
|
QCH_CON_LHM_AXI_D1_MFC0_QCH,
|
|
QCH_CON_LHM_AXI_D1_MFC1_QCH,
|
|
QCH_CON_LHM_AXI_D2_CSIS_QCH,
|
|
QCH_CON_LHM_AXI_D2_MCFP0_QCH,
|
|
QCH_CON_LHM_AXI_D2_MCSC_QCH,
|
|
QCH_CON_LHM_AXI_D3_CSIS_QCH,
|
|
QCH_CON_LHM_AXI_D3_MCFP0_QCH,
|
|
QCH_CON_LHM_AXI_D_LME_QCH,
|
|
QCH_CON_LHM_AXI_D_MCFP1_QCH,
|
|
QCH_CON_LHM_AXI_D_TAA_QCH,
|
|
QCH_CON_LHM_AXI_D_YUVPP_QCH,
|
|
QCH_CON_LHS_AXI_P_CSIS_QCH,
|
|
QCH_CON_LHS_AXI_P_HSI1_QCH,
|
|
QCH_CON_LHS_AXI_P_ITP_QCH,
|
|
QCH_CON_LHS_AXI_P_LME_QCH,
|
|
QCH_CON_LHS_AXI_P_M2M_QCH,
|
|
QCH_CON_LHS_AXI_P_MCFP0_QCH,
|
|
QCH_CON_LHS_AXI_P_MCSC_QCH,
|
|
QCH_CON_LHS_AXI_P_MFC0_QCH,
|
|
QCH_CON_LHS_AXI_P_MFC1_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH,
|
|
QCH_CON_LHS_AXI_P_SSP_QCH,
|
|
QCH_CON_LHS_AXI_P_TAA_QCH,
|
|
QCH_CON_LHS_AXI_P_YUVPP_QCH,
|
|
QCH_CON_SYSREG_BUS2_QCH,
|
|
QCH_CON_TREX_D_BUS2_QCH,
|
|
QCH_CON_TREX_P_BUS2_QCH,
|
|
QCH_CON_ADC_CMGP_QCH_S0,
|
|
QCH_CON_ADC_CMGP_QCH_S1,
|
|
DMYQCH_CON_ADC_CMGP_QCH_OSC,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH,
|
|
QCH_CON_D_TZPC_CMGP_QCH,
|
|
QCH_CON_GPIO_CMGP_QCH,
|
|
QCH_CON_I2C_CMGP0_QCH,
|
|
QCH_CON_I2C_CMGP1_QCH,
|
|
QCH_CON_I2C_CMGP2_QCH,
|
|
QCH_CON_I2C_CMGP3_QCH,
|
|
QCH_CON_I3C_CMGP_QCH_P,
|
|
DMYQCH_CON_I3C_CMGP_QCH_S,
|
|
QCH_CON_LHM_AXI_C_CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH,
|
|
QCH_CON_USI_CMGP0_QCH,
|
|
QCH_CON_USI_CMGP1_QCH,
|
|
QCH_CON_USI_CMGP2_QCH,
|
|
QCH_CON_USI_CMGP3_QCH,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH,
|
|
QCH_CON_BAAW_CP_QCH,
|
|
QCH_CON_BDU_QCH,
|
|
DMYQCH_CON_CCI_QCH,
|
|
DMYQCH_CON_CMU_CORE_CMUREF_QCH,
|
|
QCH_CON_CORE_CMU_CORE_QCH,
|
|
QCH_CON_D_TZPC_CORE_QCH,
|
|
QCH_CON_LHM_ACEL_D2_MODEM_QCH,
|
|
QCH_CON_LHM_ACE_D0_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D1_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH,
|
|
QCH_CON_LHM_AXI_D0_MODEM_QCH,
|
|
QCH_CON_LHM_AXI_D1_MODEM_QCH,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH,
|
|
QCH_CON_LHS_AXI_P_APM_QCH,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH,
|
|
QCH_CON_LHS_AXI_P_MODEM_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH,
|
|
QCH_CON_PPCFW_G3D_QCH,
|
|
QCH_CON_PPC_CPUCL0_0_QCH,
|
|
QCH_CON_PPC_CPUCL0_1_QCH,
|
|
QCH_CON_PPC_G3D0_QCH,
|
|
QCH_CON_PPC_G3D1_QCH,
|
|
QCH_CON_PPC_G3D2_QCH,
|
|
QCH_CON_PPC_G3D3_QCH,
|
|
QCH_CON_PPC_IRPS0_QCH,
|
|
QCH_CON_PPC_IRPS1_QCH,
|
|
QCH_CON_PPC_IRPS2_QCH,
|
|
QCH_CON_PPC_IRPS3_QCH,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH,
|
|
QCH_CON_PPMU_G3D0_QCH,
|
|
QCH_CON_PPMU_G3D1_QCH,
|
|
QCH_CON_PPMU_G3D2_QCH,
|
|
QCH_CON_PPMU_G3D3_QCH,
|
|
QCH_CON_SYSMMU_G3D0_QCH,
|
|
QCH_CON_SYSMMU_G3D1_QCH,
|
|
QCH_CON_SYSMMU_G3D2_QCH,
|
|
QCH_CON_SYSMMU_G3D3_QCH,
|
|
QCH_CON_SYSMMU_MODEM_QCH,
|
|
QCH_CON_SYSREG_CORE_QCH,
|
|
QCH_CON_TREX_D_CORE_QCH,
|
|
QCH_CON_TREX_P0_CORE_QCH,
|
|
QCH_CON_TREX_P1_CORE_QCH,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH,
|
|
DMYQCH_CON_CPUCL0_QCH,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH,
|
|
DMYQCH_CON_DDD_CPUCL0_0_QCH,
|
|
QCH_CON_HTU_CPUCL0_QCH,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH,
|
|
QCH_CON_BPS_CPUCL0_QCH,
|
|
QCH_CON_BUSIF_HPM_CPUCL0_QCH,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH,
|
|
QCH_CON_CSSYS_QCH,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T4_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T5_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T6_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T7_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH,
|
|
QCH_CON_LHM_AXI_G_DBGCORE_QCH,
|
|
QCH_CON_LHM_AXI_G_INT_CSSYS_QCH,
|
|
QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH,
|
|
QCH_CON_LHM_AXI_G_INT_ETR_QCH,
|
|
QCH_CON_LHM_AXI_G_INT_STM_QCH,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH,
|
|
QCH_CON_LHS_AXI_G_INT_CSSYS_QCH,
|
|
QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH,
|
|
QCH_CON_LHS_AXI_G_INT_ETR_QCH,
|
|
QCH_CON_LHS_AXI_G_INT_STM_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH,
|
|
QCH_CON_SECJTAG_QCH,
|
|
QCH_CON_SYSREG_CPUCL0_QCH,
|
|
QCH_CON_TREX_CPUCL0_QCH,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH,
|
|
DMYQCH_CON_CPUCL1_QCH,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC0,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC1,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC2,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH,
|
|
QCH_CON_HTU_CPUCL1_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL1_QCH_CLK,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH,
|
|
QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH,
|
|
DMYQCH_CON_CPUCL2_QCH,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH,
|
|
DMYQCH_CON_DDD_CPUCL0_1_QCH,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH,
|
|
QCH_CON_CSISX6_QCH_VOTF0,
|
|
QCH_CON_CSISX6_QCH_DMA,
|
|
QCH_CON_CSISX6_QCH_MCB,
|
|
QCH_CON_CSISX6_QCH_VOTF1,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH,
|
|
QCH_CON_D_TZPC_CSIS_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH,
|
|
QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH,
|
|
QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH,
|
|
QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH,
|
|
QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH,
|
|
QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH,
|
|
QCH_CON_LHM_AXI_P_CSIS_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH,
|
|
QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH,
|
|
QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH,
|
|
QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH,
|
|
QCH_CON_LHS_AST_OTF0_CSISTAA_QCH,
|
|
QCH_CON_LHS_AST_OTF1_CSISTAA_QCH,
|
|
QCH_CON_LHS_AST_OTF2_CSISTAA_QCH,
|
|
QCH_CON_LHS_AST_OTF3_CSISTAA_QCH,
|
|
QCH_CON_LHS_AXI_D0_CSIS_QCH,
|
|
QCH_CON_LHS_AXI_D1_CSIS_QCH,
|
|
QCH_CON_LHS_AXI_D2_CSIS_QCH,
|
|
QCH_CON_LHS_AXI_D3_CSIS_QCH,
|
|
QCH_CON_LHS_AXI_P_CSISPERIC1_QCH,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5,
|
|
QCH_CON_OIS_MCU_TOP_QCH,
|
|
QCH_CON_PDP_TOP_QCH_PDP_TOP,
|
|
QCH_CON_PDP_TOP_QCH_C2_PDP,
|
|
QCH_CON_PPMU_D0_QCH,
|
|
QCH_CON_PPMU_D1_QCH,
|
|
QCH_CON_PPMU_D2_QCH,
|
|
QCH_CON_PPMU_D3_QCH,
|
|
QCH_CON_QE_CSIS_DMA0_QCH,
|
|
QCH_CON_QE_CSIS_DMA1_QCH,
|
|
QCH_CON_QE_CSIS_DMA2_QCH,
|
|
QCH_CON_QE_CSIS_DMA3_QCH,
|
|
QCH_CON_QE_PDP_AF1_QCH,
|
|
QCH_CON_QE_PDP_AF2_QCH,
|
|
QCH_CON_QE_PDP_STAT_AF0_QCH,
|
|
QCH_CON_QE_PDP_STAT_IMG0_QCH,
|
|
QCH_CON_QE_PDP_STAT_IMG1_QCH,
|
|
QCH_CON_QE_PDP_STAT_IMG2_QCH,
|
|
QCH_CON_QE_STRP0_QCH,
|
|
QCH_CON_QE_STRP1_QCH,
|
|
QCH_CON_QE_STRP2_QCH,
|
|
QCH_CON_QE_STRP3_QCH,
|
|
QCH_CON_QE_ZSL0_QCH,
|
|
QCH_CON_QE_ZSL1_QCH,
|
|
QCH_CON_QE_ZSL2_QCH,
|
|
QCH_CON_QE_ZSL3_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S1,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S2,
|
|
QCH_CON_SYSREG_CSIS_QCH,
|
|
QCH_CON_VGEN_LITE_D0_QCH,
|
|
QCH_CON_VGEN_LITE_D1_QCH,
|
|
QCH_CON_VGEN_LITE_D2_QCH,
|
|
QCH_CON_DNS_QCH,
|
|
QCH_CON_DNS_QCH_VOTF0,
|
|
QCH_CON_DNS_QCH_VOTF1,
|
|
QCH_CON_DNS_QCH_VOTF2,
|
|
QCH_CON_DNS_CMU_DNS_QCH,
|
|
QCH_CON_D_TZPC_DNS_QCH,
|
|
QCH_CON_LHM_AST_CTL_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF0_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF1_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF2_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF3_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF4_ITPDNS_QCH,
|
|
QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH,
|
|
QCH_CON_LHM_AST_OTF_TAADNS_QCH,
|
|
QCH_CON_LHM_AXI_P_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_CTL_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF0_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF1_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF2_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF3_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF4_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF5_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF6_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF7_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF8_DNSITP_QCH,
|
|
QCH_CON_LHS_AST_OTF9_DNSITP_QCH,
|
|
QCH_CON_LHS_AXI_D0_DNS_QCH,
|
|
QCH_CON_LHS_AXI_D1_DNS_QCH,
|
|
QCH_CON_PPMU_D0_DNS_QCH,
|
|
QCH_CON_PPMU_D1_DNS_QCH,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S2,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S1,
|
|
QCH_CON_SYSREG_DNS_QCH,
|
|
QCH_CON_VGEN_LITE_D0_DNS_QCH,
|
|
QCH_CON_VGEN_LITE_D1_DNS_QCH,
|
|
QCH_CON_DPUB_QCH,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH,
|
|
QCH_CON_D_TZPC_DPUB_QCH,
|
|
QCH_CON_LHM_AXI_P_DPUB_QCH,
|
|
QCH_CON_SYSREG_DPUB_QCH,
|
|
QCH_CON_DPUF0_QCH_DMA,
|
|
QCH_CON_DPUF0_QCH_DPP,
|
|
QCH_CON_DPUF0_QCH_C2SERV,
|
|
QCH_CON_DPUF0_CMU_DPUF0_QCH,
|
|
QCH_CON_D_TZPC_DPUF0_QCH,
|
|
QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH,
|
|
QCH_CON_LHM_AXI_P_DPUF0_QCH,
|
|
QCH_CON_LHS_AXI_D0_DPUF0_QCH,
|
|
QCH_CON_LHS_AXI_D1_DPUF0_QCH,
|
|
QCH_CON_PPMU_DPUF0D0_QCH,
|
|
QCH_CON_PPMU_DPUF0D1_QCH,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S1,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S2,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S1,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S2,
|
|
QCH_CON_SYSREG_DPUF0_QCH,
|
|
QCH_CON_DPUF1_QCH_DMA,
|
|
QCH_CON_DPUF1_QCH_DPP,
|
|
QCH_CON_DPUF1_QCH_C2SERV,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH,
|
|
QCH_CON_D_TZPC_DPUF1_QCH,
|
|
QCH_CON_LHM_AXI_P_DPUF1_QCH,
|
|
QCH_CON_LHS_AXI_D0_DPUF1_QCH,
|
|
QCH_CON_LHS_AXI_D1_DPUF1_QCH,
|
|
QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH,
|
|
QCH_CON_PPMU_DPUF1D0_QCH,
|
|
QCH_CON_PPMU_DPUF1D1_QCH,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1,
|
|
QCH_CON_SYSREG_DPUF1_QCH,
|
|
QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH,
|
|
QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE,
|
|
QCH_CON_CLUSTER0_QCH_SCLK,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK,
|
|
QCH_CON_CLUSTER0_QCH_GICCLK,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD,
|
|
QCH_CON_CLUSTER0_QCH_PCLK,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH,
|
|
QCH_CON_CMU_DSU_SHORTSTOP_QCH,
|
|
QCH_CON_DSU_CMU_DSU_QCH,
|
|
QCH_CON_HTU_DSU_QCH,
|
|
QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ACE_D0_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ACE_D1_CLUSTER0_QCH,
|
|
QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T4_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T5_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T6_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T7_CLUSTER0_QCH,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH,
|
|
QCH_CON_ADD_APBIF_G3D_QCH,
|
|
DMYQCH_CON_ADD_G3D_QCH,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D,
|
|
QCH_CON_BUSIF_HPMG3D_QCH,
|
|
QCH_CON_BUSIF_STR_G3D_QCH,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CORE,
|
|
QCH_CON_D_TZPC_G3D_QCH,
|
|
QCH_CON_G3D_CMU_G3D_QCH,
|
|
QCH_CON_GPU_QCH,
|
|
QCH_CON_HTU_G3D_QCH_PCLK,
|
|
QCH_CON_HTU_G3D_QCH_CLK,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH,
|
|
QCH_CON_LHM_AXI_P_INT_G3D_QCH,
|
|
QCH_CON_LHS_AXI_P_INT_G3D_QCH,
|
|
QCH_CON_SYSREG_G3D_QCH,
|
|
QCH_CON_VGEN_LITE_G3D_QCH,
|
|
QCH_CON_DP_LINK_QCH_PCLK,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK,
|
|
QCH_CON_D_TZPC_HSI0_QCH,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH,
|
|
QCH_CON_LHM_AXI_D_AUDHSI0_QCH,
|
|
QCH_CON_LHM_AXI_P_HSI0_QCH,
|
|
QCH_CON_LHS_ACEL_D_HSI0_QCH,
|
|
QCH_CON_LHS_AXI_D_HSI0AUD_QCH,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH,
|
|
QCH_CON_SYSMMU_USB_QCH,
|
|
QCH_CON_SYSREG_HSI0_QCH,
|
|
DMYQCH_CON_USB31DRD_QCH_REF,
|
|
QCH_CON_USB31DRD_QCH_SLV_CTRL,
|
|
QCH_CON_USB31DRD_QCH_SLV_LINK,
|
|
QCH_CON_USB31DRD_QCH_APB,
|
|
QCH_CON_USB31DRD_QCH_PCS,
|
|
QCH_CON_USB31DRD_QCH_DBG,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH,
|
|
QCH_CON_D_TZPC_HSI1_QCH,
|
|
QCH_CON_GPIO_HSI1_QCH,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH,
|
|
QCH_CON_LHM_AXI_P_HSI1_QCH,
|
|
QCH_CON_LHS_ACEL_D_HSI1_QCH,
|
|
QCH_CON_MMC_CARD_QCH,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI,
|
|
QCH_CON_PCIE_GEN2_QCH_APB,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF,
|
|
QCH_CON_PCIE_GEN4_0_QCH_APB,
|
|
QCH_CON_PCIE_GEN4_0_QCH_DBI,
|
|
QCH_CON_PCIE_GEN4_0_QCH_AXI,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PCS_APB,
|
|
DMYQCH_CON_PCIE_GEN4_0_QCH_REF,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PMA_APB,
|
|
QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB,
|
|
QCH_CON_PCIE_IA_GEN2_QCH,
|
|
QCH_CON_PCIE_IA_GEN4_0_QCH,
|
|
QCH_CON_PPMU_HSI1_QCH,
|
|
QCH_CON_SYSMMU_HSI1_QCH,
|
|
QCH_CON_SYSREG_HSI1_QCH,
|
|
QCH_CON_UFS_EMBD_QCH,
|
|
QCH_CON_UFS_EMBD_QCH_FMP,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH,
|
|
QCH_CON_D_TZPC_ITP_QCH,
|
|
QCH_CON_ITP_QCH,
|
|
QCH_CON_ITP_CMU_ITP_QCH,
|
|
QCH_CON_LHM_AST_CTL_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF0_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF1_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF2_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF3_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF4_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF5_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF6_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF7_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF8_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF9_DNSITP_QCH,
|
|
QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH,
|
|
QCH_CON_LHM_AXI_P_ITP_QCH,
|
|
QCH_CON_LHS_AST_CTL_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF0_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF1_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF2_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF3_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF4_ITPDNS_QCH,
|
|
QCH_CON_LHS_AST_OTF_ITPMCSC_QCH,
|
|
QCH_CON_LHS_AXI_P_ITPDNS_QCH,
|
|
QCH_CON_SYSREG_ITP_QCH,
|
|
QCH_CON_D_TZPC_LME_QCH,
|
|
QCH_CON_LHM_AXI_P_LME_QCH,
|
|
QCH_CON_LHS_AXI_D_LME_QCH,
|
|
QCH_CON_LME_QCH,
|
|
QCH_CON_LME_QCH_C2,
|
|
QCH_CON_LME_CMU_LME_QCH,
|
|
QCH_CON_PPMU_LME_QCH,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1,
|
|
QCH_CON_SYSREG_LME_QCH,
|
|
QCH_CON_VGEN_LITE_LME_QCH,
|
|
QCH_CON_ASTC_QCH,
|
|
QCH_CON_D_TZPC_M2M_QCH,
|
|
QCH_CON_JPEG0_QCH,
|
|
QCH_CON_JPEG1_QCH,
|
|
QCH_CON_JSQZ_QCH,
|
|
QCH_CON_LHM_AXI_P_M2M_QCH,
|
|
QCH_CON_LHS_ACEL_D_M2M_QCH,
|
|
QCH_CON_M2M_QCH,
|
|
QCH_CON_M2M_QCH_VOTF,
|
|
QCH_CON_M2M_CMU_M2M_QCH,
|
|
QCH_CON_PPMU_D_M2M_QCH,
|
|
QCH_CON_QE_ASTC_QCH,
|
|
QCH_CON_QE_JPEG0_QCH,
|
|
QCH_CON_QE_JPEG1_QCH,
|
|
QCH_CON_QE_JSQZ_QCH,
|
|
QCH_CON_QE_M2M_QCH,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S2,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S1,
|
|
QCH_CON_SYSREG_M2M_QCH,
|
|
QCH_CON_VGEN_LITE_M2M_QCH,
|
|
QCH_CON_D_TZPC_MCFP0_QCH,
|
|
QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHM_AXI_P_MCFP0_QCH,
|
|
QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHS_AXI_D0_MCFP0_QCH,
|
|
QCH_CON_LHS_AXI_D1_MCFP0_QCH,
|
|
QCH_CON_LHS_AXI_D2_MCFP0_QCH,
|
|
QCH_CON_LHS_AXI_D3_MCFP0_QCH,
|
|
QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH,
|
|
QCH_CON_MCFP0_QCH,
|
|
QCH_CON_MCFP0_CMU_MCFP0_QCH,
|
|
QCH_CON_PPMU_D0_MCFP0_QCH,
|
|
QCH_CON_PPMU_D1_MCFP0_QCH,
|
|
QCH_CON_PPMU_D2_MCFP0_QCH,
|
|
QCH_CON_PPMU_D3_MCFP0_QCH,
|
|
QCH_CON_QE_D0_MCFP0_QCH,
|
|
QCH_CON_QE_D1_MCFP0_QCH,
|
|
QCH_CON_QE_D2_MCFP0_QCH,
|
|
QCH_CON_QE_D3_MCFP0_QCH,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S2,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S1,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S2,
|
|
QCH_CON_SYSREG_MCFP0_QCH,
|
|
QCH_CON_VGEN_LITE_MCFP0_QCH,
|
|
QCH_CON_D_TZPC_MCFP1_QCH,
|
|
QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHM_AST_VO_TAAMCFP1_QCH,
|
|
QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH,
|
|
QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH,
|
|
QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH,
|
|
QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH,
|
|
QCH_CON_LHS_AST_VO_MCFP1TAA_QCH,
|
|
QCH_CON_LHS_AXI_D_MCFP1_QCH,
|
|
QCH_CON_MCFP1_QCH,
|
|
QCH_CON_MCFP1_CMU_MCFP1_QCH,
|
|
QCH_CON_ORBMCH0_QCH_C2,
|
|
QCH_CON_ORBMCH0_QCH,
|
|
QCH_CON_ORBMCH1_QCH,
|
|
QCH_CON_ORBMCH1_QCH_C2,
|
|
QCH_CON_PPMU_ORBMCH_QCH,
|
|
QCH_CON_QE_D0_ORBMCH_QCH,
|
|
QCH_CON_QE_D1_ORBMCH_QCH,
|
|
QCH_CON_QE_D2_ORBMCH_QCH,
|
|
QCH_CON_QE_D3_ORBMCH_QCH,
|
|
QCH_CON_QE_D4_ORBMCH_QCH,
|
|
QCH_CON_QE_D5_ORBMCH_QCH,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S2,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S1,
|
|
QCH_CON_SYSREG_MCFP1_QCH,
|
|
QCH_CON_VGEN_LITE_D0_MCFP1_QCH,
|
|
QCH_CON_VGEN_LITE_D1_MCFP1_QCH,
|
|
DMYQCH_CON_ADD_MCSC_QCH,
|
|
QCH_CON_BUSIF_ADD_MCSC_QCH,
|
|
QCH_CON_BUSIF_HPM_MCSC_QCH,
|
|
QCH_CON_D_TZPC_MCSC_QCH,
|
|
QCH_CON_GDC_QCH,
|
|
QCH_CON_GDC_QCH_C2_M,
|
|
QCH_CON_GDC_QCH_C2_S,
|
|
QCH_CON_LHM_AST_OTF_ITPMCSC_QCH,
|
|
QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH,
|
|
QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH,
|
|
QCH_CON_LHM_AXI_P_MCSC_QCH,
|
|
QCH_CON_LHS_ACEL_D0_MCSC_QCH,
|
|
QCH_CON_LHS_AXI_D1_MCSC_QCH,
|
|
QCH_CON_LHS_AXI_D2_MCSC_QCH,
|
|
QCH_CON_MCSC_QCH,
|
|
QCH_CON_MCSC_QCH_C2_W,
|
|
QCH_CON_MCSC_QCH_C2_R,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH,
|
|
QCH_CON_PPMU_D0_MCSC_QCH,
|
|
QCH_CON_PPMU_D1_MCSC_QCH,
|
|
QCH_CON_PPMU_D2_MCSC_QCH,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2,
|
|
QCH_CON_SYSREG_MCSC_QCH,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH,
|
|
QCH_CON_D_TZPC_MFC0_QCH,
|
|
QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH,
|
|
QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH,
|
|
QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH,
|
|
QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH,
|
|
QCH_CON_LHM_AXI_P_MFC0_QCH,
|
|
QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH,
|
|
QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH,
|
|
QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH,
|
|
QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH,
|
|
QCH_CON_LHS_AXI_D0_MFC0_QCH,
|
|
QCH_CON_LHS_AXI_D1_MFC0_QCH,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI,
|
|
QCH_CON_MFC0_QCH,
|
|
QCH_CON_MFC0_QCH_VOTF,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH,
|
|
QCH_CON_PPMU_MFC0D0_QCH,
|
|
QCH_CON_PPMU_MFC0D1_QCH,
|
|
QCH_CON_PPMU_WFD_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2,
|
|
QCH_CON_SYSREG_MFC0_QCH,
|
|
QCH_CON_VGEN_MFC0_QCH,
|
|
QCH_CON_WFD_QCH,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH,
|
|
QCH_CON_D_TZPC_MFC1_QCH,
|
|
QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH,
|
|
QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH,
|
|
QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH,
|
|
QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH,
|
|
QCH_CON_LHM_AXI_P_MFC1_QCH,
|
|
QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH,
|
|
QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH,
|
|
QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH,
|
|
QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH,
|
|
QCH_CON_LHS_AXI_D0_MFC1_QCH,
|
|
QCH_CON_LHS_AXI_D1_MFC1_QCH,
|
|
QCH_CON_MFC1_QCH,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH,
|
|
QCH_CON_PPMU_MFC1D0_QCH,
|
|
QCH_CON_PPMU_MFC1D1_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1,
|
|
QCH_CON_SYSREG_MFC1_QCH,
|
|
QCH_CON_VGEN_MFC1_QCH,
|
|
QCH_CON_APBBR_DDRPHY_QCH,
|
|
QCH_CON_APBBR_DMC_QCH,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH,
|
|
QCH_CON_DMC_QCH,
|
|
QCH_CON_D_TZPC_MIF_QCH,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH,
|
|
QCH_CON_MIF_CMU_MIF_QCH,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH,
|
|
QCH_CON_SYSREG_MIF_QCH,
|
|
QCH_CON_D_TZPC_NPU_QCH,
|
|
QCH_CON_IP_NPUCORE_QCH_PCLK,
|
|
QCH_CON_IP_NPUCORE_QCH_ACLK,
|
|
QCH_CON_LHM_AXI_D0_NPU_QCH,
|
|
QCH_CON_LHM_AXI_D1_NPU_QCH,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU_QCH,
|
|
QCH_CON_LHM_AXI_P_NPU_QCH,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU_QCH,
|
|
QCH_CON_NPU_CMU_NPU_QCH,
|
|
QCH_CON_SYSREG_NPU_QCH,
|
|
QCH_CON_D_TZPC_NPU01_QCH,
|
|
QCH_CON_IP_NPU01CORE_QCH_PCLK,
|
|
QCH_CON_IP_NPU01CORE_QCH_ACLK,
|
|
QCH_CON_LHM_AXI_D0_NPU01_QCH,
|
|
QCH_CON_LHM_AXI_D1_NPU01_QCH,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH,
|
|
QCH_CON_LHM_AXI_P_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU01_QCH,
|
|
QCH_CON_NPU01_CMU_NPU_QCH,
|
|
QCH_CON_SYSREG_NPU01_QCH,
|
|
QCH_CON_D_TZPC_NPU10_QCH,
|
|
QCH_CON_IP_NPU10CORE_QCH_PCLK,
|
|
QCH_CON_IP_NPU10CORE_QCH_ACLK,
|
|
QCH_CON_LHM_AXI_D0_NPU10_QCH,
|
|
QCH_CON_LHM_AXI_D1_NPU10_QCH,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH,
|
|
QCH_CON_LHM_AXI_P_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU10_QCH,
|
|
QCH_CON_NPU10_CMU_NPU_QCH,
|
|
QCH_CON_SYSREG_NPU10_QCH,
|
|
DMYQCH_CON_ADD_NPUS_QCH,
|
|
DMYQCH_CON_ADM_DAP_NPUS_QCH,
|
|
QCH_CON_BUSIF_ADD_NPUS_QCH,
|
|
QCH_CON_BUSIF_HPM_NPUS_QCH,
|
|
QCH_CON_D_TZPC_NPUS_QCH,
|
|
QCH_CON_HTU_NPUS_QCH_PCLK,
|
|
QCH_CON_HTU_NPUS_QCH_CLK,
|
|
QCH_CON_IP_NPUS_QCH,
|
|
QCH_CON_IP_NPUS_QCH_C2A0,
|
|
QCH_CON_IP_NPUS_QCH_C2A1,
|
|
QCH_CON_IP_NPUS_QCH_CPU,
|
|
QCH_CON_IP_NPUS_QCH_NEON,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU00_QCH,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU01_QCH,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU10_QCH,
|
|
QCH_CON_LHM_AXI_P_INT_NPUS_QCH,
|
|
QCH_CON_LHM_AXI_P_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_D0_NPU00_QCH,
|
|
QCH_CON_LHS_AXI_D0_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_D0_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_D0_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_D1_NPU00_QCH,
|
|
QCH_CON_LHS_AXI_D1_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_D1_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_D1_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_D2_NPUS_QCH,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH,
|
|
QCH_CON_LHS_AXI_P_INT_NPUS_QCH,
|
|
QCH_CON_NPUS_CMU_NPUS_QCH,
|
|
QCH_CON_PPMU_NPUS_0_QCH,
|
|
QCH_CON_PPMU_NPUS_1_QCH,
|
|
QCH_CON_PPMU_NPUS_2_QCH,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S2,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S1,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S2,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S1,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S2,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S1,
|
|
QCH_CON_SYSREG_NPUS_QCH,
|
|
QCH_CON_VGEN_LITE_NPUS_QCH,
|
|
QCH_CON_D_TZPC_PERIC0_QCH,
|
|
QCH_CON_GPIO_PERIC0_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH,
|
|
QCH_CON_PERIC0_TOP0_QCH_UART_DBG,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_USI,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_I2C,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_USI,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_I2C,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_USI,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_I2C,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_USI,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_I2C,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_USI,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_I2C,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI05_USI,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI05_I2C,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_USI,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_I2C,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_USI,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_I2C,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_USI,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_I2C,
|
|
QCH_CON_PERIC0_TOP1_QCH_PWM,
|
|
QCH_CON_SYSREG_PERIC0_QCH,
|
|
QCH_CON_D_TZPC_PERIC1_QCH,
|
|
QCH_CON_GPIO_PERIC1_QCH,
|
|
QCH_CON_LHM_AXI_P_CSISPERIC1_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH,
|
|
QCH_CON_PERIC1_TOP0_QCH_UART_BT,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_USI,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_I2C,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_USI,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_I2C,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_USI,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_I2C,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_USI,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_I2C,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_USI,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_I2C,
|
|
QCH_CON_SYSREG_PERIC1_QCH,
|
|
QCH_CON_USI16_I3C_QCH_P,
|
|
DMYQCH_CON_USI16_I3C_QCH_S,
|
|
QCH_CON_USI17_I3C_QCH_P,
|
|
DMYQCH_CON_USI17_I3C_QCH_S,
|
|
QCH_CON_D_TZPC_PERIC2_QCH,
|
|
QCH_CON_GPIO_PERIC2_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIC2_QCH,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_USI,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_USI,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_USI,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_I2C,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_I2C,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_I2C,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_USI,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_I2C,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_USI,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_I2C,
|
|
QCH_CON_SYSREG_PERIC2_QCH,
|
|
QCH_CON_BC_EMUL_QCH,
|
|
QCH_CON_D_TZPC_PERIS_QCH,
|
|
QCH_CON_GIC_QCH,
|
|
QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH,
|
|
QCH_CON_LHM_AXI_P_PERISGIC_QCH,
|
|
QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH,
|
|
QCH_CON_MCT_QCH,
|
|
DMYQCH_CON_OTP_QCH,
|
|
QCH_CON_OTP_CON_BIRA_QCH,
|
|
QCH_CON_OTP_CON_BISR_QCH,
|
|
QCH_CON_OTP_CON_TOP_QCH,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH,
|
|
QCH_CON_SYSREG_PERIS_QCH,
|
|
QCH_CON_TMU_SUB_QCH,
|
|
QCH_CON_TMU_TOP_QCH,
|
|
QCH_CON_WDT0_QCH,
|
|
QCH_CON_WDT1_QCH,
|
|
DMYQCH_CON_BIS_S2D_QCH,
|
|
QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH,
|
|
QCH_CON_S2D_CMU_S2D_QCH,
|
|
DMYQCH_CON_ADM_DAP_SSS_QCH,
|
|
QCH_CON_BAAW_SSS_QCH,
|
|
QCH_CON_D_TZPC_SSP_QCH,
|
|
QCH_CON_LHM_AXI_D_SSPCORE_QCH,
|
|
QCH_CON_LHM_AXI_P_SSP_QCH,
|
|
QCH_CON_LHS_ACEL_D_SSP_QCH,
|
|
QCH_CON_PPMU_SSP_QCH,
|
|
QCH_CON_QE_RTIC_QCH,
|
|
QCH_CON_QE_SSPCORE_QCH,
|
|
QCH_CON_QE_SSS_QCH,
|
|
QCH_CON_RTIC_QCH,
|
|
QCH_CON_SSP_CMU_SSP_QCH,
|
|
QCH_CON_SSS_QCH,
|
|
QCH_CON_SWEEPER_D_SSP_QCH,
|
|
QCH_CON_SYSMMU_RTIC_QCH,
|
|
QCH_CON_SYSREG_SSPCTRL_QCH,
|
|
QCH_CON_VGEN_LITE_RTIC_QCH,
|
|
QCH_CON_USS_SSPCORE_QCH,
|
|
DMYQCH_CON_ADD_TAA_QCH,
|
|
QCH_CON_BUSIF_ADD_TAA_QCH,
|
|
QCH_CON_BUSIF_HPM_TAA_QCH,
|
|
QCH_CON_D_TZPC_TAA_QCH,
|
|
QCH_CON_LHM_AST_OTF0_CSISTAA_QCH,
|
|
QCH_CON_LHM_AST_OTF1_CSISTAA_QCH,
|
|
QCH_CON_LHM_AST_OTF2_CSISTAA_QCH,
|
|
QCH_CON_LHM_AST_OTF3_CSISTAA_QCH,
|
|
QCH_CON_LHM_AST_VO_MCFP1TAA_QCH,
|
|
QCH_CON_LHM_AXI_P_TAA_QCH,
|
|
QCH_CON_LHS_AST_OTF_TAADNS_QCH,
|
|
QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_VO_TAAMCFP1_QCH,
|
|
QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH,
|
|
QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH,
|
|
QCH_CON_LHS_AXI_D_TAA_QCH,
|
|
QCH_CON_PPMU_TAA_QCH,
|
|
QCH_CON_SIPU_TAA_QCH,
|
|
QCH_CON_SIPU_TAA_QCH_C2_STAT,
|
|
QCH_CON_SIPU_TAA_QCH_C2_YDS,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S1,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S2,
|
|
QCH_CON_SYSREG_TAA_QCH,
|
|
QCH_CON_TAA_CMU_TAA_QCH,
|
|
QCH_CON_VGEN_LITE_TAA0_QCH,
|
|
QCH_CON_VGEN_LITE_TAA1_QCH,
|
|
DMYQCH_CON_ADD_VPC_QCH,
|
|
DMYQCH_CON_ADM_DAP_VPC_QCH,
|
|
QCH_CON_BUSIF_ADD_VPC_QCH,
|
|
QCH_CON_BUSIF_HPM_VPC_QCH,
|
|
QCH_CON_D_TZPC_VPC_QCH,
|
|
QCH_CON_HTU_VPC_QCH_PCLK,
|
|
QCH_CON_HTU_VPC_QCH_CLK,
|
|
QCH_CON_IP_VPC_QCH,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH,
|
|
QCH_CON_LHM_AXI_P_VPC_QCH,
|
|
QCH_CON_LHM_AXI_P_VPC_800_QCH,
|
|
QCH_CON_LHS_ACEL_D0_VPC_QCH,
|
|
QCH_CON_LHS_ACEL_D1_VPC_QCH,
|
|
QCH_CON_LHS_ACEL_D2_VPC_QCH,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH,
|
|
QCH_CON_LHS_AXI_P_VPCVPD0_QCH,
|
|
QCH_CON_LHS_AXI_P_VPCVPD1_QCH,
|
|
QCH_CON_LHS_AXI_P_VPC_200_QCH,
|
|
QCH_CON_PPMU_VPC0_QCH,
|
|
QCH_CON_PPMU_VPC1_QCH,
|
|
QCH_CON_PPMU_VPC2_QCH,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S1,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S2,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S1,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S2,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S1,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S2,
|
|
QCH_CON_SYSREG_VPC_QCH,
|
|
QCH_CON_VGEN_LITE_VPC_QCH,
|
|
QCH_CON_VPC_CMU_VPC_QCH,
|
|
QCH_CON_D_TZPC_VPD_QCH,
|
|
QCH_CON_IP_VPD_QCH,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH,
|
|
QCH_CON_LHM_AXI_P_VPCVPD_QCH,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH,
|
|
QCH_CON_SYSREG_VPD_QCH,
|
|
QCH_CON_VPD_CMU_VPD_QCH,
|
|
QCH_CON_BAAW_C_VTS_QCH,
|
|
QCH_CON_BAAW_D_VTS_QCH,
|
|
QCH_CON_BUSIF_HPM_VTS_QCH,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU,
|
|
QCH_CON_DMAILBOX_TEST_QCH_ACLK,
|
|
QCH_CON_DMAILBOX_TEST_QCH_PCLK,
|
|
DMYQCH_CON_DMAILBOX_TEST_QCH_LIF,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB2_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB3_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB4_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB5_QCH_PCLK,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC,
|
|
QCH_CON_D_TZPC_VTS_QCH,
|
|
QCH_CON_GPIO_VTS_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC2_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC3_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC4_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC5_QCH,
|
|
QCH_CON_HWACG_SYS_SERIAL_LIF_QCH,
|
|
QCH_CON_LHM_AXI_D_AUDVTS_QCH,
|
|
QCH_CON_LHM_AXI_LP_VTS_QCH,
|
|
QCH_CON_LHM_AXI_P_VTS_QCH,
|
|
QCH_CON_LHS_AXI_C_VTS_QCH,
|
|
QCH_CON_LHS_AXI_D_VTS_QCH,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH,
|
|
QCH_CON_MAILBOX_APM_VTS1_QCH,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH,
|
|
QCH_CON_PDMA_VTS_QCH,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_LIF,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_HCLK,
|
|
QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF,
|
|
QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2,
|
|
QCH_CON_SWEEPER_D_VTS_QCH,
|
|
QCH_CON_SYSREG_VTS_QCH,
|
|
QCH_CON_TIMER_QCH,
|
|
QCH_CON_TIMER1_QCH,
|
|
QCH_CON_TIMER2_QCH,
|
|
QCH_CON_VGEN_LITE_QCH,
|
|
QCH_CON_VTS_CMU_VTS_QCH,
|
|
QCH_CON_WDT_VTS_QCH,
|
|
QCH_CON_D_TZPC_YUVPP_QCH,
|
|
QCH_CON_FRC_MC_QCH,
|
|
QCH_CON_LHM_AXI_P_YUVPP_QCH,
|
|
QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH,
|
|
QCH_CON_LHS_AXI_D_YUVPP_QCH,
|
|
QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH,
|
|
QCH_CON_PPMU_YUVPP_QCH,
|
|
QCH_CON_QE_D0_YUVPP_QCH,
|
|
QCH_CON_QE_D10_YUVPP_QCH,
|
|
QCH_CON_QE_D11_YUVPP_QCH,
|
|
QCH_CON_QE_D1_YUVPP_QCH,
|
|
QCH_CON_QE_D2_YUVPP_QCH,
|
|
QCH_CON_QE_D3_YUVPP_QCH,
|
|
QCH_CON_QE_D4_YUVPP_QCH,
|
|
QCH_CON_QE_D5_YUVPP_QCH,
|
|
QCH_CON_QE_D6_YUVPP_QCH,
|
|
QCH_CON_QE_D7_YUVPP_QCH,
|
|
QCH_CON_QE_D8_YUVPP_QCH,
|
|
QCH_CON_QE_D9_YUVPP_QCH,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S1,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S2,
|
|
QCH_CON_SYSREG_YUVPP_QCH,
|
|
QCH_CON_VGEN_LITE_YUVPP0_QCH,
|
|
QCH_CON_VGEN_LITE_YUVPP1_QCH,
|
|
QCH_CON_VGEN_LITE_YUVPP2_QCH,
|
|
QCH_CON_YUVPP_CMU_YUVPP_QCH,
|
|
QCH_CON_YUVPP_TOP_QCH,
|
|
QCH_CON_YUVPP_TOP_QCH_C2COM,
|
|
ALIVE_CMU_ALIVE_CONTROLLER_OPTION,
|
|
AUD_CMU_AUD_CONTROLLER_OPTION,
|
|
BUS0_CMU_BUS0_CONTROLLER_OPTION,
|
|
BUS1_CMU_BUS1_CONTROLLER_OPTION,
|
|
BUS2_CMU_BUS2_CONTROLLER_OPTION,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION,
|
|
CORE_CMU_CORE_CONTROLLER_OPTION,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION,
|
|
DNS_CMU_DNS_CONTROLLER_OPTION,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION,
|
|
DPUF0_CMU_DPUF0_CONTROLLER_OPTION,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION,
|
|
G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION,
|
|
ITP_CMU_ITP_CONTROLLER_OPTION,
|
|
LME_CMU_LME_CONTROLLER_OPTION,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION,
|
|
MCFP0_CMU_MCFP0_CONTROLLER_OPTION,
|
|
MCFP1_CMU_MCFP1_CONTROLLER_OPTION,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION,
|
|
NPU_CMU_NPU_CONTROLLER_OPTION,
|
|
NPU01_CMU_NPU_CONTROLLER_OPTION,
|
|
NPU10_CMU_NPU_CONTROLLER_OPTION,
|
|
NPUS_CMU_NPUS_CONTROLLER_OPTION,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION,
|
|
SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION,
|
|
TAA_CMU_TAA_CONTROLLER_OPTION,
|
|
VPC_CMU_VPC_CONTROLLER_OPTION,
|
|
VPD_CMU_VPD_CONTROLLER_OPTION,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION,
|
|
YUVPP_CMU_YUVPP_CONTROLLER_OPTION,
|
|
end_of_sfr,
|
|
num_of_sfr = end_of_sfr - SFR_TYPE,
|
|
};
|
|
|
|
enum sfr_access_id {
|
|
OSC_LOCKTIME_RCO_400_OSC_LOCK_TIME = SFR_ACCESS_TYPE,
|
|
OSC_CON0_RCO_400_MUX_BUSY,
|
|
OSC_CON0_RCO_400_MUX_SEL,
|
|
OSC_CON1_RCO_400_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_LOCKTIME_PLL_AUD0_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_AUD0_ENABLE,
|
|
PLL_CON3_PLL_AUD0_STABLE,
|
|
PLL_CON3_PLL_AUD0_DIV_P,
|
|
PLL_CON3_PLL_AUD0_DIV_M,
|
|
PLL_CON3_PLL_AUD0_DIV_S,
|
|
PLL_CON8_PLL_AUD0_DIV_F,
|
|
PLL_LOCKTIME_PLL_AUD1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_AUD1_ENABLE,
|
|
PLL_CON3_PLL_AUD1_STABLE,
|
|
PLL_CON3_PLL_AUD1_DIV_P,
|
|
PLL_CON3_PLL_AUD1_DIV_M,
|
|
PLL_CON3_PLL_AUD1_DIV_S,
|
|
PLL_CON8_PLL_AUD1_DIV_F,
|
|
PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_G3D_ENABLE,
|
|
PLL_CON3_PLL_G3D_STABLE,
|
|
PLL_CON3_PLL_G3D_DIV_P,
|
|
PLL_CON3_PLL_G3D_DIV_M,
|
|
PLL_CON3_PLL_G3D_DIV_S,
|
|
PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MMC_ENABLE,
|
|
PLL_CON3_PLL_MMC_STABLE,
|
|
PLL_CON3_PLL_MMC_DIV_P,
|
|
PLL_CON3_PLL_MMC_DIV_M,
|
|
PLL_CON3_PLL_MMC_DIV_S,
|
|
PLL_CON8_PLL_MMC_DIV_F,
|
|
PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED0_ENABLE,
|
|
PLL_CON3_PLL_SHARED0_STABLE,
|
|
PLL_CON3_PLL_SHARED0_DIV_P,
|
|
PLL_CON3_PLL_SHARED0_DIV_M,
|
|
PLL_CON3_PLL_SHARED0_DIV_S,
|
|
PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED1_ENABLE,
|
|
PLL_CON3_PLL_SHARED1_STABLE,
|
|
PLL_CON3_PLL_SHARED1_DIV_P,
|
|
PLL_CON3_PLL_SHARED1_DIV_M,
|
|
PLL_CON3_PLL_SHARED1_DIV_S,
|
|
PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED2_ENABLE,
|
|
PLL_CON3_PLL_SHARED2_STABLE,
|
|
PLL_CON3_PLL_SHARED2_DIV_P,
|
|
PLL_CON3_PLL_SHARED2_DIV_M,
|
|
PLL_CON3_PLL_SHARED2_DIV_S,
|
|
PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED3_ENABLE,
|
|
PLL_CON3_PLL_SHARED3_STABLE,
|
|
PLL_CON3_PLL_SHARED3_DIV_P,
|
|
PLL_CON3_PLL_SHARED3_DIV_M,
|
|
PLL_CON3_PLL_SHARED3_DIV_S,
|
|
PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED4_ENABLE,
|
|
PLL_CON3_PLL_SHARED4_STABLE,
|
|
PLL_CON3_PLL_SHARED4_DIV_P,
|
|
PLL_CON3_PLL_SHARED4_DIV_M,
|
|
PLL_CON3_PLL_SHARED4_DIV_S,
|
|
PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_SHARED_MIF_ENABLE,
|
|
PLL_CON3_PLL_SHARED_MIF_STABLE,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_P,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_M,
|
|
PLL_CON3_PLL_SHARED_MIF_DIV_S,
|
|
PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL0_ENABLE,
|
|
PLL_CON3_PLL_CPUCL0_STABLE,
|
|
PLL_CON3_PLL_CPUCL0_DIV_P,
|
|
PLL_CON3_PLL_CPUCL0_DIV_M,
|
|
PLL_CON3_PLL_CPUCL0_DIV_S,
|
|
PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL1_ENABLE,
|
|
PLL_CON3_PLL_CPUCL1_STABLE,
|
|
PLL_CON3_PLL_CPUCL1_DIV_P,
|
|
PLL_CON3_PLL_CPUCL1_DIV_M,
|
|
PLL_CON3_PLL_CPUCL1_DIV_S,
|
|
PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_CPUCL2_ENABLE,
|
|
PLL_CON3_PLL_CPUCL2_STABLE,
|
|
PLL_CON3_PLL_CPUCL2_DIV_P,
|
|
PLL_CON3_PLL_CPUCL2_DIV_M,
|
|
PLL_CON3_PLL_CPUCL2_DIV_S,
|
|
PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_DSU_ENABLE,
|
|
PLL_CON3_PLL_DSU_STABLE,
|
|
PLL_CON3_PLL_DSU_DIV_P,
|
|
PLL_CON3_PLL_DSU_DIV_M,
|
|
PLL_CON3_PLL_DSU_DIV_S,
|
|
PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_MAIN_ENABLE,
|
|
PLL_CON3_PLL_MIF_MAIN_STABLE,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_P,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_M,
|
|
PLL_CON3_PLL_MIF_MAIN_DIV_S,
|
|
PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_SUB_ENABLE,
|
|
PLL_CON3_PLL_MIF_SUB_STABLE,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_P,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_M,
|
|
PLL_CON3_PLL_MIF_SUB_DIV_S,
|
|
PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME,
|
|
PLL_CON3_PLL_MIF_S2D_ENABLE,
|
|
PLL_CON3_PLL_MIF_S2D_STABLE,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_P,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_M,
|
|
PLL_CON3_PLL_MIF_S2D_DIV_S,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CNT_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CNT_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_BUS0_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_BUS0_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_BUS0_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_BUS1_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_BUS1_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_BUS1_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_BUS2_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_BUS2_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_BUS2_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_SELECT,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_BUSY,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPUF0_BUS_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DPUF0_BUS_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPUB_BUS_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DPUB_BUS_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_UCPU_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_UCPU_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_LCPU_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_LCPU_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY,
|
|
CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_G3D_SHADER_SELECT,
|
|
CLK_CON_MUX_CLKCMU_G3D_SHADER_BUSY,
|
|
CLK_CON_MUX_CLKCMU_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPUF1_BUS_SELECT,
|
|
CLK_CON_MUX_CLKCMU_DPUF1_BUS_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CORE_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CORE_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_SELECT,
|
|
CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_BUSY,
|
|
CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_PLL_DSU_DELAY_SELECT,
|
|
CLK_CON_MUX_MUX_PLL_DSU_DELAY_BUSY,
|
|
CLK_CON_MUX_MUX_PLL_DSU_DELAY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY,
|
|
PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY,
|
|
PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DNS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLK_USB20PHY_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLK_USB20PHY_USER_BUSY,
|
|
PLL_CON1_MUX_CLK_USB20PHY_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_ITP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_LME_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_LME_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_LME_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_M2M_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL,
|
|
PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY,
|
|
PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL,
|
|
PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY,
|
|
PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_SSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_VPC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_VPD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_BUSY,
|
|
PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_BUSY,
|
|
PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLK_RCO_VTS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLK_RCO_VTS_USER_BUSY,
|
|
PLL_CON1_MUX_CLK_RCO_VTS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_MUX_SEL,
|
|
PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_BUSY,
|
|
PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMGP_ADC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMGP_ADC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKAUD_VTS_DMIC0_DIVRATIO,
|
|
CLK_CON_DIV_CLKAUD_VTS_DMIC0_BUSY,
|
|
CLK_CON_DIV_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKAUD_HSI0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKAUD_HSI0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_DIVRATIO,
|
|
CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_BUSY,
|
|
CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BUS0_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_BUS0_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BUS0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BUS2_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_BUS2_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BUS2_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VPD_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_VPD_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ITP_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_ITP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HPM_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HPM_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_NPU_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_NPU_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_CSIS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_CSIS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MCFP0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MCFP0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DNS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_DNS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_SSP_SSPCORE_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_SSP_SSPCORE_BUSY,
|
|
CLK_CON_DIV_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_M2M_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_M2M_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS1_SBIC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_BUS1_SBIC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_LME_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_LME_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VPC_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_VPC_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_BUS0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS2_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_BUS2_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CSIS_PDP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CSIS_PDP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CP_SHARED0_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CP_SHARED0_CLK_BUSY,
|
|
CLK_CON_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_BUSY,
|
|
CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CP_SHARED2_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CP_SHARED2_CLK_BUSY,
|
|
CLK_CON_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CP_HISPEEDY_CLK_DIVRATIO,
|
|
CLK_CON_DIV_CP_HISPEEDY_CLK_BUSY,
|
|
CLK_CON_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_SSP_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_SSP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_FRC_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_FRC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G3D_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_G3D_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUB_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIS_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_SSP_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_SSP_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_SSP_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_CSIS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_PDP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_SHADER_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_LME_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_GDC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_MFC0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_MFC1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU01_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPU10_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_FRC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_VTS_DMIC_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_VTS_DMIC_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKAUD_VTS_DMIC1_CG_VAL,
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CLK_CON_GAT_CLKAUD_VTS_DMIC1_MANUAL,
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CLK_CON_GAT_CLKAUD_VTS_DMIC1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_CG_VAL,
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CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_MANUAL,
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CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_CG_VAL,
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|
CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_CG_VAL,
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|
CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CP_UCPU_CLK_CG_VAL,
|
|
CLK_CON_GAT_CP_UCPU_CLK_MANUAL,
|
|
CLK_CON_GAT_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CP_LCPU_CLK_CG_VAL,
|
|
CLK_CON_GAT_CP_LCPU_CLK_MANUAL,
|
|
CLK_CON_GAT_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL,
|
|
CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
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CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL,
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CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL,
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CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
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CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL,
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CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL,
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CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_MANUAL,
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|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_TAA_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLK_VPC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_RTC_QCH_ENABLE,
|
|
QCH_CON_APBIF_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_ENABLE,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLKMON_QCH_ENABLE,
|
|
QCH_CON_CLKMON_QCH_CLOCK_REQ,
|
|
QCH_CON_CLKMON_QCH_EXPIRE_VAL,
|
|
QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DBGCORE_UART_QCH_ENABLE,
|
|
QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ,
|
|
QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL,
|
|
QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_ENABLE,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_CLOCK_REQ,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_EXPIRE_VAL,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_ENABLE,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_CLOCK_REQ,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_EXPIRE_VAL,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_ENABLE,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_CLOCK_REQ,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_EXPIRE_VAL,
|
|
QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DTZPC_ALIVE_QCH_ENABLE,
|
|
QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_DTZPC_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_ALIVE_QCH_ENABLE,
|
|
QCH_CON_GPIO_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL,
|
|
QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_PMIC_QCH_P_ENABLE,
|
|
QCH_CON_I3C_PMIC_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C_PMIC_QCH_P_EXPIRE_VAL,
|
|
QCH_CON_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_I3C_PMIC_QCH_S_ENABLE,
|
|
DMYQCH_CON_I3C_PMIC_QCH_S_CLOCK_REQ,
|
|
DMYQCH_CON_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_QCH_ENABLE,
|
|
QCH_CON_INTMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_C_MODEM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_C_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_C_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_C_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_C_VTS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_C_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_C_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_C_CMGP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_C_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_C_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_LP_VTS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_LP_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_LP_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PEM_QCH_ENABLE,
|
|
QCH_CON_PEM_QCH_CLOCK_REQ,
|
|
QCH_CON_PEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_INTR_GEN_QCH_ENABLE,
|
|
QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ,
|
|
QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL,
|
|
QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ROM_CRC32_HOST_QCH_ENABLE,
|
|
QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ,
|
|
QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE,
|
|
QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ,
|
|
QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL,
|
|
QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE,
|
|
QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL,
|
|
QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ALIVE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_ALIVE_QCH_ENABLE,
|
|
QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_ACLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK0_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK1_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK2_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK3_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ABOX_QCH_CPU_ENABLE,
|
|
DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ,
|
|
DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK4_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CNT_ENABLE,
|
|
QCH_CON_ABOX_QCH_CNT_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK5_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_SCLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_SCLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_SCLK_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_SCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK6_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_XCLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_XCLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_XCLK_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_XCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_C2A0_ENABLE,
|
|
QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_C2A1_ENABLE,
|
|
QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_AUD_CMU_AUD_QCH_ENABLE,
|
|
QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_D_AUDVTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_D_AUDVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_D_AUDVTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_AUD_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_HSI0AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_HSI0AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_HSI0AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_AUDHSI0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_AUDHSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_AUDHSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_AUDVTS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_AUDVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_AUDVTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD0_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD1_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD2_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AUD3_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AUD3_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_AUD_QCH_ENABLE,
|
|
QCH_CON_PPMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SMMU_AUD_QCH_S1_ENABLE,
|
|
QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SMMU_AUD_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SMMU_AUD_QCH_S2_ENABLE,
|
|
QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SMMU_AUD_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_AUD_QCH_ENABLE,
|
|
QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_AUD_QCH_ENABLE,
|
|
QCH_CON_TREX_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_AUD_QCH_ENABLE,
|
|
QCH_CON_WDT_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE,
|
|
QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ,
|
|
QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL,
|
|
QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_VPC_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_P_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUS0_CMU_BUS0_QCH_ENABLE,
|
|
QCH_CON_BUS0_CMU_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUS0_CMU_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUS0_CMU_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CACHEAID_BUS0_QCH_ENABLE,
|
|
QCH_CON_CACHEAID_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_CACHEAID_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_CACHEAID_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_BUS0_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_BUS0_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_BUS0_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_BUS0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D0_VPC_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D0_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D0_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D1_VPC_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D1_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D1_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D2_VPC_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D2_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D2_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D2_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D2_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D2_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIC2_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERISGIC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERISGIC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERISGIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_VPC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BUS0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D0_BUS0_QCH_ENABLE,
|
|
QCH_CON_TREX_D0_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D0_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D0_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D1_BUS0_QCH_ENABLE,
|
|
QCH_CON_TREX_D1_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D1_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D1_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_BUS0_QCH_ENABLE,
|
|
QCH_CON_TREX_P_BUS0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_BUS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P_BUS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_VTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_P_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_BUS1_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_BUS1_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_BUS1_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DIT_QCH_ENABLE,
|
|
QCH_CON_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_DIT_QCH_EXPIRE_VAL,
|
|
QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_BUS1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_HSI0_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_SBIC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_SBIC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_SBIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_SBIC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_SBIC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_SBIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DPUB_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_HSI0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_QCH_ENABLE,
|
|
QCH_CON_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDMA_QCH_ENABLE,
|
|
QCH_CON_QE_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_SPDMA_QCH_ENABLE,
|
|
QCH_CON_QE_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_SPDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SBIC_QCH_ENABLE,
|
|
QCH_CON_SBIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SBIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPDMA_QCH_ENABLE,
|
|
QCH_CON_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SPDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_ACVPS_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_ACVPS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_ACVPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_S2_ACVPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_S2_SBIC_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_S2_SBIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_S2_SBIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_S2_SBIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BUS1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_BUS1_QCH_ENABLE,
|
|
QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_BUS1_QCH_ENABLE,
|
|
QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_RB_BUS1_QCH_ENABLE,
|
|
QCH_CON_TREX_RB_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_RB_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_RB_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_BUS1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_PDMA_QCH_ENABLE,
|
|
QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUS2_CMU_BUS2_QCH_ENABLE,
|
|
QCH_CON_BUS2_CMU_BUS2_QCH_CLOCK_REQ,
|
|
QCH_CON_BUS2_CMU_BUS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUS2_CMU_BUS2_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_BUS2_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_BUS2_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_BUS2_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_BUS2_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_BUS2_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_BUS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_BUS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D0_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_HSI1_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_M2M_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_SSP_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_DNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_DNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D2_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D2_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D2_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D2_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D2_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D2_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D2_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D3_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D3_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D3_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D3_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D3_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D3_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_LME_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_TAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_YUVPP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_HSI1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_ITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_LME_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_M2M_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_SSP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_TAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_YUVPP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BUS2_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BUS2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BUS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_BUS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_BUS2_QCH_ENABLE,
|
|
QCH_CON_TREX_D_BUS2_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_BUS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D_BUS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_BUS2_QCH_ENABLE,
|
|
QCH_CON_TREX_P_BUS2_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_BUS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P_BUS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ADC_CMGP_QCH_S0_ENABLE,
|
|
QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ,
|
|
QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL,
|
|
QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ADC_CMGP_QCH_S1_ENABLE,
|
|
QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADC_CMGP_QCH_OSC_ENABLE,
|
|
DMYQCH_CON_ADC_CMGP_QCH_OSC_CLOCK_REQ,
|
|
DMYQCH_CON_ADC_CMGP_QCH_OSC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CMGP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_CMGP_QCH_ENABLE,
|
|
QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP0_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP1_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP2_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP3_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I3C_CMGP_QCH_P_ENABLE,
|
|
QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ,
|
|
QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL,
|
|
QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_I3C_CMGP_QCH_S_ENABLE,
|
|
DMYQCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ,
|
|
DMYQCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_C_CMGP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_C_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_C_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP0_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP0_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP1_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP1_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP2_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP2_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP3_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP3_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_CP_QCH_ENABLE,
|
|
QCH_CON_BAAW_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BDU_QCH_ENABLE,
|
|
QCH_CON_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CCI_QCH_ENABLE,
|
|
DMYQCH_CON_CCI_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CORE_CMU_CORE_QCH_ENABLE,
|
|
QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CORE_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D2_MODEM_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D2_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D2_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPCFW_G3D_QCH_ENABLE,
|
|
QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_PPC_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_CPUCL0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_PPC_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_CPUCL0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_G3D0_QCH_ENABLE,
|
|
QCH_CON_PPC_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_G3D1_QCH_ENABLE,
|
|
QCH_CON_PPC_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_G3D2_QCH_ENABLE,
|
|
QCH_CON_PPC_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_G3D3_QCH_ENABLE,
|
|
QCH_CON_PPC_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_IRPS0_QCH_ENABLE,
|
|
QCH_CON_PPC_IRPS0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_IRPS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_IRPS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_IRPS1_QCH_ENABLE,
|
|
QCH_CON_PPC_IRPS1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_IRPS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_IRPS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_IRPS2_QCH_ENABLE,
|
|
QCH_CON_PPC_IRPS2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_IRPS2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_IRPS2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_IRPS3_QCH_ENABLE,
|
|
QCH_CON_PPC_IRPS3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_IRPS3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_IRPS3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D2_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D3_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G3D0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G3D1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G3D2_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G3D3_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MODEM_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CORE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P0_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P1_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL0_QCH_ENABLE,
|
|
DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DDD_CPUCL0_0_QCH_ENABLE,
|
|
DMYQCH_CON_DDD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_HTU_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_HTU_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_ENABLE,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BPS_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSSYS_QCH_ENABLE,
|
|
QCH_CON_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_INT_ETR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_INT_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_INT_ETR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_INT_STM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_INT_STM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_INT_STM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_INT_ETR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_INT_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_INT_ETR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_INT_STM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_INT_STM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_INT_STM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SECJTAG_QCH_ENABLE,
|
|
QCH_CON_SECJTAG_QCH_CLOCK_REQ,
|
|
QCH_CON_SECJTAG_QCH_EXPIRE_VAL,
|
|
QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL1_QCH_ENABLE,
|
|
DMYQCH_CON_CPUCL1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC2_ENABLE,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC2_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL1_QCH_DDD_HC2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_ENABLE,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_ENABLE,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_ENABLE,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CPUCL2_QCH_ENABLE,
|
|
DMYQCH_CON_CPUCL2_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CPUCL2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DDD_CPUCL0_1_QCH_ENABLE,
|
|
DMYQCH_CON_DDD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_ENABLE,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSISX6_QCH_VOTF0_ENABLE,
|
|
QCH_CON_CSISX6_QCH_VOTF0_CLOCK_REQ,
|
|
QCH_CON_CSISX6_QCH_VOTF0_EXPIRE_VAL,
|
|
QCH_CON_CSISX6_QCH_VOTF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSISX6_QCH_DMA_ENABLE,
|
|
QCH_CON_CSISX6_QCH_DMA_CLOCK_REQ,
|
|
QCH_CON_CSISX6_QCH_DMA_EXPIRE_VAL,
|
|
QCH_CON_CSISX6_QCH_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSISX6_QCH_MCB_ENABLE,
|
|
QCH_CON_CSISX6_QCH_MCB_CLOCK_REQ,
|
|
QCH_CON_CSISX6_QCH_MCB_EXPIRE_VAL,
|
|
QCH_CON_CSISX6_QCH_MCB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSISX6_QCH_VOTF1_ENABLE,
|
|
QCH_CON_CSISX6_QCH_VOTF1_CLOCK_REQ,
|
|
QCH_CON_CSISX6_QCH_VOTF1_EXPIRE_VAL,
|
|
QCH_CON_CSISX6_QCH_VOTF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_CSIS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D2_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D2_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D2_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D3_CSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D3_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D3_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL,
|
|
QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OIS_MCU_TOP_QCH_ENABLE,
|
|
QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_OIS_MCU_TOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE,
|
|
QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ,
|
|
QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL,
|
|
QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE,
|
|
QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ,
|
|
QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL,
|
|
QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D3_QCH_ENABLE,
|
|
QCH_CON_PPMU_D3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_DMA0_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_DMA1_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_DMA2_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_CSIS_DMA3_QCH_ENABLE,
|
|
QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_AF1_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_AF2_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_STAT_AF0_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_STAT_AF0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_STAT_AF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_STAT_AF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE,
|
|
QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_STRP0_QCH_ENABLE,
|
|
QCH_CON_QE_STRP0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_STRP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_STRP1_QCH_ENABLE,
|
|
QCH_CON_QE_STRP1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_STRP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_STRP2_QCH_ENABLE,
|
|
QCH_CON_QE_STRP2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_STRP2_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_STRP3_QCH_ENABLE,
|
|
QCH_CON_QE_STRP3_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_STRP3_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_STRP3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ZSL0_QCH_ENABLE,
|
|
QCH_CON_QE_ZSL0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ZSL1_QCH_ENABLE,
|
|
QCH_CON_QE_ZSL1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ZSL2_QCH_ENABLE,
|
|
QCH_CON_QE_ZSL2_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ZSL3_QCH_ENABLE,
|
|
QCH_CON_QE_ZSL3_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ZSL3_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ZSL3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CSIS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D2_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D2_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNS_QCH_ENABLE,
|
|
QCH_CON_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNS_QCH_VOTF0_ENABLE,
|
|
QCH_CON_DNS_QCH_VOTF0_CLOCK_REQ,
|
|
QCH_CON_DNS_QCH_VOTF0_EXPIRE_VAL,
|
|
QCH_CON_DNS_QCH_VOTF0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNS_QCH_VOTF1_ENABLE,
|
|
QCH_CON_DNS_QCH_VOTF1_CLOCK_REQ,
|
|
QCH_CON_DNS_QCH_VOTF1_EXPIRE_VAL,
|
|
QCH_CON_DNS_QCH_VOTF1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNS_QCH_VOTF2_ENABLE,
|
|
QCH_CON_DNS_QCH_VOTF2_CLOCK_REQ,
|
|
QCH_CON_DNS_QCH_VOTF2_EXPIRE_VAL,
|
|
QCH_CON_DNS_QCH_VOTF2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DNS_CMU_DNS_QCH_ENABLE,
|
|
QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DNS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_CTL_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_CTL_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_CTL_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF_TAADNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF_TAADNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF_TAADNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_CTL_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_CTL_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_CTL_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF4_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF4_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF4_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF5_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF5_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF5_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF6_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF6_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF6_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF7_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF7_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF7_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF8_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF8_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF8_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF9_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF9_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF9_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_DNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_DNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_DNS_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_DNS_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_DNS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_DNS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DNS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_DNS_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D0_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_DNS_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D1_DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_QCH_ENABLE,
|
|
QCH_CON_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUB_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DPUB_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF0_QCH_DMA_ENABLE,
|
|
QCH_CON_DPUF0_QCH_DMA_CLOCK_REQ,
|
|
QCH_CON_DPUF0_QCH_DMA_EXPIRE_VAL,
|
|
QCH_CON_DPUF0_QCH_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF0_QCH_DPP_ENABLE,
|
|
QCH_CON_DPUF0_QCH_DPP_CLOCK_REQ,
|
|
QCH_CON_DPUF0_QCH_DPP_EXPIRE_VAL,
|
|
QCH_CON_DPUF0_QCH_DPP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF0_QCH_C2SERV_ENABLE,
|
|
QCH_CON_DPUF0_QCH_C2SERV_CLOCK_REQ,
|
|
QCH_CON_DPUF0_QCH_C2SERV_EXPIRE_VAL,
|
|
QCH_CON_DPUF0_QCH_C2SERV_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF0_CMU_DPUF0_QCH_ENABLE,
|
|
QCH_CON_DPUF0_CMU_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUF0_CMU_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_DPUF0_CMU_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUF0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF0D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF0D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF0D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUF0D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF0D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF0D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF0D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUF0D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF0D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF0D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUF0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_QCH_DMA_ENABLE,
|
|
QCH_CON_DPUF1_QCH_DMA_CLOCK_REQ,
|
|
QCH_CON_DPUF1_QCH_DMA_EXPIRE_VAL,
|
|
QCH_CON_DPUF1_QCH_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_QCH_DPP_ENABLE,
|
|
QCH_CON_DPUF1_QCH_DPP_CLOCK_REQ,
|
|
QCH_CON_DPUF1_QCH_DPP_EXPIRE_VAL,
|
|
QCH_CON_DPUF1_QCH_DPP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_QCH_C2SERV_ENABLE,
|
|
QCH_CON_DPUF1_QCH_C2SERV_CLOCK_REQ,
|
|
QCH_CON_DPUF1_QCH_C2SERV_EXPIRE_VAL,
|
|
QCH_CON_DPUF1_QCH_C2SERV_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_DPUF1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPUF1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPUF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_GICCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_GICCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_GICCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_GICCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DSU_CMU_DSU_QCH_ENABLE,
|
|
QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ,
|
|
QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL,
|
|
QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_DSU_QCH_ENABLE,
|
|
QCH_CON_HTU_DSU_QCH_CLOCK_REQ,
|
|
QCH_CON_HTU_DSU_QCH_EXPIRE_VAL,
|
|
QCH_CON_HTU_DSU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_ENABLE,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_G3D_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL,
|
|
QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL,
|
|
QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL,
|
|
QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL,
|
|
QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_ENABLE,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CORE_ENABLE,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CORE_CLOCK_REQ,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CORE_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_STR_G3D_QCH_CORE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_G3D_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G3D_CMU_G3D_QCH_ENABLE,
|
|
QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPU_QCH_ENABLE,
|
|
QCH_CON_GPU_QCH_CLOCK_REQ,
|
|
QCH_CON_GPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_G3D_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_G3D_QCH_ENABLE,
|
|
QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_G3D_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_PCLK_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_HSI0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_AUDHSI0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_AUDHSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_AUDHSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_HSI0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_HSI0_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_HSI0AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_HSI0AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_HSI0AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_USB_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_USB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_USB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_USB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_HSI0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_USB31DRD_QCH_REF_ENABLE,
|
|
DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ,
|
|
DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE,
|
|
QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ,
|
|
QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL,
|
|
QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE,
|
|
QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ,
|
|
QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL,
|
|
QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB31DRD_QCH_APB_ENABLE,
|
|
QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL,
|
|
QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB31DRD_QCH_PCS_ENABLE,
|
|
QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ,
|
|
QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL,
|
|
QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB31DRD_QCH_DBG_ENABLE,
|
|
QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL,
|
|
QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_HSI1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_HSI1_QCH_ENABLE,
|
|
QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_HSI1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_HSI1_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MMC_CARD_QCH_ENABLE,
|
|
QCH_CON_MMC_CARD_QCH_CLOCK_REQ,
|
|
QCH_CON_MMC_CARD_QCH_EXPIRE_VAL,
|
|
QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_DBI_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_AXI_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_AXI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_AXI_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_AXI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN4_0_QCH_REF_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN4_0_QCH_REF_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN4_0_QCH_REF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN4_0_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN4_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN4_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PCIE_IA_GEN4_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_HSI1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_HSI1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL,
|
|
QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_ITP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ITP_QCH_ENABLE,
|
|
QCH_CON_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ITP_CMU_ITP_QCH_ENABLE,
|
|
QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_CTL_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_CTL_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_CTL_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF4_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF4_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF4_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF5_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF5_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF5_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF6_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF6_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF6_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF7_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF7_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF7_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF8_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF8_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF8_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF9_DNSITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF9_DNSITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF9_DNSITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_ITP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_CTL_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_CTL_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_CTL_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_ITPDNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_ITPDNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_ITPDNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ITP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_LME_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_LME_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_LME_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LME_QCH_ENABLE,
|
|
QCH_CON_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LME_QCH_C2_ENABLE,
|
|
QCH_CON_LME_QCH_C2_CLOCK_REQ,
|
|
QCH_CON_LME_QCH_C2_EXPIRE_VAL,
|
|
QCH_CON_LME_QCH_C2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LME_CMU_LME_QCH_ENABLE,
|
|
QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_LME_CMU_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_LME_QCH_ENABLE,
|
|
QCH_CON_PPMU_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_LME_QCH_ENABLE,
|
|
QCH_CON_SYSREG_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_LME_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_LME_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_LME_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_LME_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASTC_QCH_ENABLE,
|
|
QCH_CON_ASTC_QCH_CLOCK_REQ,
|
|
QCH_CON_ASTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_M2M_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JPEG0_QCH_ENABLE,
|
|
QCH_CON_JPEG0_QCH_CLOCK_REQ,
|
|
QCH_CON_JPEG0_QCH_EXPIRE_VAL,
|
|
QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JPEG1_QCH_ENABLE,
|
|
QCH_CON_JPEG1_QCH_CLOCK_REQ,
|
|
QCH_CON_JPEG1_QCH_EXPIRE_VAL,
|
|
QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JSQZ_QCH_ENABLE,
|
|
QCH_CON_JSQZ_QCH_CLOCK_REQ,
|
|
QCH_CON_JSQZ_QCH_EXPIRE_VAL,
|
|
QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_M2M_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_M2M_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_QCH_ENABLE,
|
|
QCH_CON_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_QCH_VOTF_ENABLE,
|
|
QCH_CON_M2M_QCH_VOTF_CLOCK_REQ,
|
|
QCH_CON_M2M_QCH_VOTF_EXPIRE_VAL,
|
|
QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_M2M_CMU_M2M_QCH_ENABLE,
|
|
QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D_M2M_QCH_ENABLE,
|
|
QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ASTC_QCH_ENABLE,
|
|
QCH_CON_QE_ASTC_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ASTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JPEG0_QCH_ENABLE,
|
|
QCH_CON_QE_JPEG0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JPEG0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JPEG1_QCH_ENABLE,
|
|
QCH_CON_QE_JPEG1_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JPEG1_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JSQZ_QCH_ENABLE,
|
|
QCH_CON_QE_JSQZ_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JSQZ_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_M2M_QCH_ENABLE,
|
|
QCH_CON_QE_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_M2M_QCH_ENABLE,
|
|
QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MCFP0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D2_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D2_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D2_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D3_MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D3_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D3_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCFP0_QCH_ENABLE,
|
|
QCH_CON_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCFP0_CMU_MCFP0_QCH_ENABLE,
|
|
QCH_CON_MCFP0_CMU_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_MCFP0_CMU_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCFP0_CMU_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_MCFP0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_MCFP0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_MCFP0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D3_MCFP0_QCH_ENABLE,
|
|
QCH_CON_PPMU_D3_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D3_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D0_MCFP0_QCH_ENABLE,
|
|
QCH_CON_QE_D0_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D0_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D1_MCFP0_QCH_ENABLE,
|
|
QCH_CON_QE_D1_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D1_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D2_MCFP0_QCH_ENABLE,
|
|
QCH_CON_QE_D2_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D2_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D3_MCFP0_QCH_ENABLE,
|
|
QCH_CON_QE_D3_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D3_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MCFP0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_MCFP0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MCFP1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_MCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCFP1_QCH_ENABLE,
|
|
QCH_CON_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCFP1_CMU_MCFP1_QCH_ENABLE,
|
|
QCH_CON_MCFP1_CMU_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_MCFP1_CMU_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCFP1_CMU_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ORBMCH0_QCH_C2_ENABLE,
|
|
QCH_CON_ORBMCH0_QCH_C2_CLOCK_REQ,
|
|
QCH_CON_ORBMCH0_QCH_C2_EXPIRE_VAL,
|
|
QCH_CON_ORBMCH0_QCH_C2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ORBMCH0_QCH_ENABLE,
|
|
QCH_CON_ORBMCH0_QCH_CLOCK_REQ,
|
|
QCH_CON_ORBMCH0_QCH_EXPIRE_VAL,
|
|
QCH_CON_ORBMCH0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ORBMCH1_QCH_ENABLE,
|
|
QCH_CON_ORBMCH1_QCH_CLOCK_REQ,
|
|
QCH_CON_ORBMCH1_QCH_EXPIRE_VAL,
|
|
QCH_CON_ORBMCH1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ORBMCH1_QCH_C2_ENABLE,
|
|
QCH_CON_ORBMCH1_QCH_C2_CLOCK_REQ,
|
|
QCH_CON_ORBMCH1_QCH_C2_EXPIRE_VAL,
|
|
QCH_CON_ORBMCH1_QCH_C2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_PPMU_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D0_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D0_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D0_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D0_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D1_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D1_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D1_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D1_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D2_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D2_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D2_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D2_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D3_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D3_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D3_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D3_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D4_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D4_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D4_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D4_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D5_ORBMCH_QCH_ENABLE,
|
|
QCH_CON_QE_D5_ORBMCH_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D5_ORBMCH_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D5_ORBMCH_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_MCFP1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MCFP1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_MCFP1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D0_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_MCFP1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_MCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_MCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D1_MCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_MCSC_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_MCSC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_MCSC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_MCSC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MCSC_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_ENABLE,
|
|
QCH_CON_GDC_QCH_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_EXPIRE_VAL,
|
|
QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_C2_M_ENABLE,
|
|
QCH_CON_GDC_QCH_C2_M_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_C2_M_EXPIRE_VAL,
|
|
QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GDC_QCH_C2_S_ENABLE,
|
|
QCH_CON_GDC_QCH_C2_S_CLOCK_REQ,
|
|
QCH_CON_GDC_QCH_C2_S_EXPIRE_VAL,
|
|
QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D0_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D2_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_ENABLE,
|
|
QCH_CON_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_C2_W_ENABLE,
|
|
QCH_CON_MCSC_QCH_C2_W_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_C2_W_EXPIRE_VAL,
|
|
QCH_CON_MCSC_QCH_C2_W_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_QCH_C2_R_ENABLE,
|
|
QCH_CON_MCSC_QCH_C2_R_CLOCK_REQ,
|
|
QCH_CON_MCSC_QCH_C2_R_EXPIRE_VAL,
|
|
QCH_CON_MCSC_QCH_C2_R_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_ENABLE,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MCSC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MFC0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_EXPIRE_VAL,
|
|
QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_EXPIRE_VAL,
|
|
QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_QCH_ENABLE,
|
|
QCH_CON_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_QCH_VOTF_ENABLE,
|
|
QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ,
|
|
QCH_CON_MFC0_QCH_VOTF_EXPIRE_VAL,
|
|
QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC0D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC0D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC0D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC0D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_WFD_QCH_ENABLE,
|
|
QCH_CON_PPMU_WFD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_WFD_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MFC0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_MFC0_QCH_ENABLE,
|
|
QCH_CON_VGEN_MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WFD_QCH_ENABLE,
|
|
QCH_CON_WFD_QCH_CLOCK_REQ,
|
|
QCH_CON_WFD_QCH_EXPIRE_VAL,
|
|
QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MFC1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_MFC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC1_QCH_ENABLE,
|
|
QCH_CON_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC1D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC1D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFC1D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFC1D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MFC1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_MFC1_QCH_ENABLE,
|
|
QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_MFC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBBR_DDRPHY_QCH_ENABLE,
|
|
QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ,
|
|
QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBBR_DMC_QCH_ENABLE,
|
|
QCH_CON_APBBR_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMC_QCH_ENABLE,
|
|
QCH_CON_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_DMC_QCH_EXPIRE_VAL,
|
|
QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_MIF_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIF_CMU_MIF_QCH_ENABLE,
|
|
QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL,
|
|
QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MIF_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NPU_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE,
|
|
QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE,
|
|
QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_NPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_NPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_NPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NPU_CMU_NPU_QCH_ENABLE,
|
|
QCH_CON_NPU_CMU_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_NPU_CMU_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_NPU_CMU_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NPU_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NPU01_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPU01CORE_QCH_PCLK_ENABLE,
|
|
QCH_CON_IP_NPU01CORE_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPU01CORE_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPU01CORE_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPU01CORE_QCH_ACLK_ENABLE,
|
|
QCH_CON_IP_NPU01CORE_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPU01CORE_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPU01CORE_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NPU01_CMU_NPU_QCH_ENABLE,
|
|
QCH_CON_NPU01_CMU_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_NPU01_CMU_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_NPU01_CMU_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NPU01_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NPU10_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPU10CORE_QCH_PCLK_ENABLE,
|
|
QCH_CON_IP_NPU10CORE_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPU10CORE_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPU10CORE_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPU10CORE_QCH_ACLK_ENABLE,
|
|
QCH_CON_IP_NPU10CORE_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_IP_NPU10CORE_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_IP_NPU10CORE_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NPU10_CMU_NPU_QCH_ENABLE,
|
|
QCH_CON_NPU10_CMU_NPU_QCH_CLOCK_REQ,
|
|
QCH_CON_NPU10_CMU_NPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_NPU10_CMU_NPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NPU10_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_NPUS_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_NPUS_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_NPUS_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_NPUS_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_NPUS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_NPUS_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUS_QCH_ENABLE,
|
|
QCH_CON_IP_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUS_QCH_C2A0_ENABLE,
|
|
QCH_CON_IP_NPUS_QCH_C2A0_CLOCK_REQ,
|
|
QCH_CON_IP_NPUS_QCH_C2A0_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUS_QCH_C2A0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUS_QCH_C2A1_ENABLE,
|
|
QCH_CON_IP_NPUS_QCH_C2A1_CLOCK_REQ,
|
|
QCH_CON_IP_NPUS_QCH_C2A1_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUS_QCH_C2A1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUS_QCH_CPU_ENABLE,
|
|
QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ,
|
|
QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_NPUS_QCH_NEON_ENABLE,
|
|
QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ,
|
|
QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL,
|
|
QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_INT_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_INT_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_INT_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D2_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D2_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D2_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_INT_NPUS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_INT_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_INT_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE,
|
|
QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_NPUS_0_QCH_ENABLE,
|
|
QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_NPUS_1_QCH_ENABLE,
|
|
QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_NPUS_2_QCH_ENABLE,
|
|
QCH_CON_PPMU_NPUS_2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_NPUS_2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_NPUS_2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D2_NPUS_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_NPUS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC0_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_UART_DBG_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_UART_DBG_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_UART_DBG_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_UART_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI05_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI05_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI05_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP0_QCH_USI05_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_USI_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_TOP1_QCH_PWM_ENABLE,
|
|
QCH_CON_PERIC0_TOP1_QCH_PWM_CLOCK_REQ,
|
|
QCH_CON_PERIC0_TOP1_QCH_PWM_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_TOP1_QCH_PWM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC1_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP0_QCH_UART_BT_ENABLE,
|
|
QCH_CON_PERIC1_TOP0_QCH_UART_BT_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP0_QCH_UART_BT_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP0_QCH_UART_BT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_USI_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_USI_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_USI_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_USI_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_USI_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_ENABLE,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI16_I3C_QCH_P_ENABLE,
|
|
QCH_CON_USI16_I3C_QCH_P_CLOCK_REQ,
|
|
QCH_CON_USI16_I3C_QCH_P_EXPIRE_VAL,
|
|
QCH_CON_USI16_I3C_QCH_P_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_USI16_I3C_QCH_S_ENABLE,
|
|
DMYQCH_CON_USI16_I3C_QCH_S_CLOCK_REQ,
|
|
DMYQCH_CON_USI16_I3C_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI17_I3C_QCH_P_ENABLE,
|
|
QCH_CON_USI17_I3C_QCH_P_CLOCK_REQ,
|
|
QCH_CON_USI17_I3C_QCH_P_EXPIRE_VAL,
|
|
QCH_CON_USI17_I3C_QCH_P_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_USI17_I3C_QCH_S_ENABLE,
|
|
DMYQCH_CON_USI17_I3C_QCH_S_CLOCK_REQ,
|
|
DMYQCH_CON_USI17_I3C_QCH_S_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_PERIC2_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIC2_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_USI_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_USI_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_USI_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_ENABLE,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_USI_ENABLE,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_ENABLE,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_USI_ENABLE,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_USI_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_USI_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_USI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_ENABLE,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_CLOCK_REQ,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_EXPIRE_VAL,
|
|
QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC2_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BC_EMUL_QCH_ENABLE,
|
|
QCH_CON_BC_EMUL_QCH_CLOCK_REQ,
|
|
QCH_CON_BC_EMUL_QCH_EXPIRE_VAL,
|
|
QCH_CON_BC_EMUL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_PERIS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GIC_QCH_ENABLE,
|
|
QCH_CON_GIC_QCH_CLOCK_REQ,
|
|
QCH_CON_GIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERISGIC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERISGIC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERISGIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCT_QCH_ENABLE,
|
|
QCH_CON_MCT_QCH_CLOCK_REQ,
|
|
QCH_CON_MCT_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_OTP_QCH_ENABLE,
|
|
DMYQCH_CON_OTP_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_BIRA_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL,
|
|
QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_BISR_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL,
|
|
QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_TOP_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TMU_SUB_QCH_ENABLE,
|
|
QCH_CON_TMU_SUB_QCH_CLOCK_REQ,
|
|
QCH_CON_TMU_SUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TMU_TOP_QCH_ENABLE,
|
|
QCH_CON_TMU_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_TMU_TOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT0_QCH_ENABLE,
|
|
QCH_CON_WDT0_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT0_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT1_QCH_ENABLE,
|
|
QCH_CON_WDT1_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT1_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_BIS_S2D_QCH_ENABLE,
|
|
DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_S2D_CMU_S2D_QCH_ENABLE,
|
|
QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ,
|
|
QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_DAP_SSS_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_SSS_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_SSS_QCH_ENABLE,
|
|
QCH_CON_BAAW_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_SSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_SSP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_SSPCORE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_SSPCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_SSPCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_SSPCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_SSP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_SSP_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_SSP_QCH_ENABLE,
|
|
QCH_CON_PPMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_RTIC_QCH_ENABLE,
|
|
QCH_CON_QE_RTIC_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_RTIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_SSPCORE_QCH_ENABLE,
|
|
QCH_CON_QE_SSPCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_SSPCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_SSPCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_SSS_QCH_ENABLE,
|
|
QCH_CON_QE_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_SSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RTIC_QCH_ENABLE,
|
|
QCH_CON_RTIC_QCH_CLOCK_REQ,
|
|
QCH_CON_RTIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SSP_CMU_SSP_QCH_ENABLE,
|
|
QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SSP_CMU_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SSS_QCH_ENABLE,
|
|
QCH_CON_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_D_SSP_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_D_SSP_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_D_SSP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SWEEPER_D_SSP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_RTIC_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_RTIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_RTIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_RTIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_SSPCTRL_QCH_ENABLE,
|
|
QCH_CON_SYSREG_SSPCTRL_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_SSPCTRL_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_SSPCTRL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_RTIC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_RTIC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_RTIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_RTIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USS_SSPCORE_QCH_ENABLE,
|
|
QCH_CON_USS_SSPCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_USS_SSPCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_USS_SSPCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_TAA_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_TAA_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_TAA_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_TAA_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_TAA_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_TAA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF_TAADNS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF_TAADNS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF_TAADNS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_TAA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_TAA_QCH_ENABLE,
|
|
QCH_CON_PPMU_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_TAA_QCH_ENABLE,
|
|
QCH_CON_SIPU_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE,
|
|
QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ,
|
|
QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL,
|
|
QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE,
|
|
QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ,
|
|
QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL,
|
|
QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_TAA_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_TAA_QCH_ENABLE,
|
|
QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TAA_CMU_TAA_QCH_ENABLE,
|
|
QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ,
|
|
QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL,
|
|
QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_TAA0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_TAA0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_TAA0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_TAA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_TAA1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_TAA1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_TAA1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_TAA1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADD_VPC_QCH_ENABLE,
|
|
DMYQCH_CON_ADD_VPC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADD_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADM_DAP_VPC_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_VPC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_ADD_VPC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_ADD_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_ADD_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_ADD_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_VPC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_VPC_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_VPC_QCH_PCLK_ENABLE,
|
|
QCH_CON_HTU_VPC_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_HTU_VPC_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_VPC_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HTU_VPC_QCH_CLK_ENABLE,
|
|
QCH_CON_HTU_VPC_QCH_CLK_CLOCK_REQ,
|
|
QCH_CON_HTU_VPC_QCH_CLK_EXPIRE_VAL,
|
|
QCH_CON_HTU_VPC_QCH_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_VPC_QCH_ENABLE,
|
|
QCH_CON_IP_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_IP_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_VPC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_VPC_800_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_VPC_800_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_VPC_800_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_VPC_800_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D0_VPC_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D0_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D0_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D1_VPC_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D1_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D1_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D2_VPC_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D2_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D2_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_VPCVPD0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_VPCVPD0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_VPCVPD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_VPCVPD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_VPCVPD1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_VPCVPD1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_VPCVPD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_VPCVPD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_VPC_200_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_VPC_200_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_VPC_200_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_VPC_200_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_VPC0_QCH_ENABLE,
|
|
QCH_CON_PPMU_VPC0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_VPC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_VPC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_VPC1_QCH_ENABLE,
|
|
QCH_CON_PPMU_VPC1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_VPC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_VPC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_VPC2_QCH_ENABLE,
|
|
QCH_CON_PPMU_VPC2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_VPC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_VPC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC0_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC1_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_VPC2_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_VPC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_VPC_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VPC_CMU_VPC_QCH_ENABLE,
|
|
QCH_CON_VPC_CMU_VPC_QCH_CLOCK_REQ,
|
|
QCH_CON_VPC_CMU_VPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_VPC_CMU_VPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_VPD_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_VPD_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_VPD_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_VPD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IP_VPD_QCH_ENABLE,
|
|
QCH_CON_IP_VPD_QCH_CLOCK_REQ,
|
|
QCH_CON_IP_VPD_QCH_EXPIRE_VAL,
|
|
QCH_CON_IP_VPD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_VPCVPD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_VPCVPD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_VPCVPD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_VPCVPD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_VPD_QCH_ENABLE,
|
|
QCH_CON_SYSREG_VPD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_VPD_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_VPD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VPD_CMU_VPD_QCH_ENABLE,
|
|
QCH_CON_VPD_CMU_VPD_QCH_CLOCK_REQ,
|
|
QCH_CON_VPD_CMU_VPD_QCH_EXPIRE_VAL,
|
|
QCH_CON_VPD_CMU_VPD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_C_VTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_C_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_C_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_C_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_D_VTS_QCH_ENABLE,
|
|
QCH_CON_BAAW_D_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_D_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_D_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPM_VTS_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPM_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPM_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPM_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_TEST_QCH_ACLK_ENABLE,
|
|
QCH_CON_DMAILBOX_TEST_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_TEST_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_DMAILBOX_TEST_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMAILBOX_TEST_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMAILBOX_TEST_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMAILBOX_TEST_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMAILBOX_TEST_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_ENABLE,
|
|
DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_CLOCK_REQ,
|
|
DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB3_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB3_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB3_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB3_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB4_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB4_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB4_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB4_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB5_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB5_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB5_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB5_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_VTS_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_VTS_QCH_ENABLE,
|
|
QCH_CON_GPIO_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC3_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC3_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC3_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC4_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC4_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC4_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC4_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC5_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC5_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC5_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC5_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_AUDVTS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_AUDVTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_AUDVTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_LP_VTS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_LP_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_LP_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_C_VTS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_C_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_C_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM_VTS1_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM_VTS1_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM_VTS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM_VTS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_VTS_QCH_ENABLE,
|
|
QCH_CON_PDMA_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_PDMA_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_LIF_ENABLE,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_LIF_CLOCK_REQ,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_LIF_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_HCLK_ENABLE,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_HCLK_CLOCK_REQ,
|
|
DMYQCH_CON_SERIAL_LIF_QCH_HCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_ENABLE,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_CLOCK_REQ,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_ENABLE,
|
|
QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_ENABLE,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_CLOCK_REQ,
|
|
DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ,
|
|
DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_D_VTS_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_D_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_D_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SWEEPER_D_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_VTS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER_QCH_ENABLE,
|
|
QCH_CON_TIMER_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER_QCH_EXPIRE_VAL,
|
|
QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER1_QCH_ENABLE,
|
|
QCH_CON_TIMER1_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER2_QCH_ENABLE,
|
|
QCH_CON_TIMER2_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER2_QCH_EXPIRE_VAL,
|
|
QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VTS_CMU_VTS_QCH_ENABLE,
|
|
QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_VTS_QCH_ENABLE,
|
|
QCH_CON_WDT_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_D_TZPC_YUVPP_QCH_ENABLE,
|
|
QCH_CON_D_TZPC_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_D_TZPC_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_D_TZPC_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_FRC_MC_QCH_ENABLE,
|
|
QCH_CON_FRC_MC_QCH_CLOCK_REQ,
|
|
QCH_CON_FRC_MC_QCH_EXPIRE_VAL,
|
|
QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_YUVPP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_YUVPP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_YUVPP_QCH_ENABLE,
|
|
QCH_CON_PPMU_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D0_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D0_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D0_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D0_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D10_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D10_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D10_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D10_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D11_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D11_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D11_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D11_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D1_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D1_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D1_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D1_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D2_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D2_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D2_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D2_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D3_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D3_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D3_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D3_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D4_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D4_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D4_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D4_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D5_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D5_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D5_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D5_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D6_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D6_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D6_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D6_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D7_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D7_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D7_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D7_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D8_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D8_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D8_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D8_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_D9_YUVPP_QCH_ENABLE,
|
|
QCH_CON_QE_D9_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_D9_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_D9_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S1_ENABLE,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S2_ENABLE,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S2_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S2_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_D_YUVPP_QCH_S2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_YUVPP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_YUVPP0_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_YUVPP0_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_YUVPP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_YUVPP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_YUVPP1_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_YUVPP1_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_YUVPP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_YUVPP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VGEN_LITE_YUVPP2_QCH_ENABLE,
|
|
QCH_CON_VGEN_LITE_YUVPP2_QCH_CLOCK_REQ,
|
|
QCH_CON_VGEN_LITE_YUVPP2_QCH_EXPIRE_VAL,
|
|
QCH_CON_VGEN_LITE_YUVPP2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_YUVPP_CMU_YUVPP_QCH_ENABLE,
|
|
QCH_CON_YUVPP_CMU_YUVPP_QCH_CLOCK_REQ,
|
|
QCH_CON_YUVPP_CMU_YUVPP_QCH_EXPIRE_VAL,
|
|
QCH_CON_YUVPP_CMU_YUVPP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_YUVPP_TOP_QCH_ENABLE,
|
|
QCH_CON_YUVPP_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_YUVPP_TOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_YUVPP_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_YUVPP_TOP_QCH_C2COM_ENABLE,
|
|
QCH_CON_YUVPP_TOP_QCH_C2COM_CLOCK_REQ,
|
|
QCH_CON_YUVPP_TOP_QCH_C2COM_EXPIRE_VAL,
|
|
QCH_CON_YUVPP_TOP_QCH_C2COM_IGNORE_FORCE_PM_EN,
|
|
ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT,
|
|
YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING,
|
|
end_of_sfr_access,
|
|
num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE,
|
|
};
|
|
|
|
#endif
|