4030 lines
683 KiB
C
Executable file
4030 lines
683 KiB
C
Executable file
#include "../cmucal.h"
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#include "cmucal-node.h"
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#include "cmucal-sfr.h"
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struct cmucal_pll_table pll_aud0_rate_table[] = {
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PLL_RATE_MPSF(1179648000, 136, 3, 0, 486322451),
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};
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struct cmucal_pll_table pll_aud1_rate_table[] = {
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PLL_RATE_MPSF(67737600, 83, 2, 4, 1586362688),
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};
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struct cmucal_pll_table pll_g3d_rate_table[] = {
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PLL_RATE_MPS(858000000, 66, 2, 0),
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PLL_RATE_MPS(767000000, 59, 2, 0),
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PLL_RATE_MPS(676000000, 52, 2, 0),
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PLL_RATE_MPS(585000000, 90, 2, 1),
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PLL_RATE_MPS(494000000, 76, 2, 1),
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PLL_RATE_MPS(403000000, 62, 2, 1),
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PLL_RATE_MPS(312000000, 48, 2, 1),
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PLL_RATE_MPS(221000000, 68, 2, 2),
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PLL_RATE_MPS(130000000, 80, 2, 3),
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PLL_RATE_MPS(100000000, 123, 2, 4),
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};
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struct cmucal_pll_table pll_mmc_rate_table[] = {
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PLL_RATE_MPSF(799500000, 123, 4, 0, 330382100),
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PLL_RATE_MPSF(399750000, 123, 4, 1, 330382100),
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PLL_RATE_MPSF(99937500, 123, 4, 3, 330382100),
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};
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struct cmucal_pll_table pll_shared0_rate_table[] = {
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PLL_RATE_MPS(1066000000, 82, 2, 0),
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};
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struct cmucal_pll_table pll_shared1_rate_table[] = {
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PLL_RATE_MPS(936000000, 72, 2, 0),
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};
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struct cmucal_pll_table pll_shared2_rate_table[] = {
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PLL_RATE_MPS(799500000, 123, 2, 1),
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};
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struct cmucal_pll_table pll_shared3_rate_table[] = {
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PLL_RATE_MPS(715000000, 110, 2, 1),
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};
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struct cmucal_pll_table pll_shared4_rate_table[] = {
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PLL_RATE_MPS(663000000, 102, 2, 1),
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};
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struct cmucal_pll_table pll_shared_mif_rate_table[] = {
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(2028000000, 78, 1, 0),
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PLL_RATE_MPS(1690000000, 65, 1, 0),
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PLL_RATE_MPS(1352000000, 52, 1, 0),
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PLL_RATE_MPS(1092000000, 42, 1, 0),
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PLL_RATE_MPS(842000000, 130, 2, 1),
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};
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struct cmucal_pll_table pll_cpucl0_rate_table[] = {
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PLL_RATE_MPS(2392000000, 92, 1, 0),
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PLL_RATE_MPS(2314000000, 89, 1, 0),
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PLL_RATE_MPS(2210000000, 85, 1, 0),
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PLL_RATE_MPS(2106000000, 81, 1, 0),
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PLL_RATE_MPS(2002000000, 77, 1, 0),
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PLL_RATE_MPS(1898000000, 73, 1, 0),
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PLL_RATE_MPS(1794000000, 69, 1, 0),
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PLL_RATE_MPS(1690000000, 65, 1, 0),
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PLL_RATE_MPS(1586000000, 61, 1, 0),
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PLL_RATE_MPS(1482000000, 57, 1, 0),
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PLL_RATE_MPS(1378000000, 53, 1, 0),
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PLL_RATE_MPS(1274000000, 49, 1, 0),
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PLL_RATE_MPS(1170000000, 90, 1, 1),
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PLL_RATE_MPS(1066000000, 82, 1, 1),
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PLL_RATE_MPS(962000000, 74, 1, 1),
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PLL_RATE_MPS(858000000, 66, 1, 1),
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PLL_RATE_MPS(754000000, 58, 1, 1),
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PLL_RATE_MPS(650000000, 50, 1, 1),
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PLL_RATE_MPS(533000000, 82, 1, 2),
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PLL_RATE_MPS(403000000, 62, 1, 2),
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PLL_RATE_MPS(267000000, 82, 1, 3),
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PLL_RATE_MPS(182000000, 56, 1, 3),
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};
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struct cmucal_pll_table pll_cpucl1_rate_table[] = {
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PLL_RATE_MPS(2990000000, 345, 3, 0),
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PLL_RATE_MPS(2912000000, 336, 3, 0),
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PLL_RATE_MPS(2808000000, 324, 3, 0),
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PLL_RATE_MPS(2704000000, 312, 3, 0),
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PLL_RATE_MPS(2600000000, 300, 3, 0),
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PLL_RATE_MPS(2496000000, 288, 3, 0),
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PLL_RATE_MPS(2392000000, 276, 3, 0),
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PLL_RATE_MPS(2288000000, 264, 3, 0),
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PLL_RATE_MPS(2184000000, 252, 3, 0),
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PLL_RATE_MPS(2080000000, 240, 3, 0),
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PLL_RATE_MPS(1976000000, 228, 3, 0),
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PLL_RATE_MPS(1872000000, 216, 3, 0),
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PLL_RATE_MPS(1768000000, 204, 3, 0),
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PLL_RATE_MPS(1664000000, 192, 3, 0),
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PLL_RATE_MPS(1560000000, 180, 3, 0),
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PLL_RATE_MPS(1456000000, 168, 3, 0),
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PLL_RATE_MPS(1352000000, 156, 3, 0),
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PLL_RATE_MPS(1248000000, 144, 3, 0),
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PLL_RATE_MPS(1144000000, 264, 3, 1),
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PLL_RATE_MPS(1040000000, 240, 3, 1),
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PLL_RATE_MPS(936000000, 216, 3, 1),
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PLL_RATE_MPS(832000000, 192, 3, 1),
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PLL_RATE_MPS(728000000, 168, 3, 1),
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PLL_RATE_MPS(624000000, 144, 3, 1),
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PLL_RATE_MPS(533000000, 246, 3, 2),
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PLL_RATE_MPS(403000000, 192, 3, 2),
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PLL_RATE_MPS(267000000, 246, 3, 3),
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PLL_RATE_MPS(182000000, 168, 3, 3),
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};
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struct cmucal_pll_table pll_cpucl2_rate_table[] = {
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PLL_RATE_MPS(2990000000, 345, 3, 0),
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PLL_RATE_MPS(2912000000, 336, 3, 0),
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PLL_RATE_MPS(2808000000, 324, 3, 0),
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PLL_RATE_MPS(2704000000, 312, 3, 0),
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PLL_RATE_MPS(2600000000, 300, 3, 0),
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PLL_RATE_MPS(2496000000, 288, 3, 0),
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PLL_RATE_MPS(2392000000, 276, 3, 0),
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PLL_RATE_MPS(2288000000, 264, 3, 0),
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PLL_RATE_MPS(2184000000, 252, 3, 0),
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PLL_RATE_MPS(2080000000, 240, 3, 0),
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PLL_RATE_MPS(1976000000, 228, 3, 0),
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PLL_RATE_MPS(1872000000, 216, 3, 0),
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PLL_RATE_MPS(1768000000, 204, 3, 0),
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PLL_RATE_MPS(1664000000, 192, 3, 0),
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PLL_RATE_MPS(1560000000, 180, 3, 0),
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PLL_RATE_MPS(1456000000, 168, 3, 0),
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PLL_RATE_MPS(1352000000, 156, 3, 0),
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PLL_RATE_MPS(1248000000, 144, 3, 0),
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PLL_RATE_MPS(1144000000, 264, 3, 1),
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PLL_RATE_MPS(1040000000, 240, 3, 1),
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PLL_RATE_MPS(936000000, 216, 3, 1),
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PLL_RATE_MPS(832000000, 192, 3, 1),
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PLL_RATE_MPS(728000000, 168, 3, 1),
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PLL_RATE_MPS(624000000, 144, 3, 1),
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PLL_RATE_MPS(533000000, 246, 3, 2),
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PLL_RATE_MPS(403000000, 192, 3, 2),
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PLL_RATE_MPS(267000000, 246, 3, 3),
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PLL_RATE_MPS(182000000, 168, 3, 3),
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};
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struct cmucal_pll_table pll_dsu_rate_table[] = {
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PLL_RATE_MPS(2210000000, 85, 1, 0),
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PLL_RATE_MPS(2106000000, 81, 1, 0),
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PLL_RATE_MPS(2002000000, 77, 1, 0),
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PLL_RATE_MPS(1898000000, 73, 1, 0),
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PLL_RATE_MPS(1794000000, 69, 1, 0),
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PLL_RATE_MPS(1690000000, 65, 1, 0),
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PLL_RATE_MPS(1586000000, 61, 1, 0),
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PLL_RATE_MPS(1482000000, 57, 1, 0),
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PLL_RATE_MPS(1378000000, 53, 1, 0),
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PLL_RATE_MPS(1274000000, 49, 1, 0),
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PLL_RATE_MPS(1170000000, 90, 1, 1),
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PLL_RATE_MPS(1066000000, 82, 1, 1),
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PLL_RATE_MPS(962000000, 74, 1, 1),
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PLL_RATE_MPS(858000000, 66, 1, 1),
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PLL_RATE_MPS(754000000, 58, 1, 1),
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PLL_RATE_MPS(650000000, 50, 1, 1),
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PLL_RATE_MPS(533000000, 82, 1, 2),
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PLL_RATE_MPS(403000000, 62, 1, 2),
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PLL_RATE_MPS(266000000, 82, 1, 3),
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PLL_RATE_MPS(182000000, 56, 1, 3),
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};
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struct cmucal_pll_table pll_mif_main_rate_table[] = {
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PLL_RATE_MPS(6344000000, 366, 3, 0),
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PLL_RATE_MPS(5460000000, 315, 3, 0),
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PLL_RATE_MPS(5070000000, 390, 4, 0),
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PLL_RATE_MPS(4576000000, 264, 3, 0),
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PLL_RATE_MPS(4056000000, 234, 3, 0),
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PLL_RATE_MPS(3432000000, 198, 3, 0),
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PLL_RATE_MPS(3078000000, 592, 5, 1),
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PLL_RATE_MPS(2704000000, 312, 3, 1),
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PLL_RATE_MPS(2028000000, 234, 3, 1),
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PLL_RATE_MPS(1690000000, 195, 3, 1),
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PLL_RATE_MPS(1352000000, 156, 3, 1),
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PLL_RATE_MPS(1092000000, 252, 3, 2),
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PLL_RATE_MPS(842000000, 259, 4, 2),
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};
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struct cmucal_pll_table pll_mif_sub_rate_table[] = {
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PLL_RATE_MPS(6344000000, 366, 3, 0),
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PLL_RATE_MPS(5460000000, 315, 3, 0),
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PLL_RATE_MPS(5070000000, 390, 4, 0),
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PLL_RATE_MPS(4576000000, 264, 3, 0),
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PLL_RATE_MPS(4056000000, 234, 3, 0),
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PLL_RATE_MPS(3432000000, 198, 3, 0),
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PLL_RATE_MPS(3078000000, 592, 5, 1),
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PLL_RATE_MPS(2704000000, 312, 3, 1),
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PLL_RATE_MPS(2028000000, 234, 3, 1),
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PLL_RATE_MPS(1690000000, 195, 3, 1),
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PLL_RATE_MPS(1352000000, 156, 3, 1),
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PLL_RATE_MPS(1092000000, 252, 3, 2),
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PLL_RATE_MPS(842000000, 259, 4, 2),
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};
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struct cmucal_pll_table pll_mif_s2d_rate_table[] = {
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PLL_RATE_MPS(799500000, 369, 3, 3),
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};
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unsigned int cmucal_pll_size = 17;
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struct cmucal_pll cmucal_pll_list[] = {
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CLK_RPLL(frd_2021_rpll, PLL_AUD0, OSCCLK_AUD, PLL_LOCKTIME_PLL_AUD0_PLL_LOCK_TIME, PLL_CON3_PLL_AUD0_ENABLE, PLL_CON3_PLL_AUD0_STABLE, PLL_CON3_PLL_AUD0_DIV_P, PLL_CON3_PLL_AUD0_DIV_M, PLL_CON3_PLL_AUD0_DIV_S, PLL_CON8_PLL_AUD0_DIV_F, pll_aud0_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_AUD1, OSCCLK_AUD, PLL_LOCKTIME_PLL_AUD1_PLL_LOCK_TIME, PLL_CON3_PLL_AUD1_ENABLE, PLL_CON3_PLL_AUD1_STABLE, PLL_CON3_PLL_AUD1_DIV_P, PLL_CON3_PLL_AUD1_DIV_M, PLL_CON3_PLL_AUD1_DIV_S, PLL_CON8_PLL_AUD1_DIV_F, pll_aud1_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_G3D, OSCCLK_CMU, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_ENABLE, PLL_CON3_PLL_G3D_STABLE, PLL_CON3_PLL_G3D_DIV_P, PLL_CON3_PLL_G3D_DIV_M, PLL_CON3_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_MMC, OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON3_PLL_MMC_ENABLE, PLL_CON3_PLL_MMC_STABLE, PLL_CON3_PLL_MMC_DIV_P, PLL_CON3_PLL_MMC_DIV_M, PLL_CON3_PLL_MMC_DIV_S, PLL_CON8_PLL_MMC_DIV_F, pll_mmc_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED0_ENABLE, PLL_CON3_PLL_SHARED0_STABLE, PLL_CON3_PLL_SHARED0_DIV_P, PLL_CON3_PLL_SHARED0_DIV_M, PLL_CON3_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED1_ENABLE, PLL_CON3_PLL_SHARED1_STABLE, PLL_CON3_PLL_SHARED1_DIV_P, PLL_CON3_PLL_SHARED1_DIV_M, PLL_CON3_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED2, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED2_ENABLE, PLL_CON3_PLL_SHARED2_STABLE, PLL_CON3_PLL_SHARED2_DIV_P, PLL_CON3_PLL_SHARED2_DIV_M, PLL_CON3_PLL_SHARED2_DIV_S, EMPTY_CAL_ID, pll_shared2_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED3, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED3_ENABLE, PLL_CON3_PLL_SHARED3_STABLE, PLL_CON3_PLL_SHARED3_DIV_P, PLL_CON3_PLL_SHARED3_DIV_M, PLL_CON3_PLL_SHARED3_DIV_S, EMPTY_CAL_ID, pll_shared3_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED4, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED4_ENABLE, PLL_CON3_PLL_SHARED4_STABLE, PLL_CON3_PLL_SHARED4_DIV_P, PLL_CON3_PLL_SHARED4_DIV_M, PLL_CON3_PLL_SHARED4_DIV_S, EMPTY_CAL_ID, pll_shared4_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_SHARED_MIF, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED_MIF_ENABLE, PLL_CON3_PLL_SHARED_MIF_STABLE, PLL_CON3_PLL_SHARED_MIF_DIV_P, PLL_CON3_PLL_SHARED_MIF_DIV_M, PLL_CON3_PLL_SHARED_MIF_DIV_S, EMPTY_CAL_ID, pll_shared_mif_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL0_ENABLE, PLL_CON3_PLL_CPUCL0_STABLE, PLL_CON3_PLL_CPUCL0_DIV_P, PLL_CON3_PLL_CPUCL0_DIV_M, PLL_CON3_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 0, 0),
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CLK_PLL(pll_0522x, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL1_ENABLE, PLL_CON3_PLL_CPUCL1_STABLE, PLL_CON3_PLL_CPUCL1_DIV_P, PLL_CON3_PLL_CPUCL1_DIV_M, PLL_CON3_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0),
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CLK_PLL(pll_0522x, PLL_CPUCL2, OSCCLK_CPUCL2, PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL2_ENABLE, PLL_CON3_PLL_CPUCL2_STABLE, PLL_CON3_PLL_CPUCL2_DIV_P, PLL_CON3_PLL_CPUCL2_DIV_M, PLL_CON3_PLL_CPUCL2_DIV_S, EMPTY_CAL_ID, pll_cpucl2_rate_table, 0, 0),
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CLK_RPLL(frd_2021_rpll, PLL_DSU, OSCCLK_DSU, PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, PLL_CON3_PLL_DSU_ENABLE, PLL_CON3_PLL_DSU_STABLE, PLL_CON3_PLL_DSU_DIV_P, PLL_CON3_PLL_DSU_DIV_M, PLL_CON3_PLL_DSU_DIV_S, EMPTY_CAL_ID, pll_dsu_rate_table, 0, 0),
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CLK_PLL(pll_0516x, PLL_MIF_MAIN, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_MAIN_ENABLE, PLL_CON3_PLL_MIF_MAIN_STABLE, PLL_CON3_PLL_MIF_MAIN_DIV_P, PLL_CON3_PLL_MIF_MAIN_DIV_M, PLL_CON3_PLL_MIF_MAIN_DIV_S, EMPTY_CAL_ID, pll_mif_main_rate_table, 0, 0),
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CLK_PLL(pll_0516x, PLL_MIF_SUB, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_SUB_ENABLE, PLL_CON3_PLL_MIF_SUB_STABLE, PLL_CON3_PLL_MIF_SUB_DIV_P, PLL_CON3_PLL_MIF_SUB_DIV_M, PLL_CON3_PLL_MIF_SUB_DIV_S, EMPTY_CAL_ID, pll_mif_sub_rate_table, 0, 0),
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CLK_PLL(pll_0516x, PLL_MIF_S2D, OSCCLK_S2D, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_S2D_ENABLE, PLL_CON3_PLL_MIF_S2D_STABLE, PLL_CON3_PLL_MIF_S2D_DIV_P, PLL_CON3_PLL_MIF_S2D_DIV_M, PLL_CON3_PLL_MIF_S2D_DIV_S, EMPTY_CAL_ID, pll_mif_s2d_rate_table, 0, 0),
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};
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enum clk_id cmucal_mux_clkcmu_cmgp_bus_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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OSCCTRL_RCO_400,
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MUX_CLKCMU_ALIVE_BUS_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_bus_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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OSCCTRL_RCO_400,
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MUX_CLKCMU_ALIVE_BUS_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkcmu_vts_bus_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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OSCCTRL_RCO_400,
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MUX_CLKCMU_ALIVE_BUS_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_i3c_pmic_parents[] = {
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DIV_CLK_ALIVE_I3C_PMIC,
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MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
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};
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enum clk_id cmucal_mux_clkcmu_cmgp_peri_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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OSCCTRL_RCO_400,
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MUX_CLKCMU_ALIVE_BUS_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkcmu_cmgp_adc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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OSCCTRL_RCO_400,
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};
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enum clk_id cmucal_mux_clk_aud_uaif3_parents[] = {
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DIV_CLK_AUD_AUDIF,
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PLL_AUD1,
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IOCLK_AUDIOCDCLK3,
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OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = {
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DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
IOCLK_AUDIOCDCLK2,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
IOCLK_AUDIOCDCLK1,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
IOCLK_AUDIOCDCLK0,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_cpu_parents[] = {
|
|
DIV_CLK_AUD_CPU,
|
|
MUX_CLKCMU_AUD_CPU_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_dsif_parents[] = {
|
|
DIV_CLK_AUD_DSIF,
|
|
CLKIO_AUD_DSIF,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif4_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
IOCLK_AUDIOCDCLK4,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif5_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
IOCLK_AUDIOCDCLK5,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif6_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
AUDIO_LIF_BCLKI,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_cnt_parents[] = {
|
|
DIV_CLK_AUD_AUDIF,
|
|
PLL_AUD1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_bus_parents[] = {
|
|
DIV_CLK_AUD_BUS,
|
|
MUX_CLKCMU_AUD_BUS_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_pcmc_parents[] = {
|
|
MUX_CP_PCMC_CLK_USER,
|
|
DIV_CLK_AUD_PCMC,
|
|
};
|
|
enum clk_id cmucal_mux_bus0_cmuref_parents[] = {
|
|
OSCCLK_BUS0,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_bus1_cmuref_parents[] = {
|
|
OSCCLK_BUS1,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_bus2_cmuref_parents[] = {
|
|
OSCCLK_BUS2,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i2c0_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi0_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi1_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi2_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi3_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_clk_cmgp_adc_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKCMU_CMGP_ADC_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i2c1_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i2c2_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i2c3_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i3c_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
MUX_CLKCMU_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_mfc0_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vpd_bus_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED_MIF,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED_MIF,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_taa_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_itp_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_cpu_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hpm_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED0,
|
|
PLL_SHARED2_D2,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_parents[] = {
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_cmu_cmuref_parents[] = {
|
|
OSCCLK_CMU,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_pcie_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npu_bus_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_alive_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl2_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED_MIF,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_wfd_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_busp_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dpuf0_bus_parents[] = {
|
|
DIV_CLKCMU_DPUF0,
|
|
DIV_CLKCMU_DPUF0_ALT,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf0_alt_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED_MIF,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_mif_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvpp_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk4_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf0_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus1_bus_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_csis_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp0_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dns_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npus_bus_parents[] = {
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_gdc_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_ois_mcu_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_sspcore_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk5_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_cpu_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_bus_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_alt_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dpub_bus_parents[] = {
|
|
DIV_CLKCMU_DPUB,
|
|
DIV_CLKCMU_DPUB_ALT,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc1_mfc1_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus1_sbic_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_bus_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp1_mcfp1_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vpc_bus_parents[] = {
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus0_bus_parents[] = {
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus2_bus_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usb31drd_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usbdp_debug_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_bus_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp1_orbmch_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_pdp_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_cp_ucpu_clk_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
};
|
|
enum clk_id cmucal_mux_cp_lcpu_clk_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
};
|
|
enum clk_id cmucal_mux_cp_hispeedy_clk_parents[] = {
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvpp_frc_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_bus_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_g3d_shader_parents[] = {
|
|
PLL_G3D,
|
|
DIV_CLKCMU_G3D_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_bus_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf1_parents[] = {
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf1_alt_parents[] = {
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dpuf1_bus_parents[] = {
|
|
DIV_CLKCMU_DPUF1,
|
|
DIV_CLKCMU_DPUF1_ALT,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_busp_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsu_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
PLL_SHARED_MIF,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = {
|
|
PLL_SHARED0,
|
|
PLL_SHARED1,
|
|
PLL_SHARED2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED_MIF_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_mmc_card_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2,
|
|
PLL_MMC,
|
|
PLL_SHARED0_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_ufs_embd_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_core_cmuref_parents[] = {
|
|
OSCCLK_CORE,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl0_cmuref_parents[] = {
|
|
OSCCLK_CPUCL0,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_core_parents[] = {
|
|
MUX_CLK_CPUCL0_CORE_STR,
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
OSCCLK_DSU,
|
|
PLL_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_core_delay_parents[] = {
|
|
PLL_CPUCL0,
|
|
MUX_PLL_CPUCL0_DELAY,
|
|
};
|
|
enum clk_id cmucal_mux_pll_cpucl0_delay_parents[] = {
|
|
PLL_CPUCL0,
|
|
PLL_CPUCL0,
|
|
PLL_CPUCL0,
|
|
PLL_CPUCL0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_core_parents[] = {
|
|
MUX_CLK_CPUCL1_CORE_STR,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
OSCCLK_CPUCL1,
|
|
OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl1_cmuref_parents[] = {
|
|
OSCCLK_CPUCL1,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl2_cmuref_parents[] = {
|
|
OSCCLK_CPUCL2,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_core_parents[] = {
|
|
MUX_CLK_CPUCL2_CORE_STR,
|
|
MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
OSCCLK_CPUCL2,
|
|
OSCCLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_cluster_parents[] = {
|
|
MUX_CLK_DSU_CLUSTER_STR,
|
|
MUX_CLKCMU_DSU_SWITCH_USER,
|
|
OSCCLK_DSU,
|
|
OSCCLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_dsu_cmuref_parents[] = {
|
|
OSCCLK_DSU,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_pll_dsu_delay_parents[] = {
|
|
PLL_DSU,
|
|
PLL_DSU,
|
|
PLL_DSU,
|
|
PLL_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_cluster_delay_parents[] = {
|
|
PLL_DSU,
|
|
MUX_PLL_DSU_DELAY,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_bus_parents[] = {
|
|
MUX_CLK_G3D_SHADER_STR,
|
|
MUX_CLKCMU_G3D_BUS_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_hsi0_bus_parents[] = {
|
|
MUX_CLKCMU_HSI0_BUS_USER,
|
|
MUX_CLKAUD_HSI0_BUS_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_hsi0_usb31drd_parents[] = {
|
|
MUX_CLKCMU_HSI0_USB31DRD_USER,
|
|
MUX_CLKAUD_HSI0_USB31DRD_USER,
|
|
DIV_CLK_HSI0_USB31DRD,
|
|
OSCCLK_HSI0,
|
|
};
|
|
enum clk_id cmucal_mux_mif_cmuref_parents[] = {
|
|
OSCCLK_MIF,
|
|
CLKCMU_CMU_BOOST_MIF,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi00_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi04_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi_i2c_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi14_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi01_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi15_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi05_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi03_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_uart_dbg_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi02_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi13_usi_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_uart_bt_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi_i2c_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi11_usi_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi12_usi_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi16_usi_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi17_usi_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi18_usi_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi10_usi_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi09_usi_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi07_usi_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi_i2c_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi06_usi_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi08_usi_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_s2d_core_parents[] = {
|
|
OSCCLK_S2D,
|
|
CLK_MIF_BUSD_S2D,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_dmic_if_parents[] = {
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
|
MUX_CLKAUD_VTS_DMIC0_USER,
|
|
MUX_CLKAUD_VTS_DMIC1_USER,
|
|
OSCCLK_RCO_VTS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_dmic_aud_parents[] = {
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
|
MUX_CLKAUD_VTS_DMIC0_USER,
|
|
MUX_CLKAUD_VTS_DMIC1_USER,
|
|
OSCCLK_RCO_VTS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_serial_lif_parents[] = {
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
|
MUX_CLKAUD_VTS_DMIC0_USER,
|
|
MUX_CLKAUD_VTS_DMIC1_USER,
|
|
OSCCLK_RCO_VTS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_dmic_ahb_parents[] = {
|
|
MUX_CLK_RCO_VTS_USER,
|
|
MUX_CLKCMU_VTS_BUS_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_serial_lif_core_parents[] = {
|
|
MUX_CLK_RCO_VTS_USER,
|
|
MUX_CLKCMU_VTS_BUS_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_alive_bus_user_parents[] = {
|
|
OSCCLK_RCO_ALIVE,
|
|
CLKCMU_ALIVE_BUS,
|
|
};
|
|
enum clk_id cmucal_oscctrl_rco_400_parents[] = {
|
|
OSCCLK_RCO_ALIVE,
|
|
CLK_RCO_400,
|
|
};
|
|
enum clk_id cmucal_mux_clk_rco_alive_user_parents[] = {
|
|
OSCCLK_RCO_ALIVE,
|
|
CLK_RCO_ALIVE,
|
|
};
|
|
enum clk_id cmucal_mux_clkmux_alive_rco_i3c_pmic_user_parents[] = {
|
|
OSCCLK_RCO_ALIVE,
|
|
CLK_RCO_I3C_PMIC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_cpu_user_parents[] = {
|
|
OSCCLK_AUD,
|
|
CLKCMU_AUD_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_bus_user_parents[] = {
|
|
OSCCLK_AUD,
|
|
CLKCMU_AUD_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_cp_pcmc_clk_user_parents[] = {
|
|
OSCCLK_AUD,
|
|
CP_PCMC_CLK,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus0_bus_user_parents[] = {
|
|
OSCCLK_BUS0,
|
|
CLKCMU_BUS0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus1_bus_user_parents[] = {
|
|
OSCCLK_BUS1,
|
|
CLKCMU_BUS1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus1_sbic_user_parents[] = {
|
|
OSCCLK_BUS1,
|
|
CLKCMU_BUS1_SBIC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus2_bus_user_parents[] = {
|
|
OSCCLK_BUS2,
|
|
CLKCMU_BUS2_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmgp_bus_user_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
CLKCMU_CMGP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmgp_peri_user_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
CLKCMU_CMGP_PERI,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmgp_adc_user_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
CLKCMU_CMGP_ADC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = {
|
|
OSCCLK_CORE,
|
|
CLKCMU_CORE_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = {
|
|
OSCCLK_CPUCL0,
|
|
CLKCMU_CPUCL0_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents[] = {
|
|
OSCCLK_CPUCL0_GLB,
|
|
CLKCMU_CPUCL0_DBG_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_busp_user_parents[] = {
|
|
OSCCLK_CPUCL0_GLB,
|
|
CLKCMU_CPUCL0_BUSP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = {
|
|
OSCCLK_CPUCL1,
|
|
CLKCMU_CPUCL1_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl2_switch_user_parents[] = {
|
|
OSCCLK_CPUCL2,
|
|
CLKCMU_CPUCL2_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_csis_user_parents[] = {
|
|
OSCCLK_CSIS,
|
|
CLKCMU_CSIS_CSIS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_ois_mcu_user_parents[] = {
|
|
OSCCLK_CSIS,
|
|
CLKCMU_CSIS_OIS_MCU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_pdp_user_parents[] = {
|
|
OSCCLK_CSIS,
|
|
CLKCMU_CSIS_PDP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dns_bus_user_parents[] = {
|
|
OSCCLK_DNS,
|
|
CLKCMU_DNS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_bus_user_parents[] = {
|
|
OSCCLK_DPUB,
|
|
CLKCMU_DPUB_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf0_bus_user_parents[] = {
|
|
OSCCLK_DPUF0,
|
|
CLKCMU_DPUF0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf1_bus_user_parents[] = {
|
|
OSCCLK_DPUF1,
|
|
CLKCMU_DPUF1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsu_switch_user_parents[] = {
|
|
OSCCLK_DSU,
|
|
CLKCMU_DSU_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_bus_user_parents[] = {
|
|
OSCCLK_G3D,
|
|
CLKCMU_G3D_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_embedded_g3d_shader_user_parents[] = {
|
|
OSCCLK_G3D,
|
|
DIV_CLK_G3D_SHADER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_shader_user_parents[] = {
|
|
OSCCLK_G3D,
|
|
CLKCMU_G3D_SHADER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_embedded_g3d_busd_user_parents[] = {
|
|
OSCCLK_G3D,
|
|
DIV_CLK_G3D_BUSD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_bus_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKCMU_HSI0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usb31drd_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKCMU_HSI0_USB31DRD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usbdp_debug_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKCMU_HSI0_USBDP_DEBUG,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKCMU_HSI0_DPGTC,
|
|
};
|
|
enum clk_id cmucal_mux_clkaud_hsi0_bus_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKAUD_HSI0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkaud_hsi0_usb31drd_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLKAUD_HSI0_USB31DRD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_usb20phy_user_parents[] = {
|
|
OSCCLK_HSI0,
|
|
CLK_USB20PHY,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_bus_user_parents[] = {
|
|
OSCCLK_HSI1,
|
|
CLKCMU_HSI1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_pcie_user_parents[] = {
|
|
OSCCLK_HSI1,
|
|
CLKCMU_HSI1_PCIE,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_mmc_card_user_parents[] = {
|
|
OSCCLK_HSI1,
|
|
CLKCMU_HSI1_MMC_CARD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_ufs_embd_user_parents[] = {
|
|
OSCCLK_HSI1,
|
|
CLKCMU_HSI1_UFS_EMBD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_itp_bus_user_parents[] = {
|
|
OSCCLK_ITP,
|
|
CLKCMU_ITP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_bus_user_parents[] = {
|
|
OSCCLK_LME,
|
|
CLKCMU_LME_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_bus_user_parents[] = {
|
|
OSCCLK_M2M,
|
|
CLKCMU_M2M_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp0_bus_user_parents[] = {
|
|
OSCCLK_MCFP0,
|
|
CLKCMU_MCFP0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp1_mcfp1_user_parents[] = {
|
|
OSCCLK_MCFP1,
|
|
CLKCMU_MCFP1_MCFP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcfp1_orbmch_user_parents[] = {
|
|
OSCCLK_MCFP1,
|
|
CLKCMU_MCFP1_ORBMCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_bus_user_parents[] = {
|
|
OSCCLK_MCSC,
|
|
CLKCMU_MCSC_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_gdc_user_parents[] = {
|
|
OSCCLK_MCSC,
|
|
CLKCMU_MCSC_GDC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_mfc0_user_parents[] = {
|
|
OSCCLK_MFC0,
|
|
CLKCMU_MFC0_MFC0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_wfd_user_parents[] = {
|
|
OSCCLK_MFC0,
|
|
CLKCMU_MFC0_WFD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc1_mfc1_user_parents[] = {
|
|
OSCCLK_MFC1,
|
|
CLKCMU_MFC1_MFC1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_busp_user_parents[] = {
|
|
OSCCLK_MIF,
|
|
CLKCMU_MIF_BUSP,
|
|
};
|
|
enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = {
|
|
OSCCLK_MIF,
|
|
CLKCMU_MIF01_SWITCH,
|
|
PLL_MIF_MAIN,
|
|
PLL_MIF_SUB,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npu_bus_user_parents[] = {
|
|
OSCCLK_NPU,
|
|
CLKCMU_NPU_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npu01_bus_user_parents[] = {
|
|
OSCCLK_NPU,
|
|
CLKCMU_NPU_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npu10_bus_user_parents[] = {
|
|
OSCCLK_NPU,
|
|
CLKCMU_NPU_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_npus_bus_user_parents[] = {
|
|
OSCCLK_NPUS,
|
|
CLKCMU_NPUS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_bus_user_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip0_user_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip1_user_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_bus_user_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip0_user_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip1_user_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip0_user_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip1_user_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_bus_user_parents[] = {
|
|
OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_bus_user_parents[] = {
|
|
OSCCLK_PERIS,
|
|
CLKCMU_PERIS_BUS,
|
|
};
|
|
enum clk_id cmucal_clkcmu_mif_ddrphy2x_s2d_parents[] = {
|
|
OSCCLK_S2D,
|
|
PLL_MIF_S2D,
|
|
PLL_MIF_S2D,
|
|
PLL_MIF_S2D,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_bus_user_parents[] = {
|
|
OSCCLK_SSP,
|
|
CLKCMU_SSP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_sspcore_user_parents[] = {
|
|
OSCCLK_SSP,
|
|
CLKCMU_SSP_SSPCORE,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_taa_bus_user_parents[] = {
|
|
OSCCLK_TAA,
|
|
CLKCMU_TAA_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vpc_bus_user_parents[] = {
|
|
OSCCLK_VPC,
|
|
CLKCMU_VPC_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vpd_bus_user_parents[] = {
|
|
OSCCLK_VPD,
|
|
CLKCMU_VPD_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_bus_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKCMU_VTS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkaud_vts_dmic0_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKAUD_VTS_DMIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clkaud_vts_dmic1_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKAUD_VTS_DMIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_dmic_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKCMU_VTS_DMIC,
|
|
};
|
|
enum clk_id cmucal_mux_clk_rco_vts_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLK_RCO_VTS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvpp_bus_user_parents[] = {
|
|
OSCCLK_YUVPP,
|
|
CLKCMU_YUVPP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvpp_frc_user_parents[] = {
|
|
OSCCLK_YUVPP,
|
|
CLKCMU_YUVPP_FRC,
|
|
};
|
|
enum clk_id cmucal_mux_hchgen_clk_aud_cpu_parents[] = {
|
|
MUX_CLK_AUD_CPU,
|
|
OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_core_str_parents[] = {
|
|
MUX_CLK_CPUCL0_CORE_DELAY,
|
|
STRETCHER_CLK_CPUCL0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_core_str_parents[] = {
|
|
PLL_CPUCL1,
|
|
STRETCHER_CLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_core_str_parents[] = {
|
|
PLL_CPUCL2,
|
|
STRETCHER_CLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_cluster_str_parents[] = {
|
|
MUX_CLK_DSU_CLUSTER_DELAY,
|
|
STRETCHER_CLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_shader_str_parents[] = {
|
|
MUX_CLKCMU_G3D_SHADER_USER,
|
|
STRETCHER_CLK_G3D,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peris_gic_parents[] = {
|
|
MUX_CLKCMU_PERIS_BUS_USER,
|
|
OSCCLK_PERIS,
|
|
};
|
|
unsigned int cmucal_mux_size = 344;
|
|
struct cmucal_mux cmucal_mux_list[] = {
|
|
CLK_MUX(MUX_CLKCMU_CMGP_BUS, cmucal_mux_clkcmu_cmgp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_ALIVE_BUS, cmucal_mux_clk_alive_bus_parents, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_BUS, cmucal_mux_clkcmu_vts_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_ALIVE_I3C_PMIC, cmucal_mux_clk_alive_i3c_pmic_parents, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_PERI, cmucal_mux_clkcmu_cmgp_peri_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_ADC, cmucal_mux_clkcmu_cmgp_adc_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF3, cmucal_mux_clk_aud_uaif3_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_DSIF, cmucal_mux_clk_aud_dsif_parents, CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF4, cmucal_mux_clk_aud_uaif4_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF5, cmucal_mux_clk_aud_uaif5_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_UAIF6, cmucal_mux_clk_aud_uaif6_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_CNT, cmucal_mux_clk_aud_cnt_parents, CLK_CON_MUX_MUX_CLK_AUD_CNT_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CNT_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_BUS, cmucal_mux_clk_aud_bus_parents, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_AUD_PCMC, cmucal_mux_clk_aud_pcmc_parents, CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_BUS0_CMUREF, cmucal_mux_bus0_cmuref_parents, CLK_CON_MUX_MUX_BUS0_CMUREF_SELECT, CLK_CON_MUX_MUX_BUS0_CMUREF_BUSY, CLK_CON_MUX_MUX_BUS0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_BUS1_CMUREF, cmucal_mux_bus1_cmuref_parents, CLK_CON_MUX_MUX_BUS1_CMUREF_SELECT, CLK_CON_MUX_MUX_BUS1_CMUREF_BUSY, CLK_CON_MUX_MUX_BUS1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_BUS2_CMUREF, cmucal_mux_bus2_cmuref_parents, CLK_CON_MUX_MUX_BUS2_CMUREF_SELECT, CLK_CON_MUX_MUX_BUS2_CMUREF_BUSY, CLK_CON_MUX_MUX_BUS2_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_I2C0, cmucal_mux_clk_cmgp_i2c0_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_USI0, cmucal_mux_clk_cmgp_usi0_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_USI1, cmucal_mux_clk_cmgp_usi1_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_USI2, cmucal_mux_clk_cmgp_usi2_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_USI3, cmucal_mux_clk_cmgp_usi3_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLK_CMGP_ADC, cmucal_clk_cmgp_adc_parents, CLK_CON_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_I2C1, cmucal_mux_clk_cmgp_i2c1_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_I2C2, cmucal_mux_clk_cmgp_i2c2_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C2_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C2_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_I2C3, cmucal_mux_clk_cmgp_i2c3_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C3_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C3_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_I3C, cmucal_mux_clk_cmgp_i3c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_MFC0, cmucal_mux_clkcmu_mfc0_mfc0_parents, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VPD_BUS, cmucal_mux_clkcmu_vpd_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_TAA_BUS, cmucal_mux_clkcmu_taa_bus_parents, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ITP_BUS, cmucal_mux_clkcmu_itp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_CPU, cmucal_mux_clkcmu_aud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS, cmucal_mux_clkcmu_cpucl0_dbg_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_BUS, cmucal_mux_clkcmu_peric0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_BUS, cmucal_mux_clkcmu_peric1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_BUS, cmucal_mux_clkcmu_peris_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_PCIE, cmucal_mux_clkcmu_hsi1_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NPU_BUS, cmucal_mux_clkcmu_npu_bus_parents, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ALIVE_BUS, cmucal_mux_clkcmu_alive_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_BUS, cmucal_mux_clkcmu_hsi1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH, cmucal_mux_clkcmu_cpucl2_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_WFD, cmucal_mux_clkcmu_mfc0_wfd_parents, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_BUSP, cmucal_mux_clkcmu_mif_busp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP0, cmucal_mux_clkcmu_peric0_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP0, cmucal_mux_clkcmu_peric1_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DPUF0_BUS, cmucal_clkcmu_dpuf0_bus_parents, CLK_CON_MUX_CLKCMU_DPUF0_BUS_SELECT, CLK_CON_MUX_CLKCMU_DPUF0_BUS_BUSY, CLK_CON_MUX_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF0_ALT, cmucal_mux_clkcmu_dpuf0_alt_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_BUS, cmucal_mux_clkcmu_hsi0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST_MIF, cmucal_mux_clkcmu_cmu_boost_mif_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVPP_BUS, cmucal_mux_clkcmu_yuvpp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK4, cmucal_mux_clkcmu_cis_clk4_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF0, cmucal_mux_clkcmu_dpuf0_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF0_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF0_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST, cmucal_mux_clkcmu_cmu_boost_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_BUS, cmucal_mux_clkcmu_bus1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_CSIS, cmucal_mux_clkcmu_csis_csis_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP0_BUS, cmucal_mux_clkcmu_mcfp0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_BUS, cmucal_mux_clkcmu_mcsc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DNS_BUS, cmucal_mux_clkcmu_dns_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NPUS_BUS, cmucal_mux_clkcmu_npus_bus_parents, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_GDC, cmucal_mux_clkcmu_mcsc_gdc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_OIS_MCU, cmucal_mux_clkcmu_csis_ois_mcu_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_SSPCORE, cmucal_mux_clkcmu_ssp_sspcore_parents, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_SELECT, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_BUSY, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK5, cmucal_mux_clkcmu_cis_clk5_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST_CPU, cmucal_mux_clkcmu_cmu_boost_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_BUS, cmucal_mux_clkcmu_m2m_bus_parents, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB_ALT, cmucal_mux_clkcmu_dpub_alt_parents, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DPUB_BUS, cmucal_clkcmu_dpub_bus_parents, CLK_CON_MUX_CLKCMU_DPUB_BUS_SELECT, CLK_CON_MUX_CLKCMU_DPUB_BUS_BUSY, CLK_CON_MUX_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB, cmucal_mux_clkcmu_dpub_parents, CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC1_MFC1, cmucal_mux_clkcmu_mfc1_mfc1_parents, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_SBIC, cmucal_mux_clkcmu_bus1_sbic_parents, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_BUS, cmucal_mux_clkcmu_lme_bus_parents, CLK_CON_MUX_MUX_CLKCMU_LME_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_LME_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP1_MCFP1, cmucal_mux_clkcmu_mcfp1_mcfp1_parents, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VPC_BUS, cmucal_mux_clkcmu_vpc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS0_BUS, cmucal_mux_clkcmu_bus0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS2_BUS, cmucal_mux_clkcmu_bus2_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USB31DRD, cmucal_mux_clkcmu_hsi0_usb31drd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USBDP_DEBUG, cmucal_mux_clkcmu_hsi0_usbdp_debug_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_DPGTC, cmucal_mux_clkcmu_hsi0_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_BUS, cmucal_mux_clkcmu_aud_bus_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP1_ORBMCH, cmucal_mux_clkcmu_mcfp1_orbmch_parents, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_PDP, cmucal_mux_clkcmu_csis_pdp_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_UCPU_CLK, cmucal_mux_cp_ucpu_clk_parents, CLK_CON_MUX_MUX_CP_UCPU_CLK_SELECT, CLK_CON_MUX_MUX_CP_UCPU_CLK_BUSY, CLK_CON_MUX_MUX_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_LCPU_CLK, cmucal_mux_cp_lcpu_clk_parents, CLK_CON_MUX_MUX_CP_LCPU_CLK_SELECT, CLK_CON_MUX_MUX_CP_LCPU_CLK_BUSY, CLK_CON_MUX_MUX_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_HISPEEDY_CLK, cmucal_mux_cp_hispeedy_clk_parents, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP1, cmucal_mux_clkcmu_peric0_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP1, cmucal_mux_clkcmu_peric1_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_BUS, cmucal_mux_clkcmu_ssp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVPP_FRC, cmucal_mux_clkcmu_yuvpp_frc_parents, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_SELECT, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_BUSY, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_BUS, cmucal_mux_clkcmu_g3d_bus_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_G3D_SHADER, cmucal_clkcmu_g3d_shader_parents, CLK_CON_MUX_CLKCMU_G3D_SHADER_SELECT, CLK_CON_MUX_CLKCMU_G3D_SHADER_BUSY, CLK_CON_MUX_CLKCMU_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP0, cmucal_mux_clkcmu_peric2_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_BUS, cmucal_mux_clkcmu_peric2_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP1, cmucal_mux_clkcmu_peric2_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF1, cmucal_mux_clkcmu_dpuf1_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF1_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF1_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF1_ALT, cmucal_mux_clkcmu_dpuf1_alt_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DPUF1_BUS, cmucal_clkcmu_dpuf1_bus_parents, CLK_CON_MUX_CLKCMU_DPUF1_BUS_SELECT, CLK_CON_MUX_CLKCMU_DPUF1_BUS_BUSY, CLK_CON_MUX_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_BUSP, cmucal_mux_clkcmu_cpucl0_busp_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSU_SWITCH, cmucal_mux_clkcmu_dsu_switch_parents, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_MMC_CARD, cmucal_mux_clkcmu_hsi1_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_UFS_EMBD, cmucal_mux_clkcmu_hsi1_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CORE_CMUREF, cmucal_mux_core_cmuref_parents, CLK_CON_MUX_MUX_CORE_CMUREF_SELECT, CLK_CON_MUX_MUX_CORE_CMUREF_BUSY, CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL0_CMUREF, cmucal_mux_cpucl0_cmuref_parents, CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_CORE, cmucal_mux_clk_cpucl0_core_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_CORE_DELAY, cmucal_mux_clk_cpucl0_core_delay_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_PLL_CPUCL0_DELAY, cmucal_mux_pll_cpucl0_delay_parents, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_SELECT, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_BUSY, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_CORE, cmucal_mux_clk_cpucl1_core_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL1_CMUREF, cmucal_mux_cpucl1_cmuref_parents, CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL2_CMUREF, cmucal_mux_cpucl2_cmuref_parents, CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_CORE, cmucal_mux_clk_cpucl2_core_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_CLUSTER, cmucal_mux_clk_dsu_cluster_parents, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_SELECT, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_BUSY, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_DSU_CMUREF, cmucal_mux_dsu_cmuref_parents, CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_PLL_DSU_DELAY, cmucal_mux_pll_dsu_delay_parents, CLK_CON_MUX_MUX_PLL_DSU_DELAY_SELECT, CLK_CON_MUX_MUX_PLL_DSU_DELAY_BUSY, CLK_CON_MUX_MUX_PLL_DSU_DELAY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_CLUSTER_DELAY, cmucal_mux_clk_dsu_cluster_delay_parents, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_SELECT, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_BUSY, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_BUS, cmucal_mux_clk_g3d_bus_parents, CLK_CON_MUX_MUX_CLK_G3D_BUS_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUS_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_HSI0_BUS, cmucal_mux_clk_hsi0_bus_parents, CLK_CON_MUX_MUX_CLK_HSI0_BUS_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_BUS_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_HSI0_USB31DRD, cmucal_mux_clk_hsi0_usb31drd_parents, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_USI00_USI, cmucal_mux_clk_peric0_usi00_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_USI04_USI, cmucal_mux_clk_peric0_usi04_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_USI_I2C, cmucal_mux_clk_peric0_usi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_USI14_USI, cmucal_mux_clk_peric0_usi14_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI01_USI, cmucal_mux_clk_peric0_usi01_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI15_USI, cmucal_mux_clk_peric0_usi15_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI05_USI, cmucal_mux_clk_peric0_usi05_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI03_USI, cmucal_mux_clk_peric0_usi03_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_UART_DBG, cmucal_mux_clk_peric0_uart_dbg_parents, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI02_USI, cmucal_mux_clk_peric0_usi02_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC0_USI13_USI, cmucal_mux_clk_peric0_usi13_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_UART_BT, cmucal_mux_clk_peric1_uart_bt_parents, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI_I2C, cmucal_mux_clk_peric1_usi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI11_USI, cmucal_mux_clk_peric1_usi11_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI12_USI, cmucal_mux_clk_peric1_usi12_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI16_USI, cmucal_mux_clk_peric1_usi16_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI17_USI, cmucal_mux_clk_peric1_usi17_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC1_USI18_USI, cmucal_mux_clk_peric1_usi18_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI07_USI, cmucal_mux_clk_peric2_usi07_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI_I2C, cmucal_mux_clk_peric2_usi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI06_USI, cmucal_mux_clk_peric2_usi06_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI08_USI, cmucal_mux_clk_peric2_usi08_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI09_USI, cmucal_mux_clk_peric2_usi09_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_PERIC2_USI10_USI, cmucal_mux_clk_peric2_usi10_usi_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_S2D_CORE, cmucal_mux_clk_s2d_core_parents, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_VTS_DMIC_IF, cmucal_mux_clk_vts_dmic_if_parents, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_VTS_DMIC_AUD, cmucal_mux_clk_vts_dmic_aud_parents, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_VTS_SERIAL_LIF, cmucal_mux_clk_vts_serial_lif_parents, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_SELECT, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_VTS_DMIC_AHB, cmucal_mux_clk_vts_dmic_ahb_parents, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_VTS_SERIAL_LIF_CORE, cmucal_mux_clk_vts_serial_lif_core_parents, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_SELECT, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_BUSY, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(ALIVE_CMU_ALIVE_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(ALIVE_CMU_ALIVE_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(AUD_CMU_AUD_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(AUD_CMU_AUD_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS0_CMU_BUS0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS0_CMU_BUS0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS1_CMU_BUS1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS1_CMU_BUS1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS2_CMU_BUS2_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(BUS2_CMU_BUS2_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CMGP_CMU_CMGP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CMGP_CMU_CMGP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CMU_CMU_TOP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CMU_CMU_TOP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CORE_CMU_CORE_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CORE_CMU_CORE_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL2_CMU_CPUCL2_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CPUCL2_CMU_CPUCL2_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CSIS_CMU_CSIS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(CSIS_CMU_CSIS_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DNS_CMU_DNS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DNS_CMU_DNS_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUB_CMU_DPUB_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUB_CMU_DPUB_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF0_CMU_DPUF0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF0_CMU_DPUF0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF1_CMU_DPUF1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF1_CMU_DPUF1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DSU_CMU_DSU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DSU_CMU_DSU_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3D_CMU_G3D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3D_CMU_G3D_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3D_EMBEDDED_CMU_G3D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3D_EMBEDDED_CMU_G3D_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI0_CMU_HSI0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI0_CMU_HSI0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI1_CMU_HSI1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI1_CMU_HSI1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(ITP_CMU_ITP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(ITP_CMU_ITP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(LME_CMU_LME_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(LME_CMU_LME_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(M2M_CMU_M2M_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(M2M_CMU_M2M_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCFP0_CMU_MCFP0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCFP0_CMU_MCFP0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCFP1_CMU_MCFP1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCFP1_CMU_MCFP1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCSC_CMU_MCSC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCSC_CMU_MCSC_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC0_CMU_MFC0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC0_CMU_MFC0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC1_CMU_MFC1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC1_CMU_MFC1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MIF_CMU_MIF_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MIF_CMU_MIF_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU_CMU_NPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU_CMU_NPU_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU01_CMU_NPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU01_CMU_NPU_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU10_CMU_NPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPU10_CMU_NPU_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPUS_CMU_NPUS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NPUS_CMU_NPUS_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC2_CMU_PERIC2_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC2_CMU_PERIC2_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIS_CMU_PERIS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIS_CMU_PERIS_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SSP_CMU_SSP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SSP_CMU_SSP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SSP_EMBEDDED_CMU_SSP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SSP_EMBEDDED_CMU_SSP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(TAA_CMU_TAA_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(TAA_CMU_TAA_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(VPC_CMU_VPC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(VPC_CMU_VPC_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(VPD_CMU_VPD_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(VPD_CMU_VPD_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(VTS_CMU_VTS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(VTS_CMU_VTS_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(YUVPP_CMU_YUVPP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(YUVPP_CMU_YUVPP_CLKOUT1, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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CLK_MUX(OSCCTRL_RCO_400, cmucal_oscctrl_rco_400_parents, OSC_CON0_RCO_400_MUX_SEL, OSC_CON0_RCO_400_MUX_BUSY, OSC_CON1_RCO_400_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ALIVE_BUS_USER, cmucal_mux_clkcmu_alive_bus_user_parents, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_RCO_ALIVE_USER, cmucal_mux_clk_rco_alive_user_parents, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, cmucal_mux_clkmux_alive_rco_i3c_pmic_user_parents, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_CPU_USER, cmucal_mux_clkcmu_aud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_BUS_USER, cmucal_mux_clkcmu_aud_bus_user_parents, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_PCMC_CLK_USER, cmucal_mux_cp_pcmc_clk_user_parents, PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS0_BUS_USER, cmucal_mux_clkcmu_bus0_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_BUS_USER, cmucal_mux_clkcmu_bus1_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_SBIC_USER, cmucal_mux_clkcmu_bus1_sbic_user_parents, PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS2_BUS_USER, cmucal_mux_clkcmu_bus2_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_BUS_USER, cmucal_mux_clkcmu_cmgp_bus_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_PERI_USER, cmucal_mux_clkcmu_cmgp_peri_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_ADC_USER, cmucal_mux_clkcmu_cmgp_adc_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS_USER, cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_BUSP_USER, cmucal_mux_clkcmu_cpucl0_busp_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH_USER, cmucal_mux_clkcmu_cpucl2_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_CSIS_USER, cmucal_mux_clkcmu_csis_csis_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_OIS_MCU_USER, cmucal_mux_clkcmu_csis_ois_mcu_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_PDP_USER, cmucal_mux_clkcmu_csis_pdp_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DNS_BUS_USER, cmucal_mux_clkcmu_dns_bus_user_parents, PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DNS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB_BUS_USER, cmucal_mux_clkcmu_dpub_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF0_BUS_USER, cmucal_mux_clkcmu_dpuf0_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF1_BUS_USER, cmucal_mux_clkcmu_dpuf1_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSU_SWITCH_USER, cmucal_mux_clkcmu_dsu_switch_user_parents, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_BUS_USER, cmucal_mux_clkcmu_g3d_bus_user_parents, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER, cmucal_mux_clkcmu_embedded_g3d_shader_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_BUSY, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_SHADER_USER, cmucal_mux_clkcmu_g3d_shader_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, cmucal_mux_clkcmu_embedded_g3d_busd_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_BUSY, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_BUS_USER, cmucal_mux_clkcmu_hsi0_bus_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USB31DRD_USER, cmucal_mux_clkcmu_hsi0_usb31drd_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USBDP_DEBUG_USER, cmucal_mux_clkcmu_hsi0_usbdp_debug_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_DPGTC_USER, cmucal_mux_clkcmu_hsi0_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKAUD_HSI0_BUS_USER, cmucal_mux_clkaud_hsi0_bus_user_parents, PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_BUSY, PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKAUD_HSI0_USB31DRD_USER, cmucal_mux_clkaud_hsi0_usb31drd_user_parents, PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_BUSY, PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_USB20PHY_USER, cmucal_mux_clk_usb20phy_user_parents, PLL_CON0_MUX_CLK_USB20PHY_USER_MUX_SEL, PLL_CON0_MUX_CLK_USB20PHY_USER_BUSY, PLL_CON1_MUX_CLK_USB20PHY_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_BUS_USER, cmucal_mux_clkcmu_hsi1_bus_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_PCIE_USER, cmucal_mux_clkcmu_hsi1_pcie_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_MMC_CARD_USER, cmucal_mux_clkcmu_hsi1_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_UFS_EMBD_USER, cmucal_mux_clkcmu_hsi1_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ITP_BUS_USER, cmucal_mux_clkcmu_itp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ITP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_BUS_USER, cmucal_mux_clkcmu_lme_bus_user_parents, PLL_CON0_MUX_CLKCMU_LME_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_LME_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_LME_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_BUS_USER, cmucal_mux_clkcmu_m2m_bus_user_parents, PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_M2M_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP0_BUS_USER, cmucal_mux_clkcmu_mcfp0_bus_user_parents, PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP1_MCFP1_USER, cmucal_mux_clkcmu_mcfp1_mcfp1_user_parents, PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCFP1_ORBMCH_USER, cmucal_mux_clkcmu_mcfp1_orbmch_user_parents, PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_BUS_USER, cmucal_mux_clkcmu_mcsc_bus_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_GDC_USER, cmucal_mux_clkcmu_mcsc_gdc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_MFC0_USER, cmucal_mux_clkcmu_mfc0_mfc0_user_parents, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_WFD_USER, cmucal_mux_clkcmu_mfc0_wfd_user_parents, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLKCMU_MFC1_MFC1_USER, cmucal_mux_clkcmu_mfc1_mfc1_user_parents, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLKCMU_NPU_BUS_USER, cmucal_mux_clkcmu_npu_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NPU01_BUS_USER, cmucal_mux_clkcmu_npu01_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NPU10_BUS_USER, cmucal_mux_clkcmu_npu10_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NPUS_BUS_USER, cmucal_mux_clkcmu_npus_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_BUS_USER, cmucal_mux_clkcmu_peric0_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP0_USER, cmucal_mux_clkcmu_peric0_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP1_USER, cmucal_mux_clkcmu_peric0_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_BUS_USER, cmucal_mux_clkcmu_peric1_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP0_USER, cmucal_mux_clkcmu_peric1_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP1_USER, cmucal_mux_clkcmu_peric1_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP0_USER, cmucal_mux_clkcmu_peric2_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP1_USER, cmucal_mux_clkcmu_peric2_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_BUS_USER, cmucal_mux_clkcmu_peric2_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_BUS_USER, cmucal_mux_clkcmu_peris_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_MIF_DDRPHY2X_S2D, cmucal_clkcmu_mif_ddrphy2x_s2d_parents, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_BUS_USER, cmucal_mux_clkcmu_ssp_bus_user_parents, PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_SSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_SSPCORE_USER, cmucal_mux_clkcmu_ssp_sspcore_user_parents, PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_BUSY, PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_TAA_BUS_USER, cmucal_mux_clkcmu_taa_bus_user_parents, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VPC_BUS_USER, cmucal_mux_clkcmu_vpc_bus_user_parents, PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_VPC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VPD_BUS_USER, cmucal_mux_clkcmu_vpd_bus_user_parents, PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_VPD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_BUS_USER, cmucal_mux_clkcmu_vts_bus_user_parents, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKAUD_VTS_DMIC0_USER, cmucal_mux_clkaud_vts_dmic0_user_parents, PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_BUSY, PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKAUD_VTS_DMIC1_USER, cmucal_mux_clkaud_vts_dmic1_user_parents, PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_BUSY, PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_DMIC_USER, cmucal_mux_clkcmu_vts_dmic_user_parents, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_RCO_VTS_USER, cmucal_mux_clk_rco_vts_user_parents, PLL_CON0_MUX_CLK_RCO_VTS_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_VTS_USER_BUSY, PLL_CON1_MUX_CLK_RCO_VTS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVPP_BUS_USER, cmucal_mux_clkcmu_yuvpp_bus_user_parents, PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVPP_FRC_USER, cmucal_mux_clkcmu_yuvpp_frc_user_parents, PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_BUSY, PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_HCHGEN_CLK_AUD_CPU, cmucal_mux_hchgen_clk_aud_cpu_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_CORE_STR, cmucal_mux_clk_cpucl0_core_str_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_CORE_STR, cmucal_mux_clk_cpucl1_core_str_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_CORE_STR, cmucal_mux_clk_cpucl2_core_str_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_CLUSTER_STR, cmucal_mux_clk_dsu_cluster_str_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_BUSY, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_SHADER_STR, cmucal_mux_clk_g3d_shader_str_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_BUSY, CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIS_GIC, cmucal_mux_clk_peris_gic_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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};
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unsigned int cmucal_div_size = 214;
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struct cmucal_div cmucal_div_list[] = {
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CLK_DIV(CLKCMU_VTS_BUS, GATE_CLKCMU_VTS_BUS, CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY, CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_BUS, MUX_CLK_ALIVE_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMGP_BUS, GATE_CLKCMU_CMGP_BUS, CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_I3C_PMIC, MUX_CLK_ALIVE_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMGP_PERI, GATE_CLKCMU_CMGP_PERI, CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY, CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMGP_ADC, GATE_CLKCMU_CMGP_ADC, CLK_CON_DIV_CLKCMU_CMGP_ADC_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_ADC_BUSY, CLK_CON_DIV_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_DBGCORE_UART, MUX_CLK_ALIVE_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU, PLL_AUD0, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD0, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_DSIF, PLL_AUD1, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF3, MUX_CLK_AUD_UAIF3, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_BUS, PLL_AUD0, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_BUSP, MUX_CLK_AUD_BUS, CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CNT, MUX_CLK_AUD_CNT, CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF4, MUX_CLK_AUD_UAIF4, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF5, MUX_CLK_AUD_UAIF5, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_SCLK, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_SCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_SCLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_DMIC1, PLL_AUD1, CLK_CON_DIV_DIV_CLK_AUD_DMIC1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DMIC1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKAUD_VTS_DMIC0, GATE_CLKAUD_VTS_DMIC0, CLK_CON_DIV_CLKAUD_VTS_DMIC0_DIVRATIO, CLK_CON_DIV_CLKAUD_VTS_DMIC0_BUSY, CLK_CON_DIV_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKAUD_HSI0_BUS, GATE_CLKAUD_HSI0_BUS, CLK_CON_DIV_CLKAUD_HSI0_BUS_DIVRATIO, CLK_CON_DIV_CLKAUD_HSI0_BUS_BUSY, CLK_CON_DIV_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKAUD_HSI0_USB31DRD, GATE_CLKAUD_HSI0_USB31DRD, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_DIVRATIO, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_BUSY, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_PCMC, PLL_AUD0, CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BUS0_BUSP, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_DIV_DIV_CLK_BUS0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUS0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUS0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BUS1_BUSP, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BUS2_BUSP, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_DIV_DIV_CLK_BUS2_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUS2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUS2_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I2C0, MUX_CLK_CMGP_I2C0, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI1, MUX_CLK_CMGP_USI1, CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI0, MUX_CLK_CMGP_USI0, CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI2, MUX_CLK_CMGP_USI2, CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI3, MUX_CLK_CMGP_USI3, CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I2C1, MUX_CLK_CMGP_I2C1, CLK_CON_DIV_DIV_CLK_CMGP_I2C1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I2C2, MUX_CLK_CMGP_I2C2, CLK_CON_DIV_DIV_CLK_CMGP_I2C2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C2_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I2C3, MUX_CLK_CMGP_I2C3, CLK_CON_DIV_DIV_CLK_CMGP_I2C3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C3_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I3C, MUX_CLK_CMGP_I3C, CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ALIVE_BUS, GATE_CLKCMU_ALIVE_BUS, CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_BUS, GATE_CLKCMU_PERIC0_BUS, CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIS_BUS, GATE_CLKCMU_PERIS_BUS, CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF0_ALT, GATE_CLKCMU_DPUF0_BUS, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC0_MFC0, GATE_CLKCMU_MFC0_MFC0, CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY, CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_VPD_BUS, GATE_CLKCMU_VPD_BUS, CLK_CON_DIV_CLKCMU_VPD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VPD_BUS_BUSY, CLK_CON_DIV_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_BUS, GATE_CLKCMU_PERIC1_BUS, CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL2_SWITCH, GATE_CLKCMU_CPUCL2_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_TAA_BUS, GATE_CLKCMU_TAA_BUS, CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY, CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ITP_BUS, GATE_CLKCMU_ITP_BUS, CLK_CON_DIV_CLKCMU_ITP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ITP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_AUD_CPU, GATE_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_DBG_BUS, GATE_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST_MIF, MUX_CLKCMU_CMU_BOOST_MIF, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_NPU_BUS, GATE_CLKCMU_NPU_BUS, CLK_CON_DIV_CLKCMU_NPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC0_WFD, GATE_CLKCMU_MFC0_WFD, CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MIF_BUSP, GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_IP0, GATE_CLKCMU_PERIC0_IP0, CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_IP0, GATE_CLKCMU_PERIC1_IP0, CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF0, GATE_CLKCMU_DPUF0, CLK_CON_DIV_DIV_CLKCMU_DPUF0_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF0_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_BUS, GATE_CLKCMU_HSI0_BUS, CLK_CON_DIV_CLKCMU_HSI0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_BUS_BUSY, CLK_CON_DIV_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_YUVPP_BUS, GATE_CLKCMU_YUVPP_BUS, CLK_CON_DIV_CLKCMU_YUVPP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_YUVPP_BUS_BUSY, CLK_CON_DIV_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK4, GATE_CLKCMU_CIS_CLK4, CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST, MUX_CLKCMU_CMU_BOOST, CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUS1_BUS, GATE_CLKCMU_BUS1_BUS, CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_CSIS, GATE_CLKCMU_CSIS_CSIS, CLK_CON_DIV_CLKCMU_CSIS_CSIS_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_CSIS_BUSY, CLK_CON_DIV_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MCFP0_BUS, GATE_CLKCMU_MCFP0_BUS, CLK_CON_DIV_CLKCMU_MCFP0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MCFP0_BUS_BUSY, CLK_CON_DIV_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MCSC_BUS, GATE_CLKCMU_MCSC_BUS, CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DNS_BUS, GATE_CLKCMU_DNS_BUS, CLK_CON_DIV_CLKCMU_DNS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DNS_BUS_BUSY, CLK_CON_DIV_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_NPUS_BUS, GATE_CLKCMU_NPUS_BUS, CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI1_BUS, GATE_CLKCMU_HSI1_BUS, CLK_CON_DIV_CLKCMU_HSI1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_BUS_BUSY, CLK_CON_DIV_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MCSC_GDC, GATE_CLKCMU_MCSC_GDC, CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_OIS_MCU, GATE_CLKCMU_CSIS_OIS_MCU, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_SSP_SSPCORE, GATE_CLKCMU_SSP_SSPCORE, CLK_CON_DIV_CLKCMU_SSP_SSPCORE_DIVRATIO, CLK_CON_DIV_CLKCMU_SSP_SSPCORE_BUSY, CLK_CON_DIV_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK5, GATE_CLKCMU_CIS_CLK5, CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST_CPU, MUX_CLKCMU_CMU_BOOST_CPU, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_M2M_BUS, GATE_CLKCMU_M2M_BUS, CLK_CON_DIV_CLKCMU_M2M_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_M2M_BUS_BUSY, CLK_CON_DIV_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUB_ALT, GATE_CLKCMU_DPUB_BUS, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUB, GATE_CLKCMU_DPUB, CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC1_MFC1, GATE_CLKCMU_MFC1_MFC1, CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY, CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUS1_SBIC, GATE_CLKCMU_BUS1_SBIC, CLK_CON_DIV_CLKCMU_BUS1_SBIC_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS1_SBIC_BUSY, CLK_CON_DIV_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_LME_BUS, GATE_CLKCMU_LME_BUS, CLK_CON_DIV_CLKCMU_LME_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_LME_BUS_BUSY, CLK_CON_DIV_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MCFP1_MCFP1, GATE_CLKCMU_MCFP1_MCFP1, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_DIVRATIO, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_BUSY, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_VPC_BUS, GATE_CLKCMU_VPC_BUS, CLK_CON_DIV_CLKCMU_VPC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VPC_BUS_BUSY, CLK_CON_DIV_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUS0_BUS, GATE_CLKCMU_BUS0_BUS, CLK_CON_DIV_CLKCMU_BUS0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS0_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUS2_BUS, GATE_CLKCMU_BUS2_BUS, CLK_CON_DIV_CLKCMU_BUS2_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS2_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_USB31DRD, GATE_CLKCMU_HSI0_USB31DRD_CPY, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_DPGTC, GATE_CLKCMU_HSI0_DPGTC_CPY, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_AUD_BUS, GATE_CLKCMU_AUD_BUS, CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY, CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MCFP1_ORBMCH, GATE_CLKCMU_MCFP1_ORBMCH, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_DIVRATIO, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_BUSY, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_PDP, GATE_CLKCMU_CSIS_PDP, CLK_CON_DIV_CLKCMU_CSIS_PDP_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_PDP_BUSY, CLK_CON_DIV_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CP_SHARED0_CLK, GATE_CP_SHARED0_CLK, CLK_CON_DIV_CP_SHARED0_CLK_DIVRATIO, CLK_CON_DIV_CP_SHARED0_CLK_BUSY, CLK_CON_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CP_SHARED1_CLK, GATE_CP_SHARED1_CLK, CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO, CLK_CON_DIV_CP_SHARED1_CLK_BUSY, CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CP_SHARED2_CLK, GATE_CP_SHARED2_CLK, CLK_CON_DIV_CP_SHARED2_CLK_DIVRATIO, CLK_CON_DIV_CP_SHARED2_CLK_BUSY, CLK_CON_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CP_HISPEEDY_CLK, GATE_CP_HISPEEDY_CLK, CLK_CON_DIV_CP_HISPEEDY_CLK_DIVRATIO, CLK_CON_DIV_CP_HISPEEDY_CLK_BUSY, CLK_CON_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_IP1, GATE_CLKCMU_PERIC0_IP1, CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_IP1, GATE_CLKCMU_PERIC1_IP1, CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_SSP_BUS, GATE_CLKCMU_SSP_BUS, CLK_CON_DIV_CLKCMU_SSP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_SSP_BUS_BUSY, CLK_CON_DIV_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_YUVPP_FRC, GATE_CLKCMU_YUVPP_FRC, CLK_CON_DIV_CLKCMU_YUVPP_FRC_DIVRATIO, CLK_CON_DIV_CLKCMU_YUVPP_FRC_BUSY, CLK_CON_DIV_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_G3D_BUS, GATE_CLKCMU_G3D_BUS, CLK_CON_DIV_CLKCMU_G3D_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_BUS_BUSY, CLK_CON_DIV_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_BUS, GATE_CLKCMU_PERIC2_BUS, CLK_CON_DIV_CLKCMU_PERIC2_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_IP0, GATE_CLKCMU_PERIC2_IP0, CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_IP1, GATE_CLKCMU_PERIC2_IP1, CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF1, GATE_CLKCMU_DPUF1, CLK_CON_DIV_DIV_CLKCMU_DPUF1_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF1_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF1_ALT, GATE_CLKCMU_DPUF1_BUS, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_BUSP, GATE_CLKCMU_CPUCL0_BUSP, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DSU_SWITCH, GATE_CLKCMU_DSU_SWITCH, CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI1_MMC_CARD, GATE_CLKCMU_HSI1_MMC_CARD, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI1_UFS_EMBD, GATE_CLKCMU_HSI1_UFS_EMBD, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_SHORTSTOP_CORE, DIV_CLK_CPUCL0_CORE, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_DBG_BUS, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_DBG_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_SHORTSTOP_CORE, DIV_CLK_CPUCL1_CORE, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_HTU, MUX_CLK_CPUCL1_CORE, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL2_SHORTSTOP_CORE, DIV_CLK_CPUCL2_CORE, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL2_HTU, MUX_CLK_CPUCL2_CORE, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSIS_BUSP, DIV_CLK_CSIS_CSIS, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DNS_BUSP, DIV_CLK_DNS_BUS, CLK_CON_DIV_DIV_CLK_DNS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DNS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DNS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUB_BUSP, MUX_CLKCMU_DPUB_BUS_USER, CLK_CON_DIV_DIV_CLK_DPUB_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUB_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPUB_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUF0_BUSP, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUF1_BUSP, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSU_SHORTSTOP_CLUSTER, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_BUSY, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_ACLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_PCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_PERIPHCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_ATCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_BCLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUS, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ITP_BUSP, DIV_CLK_ITP_BUS, CLK_CON_DIV_DIV_CLK_ITP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ITP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ITP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_LME_BUSP, DIV_CLK_LME_BUS, CLK_CON_DIV_DIV_CLK_LME_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_LME_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_LME_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_M2M_BUSP, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCFP0_BUSP, DIV_CLK_MCFP0_BUS, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCFP1_BUSP, DIV_CLK_MCFP1_MCFP1, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_BUSP, DIV_CLK_MCSC_BUS, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC0_BUSP, DIV_CLK_MFC0_MFC0, CLK_CON_DIV_DIV_CLK_MFC0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC1_BUSP, DIV_CLK_MFC1_MFC1, CLK_CON_DIV_DIV_CLK_MFC1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU_BUSP, DIV_CLK_NPU_BUS, CLK_CON_DIV_DIV_CLK_NPU_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPU_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU01_BUSP, DIV_CLK_NPU01_BUS, CLK_CON_DIV_DIV_CLK_NPU01_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPU01_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPU01_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU10_BUSP, DIV_CLK_NPU10_BUS, CLK_CON_DIV_DIV_CLK_NPU10_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPU10_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPU10_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPUS_BUSP, DIV_CLK_NPUS_BUS, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI00_USI, MUX_CLK_PERIC0_USI00_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI01_USI, MUX_CLK_PERIC0_USI01_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI02_USI, MUX_CLK_PERIC0_USI02_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI03_USI, MUX_CLK_PERIC0_USI03_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI04_USI, MUX_CLK_PERIC0_USI04_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI05_USI, MUX_CLK_PERIC0_USI05_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI_I2C, MUX_CLK_PERIC0_USI_I2C, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_UART_DBG, MUX_CLK_PERIC0_UART_DBG, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI13_USI, MUX_CLK_PERIC0_USI13_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI14_USI, MUX_CLK_PERIC0_USI14_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI15_USI, MUX_CLK_PERIC0_USI15_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_UART_BT, MUX_CLK_PERIC1_UART_BT, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI_I2C, MUX_CLK_PERIC1_USI_I2C, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI18_USI, MUX_CLK_PERIC1_USI18_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI12_USI, MUX_CLK_PERIC1_USI12_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI11_USI, MUX_CLK_PERIC1_USI11_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI16_USI, MUX_CLK_PERIC1_USI16_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI17_USI, MUX_CLK_PERIC1_USI17_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI08_USI, MUX_CLK_PERIC2_USI08_USI, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI_I2C, MUX_CLK_PERIC2_USI_I2C, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI06_USI, MUX_CLK_PERIC2_USI06_USI, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI07_USI, MUX_CLK_PERIC2_USI07_USI, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI09_USI, MUX_CLK_PERIC2_USI09_USI, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI10_USI, MUX_CLK_PERIC2_USI10_USI, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIS_BUSP, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_DIV_DIV_CLK_PERIS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_PERIS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_SSP_BUSP, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_DIV_DIV_CLK_SSP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_SSP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_SSP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_TAA_BUSP, DIV_CLK_TAA_BUS, CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VPC_BUSP, DIV_CLK_VPC_BUS, CLK_CON_DIV_DIV_CLK_VPC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VPC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VPC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VPD_BUSP, DIV_CLK_VPD_BUS, CLK_CON_DIV_DIV_CLK_VPD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VPD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VPD_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_IF, MUX_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_BUS, MUX_CLKCMU_VTS_BUS_USER, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_AUD, MUX_CLK_VTS_DMIC_AUD, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_AUD_DIV2, DIV_CLK_VTS_DMIC_AUD, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_SERIAL_LIF, MUX_CLK_VTS_SERIAL_LIF, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_AHB, MUX_CLK_VTS_DMIC_AHB, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_SERIAL_LIF_CORE, MUX_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_YUVPP_BUSP, DIV_CLK_YUVPP_BUS, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_CORE, MUX_CLK_CPUCL0_CORE, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CORE, MUX_CLK_CPUCL1_CORE, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL2_CORE, MUX_CLK_CPUCL2_CORE, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSIS_CSIS, MUX_CLKCMU_CSIS_CSIS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CSIS_CSIS_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSIS_PDP, MUX_CLKCMU_CSIS_PDP_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CSIS_PDP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DNS_BUS, MUX_CLKCMU_DNS_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DNS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSU_CLUSTER, MUX_CLK_DSU_CLUSTER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_SHADER, MUX_CLK_G3D_SHADER_STR, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_SHADER_BUSY, CLK_CON_DIV_DIV_CLK_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_BUSD, MUX_CLK_G3D_BUS, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ITP_BUS, MUX_CLKCMU_ITP_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_ITP_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_LME_BUS, MUX_CLKCMU_LME_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_LME_BUS_BUSY, CLK_CON_DIV_DIV_CLK_LME_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCFP0_BUS, MUX_CLKCMU_MCFP0_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCFP0_BUS_BUSY, CLK_CON_DIV_DIV_CLK_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCFP1_MCFP1, MUX_CLKCMU_MCFP1_MCFP1_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_BUSY, CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCFP1_ORBMCH, MUX_CLKCMU_MCFP1_ORBMCH_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_BUSY, CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_BUS, MUX_CLKCMU_MCSC_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCSC_BUS_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_GDC, MUX_CLKCMU_MCSC_GDC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCSC_GDC_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC0_MFC0, MUX_CLKCMU_MFC0_MFC0_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MFC0_MFC0_BUSY, CLK_CON_DIV_DIV_CLK_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC1_MFC1, MUX_CLKCMU_MFC1_MFC1_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MFC1_MFC1_BUSY, CLK_CON_DIV_DIV_CLK_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU_BUS, MUX_CLKCMU_NPU_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPU_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU01_BUS, MUX_CLKCMU_NPU01_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPU01_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPU01_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPU10_BUS, MUX_CLKCMU_NPU10_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPU10_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPU10_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NPUS_BUS, MUX_CLKCMU_NPUS_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_TAA_BUS, MUX_CLKCMU_TAA_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_TAA_BUS_BUSY, CLK_CON_DIV_DIV_CLK_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VPC_BUS, MUX_CLKCMU_VPC_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_VPC_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VPD_BUS, MUX_CLKCMU_VPD_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_VPD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_YUVPP_BUS, MUX_CLKCMU_YUVPP_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_YUVPP_BUS_BUSY, CLK_CON_DIV_DIV_CLK_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_YUVPP_FRC, MUX_CLKCMU_YUVPP_FRC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_YUVPP_FRC_BUSY, CLK_CON_DIV_DIV_CLK_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING),
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};
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unsigned int cmucal_gate_size = 1797;
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struct cmucal_gate cmucal_gate_list[] = {
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK, OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMGP_BUS, MUX_CLKCMU_CMGP_BUS, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK, MUX_CLK_ALIVE_I3C_PMIC, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK, MUX_CLK_ALIVE_I3C_PMIC, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMGP_PERI, MUX_CLKCMU_CMGP_PERI, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMGP_ADC, MUX_CLKCMU_CMGP_ADC, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_VTS_DMIC, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKCMU_VTS_DMIC_CG_VAL, CLK_CON_GAT_CLKCMU_VTS_DMIC_MANUAL, CLK_CON_GAT_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, MUX_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, MUX_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK, OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, DIV_CLK_AUD_CNT, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK, DIV_CLK_AUD_CNT, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK, DIV_CLK_AUD_SCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK, DIV_CLK_AUD_SCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKAUD_VTS_DMIC1, DIV_CLK_AUD_DMIC1, CLK_CON_GAT_CLKAUD_VTS_DMIC1_CG_VAL, CLK_CON_GAT_CLKAUD_VTS_DMIC1_MANUAL, CLK_CON_GAT_CLKAUD_VTS_DMIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKAUD_VTS_DMIC0, PLL_AUD0, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_MANUAL, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKAUD_HSI0_BUS, PLL_AUD0, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKAUD_HSI0_USB31DRD, PLL_AUD0, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_MANUAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, MUX_CLK_AUD_PCMC, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, MUX_CLK_AUD_PCMC, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK, MUX_CLKCMU_BUS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, DIV_CLK_BUS0_BUSP, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_SBIC_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_SBIC_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM, MUX_CLKCMU_BUS1_SBIC_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_SBIC_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS2_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK, DIV_CLK_BUS2_BUSP, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CMGP, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK, CLK_CMGP_ADC, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK, DIV_CLK_CMGP_I3C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK, DIV_CLK_CMGP_I3C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK, MUX_CLKCMU_CMGP_BUS_USER, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ALIVE_BUS, MUX_CLKCMU_ALIVE_BUS, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_MIF01_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC0_MFC0, MUX_CLKCMU_MFC0_MFC0, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_BUS, MUX_CLKCMU_HSI1_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF0_BUS, MUX_CLKCMU_DPUF0_ALT, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_VPD_BUS, MUX_CLKCMU_VPD_BUS, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL2_SWITCH, MUX_CLKCMU_CPUCL2_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_TAA_BUS, MUX_CLKCMU_TAA_BUS, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ITP_BUS, MUX_CLKCMU_ITP_BUS, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_CPU, MUX_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_PCIE, MUX_CLKCMU_HSI1_PCIE, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_BUS, MUX_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NPU_BUS, MUX_CLKCMU_NPU_BUS, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC0_WFD, MUX_CLKCMU_MFC0_WFD, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MIF_BUSP, MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_IP0, MUX_CLKCMU_PERIC0_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_IP0, MUX_CLKCMU_PERIC1_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF0, MUX_CLKCMU_DPUF0, CLK_CON_GAT_GATE_CLKCMU_DPUF0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_BUS, MUX_CLKCMU_HSI0_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_YUVPP_BUS, MUX_CLKCMU_YUVPP_BUS, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK4, MUX_CLKCMU_CIS_CLK4, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_CSIS, MUX_CLKCMU_CSIS_CSIS, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCFP0_BUS, MUX_CLKCMU_MCFP0_BUS, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_BUS, MUX_CLKCMU_MCSC_BUS, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DNS_BUS, MUX_CLKCMU_DNS_BUS, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NPUS_BUS, MUX_CLKCMU_NPUS_BUS, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_GDC, MUX_CLKCMU_MCSC_GDC, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_OIS_MCU, MUX_CLKCMU_CSIS_OIS_MCU, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_SSP_SSPCORE, MUX_CLKCMU_SSP_SSPCORE, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK5, MUX_CLKCMU_CIS_CLK5, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_M2M_BUS, MUX_CLKCMU_M2M_BUS, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUB_BUS, MUX_CLKCMU_DPUB_ALT, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUB, MUX_CLKCMU_DPUB, CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC1_MFC1, MUX_CLKCMU_MFC1_MFC1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUS1_SBIC, MUX_CLKCMU_BUS1_SBIC, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_LME_BUS, MUX_CLKCMU_LME_BUS, CLK_CON_GAT_GATE_CLKCMU_LME_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_LME_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCFP1_MCFP1, MUX_CLKCMU_MCFP1_MCFP1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_VPC_BUS, MUX_CLKCMU_VPC_BUS, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUS0_BUS, MUX_CLKCMU_BUS0_BUS, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUS2_BUS, MUX_CLKCMU_BUS2_BUS, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY, MUX_CLKCMU_HSI0_USBDP_DEBUG, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_USB31DRD_CPY, MUX_CLKCMU_HSI0_USB31DRD, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_DPGTC_CPY, MUX_CLKCMU_HSI0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_BUS, MUX_CLKCMU_AUD_BUS, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCFP1_ORBMCH, MUX_CLKCMU_MCFP1_ORBMCH, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_PDP, MUX_CLKCMU_CSIS_PDP, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CP_UCPU_CLK, MUX_CP_UCPU_CLK, CLK_CON_GAT_CP_UCPU_CLK_CG_VAL, CLK_CON_GAT_CP_UCPU_CLK_MANUAL, CLK_CON_GAT_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CP_LCPU_CLK, MUX_CP_LCPU_CLK, CLK_CON_GAT_CP_LCPU_CLK_CG_VAL, CLK_CON_GAT_CP_LCPU_CLK_MANUAL, CLK_CON_GAT_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED0_CLK, PLL_SHARED2, CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED1_CLK, PLL_SHARED3, CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED2_CLK, PLL_SHARED4, CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_HISPEEDY_CLK, MUX_CP_HISPEEDY_CLK, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_IP1, MUX_CLKCMU_PERIC0_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_IP1, MUX_CLKCMU_PERIC1_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_SSP_BUS, MUX_CLKCMU_SSP_BUS, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_YUVPP_FRC, MUX_CLKCMU_YUVPP_FRC, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_BUS, MUX_CLKCMU_G3D_BUS, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_IP0, MUX_CLKCMU_PERIC2_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_BUS, MUX_CLKCMU_PERIC2_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_IP1, MUX_CLKCMU_PERIC2_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_MIF23_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF1_BUS, MUX_CLKCMU_DPUF1_ALT, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF1, MUX_CLKCMU_DPUF1, CLK_CON_GAT_GATE_CLKCMU_DPUF1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_BUSP, MUX_CLKCMU_CPUCL0_BUSP, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSU_SWITCH, MUX_CLKCMU_DSU_SWITCH, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_UFS_EMBD, MUX_CLKCMU_HSI1_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_MMC_CARD, MUX_CLKCMU_HSI1_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, OSCCLK_CORE, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK, CLK_CPUCL0_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN, MUX_CLK_CPUCL0_CORE, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CLUSTER_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_BUS, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0_GLB, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK, CLK_CPUCL0_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK, DIV_CLK_CPUCL1_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2, MUX_CLK_CPUCL1_CORE, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK, CLK_CPUCL0_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK, DIV_CLK_CPUCL2_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK, DIV_CLK_CPUCL2_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN, MUX_CLK_CPUCL2_CORE, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK, OSCCLK_CSIS, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_PDP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1, DIV_CLK_CSIS_CSIS, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK, DIV_CLK_DNS_BUSP, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2, DIV_CLK_DNS_BUS, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_BUSP, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK, DIV_CLK_DPUB_BUSP, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_BUSP, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_BUSP, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DPUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK, DIV_CLK_DPUB_BUSP, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK, DIV_CLK_DPUF0_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF0_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK, DIV_CLK_DPUF1_BUSP, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_CLUSTER_PCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, DIV_CLK_DSU_CLUSTER, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE, MUX_CLK_DSU_CLUSTER, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK, MUX_CLK_DSU_CLUSTER, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_BCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_BCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_BCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, CLK_G3D_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_G3D_SHADER_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, MUX_CLKCMU_HSI0_USBDP_DEBUG_USER, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, MUX_CLK_HSI0_USB31DRD, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, MUX_CLKCMU_HSI0_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_BUS, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_HSI1_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_HSI1_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_HSI1_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, OSCCLK_HSI1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK, DIV_CLK_ITP_BUSP, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK, DIV_CLK_ITP_BUS, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK, DIV_CLK_LME_BUSP, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK, DIV_CLK_LME_BUS, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, MUX_CLKCMU_M2M_BUS_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK, OSCCLK_MCFP0, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK, DIV_CLK_MCFP0_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP0_BUS, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK, DIV_CLK_MCFP1_MCFP1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK, DIV_CLK_MCFP1_ORBMCH, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK, DIV_CLK_MCFP1_BUSP, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK, CLK_MCSC_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK, OSCCLK_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S, DIV_CLK_MCSC_GDC, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK, DIV_CLK_MCSC_BUS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_BUSP, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK, DIV_CLK_MFC0_MFC0, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC1_BUSP, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_MFC1_MFC1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, DIV_CLK_NPU_BUS, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU_BUSP, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, DIV_CLK_NPU01_BUS, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU01_BUSP, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, DIV_CLK_NPU10_BUS, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, DIV_CLK_NPU10_BUSP, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK, OSCCLK_NPUS, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK, CLK_NPUS_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIC0, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, DIV_CLK_PERIC0_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI13_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI15_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, DIV_CLK_PERIC0_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, DIV_CLK_PERIC0_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, DIV_CLK_PERIC0_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, DIV_CLK_PERIC0_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, DIV_CLK_PERIC0_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, DIV_CLK_PERIC0_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, DIV_CLK_PERIC0_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, DIV_CLK_PERIC0_USI13_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, DIV_CLK_PERIC0_USI15_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI16_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI17_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, DIV_CLK_PERIC1_USI16_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, DIV_CLK_PERIC1_USI17_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIC1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, DIV_CLK_PERIC1_USI12_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, DIV_CLK_PERIC1_USI18_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI12_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI18_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14, DIV_CLK_PERIC2_USI08_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12, DIV_CLK_PERIC2_USI07_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10, DIV_CLK_PERIC2_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIC2, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI07_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI08_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI09_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI10_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0, DIV_CLK_PERIC2_USI09_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2, DIV_CLK_PERIC2_USI10_USI, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3, DIV_CLK_PERIC2_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3, MUX_CLKCMU_PERIC2_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK, DIV_CLK_PERIS_BUSP, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, I_SCLK_S2D, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, I_SCLK_S2D, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK, OSCCLK_SSP, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK, MUX_CLKCMU_SSP_SSPCORE_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_SSPCORE_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM, MUX_CLKCMU_SSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_BUSP, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK, OSCCLK_TAA, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK, CLK_TAA_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK, DIV_CLK_TAA_BUS, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK, OSCCLK_VPC, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK, CLK_VPC_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN, MUX_CLKCMU_VPC_BUS_USER, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK, DIV_CLK_VPC_BUSP, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK, DIV_CLK_VPC_BUS, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK, DIV_CLK_VPD_BUSP, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK, DIV_CLK_VPD_BUSP, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK, DIV_CLK_VPD_BUSP, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK, DIV_CLK_VPD_BUSP, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK, DIV_CLK_VPD_BUSP, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK, DIV_CLK_VPD_BUS, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_VTS, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, DIV_CLK_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, DIV_CLK_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK, DIV_CLK_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2, DIV_CLK_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C, MUX_CLK_RCO_VTS_USER, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_DMIC_AHB, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK, DIV_CLK_YUVPP_FRC, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_FRC, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM, DIV_CLK_YUVPP_FRC, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK, DIV_CLK_YUVPP_BUS, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK, DIV_CLK_YUVPP_BUSP, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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};
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unsigned int cmucal_fixed_rate_size = 66;
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struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = {
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FIXEDRATE(OSCCLK_RCO_ALIVE, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_400, 393216000, EMPTY_CAL_ID),// if it need?
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FIXEDRATE(OSCCLK_ALIVE, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_ALIVE, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_I3C_PMIC, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(RTCCLK_ALIVE, 32768, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_AUD, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK0, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK1, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK2, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK3, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(CLKIO_AUD_DSIF, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK4, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK5, 10000000, EMPTY_CAL_ID),
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FIXEDRATE(AUDIO_LIF_BCLKI, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_BUS0, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_BUS1, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_BUS2, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CMGP, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_RCO_CMGP, 24576000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(STRETCHER_CLK_CPUCL0, 1200000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL0_GLB, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(STRETCHER_CLK_CPUCL1, 1500000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL2, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(STRETCHER_CLK_CPUCL2, 1600000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CSIS, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DNS, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DPUB, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DPUF0, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DPUF1, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DSU, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(STRETCHER_CLK_DSU, 1100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(STRETCHER_CLK_G3D, 160000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_HSI0, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(CLK_USB20PHY, 60000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_HSI1, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_ITP, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_LME, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_M2M, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MCFP0, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MCFP1, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MCSC, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MFC0, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MFC1, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NPU, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NPUS, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIC0, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIC1, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIC2, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIS, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_S2D, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(I_SCLK_S2D, 6500000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_SSP, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_TAA, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_VPC, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_VPD, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_RCO_VTS, 24576000, EMPTY_CAL_ID),
|
|
FIXEDRATE(CLK_RCO_VTS, 49152000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_YUVPP, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(CP_PCMC_CLK, 49152000, EMPTY_CAL_ID),
|
|
};
|
|
|
|
unsigned int cmucal_fixed_factor_size = 18;
|
|
struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = {
|
|
FIXEDFACTOR(CLKCMU_HSI1_PCIE, GATE_CLKCMU_HSI1_PCIE, 7, CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLKCMU_HSI0_USBDP_DEBUG, GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY, 7, CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL0_ADD_CH_CLK, OSCCLK_CPUCL0_GLB, 11, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_G3D_ADD_CH_CLK, OSCCLK_G3D, 11, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_HSI0_USB31DRD, MUX_CLK_USB20PHY_USER, 2, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_MCSC_ADD_CH_CLK, OSCCLK_MCSC, 11, CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_MIF_BUSD, CLKMUX_MIF_DDRPHY2X, 3, CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_NPUS_ADD_CH_CLK, OSCCLK_NPUS, 11, CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLKCMU_OTP, OSCCLK_PERIS, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_MIF_BUSD_S2D, CLKCMU_MIF_DDRPHY2X_S2D, 3, CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_TAA_ADD_CH_CLK, OSCCLK_TAA, 11, CLK_CON_DIV_CLK_TAA_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_VPC_ADD_CH_CLK, OSCCLK_VPC, 11, CLK_CON_DIV_CLK_VPC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(PLL_SHARED0_D2, PLL_SHARED0, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED1_D2, PLL_SHARED1, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED2_D2, PLL_SHARED2, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED3_D2, PLL_SHARED3, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED4_D2, PLL_SHARED4, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED_MIF_D2, PLL_SHARED_MIF, 1, EMPTY_CAL_ID),
|
|
};
|
|
|