9b478dd1ae
[ Upstream commit 10b6b4a8ac6120ec36555fd286eed577f7632e3b ] Picasso was the first APU that introduced s2idle support from AMD, and it was predating before vendors started to use `StorageD3Enable` in their firmware. Windows doesn't have problems with this hardware and NVME so it was likely on the list of hardcoded CPUs to use this behavior in Windows. Add it to the list for Linux to avoid NVME resume issues. Reported-by: Stuart Axon <stuaxo2@yahoo.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2449 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Stable-dep-of: e79a10652bbd ("ACPI: x86: Force StorageD3Enable on more products") Signed-off-by: Sasha Levin <sashal@kernel.org>
217 lines
7.7 KiB
C
Executable file
217 lines
7.7 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* X86 ACPI Utility Functions
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*
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
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*/
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include "../internal.h"
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/*
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* Some ACPI devices are hidden (status == 0x0) in recent BIOS-es because
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* some recent Windows drivers bind to one device but poke at multiple
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* devices at the same time, so the others get hidden.
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*
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* Some BIOS-es (temporarily) hide specific APCI devices to work around Windows
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* driver bugs. We use DMI matching to match known cases of this.
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*
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* Likewise sometimes some not-actually present devices are sometimes
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* reported as present, which may cause issues.
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*
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* We work around this by using the below quirk list to override the status
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* reported by the _STA method with a fixed value (ACPI_STA_DEFAULT or 0).
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* Note this MUST only be done for devices where this is safe.
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*
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* This status overriding is limited to specific CPU (SoC) models both to
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* avoid potentially causing trouble on other models and because some HIDs
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* are re-used on different SoCs for completely different devices.
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*/
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struct override_status_id {
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struct acpi_device_id hid[2];
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struct x86_cpu_id cpu_ids[2];
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struct dmi_system_id dmi_ids[2]; /* Optional */
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const char *uid;
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const char *path;
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unsigned long long status;
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};
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#define ENTRY(status, hid, uid, path, cpu_model, dmi...) { \
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{ { hid, }, {} }, \
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{ X86_MATCH_INTEL_FAM6_MODEL(cpu_model, NULL), {} }, \
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{ { .matches = dmi }, {} }, \
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uid, \
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path, \
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status, \
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}
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#define PRESENT_ENTRY_HID(hid, uid, cpu_model, dmi...) \
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ENTRY(ACPI_STA_DEFAULT, hid, uid, NULL, cpu_model, dmi)
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#define NOT_PRESENT_ENTRY_HID(hid, uid, cpu_model, dmi...) \
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ENTRY(0, hid, uid, NULL, cpu_model, dmi)
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#define PRESENT_ENTRY_PATH(path, cpu_model, dmi...) \
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ENTRY(ACPI_STA_DEFAULT, "", NULL, path, cpu_model, dmi)
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#define NOT_PRESENT_ENTRY_PATH(path, cpu_model, dmi...) \
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ENTRY(0, "", NULL, path, cpu_model, dmi)
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static const struct override_status_id override_status_ids[] = {
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/*
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* Bay / Cherry Trail PWM directly poked by GPU driver in win10,
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* but Linux uses a separate PWM driver, harmless if not used.
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*/
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PRESENT_ENTRY_HID("80860F09", "1", ATOM_SILVERMONT, {}),
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PRESENT_ENTRY_HID("80862288", "1", ATOM_AIRMONT, {}),
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/*
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* The INT0002 device is necessary to clear wakeup interrupt sources
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* on Cherry Trail devices, without it we get nobody cared IRQ msgs.
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*/
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PRESENT_ENTRY_HID("INT0002", "1", ATOM_AIRMONT, {}),
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/*
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* On the Dell Venue 11 Pro 7130 and 7139, the DSDT hides
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* the touchscreen ACPI device until a certain time
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* after _SB.PCI0.GFX0.LCD.LCD1._ON gets called has passed
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* *and* _STA has been called at least 3 times since.
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*/
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PRESENT_ENTRY_HID("SYNA7500", "1", HASWELL_L, {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7130"),
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}),
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PRESENT_ENTRY_HID("SYNA7500", "1", HASWELL_L, {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7139"),
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}),
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/*
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* The GPD win BIOS dated 20170221 has disabled the accelerometer, the
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* drivers sometimes cause crashes under Windows and this is how the
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* manufacturer has solved this :| The DMI match may not seem unique,
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* but it is. In the 67000+ DMI decode dumps from linux-hardware.org
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* only 116 have board_vendor set to "AMI Corporation" and of those 116
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* only the GPD win and pocket entries' board_name is "Default string".
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*
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* Unfortunately the GPD pocket also uses these strings and its BIOS
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* was copy-pasted from the GPD win, so it has a disabled KIOX000A
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* node which we should not enable, thus we also check the BIOS date.
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*/
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PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "02/21/2017")
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}),
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PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "03/20/2017")
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}),
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PRESENT_ENTRY_HID("KIOX000A", "1", ATOM_AIRMONT, {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "05/25/2017")
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}),
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/*
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* The GPD win/pocket have a PCI wifi card, but its DSDT has the SDIO
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* mmc controller enabled and that has a child-device which _PS3
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* method sets a GPIO causing the PCI wifi card to turn off.
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* See above remark about uniqueness of the DMI match.
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*/
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NOT_PRESENT_ENTRY_PATH("\\_SB_.PCI0.SDHB.BRC1", ATOM_AIRMONT, {
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DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"),
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DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
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}),
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};
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bool acpi_device_override_status(struct acpi_device *adev, unsigned long long *status)
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{
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bool ret = false;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(override_status_ids); i++) {
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if (!x86_match_cpu(override_status_ids[i].cpu_ids))
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continue;
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if (override_status_ids[i].dmi_ids[0].matches[0].slot &&
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!dmi_check_system(override_status_ids[i].dmi_ids))
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continue;
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if (override_status_ids[i].path) {
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struct acpi_buffer path = { ACPI_ALLOCATE_BUFFER, NULL };
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bool match;
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if (acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &path))
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continue;
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match = strcmp((char *)path.pointer, override_status_ids[i].path) == 0;
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kfree(path.pointer);
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if (!match)
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continue;
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} else {
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if (acpi_match_device_ids(adev, override_status_ids[i].hid))
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continue;
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if (!adev->pnp.unique_id ||
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strcmp(adev->pnp.unique_id, override_status_ids[i].uid))
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continue;
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}
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*status = override_status_ids[i].status;
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ret = true;
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break;
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}
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return ret;
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}
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/*
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* AMD systems from Renoir and Lucienne *require* that the NVME controller
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* is put into D3 over a Modern Standby / suspend-to-idle cycle.
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*
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* This is "typically" accomplished using the `StorageD3Enable`
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* property in the _DSD that is checked via the `acpi_storage_d3` function
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* but this property was introduced after many of these systems launched
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* and most OEM systems don't have it in their BIOS.
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*
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* The Microsoft documentation for StorageD3Enable mentioned that Windows has
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* a hardcoded allowlist for D3 support, which was used for these platforms.
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*
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* This allows quirking on Linux in a similar fashion.
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*
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* Cezanne systems shouldn't *normally* need this as the BIOS includes
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* StorageD3Enable. But for two reasons we have added it.
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* 1) The BIOS on a number of Dell systems have ambiguity
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* between the same value used for _ADR on ACPI nodes GPP1.DEV0 and GPP1.NVME.
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* GPP1.NVME is needed to get StorageD3Enable node set properly.
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* https://bugzilla.kernel.org/show_bug.cgi?id=216440
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* https://bugzilla.kernel.org/show_bug.cgi?id=216773
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* https://bugzilla.kernel.org/show_bug.cgi?id=217003
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* 2) On at least one HP system StorageD3Enable is missing on the second NVME
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disk in the system.
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*/
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static const struct x86_cpu_id storage_d3_cpu_ids[] = {
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 24, NULL), /* Picasso */
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /* Renoir */
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL), /* Lucienne */
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL), /* Cezanne */
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{}
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};
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bool force_storage_d3(void)
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{
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return x86_match_cpu(storage_d3_cpu_ids);
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}
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