1113 lines
56 KiB
C
Executable file
1113 lines
56 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos9830 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_9925_EVT0_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_9925_EVT0_H
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#define NONE (0 + 0)
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#define OSCCLK1 (0 + 1)
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#define OSCCLK2 (0 + 2)
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/* ALIVE */
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#define CLK_ALIVE_BASE (10)
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#define UMUX_CLK_RCO_ALIVE (CLK_ALIVE_BASE + 0)
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#define UMUX_CLKMUX_ALIVE_RCO_SPMI (CLK_ALIVE_BASE + 1)
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#define GATE_ALIVE_CMU_ALIVE_QCH (CLK_ALIVE_BASE + 2)
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#define GATE_APBIF_GPIO_ALIVE_QCH (CLK_ALIVE_BASE + 3)
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#define GATE_APBIF_INTCOMB_VGPIO2AP_QCH (CLK_ALIVE_BASE + 4)
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#define GATE_APBIF_INTCOMB_VGPIO2APM_QCH (CLK_ALIVE_BASE + 5)
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#define GATE_APBIF_INTCOMB_VGPIO2PMU_QCH (CLK_ALIVE_BASE + 6)
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#define GATE_APBIF_PMU_ALIVE_QCH (CLK_ALIVE_BASE + 7)
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#define GATE_APM_DMA_QCH_APB (CLK_ALIVE_BASE + 8)
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#define GATE_CHUB_RTC_QCH (CLK_ALIVE_BASE + 9)
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#define GATE_CLKMON_QCH (CLK_ALIVE_BASE + 10)
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#define GATE_DBGCORE_UART_QCH (CLK_ALIVE_BASE + 11)
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#define GATE_DTZPC_ALIVE_QCH (CLK_ALIVE_BASE + 12)
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#define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_ALIVE_BASE + 13)
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#define GATE_GREBEINTEGRATION_QCH_DBG (CLK_ALIVE_BASE + 14)
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#define GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH (CLK_ALIVE_BASE + 15)
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#define GATE_INTMEM_QCH (CLK_ALIVE_BASE + 16)
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#define GATE_LH_AXI_SI_D_APM_QCH (CLK_ALIVE_BASE + 17)
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#define GATE_MAILBOX_APM_AP_QCH (CLK_ALIVE_BASE + 18)
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#define GATE_MAILBOX_APM_CHUB_QCH (CLK_ALIVE_BASE + 19)
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#define GATE_MAILBOX_APM_CP_QCH (CLK_ALIVE_BASE + 20)
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#define GATE_MAILBOX_APM_GNSS_QCH (CLK_ALIVE_BASE + 21)
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#define GATE_MAILBOX_APM_VTS_QCH (CLK_ALIVE_BASE + 22)
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#define GATE_MAILBOX_AP_CHUB_QCH (CLK_ALIVE_BASE + 23)
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#define GATE_MAILBOX_AP_CP_QCH (CLK_ALIVE_BASE + 24)
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#define GATE_MAILBOX_AP_CP_S_QCH (CLK_ALIVE_BASE + 25)
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#define GATE_MAILBOX_AP_DBGCORE_QCH (CLK_ALIVE_BASE + 26)
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#define GATE_MAILBOX_AP_GNSS_QCH (CLK_ALIVE_BASE + 27)
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#define GATE_MAILBOX_CP_CHUB_QCH (CLK_ALIVE_BASE + 28)
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#define GATE_MAILBOX_CP_GNSS_QCH (CLK_ALIVE_BASE + 29)
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#define GATE_MAILBOX_GNSS_CHUB_QCH (CLK_ALIVE_BASE + 30)
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#define GATE_MAILBOX_SHARED_SRAM_QCH (CLK_ALIVE_BASE + 31)
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#define GATE_MAILBOX_VTS_CHUB_QCH (CLK_ALIVE_BASE + 32)
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#define GATE_MCT_ALIVE_QCH (CLK_ALIVE_BASE + 33)
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#define GATE_PMU_QCH_PMU (CLK_ALIVE_BASE + 34)
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#define GATE_PMU_QCH_PMLINK (CLK_ALIVE_BASE + 35)
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#define GATE_PMU_INTR_GEN_QCH (CLK_ALIVE_BASE + 36)
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#define GATE_ROM_CRC32_HOST_QCH (CLK_ALIVE_BASE + 37)
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#define GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH (CLK_ALIVE_BASE + 38)
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#define GATE_RTC_QCH (CLK_ALIVE_BASE + 39)
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#define GATE_SLH_AXI_MI_C_CHUB_QCH (CLK_ALIVE_BASE + 40)
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#define GATE_SLH_AXI_MI_C_GNSS_QCH (CLK_ALIVE_BASE + 41)
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#define GATE_SLH_AXI_MI_C_MODEM_QCH (CLK_ALIVE_BASE + 42)
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#define GATE_SLH_AXI_MI_C_VTS_QCH (CLK_ALIVE_BASE + 43)
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#define GATE_SLH_AXI_MI_ID_DBGCORE_QCH (CLK_ALIVE_BASE + 44)
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#define GATE_SLH_AXI_MI_P_APM_QCH (CLK_ALIVE_BASE + 45)
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#define GATE_SLH_AXI_SI_C_CMGP_QCH (CLK_ALIVE_BASE + 46)
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#define GATE_SLH_AXI_SI_IP_APM_QCH (CLK_ALIVE_BASE + 47)
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#define GATE_SLH_AXI_SI_LP_CHUB_QCH (CLK_ALIVE_BASE + 48)
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#define GATE_SLH_AXI_SI_LP_VTS_QCH (CLK_ALIVE_BASE + 49)
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#define GATE_SLH_AXI_SI_PPU_ALIVE_CPUCL0_QCH (CLK_ALIVE_BASE + 50)
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#define GATE_SLH_AXI_SI_P_ALIVEDNC_QCH (CLK_ALIVE_BASE + 51)
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#define GATE_SPC_ALIVE_QCH (CLK_ALIVE_BASE + 52)
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#define GATE_SPMI_MASTER_PMIC_QCH_P (CLK_ALIVE_BASE + 53)
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#define GATE_SPMI_MASTER_PMIC_QCH_S (CLK_ALIVE_BASE + 54)
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#define GATE_SWEEPER_P_ALIVE_QCH (CLK_ALIVE_BASE + 55)
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#define GATE_SYSREG_ALIVE_QCH (CLK_ALIVE_BASE + 56)
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#define GATE_TOP_RTC_QCH (CLK_ALIVE_BASE + 57)
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#define GATE_VGEN_LITE_ALIVE_QCH (CLK_ALIVE_BASE + 58)
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#define GATE_WDT_ALIVE_QCH (CLK_ALIVE_BASE + 59)
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#define DOUT_CLKALIVE_UFD_NOC (CLK_ALIVE_BASE + 60)
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#define DOUT_CLKALIVE_VTS_NOC (CLK_ALIVE_BASE + 61)
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#define DOUT_DIV_CLK_ALIVE_NOC (CLK_ALIVE_BASE + 62)
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#define DOUT_CLKALIVE_CMGP_NOC (CLK_ALIVE_BASE + 63)
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#define DOUT_DIV_CLK_ALIVE_SPMI (CLK_ALIVE_BASE + 64)
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#define DOUT_CLKALIVE_CMGP_PERI (CLK_ALIVE_BASE + 65)
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#define DOUT_DIV_CLK_ALIVE_DBGCORE_UART (CLK_ALIVE_BASE + 66)
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#define DOUT_CLKALIVE_CHUB_NOC (CLK_ALIVE_BASE + 67)
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#define DOUT_CLKALIVE_CHUB_PERI (CLK_ALIVE_BASE + 68)
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#define DOUT_CLKALIVE_DBGCORE_NOC (CLK_ALIVE_BASE + 69)
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#define DOUT_CLKALIVE_DNC_NOC (CLK_ALIVE_BASE + 70)
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#define DOUT_CLKALIVE_GNPU_NOC (CLK_ALIVE_BASE + 71)
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#define DOUT_CLKALIVE_SDMA_NOC (CLK_ALIVE_BASE + 72)
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#define DOUT_DIV_CLK_ALIVE_PMU_SUB (CLK_ALIVE_BASE + 73)
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#define DOUT_CLKALIVE_GNPUP_NOC (CLK_ALIVE_BASE + 74)
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#define DOUT_CLKCMU_ALIVE_NOC (CLK_ALIVE_BASE + 75)
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/* AUD */
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#define CLK_AUD_BASE (100)
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#define UMUX_CLKCMU_AUD_CPU (CLK_AUD_BASE + 0)
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#define UMUX_CLKCMU_AUD_NOC (CLK_AUD_BASE + 1)
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#define UMUX_CP_PCMC_CLK (CLK_AUD_BASE + 2)
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#define UMUX_CLK_AUD_RCO (CLK_AUD_BASE + 3)
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#define UMUX_CLKCMU_AUD_AUDIF0 (CLK_AUD_BASE + 4)
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#define UMUX_CLKCMU_AUD_AUDIF1 (CLK_AUD_BASE + 5)
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#define UMUX_CLKVTS_AUD_DMIC0 (CLK_AUD_BASE + 6)
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#define UMUX_CLKVTS_AUD_DMIC1 (CLK_AUD_BASE + 7)
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#define GATE_ABOX_QCH_ACLK (CLK_AUD_BASE + 8)
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#define GATE_ABOX_QCH_BCLK_DSIF (CLK_AUD_BASE + 9)
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#define GATE_ABOX_QCH_BCLK0 (CLK_AUD_BASE + 10)
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#define GATE_ABOX_QCH_BCLK1 (CLK_AUD_BASE + 11)
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#define GATE_ABOX_QCH_BCLK2 (CLK_AUD_BASE + 12)
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#define GATE_ABOX_QCH_BCLK3 (CLK_AUD_BASE + 13)
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#define GATE_ABOX_QCH_CPU (CLK_AUD_BASE + 14)
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#define GATE_ABOX_QCH_BCLK4 (CLK_AUD_BASE + 15)
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#define GATE_ABOX_QCH_CNT (CLK_AUD_BASE + 16)
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#define GATE_ABOX_QCH_BCLK5 (CLK_AUD_BASE + 17)
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#define GATE_ABOX_QCH_CCLK_ASB (CLK_AUD_BASE + 18)
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#define GATE_ABOX_QCH_BCLK6 (CLK_AUD_BASE + 19)
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#define GATE_ABOX_QCH_XCLK0 (CLK_AUD_BASE + 20)
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#define GATE_ABOX_QCH_PCMC_CLK (CLK_AUD_BASE + 21)
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#define GATE_ABOX_QCH_C2A0 (CLK_AUD_BASE + 22)
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#define GATE_ABOX_QCH_C2A1 (CLK_AUD_BASE + 23)
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#define GATE_ABOX_QCH_XCLK1 (CLK_AUD_BASE + 24)
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#define GATE_ABOX_QCH_XCLK2 (CLK_AUD_BASE + 25)
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#define GATE_ABOX_QCH_CPU0 (CLK_AUD_BASE + 26)
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#define GATE_ABOX_QCH_CPU1 (CLK_AUD_BASE + 27)
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#define GATE_ABOX_QCH_CPU2 (CLK_AUD_BASE + 28)
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#define GATE_ABOX_QCH_NEON0 (CLK_AUD_BASE + 29)
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#define GATE_ABOX_QCH_NEON1 (CLK_AUD_BASE + 30)
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#define GATE_ABOX_QCH_NEON2 (CLK_AUD_BASE + 31)
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#define GATE_ABOX_QCH_L2 (CLK_AUD_BASE + 32)
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#define GATE_AUD_CMU_AUD_QCH (CLK_AUD_BASE + 33)
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#define GATE_BAAW_D_AUDVTS_QCH (CLK_AUD_BASE + 34)
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#define GATE_DFTMUX_AUD_QCH (CLK_AUD_BASE + 35)
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#define GATE_DMIC_AUD0_QCH_PCLK (CLK_AUD_BASE + 36)
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#define GATE_DMIC_AUD0_QCH_DMIC (CLK_AUD_BASE + 37)
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#define GATE_DMIC_AUD1_QCH_PCLK (CLK_AUD_BASE + 38)
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#define GATE_DMIC_AUD1_QCH_DMIC (CLK_AUD_BASE + 39)
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#define GATE_DMIC_AUD2_QCH_PCLK (CLK_AUD_BASE + 40)
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#define GATE_DMIC_AUD2_QCH_DMIC (CLK_AUD_BASE + 41)
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#define GATE_D_TZPC_AUD_QCH (CLK_AUD_BASE + 42)
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#define GATE_LH_QDI_SI_D_AUD_QCH (CLK_AUD_BASE + 43)
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#define GATE_MAILBOX_AUD0_QCH (CLK_AUD_BASE + 44)
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#define GATE_MAILBOX_AUD1_QCH (CLK_AUD_BASE + 45)
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#define GATE_MAILBOX_AUD2_QCH (CLK_AUD_BASE + 46)
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#define GATE_MAILBOX_AUD3_QCH (CLK_AUD_BASE + 47)
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#define GATE_PPMU_AUD_QCH (CLK_AUD_BASE + 48)
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#define GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH (CLK_AUD_BASE + 49)
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#define GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH (CLK_AUD_BASE + 50)
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#define GATE_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH (CLK_AUD_BASE + 51)
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#define GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH (CLK_AUD_BASE + 52)
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#define GATE_SERIAL_LIF_QCH_PCLK (CLK_AUD_BASE + 53)
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#define GATE_SERIAL_LIF_QCH_LIF (CLK_AUD_BASE + 54)
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#define GATE_SERIAL_LIF_QCH_ACLK (CLK_AUD_BASE + 55)
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#define GATE_SLH_ASTL_SI_G_PPMU_AUD_QCH (CLK_AUD_BASE + 56)
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#define GATE_SLH_AXI_MI_LD_HSI0AUD_QCH (CLK_AUD_BASE + 57)
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#define GATE_SLH_AXI_MI_P_AUD_QCH (CLK_AUD_BASE + 58)
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#define GATE_SLH_AXI_SI_LD_AUDHSI0_QCH (CLK_AUD_BASE + 59)
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#define GATE_SLH_AXI_SI_LD_AUDVTS_QCH (CLK_AUD_BASE + 60)
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#define GATE_SMMU_AUD_QCH_S1 (CLK_AUD_BASE + 61)
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#define GATE_SMMU_AUD_QCH_S2 (CLK_AUD_BASE + 62)
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#define GATE_SYSREG_AUD_QCH (CLK_AUD_BASE + 63)
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#define GATE_TREX_AUD_QCH (CLK_AUD_BASE + 64)
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#define GATE_VGEN_LITE_AUD_QCH (CLK_AUD_BASE + 65)
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#define GATE_WDT_AUD_QCH (CLK_AUD_BASE + 66)
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#define DOUT_DIV_CLK_AUD_CPU_PCLKDBG (CLK_AUD_BASE + 67)
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#define DOUT_DIV_CLK_AUD_DSIF (CLK_AUD_BASE + 68)
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#define DOUT_DIV_CLK_AUD_UAIF0 (CLK_AUD_BASE + 69)
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#define DOUT_DIV_CLK_AUD_UAIF1 (CLK_AUD_BASE + 70)
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#define DOUT_DIV_CLK_AUD_UAIF2 (CLK_AUD_BASE + 71)
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#define DOUT_DIV_CLK_AUD_UAIF3 (CLK_AUD_BASE + 72)
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#define DOUT_DIV_CLK_AUD_CPU_ACLK (CLK_AUD_BASE + 73)
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#define DOUT_DIV_CLK_AUD_NOC (CLK_AUD_BASE + 74)
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#define DOUT_DIV_CLK_AUD_NOCP (CLK_AUD_BASE + 75)
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#define DOUT_DIV_CLK_AUD_CNT (CLK_AUD_BASE + 76)
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#define DOUT_DIV_CLK_AUD_UAIF4 (CLK_AUD_BASE + 77)
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#define DOUT_DIV_CLK_AUD_UAIF5 (CLK_AUD_BASE + 78)
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#define DOUT_DIV_CLK_AUD_UAIF6 (CLK_AUD_BASE + 79)
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#define DOUT_CLKAUD_HSI0_NOC (CLK_AUD_BASE + 80)
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#define DOUT_DIV_CLK_AUD_PCMC (CLK_AUD_BASE + 81)
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#define DOUT_DIV_CLK_AUD_AUDIF (CLK_AUD_BASE + 82)
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#define DOUT_DIV_CLK_AUD_SERIAL_LIF (CLK_AUD_BASE + 83)
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#define DOUT_DIV_CLK_AUD_SERIAL_LIF_CORE (CLK_AUD_BASE + 84)
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#define DOUT_CLK_AUD_MCLK (CLK_AUD_BASE + 85)
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#define MOUT_MUX_CLK_AUD_PCMC (CLK_AUD_BASE + 86)
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#define MOUT_MUX_CLK_AUD_SCLK (CLK_AUD_BASE + 87)
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#define MOUT_CLK_AUD_UAIF6 (CLK_AUD_BASE + 88)
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#define MOUT_CLK_AUD_UAIF0 (CLK_AUD_BASE + 89)
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#define MOUT_CLK_AUD_UAIF1 (CLK_AUD_BASE + 90)
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#define MOUT_CLK_AUD_UAIF2 (CLK_AUD_BASE + 91)
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#define MOUT_CLK_AUD_UAIF3 (CLK_AUD_BASE + 92)
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#define MOUT_CLK_AUD_UAIF4 (CLK_AUD_BASE + 93)
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#define MOUT_CLK_AUD_UAIF5 (CLK_AUD_BASE + 94)
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#define MOUT_CLK_AUD_SERIAL_LIF (CLK_AUD_BASE + 95)
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/* NOCL1A */
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#define CLK_NOCL1A_BASE (200)
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#define UMUX_CLKCMU_NOCL1A_NOC (CLK_NOCL1A_BASE + 0)
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#define GATE_SYSREG_NOCL1A_QCH (CLK_NOCL1A_BASE + 1)
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#define GATE_TREX_D_NOCL1A_QCH (CLK_NOCL1A_BASE + 2)
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#define GATE_TREX_P_NOCL1A_QCH (CLK_NOCL1A_BASE + 3)
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/* NOCL1B */
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#define CLK_NOCL1B_BASE (250)
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#define UMUX_CLKCMU_NOCL1B_NOC0 (CLK_NOCL1B_BASE + 0)
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#define GATE_SYSREG_NOCL1B_QCH (CLK_NOCL1B_BASE + 1)
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#define GATE_TREX_D_NOCL1B_QCH (CLK_NOCL1B_BASE + 2)
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#define GATE_TREX_P_NOCL1B_QCH (CLK_NOCL1B_BASE + 3)
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#define GATE_TREX_RB_NOCL1B_QCH (CLK_NOCL1B_BASE + 4)
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#define GATE_VGEN_LITE_NOCL1B_QCH (CLK_NOCL1B_BASE + 5)
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/* NOCL1C */
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#define CLK_NOCL1C_BASE (300)
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#define UMUX_CLKCMU_NOCL1B_NOC1 (CLK_NOCL1C_BASE + 0)
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/* CMGP */
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#define CLK_CMGP_BASE (350)
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#define GATE_APBIF_GPIO_CMGP_QCH (CLK_CMGP_BASE + 0)
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#define GATE_CMGP_CMU_CMGP_QCH (CLK_CMGP_BASE + 1)
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#define GATE_CMGP_I2C_QCH (CLK_CMGP_BASE + 2)
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#define GATE_D_TZPC_CMGP_QCH (CLK_CMGP_BASE + 3)
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#define GATE_I2C_CMGP2_QCH (CLK_CMGP_BASE + 4)
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#define GATE_I2C_CMGP3_QCH (CLK_CMGP_BASE + 5)
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#define GATE_I2C_CMGP4_QCH (CLK_CMGP_BASE + 6)
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#define GATE_I2C_CMGP5_QCH (CLK_CMGP_BASE + 7)
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#define GATE_I2C_CMGP6_QCH (CLK_CMGP_BASE + 8)
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#define GATE_I3C_CMGP_QCH_P (CLK_CMGP_BASE + 9)
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#define GATE_I3C_CMGP_QCH_S (CLK_CMGP_BASE + 10)
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#define GATE_SLH_AXI_MI_C_CMGP_QCH (CLK_CMGP_BASE + 11)
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#define GATE_SLH_AXI_SI_LP_CMGPUFD_QCH (CLK_CMGP_BASE + 12)
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#define GATE_SPI_I2C_CMGP0_QCH (CLK_CMGP_BASE + 13)
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#define GATE_SPI_I2C_CMGP1_QCH (CLK_CMGP_BASE + 14)
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#define GATE_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH (CLK_CMGP_BASE + 15)
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#define GATE_SYSREG_CMGP_QCH (CLK_CMGP_BASE + 16)
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#define GATE_SYSREG_CMGP2APM_QCH (CLK_CMGP_BASE + 17)
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#define GATE_SYSREG_CMGP2CHUB_QCH (CLK_CMGP_BASE + 18)
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#define GATE_SYSREG_CMGP2CP_QCH (CLK_CMGP_BASE + 19)
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#define GATE_SYSREG_CMGP2GNSS_QCH (CLK_CMGP_BASE + 20)
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#define GATE_SYSREG_CMGP2PMU_AP_QCH (CLK_CMGP_BASE + 21)
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#define GATE_USI_CMGP0_QCH (CLK_CMGP_BASE + 22)
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#define GATE_USI_CMGP1_QCH (CLK_CMGP_BASE + 23)
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#define GATE_USI_CMGP2_QCH (CLK_CMGP_BASE + 24)
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#define GATE_USI_CMGP3_QCH (CLK_CMGP_BASE + 25)
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#define GATE_USI_CMGP4_QCH (CLK_CMGP_BASE + 26)
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#define GATE_USI_CMGP5_QCH (CLK_CMGP_BASE + 27)
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#define GATE_USI_CMGP6_QCH (CLK_CMGP_BASE + 28)
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#define DOUT_DIV_CLK_CMGP_USI4 (CLK_CMGP_BASE + 29)
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#define DOUT_DIV_CLK_CMGP_USI1 (CLK_CMGP_BASE + 30)
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#define DOUT_DIV_CLK_CMGP_USI0 (CLK_CMGP_BASE + 31)
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#define DOUT_DIV_CLK_CMGP_USI2 (CLK_CMGP_BASE + 32)
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#define DOUT_DIV_CLK_CMGP_USI3 (CLK_CMGP_BASE + 33)
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#define DOUT_DIV_CLK_CMGP_USI5 (CLK_CMGP_BASE + 34)
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#define DOUT_DIV_CLK_CMGP_USI6 (CLK_CMGP_BASE + 35)
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#define DOUT_DIV_CLK_CMGP_I3C (CLK_CMGP_BASE + 36)
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#define DOUT_DIV_CLK_CMGP_I2C (CLK_CMGP_BASE + 37)
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#define DOUT_DIV_CLK_CMGP_SPI_MS_CTRL (CLK_CMGP_BASE + 38)
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#define DOUT_DIV_CLK_CMGP_SPI_I2C0 (CLK_CMGP_BASE + 39)
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#define DOUT_DIV_CLK_CMGP_SPI_I2C1 (CLK_CMGP_BASE + 40)
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/* TOP */
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#define CLK_TOP_BASE (450)
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#define GATE_CMU_TOP_CMUREF_QCH (CLK_TOP_BASE + 0)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK0 (CLK_TOP_BASE + 1)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK1 (CLK_TOP_BASE + 2)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK2 (CLK_TOP_BASE + 3)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK3 (CLK_TOP_BASE + 4)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK4 (CLK_TOP_BASE + 5)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK5 (CLK_TOP_BASE + 6)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK6 (CLK_TOP_BASE + 7)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK7 (CLK_TOP_BASE + 8)
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#define DOUT_DIV_CLKCMU_CIS_CLK0 (CLK_TOP_BASE + 9)
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#define DOUT_DIV_CLKCMU_CIS_CLK1 (CLK_TOP_BASE + 10)
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#define DOUT_DIV_CLKCMU_CIS_CLK2 (CLK_TOP_BASE + 11)
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#define DOUT_DIV_CLKCMU_CIS_CLK3 (CLK_TOP_BASE + 12)
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#define DOUT_DIV_CLKCMU_CIS_CLK4 (CLK_TOP_BASE + 13)
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#define DOUT_DIV_CLKCMU_CIS_CLK5 (CLK_TOP_BASE + 14)
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#define DOUT_DIV_CLKCMU_CIS_CLK6 (CLK_TOP_BASE + 15)
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#define DOUT_DIV_CLKCMU_CIS_CLK7 (CLK_TOP_BASE + 16)
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#define DOUT_DIV_CLKCMU_AUD_AUDIF0 (CLK_TOP_BASE + 17)
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#define MOUT_MUX_CLKCMU_AUD_AUDIF0 (CLK_TOP_BASE + 18)
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#define DOUT_DIV_CLKCMU_AUD_AUDIF1 (CLK_TOP_BASE + 19)
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#define MOUT_MUX_CLKCMU_AUD_AUDIF1 (CLK_TOP_BASE + 20)
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#define POUT_SHARED3_D1 (CLK_TOP_BASE + 21)
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#define POUT_SHARED4_D1 (CLK_TOP_BASE + 22)
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/* NOCL0 */
|
|
#define CLK_NOCL0_BASE (500)
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|
#define UMUX_CLKCMU_NOCL0_NOC (CLK_NOCL0_BASE + 0)
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#define GATE_CACHEAID_NOCL0_QCH (CLK_NOCL0_BASE + 1)
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#define GATE_CCI_QCH (CLK_NOCL0_BASE + 2)
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#define GATE_CCI_QCH_S (CLK_NOCL0_BASE + 3)
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#define GATE_CMU_NOCL0_CMUREF_QCH (CLK_NOCL0_BASE + 4)
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#define GATE_D_TZPC_NOCL0_QCH (CLK_NOCL0_BASE + 5)
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|
|
|
|
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/* CSIS */
|
|
#define CLK_CSIS_BASE (550)
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#define UMUX_CLKCMU_CSIS_NOC (CLK_CSIS_BASE + 0)
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#define UMUX_CLKCMU_CSIS_OIS_MCU (CLK_CSIS_BASE + 1)
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#define UMUX_CLKCMU_CSIS_DCPHY (CLK_CSIS_BASE + 2)
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#define GATE_CSIS_CMU_CSIS_QCH (CLK_CSIS_BASE + 3)
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#define GATE_CSIS_PDP_QCH_VOTF0 (CLK_CSIS_BASE + 4)
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#define GATE_CSIS_PDP_QCH_DMA (CLK_CSIS_BASE + 5)
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#define GATE_CSIS_PDP_QCH_MCB (CLK_CSIS_BASE + 6)
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#define GATE_CSIS_PDP_QCH_VOTF1 (CLK_CSIS_BASE + 7)
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#define GATE_CSIS_PDP_QCH_PDP (CLK_CSIS_BASE + 8)
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#define GATE_CSIS_PDP_QCH_PDP_VOTF (CLK_CSIS_BASE + 9)
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#define GATE_D_TZPC_CSIS_QCH (CLK_CSIS_BASE + 10)
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#define GATE_LH_AST_SI_OTF0_CSISCSTAT_QCH (CLK_CSIS_BASE + 11)
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#define GATE_LH_AST_SI_OTF1_CSISCSTAT_QCH (CLK_CSIS_BASE + 12)
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#define GATE_LH_AST_SI_OTF2_CSISCSTAT_QCH (CLK_CSIS_BASE + 13)
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#define GATE_LH_AST_SI_OTF3_CSISCSTAT_QCH (CLK_CSIS_BASE + 14)
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#define GATE_LH_AXI_SI_D0_CSIS_QCH (CLK_CSIS_BASE + 15)
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#define GATE_LH_AXI_SI_D1_CSIS_QCH (CLK_CSIS_BASE + 16)
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#define GATE_LH_AXI_SI_D2_CSIS_QCH (CLK_CSIS_BASE + 17)
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#define GATE_LH_AXI_SI_D3_CSIS_QCH (CLK_CSIS_BASE + 18)
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#define GATE_LH_AXI_SI_D4_CSIS_QCH (CLK_CSIS_BASE + 19)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0 (CLK_CSIS_BASE + 20)
|
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1 (CLK_CSIS_BASE + 21)
|
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2 (CLK_CSIS_BASE + 22)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3 (CLK_CSIS_BASE + 23)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4 (CLK_CSIS_BASE + 24)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5 (CLK_CSIS_BASE + 25)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS6 (CLK_CSIS_BASE + 26)
|
|
#define GATE_OIS_MCU_TOP_QCH (CLK_CSIS_BASE + 27)
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|
|
|
/* DNC */
|
|
#define CLK_DNC_BASE (600)
|
|
#define UMUX_CLKCMU_DNC_NOC (CLK_DNC_BASE + 0)
|
|
#define GATE_ADD_DNC_QCH (CLK_DNC_BASE + 1)
|
|
#define GATE_ADM_DAP_DNC_QCH (CLK_DNC_BASE + 2)
|
|
#define GATE_BAAW_DNCCHUB_QCH (CLK_DNC_BASE + 3)
|
|
#define GATE_BAAW_DNCVTS_QCH (CLK_DNC_BASE + 4)
|
|
#define GATE_BUSIF_ADD_DNC_QCH (CLK_DNC_BASE + 5)
|
|
#define GATE_BUSIF_DDD_DNC_QCH (CLK_DNC_BASE + 6)
|
|
#define GATE_BUSIF_HPM_DNC_QCH (CLK_DNC_BASE + 7)
|
|
#define GATE_DNC_CMU_DNC_QCH (CLK_DNC_BASE + 8)
|
|
#define GATE_D_TZPC_DNC_QCH (CLK_DNC_BASE + 9)
|
|
#define GATE_HTU_DNC_QCH_PCLK (CLK_DNC_BASE + 10)
|
|
#define GATE_HTU_DNC_QCH_CLK (CLK_DNC_BASE + 11)
|
|
#define GATE_IP_DNC_QCH (CLK_DNC_BASE + 12)
|
|
#define GATE_SYSREG_DNC_QCH (CLK_DNC_BASE + 13)
|
|
#define GATE_TREX_D_DNC_QCH (CLK_DNC_BASE + 14)
|
|
#define GATE_VGEN_DNC_QCH (CLK_DNC_BASE + 15)
|
|
#define GATE_VGEN_LITE_DNC_QCH (CLK_DNC_BASE + 16)
|
|
|
|
|
|
/* DPUB */
|
|
#define CLK_DPUB_BASE (650)
|
|
#define UMUX_CLKCMU_DPUB_NOC (CLK_DPUB_BASE + 0)
|
|
#define UMUX_CLKCMU_DPUB_DSIM (CLK_DPUB_BASE + 1)
|
|
#define GATE_DPUB_QCH_DECON (CLK_DPUB_BASE + 2)
|
|
#define GATE_DPUB_QCH_DSIM0 (CLK_DPUB_BASE + 3)
|
|
#define GATE_DPUB_QCH_DSIM1 (CLK_DPUB_BASE + 4)
|
|
#define GATE_DPUB_QCH_DSIM2 (CLK_DPUB_BASE + 5)
|
|
#define GATE_DPUB_CMU_DPUB_QCH (CLK_DPUB_BASE + 6)
|
|
#define GATE_D_TZPC_DPUB_QCH (CLK_DPUB_BASE + 7)
|
|
#define GATE_SYSREG_DPUB_QCH (CLK_DPUB_BASE + 8)
|
|
|
|
|
|
/* DPUF0 */
|
|
#define CLK_DPUF0_BASE (700)
|
|
#define UMUX_CLKCMU_DPUF0_NOC (CLK_DPUF0_BASE + 0)
|
|
#define GATE_DPUF0_QCH_DPUF (CLK_DPUF0_BASE + 1)
|
|
#define GATE_DPUF0_QCH_VOTF (CLK_DPUF0_BASE + 2)
|
|
#define GATE_DPUF0_CMU_DPUF0_QCH (CLK_DPUF0_BASE + 3)
|
|
#define GATE_D_TZPC_DPUF0_QCH (CLK_DPUF0_BASE + 4)
|
|
#define GATE_SYSMMU_DPUF0D0_QCH_S1 (CLK_DPUF0_BASE + 5)
|
|
#define GATE_SYSMMU_DPUF0D0_QCH_S2 (CLK_DPUF0_BASE + 6)
|
|
#define GATE_SYSMMU_DPUF0D1_QCH_S1 (CLK_DPUF0_BASE + 7)
|
|
#define GATE_SYSMMU_DPUF0D1_QCH_S2 (CLK_DPUF0_BASE + 8)
|
|
#define GATE_SYSREG_DPUF0_QCH (CLK_DPUF0_BASE + 9)
|
|
|
|
/* DPUF1 */
|
|
#define CLK_DPUF1_BASE (750)
|
|
#define UMUX_CLKCMU_DPUF1_NOC (CLK_DPUF1_BASE + 0)
|
|
#define GATE_DPUF1_QCH_DPUF (CLK_DPUF1_BASE + 1)
|
|
#define GATE_DPUF1_QCH_VOTF (CLK_DPUF1_BASE + 2)
|
|
#define GATE_DPUF1_CMU_DPUF1_QCH (CLK_DPUF1_BASE + 3)
|
|
#define GATE_D_TZPC_DPUF1_QCH (CLK_DPUF1_BASE + 4)
|
|
#define GATE_LH_AXI_SI_D0_DPUF1DPUF0_QCH (CLK_DPUF1_BASE + 5)
|
|
#define GATE_LH_AXI_SI_D1_DPUF1DPUF0_QCH (CLK_DPUF1_BASE + 6)
|
|
#define GATE_PPMU_DPUF1D0_QCH (CLK_DPUF1_BASE + 7)
|
|
#define GATE_PPMU_DPUF1D1_QCH (CLK_DPUF1_BASE + 8)
|
|
#define GATE_SIU_DPUF1_QCH (CLK_DPUF1_BASE + 9)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_DPUF1_QCH (CLK_DPUF1_BASE + 10)
|
|
#define GATE_SLH_AXI_MI_P_DPUF1_QCH (CLK_DPUF1_BASE + 11)
|
|
#define GATE_SYSMMU_DPUF1D0_QCH_S1 (CLK_DPUF1_BASE + 12)
|
|
#define GATE_SYSMMU_DPUF1D0_QCH_S2 (CLK_DPUF1_BASE + 13)
|
|
#define GATE_SYSMMU_DPUF1D1_QCH_S1 (CLK_DPUF1_BASE + 14)
|
|
#define GATE_SYSMMU_DPUF1D1_QCH_S2 (CLK_DPUF1_BASE + 15)
|
|
#define GATE_SYSREG_DPUF1_QCH (CLK_DPUF1_BASE + 16)
|
|
|
|
|
|
/* DSU */
|
|
#define CLK_DSU_BASE (800)
|
|
#define UMUX_CLKCMU_DSU_SWITCH (CLK_DSU_BASE + 0)
|
|
#define GATE_CMU_DSU_CMUREF_QCH (CLK_DSU_BASE + 1)
|
|
#define GATE_DSU_CMU_DSU_QCH (CLK_DSU_BASE + 2)
|
|
#define GATE_HTU_DSU_QCH_PCLK (CLK_DSU_BASE + 3)
|
|
|
|
/* G3D */
|
|
#define CLK_G3D_BASE (850)
|
|
#define UMUX_CLKCMU_G3D_NOCP (CLK_G3D_BASE + 0)
|
|
#define UMUX_CLKCMU_G3D_SWITCH (CLK_G3D_BASE + 1)
|
|
#define GATE_BG3D_PWRCTL_QCH (CLK_G3D_BASE + 2)
|
|
#define GATE_BUSIF_HPMG3D_QCH (CLK_G3D_BASE + 3)
|
|
#define GATE_CFM_G3D_QCH (CLK_G3D_BASE + 4)
|
|
#define GATE_D_TZPC_G3D_QCH (CLK_G3D_BASE + 5)
|
|
#define GATE_G3D_CMU_G3D_QCH (CLK_G3D_BASE + 6)
|
|
#define GATE_SLH_AXI_MI_P_G3D_QCH (CLK_G3D_BASE + 7)
|
|
#define GATE_SLH_AXI_SI_P_INT_G3D_QCH (CLK_G3D_BASE + 8)
|
|
#define GATE_SYSREG_G3D_QCH (CLK_G3D_BASE + 9)
|
|
#define GATE_ADD_APBIF_G3D_QCH (CLK_G3D_BASE + 10)
|
|
#define GATE_ADD_G3D_QCH (CLK_G3D_BASE + 11)
|
|
#define GATE_ADM_DAP_G_G3D_QCH (CLK_G3D_BASE + 12)
|
|
#define GATE_ASB_G3D_QCH_LH_D0_G3D (CLK_G3D_BASE + 13)
|
|
#define GATE_ASB_G3D_QCH_LH_D1_G3D (CLK_G3D_BASE + 14)
|
|
#define GATE_ASB_G3D_QCH_LH_D2_G3D (CLK_G3D_BASE + 15)
|
|
#define GATE_ASB_G3D_QCH_LH_D3_G3D (CLK_G3D_BASE + 16)
|
|
#define GATE_ASB_G3D_QCH_S_LH_P_G3D (CLK_G3D_BASE + 17)
|
|
#define GATE_BUSIF_DDC_G3D_QCH (CLK_G3D_BASE + 18)
|
|
#define GATE_BUSIF_STR_G3D_QCH (CLK_G3D_BASE + 19)
|
|
#define GATE_BUSIF_STR_G3D_QCH_CORE (CLK_G3D_BASE + 20)
|
|
#define GATE_G3DCORE_CMU_G3DCORE_QCH (CLK_G3D_BASE + 21)
|
|
#define GATE_GPU_QCH (CLK_G3D_BASE + 22)
|
|
#define GATE_HTU_G3D_QCH_PCLK (CLK_G3D_BASE + 23)
|
|
#define GATE_HTU_G3D_QCH_CLK (CLK_G3D_BASE + 24)
|
|
#define GATE_LH_ATB_SI_T_DDCG3D_QCH (CLK_G3D_BASE + 25)
|
|
#define GATE_RSTNSYNC_CLK_G3DCORE_NOCP_QCH (CLK_G3D_BASE + 26)
|
|
#define GATE_STR_G3D_QCH (CLK_G3D_BASE + 27)
|
|
#define GATE_U_DDD_CTRL_CORE__G3D_QCH (CLK_G3D_BASE + 28)
|
|
|
|
|
|
/* HSI0 */
|
|
#define CLK_HSI0_BASE (900)
|
|
#define UMUX_CLKCMU_HSI0_DPOSC (CLK_HSI0_BASE + 0)
|
|
#define UMUX_CLKCMU_HSI0_NOC (CLK_HSI0_BASE + 1)
|
|
#define UMUX_CLKCMU_HSI0_USB32DRD (CLK_HSI0_BASE + 2)
|
|
#define UMUX_CLKCMU_HSI0_DPGTC (CLK_HSI0_BASE + 3)
|
|
#define UMUX_CLKAUD_HSI0_NOC (CLK_HSI0_BASE + 4)
|
|
#define GATE_D_TZPC_HSI0_QCH (CLK_HSI0_BASE + 5)
|
|
#define GATE_HSI0_CMU_HSI0_QCH (CLK_HSI0_BASE + 6)
|
|
#define GATE_PPMU_HSI0_BUS1_QCH (CLK_HSI0_BASE + 7)
|
|
#define GATE_SLH_ACEL_SI_D_HSI0_QCH (CLK_HSI0_BASE + 8)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_HSI0_QCH (CLK_HSI0_BASE + 9)
|
|
#define GATE_SLH_AXI_MI_LD_AUDHSI0_QCH (CLK_HSI0_BASE + 10)
|
|
#define GATE_SLH_AXI_MI_P_HSI0_QCH (CLK_HSI0_BASE + 11)
|
|
#define GATE_SLH_AXI_SI_LD_HSI0AUD_QCH (CLK_HSI0_BASE + 12)
|
|
#define GATE_SPC_HSI0_QCH (CLK_HSI0_BASE + 13)
|
|
#define GATE_SYSMMU_D_HSI0_QCH (CLK_HSI0_BASE + 14)
|
|
#define GATE_SYSREG_HSI0_QCH (CLK_HSI0_BASE + 15)
|
|
#define GATE_USB32DRD_QCH_S_SUBCTRL (CLK_HSI0_BASE + 16)
|
|
#define GATE_USB32DRD_QCH_S_LINK (CLK_HSI0_BASE + 17)
|
|
#define GATE_USB32DRD_QCH_S_CTRL (CLK_HSI0_BASE + 18)
|
|
#define GATE_USB32DRD_QCH_S_TCA (CLK_HSI0_BASE + 19)
|
|
#define GATE_USB32DRD_QCH_S_EUSBCTL (CLK_HSI0_BASE + 20)
|
|
#define GATE_USB32DRD_QCH_S_EUSBPHY (CLK_HSI0_BASE + 21)
|
|
#define GATE_VGEN_LITE_HSI0_QCH (CLK_HSI0_BASE + 22)
|
|
#define DOUT_CLKCMU_HSI0_USB32DRD (CLK_HSI0_BASE + 23)
|
|
#define DOUT_CLKCMU_HSI0_DPGTC (CLK_HSI0_BASE + 24)
|
|
#define MOUT_CLK_HSI0_USB32DRD (CLK_HSI0_BASE + 25)
|
|
|
|
/* HSI1 */
|
|
#define CLK_HSI1_BASE (950)
|
|
#define UMUX_CLKCMU_HSI1_NOC (CLK_HSI1_BASE + 0)
|
|
#define UMUX_CLKCMU_HSI1_PCIE (CLK_HSI1_BASE + 1)
|
|
#define UMUX_CLKCMU_HSI1_MMC_CARD (CLK_HSI1_BASE + 2)
|
|
#define UMUX_CLKCMU_HSI1_UFS_EMBD (CLK_HSI1_BASE + 3)
|
|
#define GATE_D_TZPC_HSI1_QCH (CLK_HSI1_BASE + 4)
|
|
#define GATE_GPIO_HSI1_QCH (CLK_HSI1_BASE + 5)
|
|
#define GATE_GPIO_HSI1UFS_QCH (CLK_HSI1_BASE + 6)
|
|
#define GATE_HSI1_CMU_HSI1_QCH (CLK_HSI1_BASE + 7)
|
|
#define GATE_LH_ACEL_SI_D_HSI1_QCH (CLK_HSI1_BASE + 8)
|
|
#define GATE_PPMU_HSI1_QCH (CLK_HSI1_BASE + 9)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_HSI1_QCH (CLK_HSI1_BASE + 10)
|
|
#define GATE_SLH_AXI_MI_P_HSI1_QCH (CLK_HSI1_BASE + 11)
|
|
#define GATE_SPC_HSI1_QCH (CLK_HSI1_BASE + 12)
|
|
#define GATE_SYSMMU_HSI1_QCH_S1 (CLK_HSI1_BASE + 13)
|
|
#define GATE_SYSMMU_HSI1_QCH_S2 (CLK_HSI1_BASE + 14)
|
|
#define GATE_SYSREG_HSI1_QCH (CLK_HSI1_BASE + 15)
|
|
#define GATE_UFS_EMBD_QCH (CLK_HSI1_BASE + 16)
|
|
#define GATE_UFS_EMBD_QCH_FMP (CLK_HSI1_BASE + 17)
|
|
#define GATE_VGEN_LITE_HSI1_QCH (CLK_HSI1_BASE + 18)
|
|
#define DOUT_DIV_CLKCMU_HSI1_MMC_CARD_SM (CLK_HSI1_BASE + 19)
|
|
#define DOUT_CLKCMU_HSI1_UFS_EMBD (CLK_HSI1_BASE + 20)
|
|
#define GATE_PCIE_GEN2_QCH_REF (CLK_HSI1_BASE + 21)
|
|
#define GATE_PCIE_GEN3_QCH_REF (CLK_HSI1_BASE + 22)
|
|
|
|
|
|
/* LME */
|
|
#define CLK_LME_BASE (1000)
|
|
#define UMUX_CLKCMU_LME_NOC (CLK_LME_BASE + 0)
|
|
#define UMUX_CLKCMU_LME_FRC (CLK_LME_BASE + 1)
|
|
#define GATE_D_TZPC_LME_QCH (CLK_LME_BASE + 2)
|
|
#define GATE_FRC_MC_QCH (CLK_LME_BASE + 3)
|
|
#define GATE_LH_AXI_SI_D_LME_QCH (CLK_LME_BASE + 4)
|
|
#define GATE_LME_QCH_0 (CLK_LME_BASE + 5)
|
|
#define GATE_LME_QCH_1 (CLK_LME_BASE + 6)
|
|
#define GATE_LME_CMU_LME_QCH (CLK_LME_BASE + 7)
|
|
#define GATE_PPMU_D_LME_QCH (CLK_LME_BASE + 8)
|
|
#define GATE_QE_D0_LME_QCH (CLK_LME_BASE + 9)
|
|
#define GATE_QE_D1_LME_QCH (CLK_LME_BASE + 10)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_LME_QCH (CLK_LME_BASE + 11)
|
|
#define GATE_SLH_AXI_MI_P_LME_QCH (CLK_LME_BASE + 12)
|
|
#define GATE_SYSMMU_D_LME_QCH_S1 (CLK_LME_BASE + 13)
|
|
#define GATE_SYSMMU_D_LME_QCH_S2 (CLK_LME_BASE + 14)
|
|
#define GATE_SYSREG_LME_QCH (CLK_LME_BASE + 15)
|
|
#define GATE_VGEN_LITE_D_LME_QCH (CLK_LME_BASE + 16)
|
|
#define DOUT_DIV_CLK_LME_NOCP (CLK_LME_BASE + 17)
|
|
|
|
|
|
/* M2M */
|
|
#define CLK_M2M_BASE (1050)
|
|
#define UMUX_CLKCMU_M2M_NOC (CLK_M2M_BASE + 0)
|
|
#define GATE_D_TZPC_M2M_QCH (CLK_M2M_BASE + 1)
|
|
#define GATE_LH_ACEL_SI_D_M2M_QCH (CLK_M2M_BASE + 2)
|
|
#define GATE_M2M_QCH (CLK_M2M_BASE + 3)
|
|
#define GATE_M2M_QCH_VOTF (CLK_M2M_BASE + 4)
|
|
#define GATE_M2M_CMU_M2M_QCH (CLK_M2M_BASE + 5)
|
|
#define GATE_PPMU_D_M2M_QCH (CLK_M2M_BASE + 6)
|
|
#define GATE_QE_ASTC_QCH (CLK_M2M_BASE + 7)
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#define GATE_QE_JPEG0_QCH (CLK_M2M_BASE + 8)
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#define GATE_QE_JPEG1_QCH (CLK_M2M_BASE + 9)
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#define GATE_QE_JSQZ_QCH (CLK_M2M_BASE + 10)
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#define GATE_QE_M2M_QCH (CLK_M2M_BASE + 11)
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#define GATE_SLH_ASTL_SI_G_PPMU_M2M_QCH (CLK_M2M_BASE + 12)
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#define GATE_SLH_AXI_MI_P_M2M_QCH (CLK_M2M_BASE + 13)
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#define GATE_SYSMMU_D_M2M_PM_QCH_S2 (CLK_M2M_BASE + 14)
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#define GATE_SYSMMU_D_M2M_PM_QCH_S1 (CLK_M2M_BASE + 15)
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#define GATE_SYSREG_M2M_QCH (CLK_M2M_BASE + 16)
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#define GATE_VGEN_LITE_M2M_QCH (CLK_M2M_BASE + 17)
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#define DOUT_DIV_CLK_M2M_NOCP (CLK_M2M_BASE + 18)
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/* MCFP */
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#define CLK_MCFP_BASE (1100)
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#define UMUX_CLKCMU_MCFP_NOC (CLK_MCFP_BASE + 0)
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#define GATE_D_TZPC_MCFP_QCH (CLK_MCFP_BASE + 1)
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#define GATE_LH_AST_MI_OTF_RGBPMCFP_QCH (CLK_MCFP_BASE + 2)
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#define GATE_LH_AST_MI_OTF_YUVPMCFP_QCH (CLK_MCFP_BASE + 3)
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#define GATE_LH_AST_SI_OTF0_MCFPYUVP_QCH (CLK_MCFP_BASE + 4)
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#define GATE_LH_AXI_SI_D0_MCFP_QCH (CLK_MCFP_BASE + 5)
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#define GATE_LH_AXI_SI_D1_MCFP_QCH (CLK_MCFP_BASE + 6)
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#define GATE_LH_AXI_SI_D2_MCFP_QCH (CLK_MCFP_BASE + 7)
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#define GATE_MCFP_QCH (CLK_MCFP_BASE + 8)
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#define GATE_MCFP_CMU_MCFP_QCH (CLK_MCFP_BASE + 9)
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#define GATE_PPMU_D0_MCFP_QCH (CLK_MCFP_BASE + 10)
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#define GATE_PPMU_D1_MCFP_QCH (CLK_MCFP_BASE + 11)
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#define GATE_PPMU_D2_MCFP_QCH (CLK_MCFP_BASE + 12)
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#define GATE_PPMU_D3_MCFP_QCH (CLK_MCFP_BASE + 13)
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#define GATE_PPMU_D4_MCFP_QCH (CLK_MCFP_BASE + 14)
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#define GATE_PPMU_D5_MCFP_QCH (CLK_MCFP_BASE + 15)
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#define GATE_RSTNSYNC_CLK_MCFP_NOCD_MCFP_SW_RESET_QCH (CLK_MCFP_BASE + 16)
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#define GATE_SIU_G_PPMU_MCFP_QCH (CLK_MCFP_BASE + 17)
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#define GATE_SLH_ASTL_SI_G_PPMU_MCFP_QCH (CLK_MCFP_BASE + 18)
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#define GATE_SLH_AXI_MI_P_MCFP_QCH (CLK_MCFP_BASE + 19)
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#define GATE_SLH_AXI_SI_D3_MCFP_QCH (CLK_MCFP_BASE + 20)
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#define GATE_SLH_AXI_SI_D4_MCFP_QCH (CLK_MCFP_BASE + 21)
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#define GATE_SLH_AXI_SI_D5_MCFP_QCH (CLK_MCFP_BASE + 22)
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#define GATE_SYSMMU_D0_MCFP_QCH_S1 (CLK_MCFP_BASE + 23)
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#define GATE_SYSMMU_D0_MCFP_QCH_S2 (CLK_MCFP_BASE + 24)
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#define GATE_SYSMMU_D1_MCFP_QCH_S1 (CLK_MCFP_BASE + 25)
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#define GATE_SYSMMU_D1_MCFP_QCH_S2 (CLK_MCFP_BASE + 26)
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#define GATE_SYSMMU_D2_MCFP_QCH_S1 (CLK_MCFP_BASE + 27)
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#define GATE_SYSMMU_D2_MCFP_QCH_S2 (CLK_MCFP_BASE + 28)
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#define GATE_SYSMMU_D3_MCFP_QCH_S1 (CLK_MCFP_BASE + 29)
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#define GATE_SYSMMU_D3_MCFP_QCH_S2 (CLK_MCFP_BASE + 30)
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#define GATE_SYSMMU_D4_MCFP_QCH_S1 (CLK_MCFP_BASE + 31)
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#define GATE_SYSMMU_D4_MCFP_QCH_S2 (CLK_MCFP_BASE + 32)
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#define GATE_SYSMMU_D5_MCFP_QCH_S1 (CLK_MCFP_BASE + 33)
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#define GATE_SYSMMU_D5_MCFP_QCH_S2 (CLK_MCFP_BASE + 34)
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#define GATE_SYSREG_MCFP_QCH (CLK_MCFP_BASE + 35)
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#define GATE_VGEN_LITE_D0_MCFP_QCH (CLK_MCFP_BASE + 36)
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#define GATE_VGEN_LITE_D1_MCFP_QCH (CLK_MCFP_BASE + 37)
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/* MCSC */
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#define CLK_MCSC_BASE (1200)
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#define UMUX_CLKCMU_MCSC_NOC (CLK_MCSC_BASE + 0)
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#define UMUX_CLKCMU_MCSC_GDC (CLK_MCSC_BASE + 1)
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#define GATE_D_TZPC_MCSC_QCH (CLK_MCSC_BASE + 2)
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#define GATE_LH_ACEL_SI_D0_MCSC_QCH (CLK_MCSC_BASE + 3)
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#define GATE_LH_AST_MI_OTF_DRCPMCSC_QCH (CLK_MCSC_BASE + 4)
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#define GATE_LH_AXI_SI_D1_MCSC_QCH (CLK_MCSC_BASE + 5)
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#define GATE_LH_AXI_SI_D2_MCSC_QCH (CLK_MCSC_BASE + 6)
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#define GATE_MCSC_QCH (CLK_MCSC_BASE + 7)
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#define GATE_MCSC_QCH_C2R (CLK_MCSC_BASE + 8)
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#define GATE_MCSC_QCH_C2W (CLK_MCSC_BASE + 9)
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#define GATE_MCSC_CMU_MCSC_QCH (CLK_MCSC_BASE + 10)
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#define GATE_PPMU_D0_MCSC_QCH (CLK_MCSC_BASE + 11)
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#define GATE_PPMU_D1_MCSC_QCH (CLK_MCSC_BASE + 12)
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#define GATE_PPMU_D2_MCSC_QCH (CLK_MCSC_BASE + 13)
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#define GATE_SIU_G_PPMU_MCSC_QCH (CLK_MCSC_BASE + 14)
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#define GATE_SLH_ASTL_MI_IG_PPMU_D0_MCSC_QCH (CLK_MCSC_BASE + 15)
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#define GATE_SLH_ASTL_SI_G_PPMU_MCSC_QCH (CLK_MCSC_BASE + 16)
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|
#define GATE_SLH_ASTL_SI_IG_PPMU_D0_MCSC_QCH (CLK_MCSC_BASE + 17)
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|
#define GATE_SLH_AXI_MI_P_MCSC_QCH (CLK_MCSC_BASE + 18)
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|
#define GATE_SYSMMU_D0_MCSC_QCH_S1 (CLK_MCSC_BASE + 19)
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#define GATE_SYSMMU_D0_MCSC_QCH_S2 (CLK_MCSC_BASE + 20)
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#define GATE_SYSMMU_D1_MCSC_QCH_S1 (CLK_MCSC_BASE + 21)
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#define GATE_SYSMMU_D1_MCSC_QCH_S2 (CLK_MCSC_BASE + 22)
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#define GATE_SYSMMU_D2_MCSC_QCH_S1 (CLK_MCSC_BASE + 23)
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#define GATE_SYSMMU_D2_MCSC_QCH_S2 (CLK_MCSC_BASE + 24)
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#define GATE_SYSREG_MCSC_QCH (CLK_MCSC_BASE + 25)
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|
#define GATE_VGEN_LITE_D0_MCSC_QCH (CLK_MCSC_BASE + 26)
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#define GATE_VGEN_LITE_D1_MCSC_QCH (CLK_MCSC_BASE + 27)
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/* MFC0 */
|
|
#define CLK_MFC0_BASE (1250)
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|
#define UMUX_CLKCMU_MFC0_MFC0 (CLK_MFC0_BASE + 0)
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|
#define UMUX_CLKCMU_MFC0_WFD (CLK_MFC0_BASE + 1)
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|
#define GATE_D_TZPC_MFC0_QCH (CLK_MFC0_BASE + 2)
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#define GATE_MFC0_QCH (CLK_MFC0_BASE + 3)
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#define GATE_MFC0_QCH_VOTF (CLK_MFC0_BASE + 4)
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#define GATE_MFC0_CMU_MFC0_QCH (CLK_MFC0_BASE + 5)
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#define GATE_PPMU_MFC0D0_QCH (CLK_MFC0_BASE + 6)
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#define GATE_PPMU_MFC0D1_QCH (CLK_MFC0_BASE + 7)
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#define GATE_PPMU_WFD_QCH (CLK_MFC0_BASE + 8)
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|
#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 9)
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|
#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 10)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 11)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 12)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 13)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 14)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 15)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 16)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH (CLK_MFC0_BASE + 17)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH (CLK_MFC0_BASE + 18)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 19)
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#define GATE_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH (CLK_MFC0_BASE + 20)
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#define GATE_SIU_G_PPMU_MFC0_QCH (CLK_MFC0_BASE + 21)
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#define GATE_SLH_ASTL_SI_G_PPMU_MFC0_QCH (CLK_MFC0_BASE + 22)
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#define GATE_SLH_AXI_MI_P_MFC0_QCH (CLK_MFC0_BASE + 23)
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#define GATE_SYSMMU_MFC0D0_QCH_S1 (CLK_MFC0_BASE + 24)
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#define GATE_SYSMMU_MFC0D0_QCH_S2 (CLK_MFC0_BASE + 25)
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#define GATE_SYSMMU_MFC0D1_QCH_S1 (CLK_MFC0_BASE + 26)
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#define GATE_SYSMMU_MFC0D1_QCH_S2 (CLK_MFC0_BASE + 27)
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#define GATE_SYSREG_MFC0_QCH (CLK_MFC0_BASE + 28)
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#define GATE_VGEN_LITE_MFC0_QCH (CLK_MFC0_BASE + 29)
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/* MFC1 */
|
|
#define CLK_MFC1_BASE (1300)
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|
#define UMUX_CLKCMU_MFC1_MFC1 (CLK_MFC1_BASE + 0)
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#define GATE_ADM_APB_MFC0MFC1_QCH (CLK_MFC1_BASE + 1)
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#define GATE_D_TZPC_MFC1_QCH (CLK_MFC1_BASE + 2)
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#define GATE_MFC1_QCH (CLK_MFC1_BASE + 3)
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#define GATE_MFC1_CMU_MFC1_QCH (CLK_MFC1_BASE + 4)
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#define GATE_PPMU_MFC1D0_QCH (CLK_MFC1_BASE + 5)
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#define GATE_PPMU_MFC1D1_QCH (CLK_MFC1_BASE + 6)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 7)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 8)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 9)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 10)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 11)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 12)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 13)
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#define GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 14)
|
|
#define GATE_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 15)
|
|
#define GATE_SIU_G_PPMU_MFC1_QCH (CLK_MFC1_BASE + 16)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_MFC1_QCH (CLK_MFC1_BASE + 17)
|
|
#define GATE_SLH_AXI_MI_P_MFC1_QCH (CLK_MFC1_BASE + 18)
|
|
#define GATE_SYSMMU_MFC1D0_QCH_S1 (CLK_MFC1_BASE + 19)
|
|
#define GATE_SYSMMU_MFC1D0_QCH_S2 (CLK_MFC1_BASE + 20)
|
|
#define GATE_SYSMMU_MFC1D1_QCH_S1 (CLK_MFC1_BASE + 21)
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#define GATE_SYSMMU_MFC1D1_QCH_S2 (CLK_MFC1_BASE + 22)
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#define GATE_SYSREG_MFC1_QCH (CLK_MFC1_BASE + 23)
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|
#define GATE_VGEN_MFC1_QCH (CLK_MFC1_BASE + 24)
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|
|
|
|
|
/* MIF */
|
|
#define CLK_MIF_BASE (1350)
|
|
#define UMUX_CLKCMU_MIF_NOCP (CLK_MIF_BASE + 0)
|
|
#define GATE_BUSIF_DDD_MIF_QCH (CLK_MIF_BASE + 1)
|
|
#define GATE_CMU_MIF_CMUREF_QCH (CLK_MIF_BASE + 2)
|
|
#define GATE_DMC_QCH (CLK_MIF_BASE + 3)
|
|
#define GATE_D_TZPC_MIF_QCH (CLK_MIF_BASE + 4)
|
|
#define GATE_LH_AST_SI_G_DMC_QCH (CLK_MIF_BASE + 5)
|
|
#define GATE_MIF_CMU_MIF_QCH (CLK_MIF_BASE + 6)
|
|
#define GATE_QCH_ADAPTER_PPC_DEBUG_QCH (CLK_MIF_BASE + 7)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_MIF_QCH (CLK_MIF_BASE + 8)
|
|
#define GATE_SLH_AXI_MI_P_MIF_QCH (CLK_MIF_BASE + 9)
|
|
#define GATE_SPC_MIF_QCH (CLK_MIF_BASE + 10)
|
|
#define GATE_SYSREG_MIF_QCH (CLK_MIF_BASE + 11)
|
|
#define GATE_SYSREG_PRIVATE_MIF_QCH (CLK_MIF_BASE + 12)
|
|
#define MUX_MIF_DDRPHY2X (CLK_MIF_BASE + 13)
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|
|
|
|
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/* GNPU */
|
|
#define CLK_GNPU_BASE (1400)
|
|
#define UMUX_CLKCMU_GNPU_NOC (CLK_GNPU_BASE + 0)
|
|
#define UMUX_CLKCMU_GNPUP_NOC (CLK_GNPU_BASE + 1)
|
|
#define GATE_D_TZPC_GNPU_QCH (CLK_GNPU_BASE + 2)
|
|
#define GATE_GNPU_CMU_GNPU_QCH (CLK_GNPU_BASE + 3)
|
|
#define GATE_IP_NPUCORE_QCH_CORE (CLK_GNPU_BASE + 4)
|
|
#define GATE_IP_NPUCORE_QCH_SRAM (CLK_GNPU_BASE + 5)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_BU0_QCH (CLK_GNPU_BASE + 6)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_BU1_QCH (CLK_GNPU_BASE + 7)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_BU2_QCH (CLK_GNPU_BASE + 8)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_BU3_QCH (CLK_GNPU_BASE + 9)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_CU_WCH_QCH (CLK_GNPU_BASE + 10)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_NPUC_DONE_QCH (CLK_GNPU_BASE + 11)
|
|
#define GATE_LH_AST_MI_LD_GNPUP_RDREQ_QCH (CLK_GNPU_BASE + 12)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU0_QCH (CLK_GNPU_BASE + 13)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU1_QCH (CLK_GNPU_BASE + 14)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU10_QCH (CLK_GNPU_BASE + 15)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU11_QCH (CLK_GNPU_BASE + 16)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU12_QCH (CLK_GNPU_BASE + 17)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU13_QCH (CLK_GNPU_BASE + 18)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU14_QCH (CLK_GNPU_BASE + 19)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU15_QCH (CLK_GNPU_BASE + 20)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU16_QCH (CLK_GNPU_BASE + 21)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU17_QCH (CLK_GNPU_BASE + 22)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU18_QCH (CLK_GNPU_BASE + 23)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU19_QCH (CLK_GNPU_BASE + 24)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU2_QCH (CLK_GNPU_BASE + 25)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU20_QCH (CLK_GNPU_BASE + 26)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU21_QCH (CLK_GNPU_BASE + 27)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU22_QCH (CLK_GNPU_BASE + 28)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU23_QCH (CLK_GNPU_BASE + 29)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU24_QCH (CLK_GNPU_BASE + 30)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU25_QCH (CLK_GNPU_BASE + 31)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU26_QCH (CLK_GNPU_BASE + 32)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU27_QCH (CLK_GNPU_BASE + 33)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU28_QCH (CLK_GNPU_BASE + 34)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU29_QCH (CLK_GNPU_BASE + 35)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU3_QCH (CLK_GNPU_BASE + 36)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU30_QCH (CLK_GNPU_BASE + 37)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU31_QCH (CLK_GNPU_BASE + 38)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU4_QCH (CLK_GNPU_BASE + 39)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU5_QCH (CLK_GNPU_BASE + 40)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU6_QCH (CLK_GNPU_BASE + 41)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU7_QCH (CLK_GNPU_BASE + 42)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU8_QCH (CLK_GNPU_BASE + 43)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AU9_QCH (CLK_GNPU_BASE + 44)
|
|
#define GATE_LH_AST_SI_LD_GNPU_AULOADER_QCH (CLK_GNPU_BASE + 45)
|
|
#define GATE_LH_AST_SI_LD_GNPU_CU_RDATA_QCH (CLK_GNPU_BASE + 46)
|
|
#define GATE_LH_AST_SI_LD_GNPU_NPUC_SETREG_QCH (CLK_GNPU_BASE + 47)
|
|
#define GATE_LH_AST_SI_LD_GNPU_SRAM_WRRESP_QCH (CLK_GNPU_BASE + 48)
|
|
#define GATE_LH_AXI_MI_D0_GNPU_QCH (CLK_GNPU_BASE + 49)
|
|
#define GATE_LH_AXI_MI_D1_GNPU_QCH (CLK_GNPU_BASE + 50)
|
|
#define GATE_LH_AXI_MI_D_CTRL_GNPU_QCH (CLK_GNPU_BASE + 51)
|
|
#define GATE_LH_AXI_SI_D_RQ_GNPU_QCH (CLK_GNPU_BASE + 52)
|
|
#define GATE_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH (CLK_GNPU_BASE + 53)
|
|
#define GATE_SLH_AXI_MI_P_GNPU_QCH (CLK_GNPU_BASE + 54)
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#define GATE_SLH_AXI_SI_D_CMDQ_GNPU_QCH (CLK_GNPU_BASE + 55)
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#define GATE_SYSREG_GNPU_QCH (CLK_GNPU_BASE + 56)
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#define GATE_D_TZPC_GNPUP_QCH (CLK_GNPU_BASE + 57)
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#define GATE_GNPUP_CMU_GNPUP_QCH (CLK_GNPU_BASE + 58)
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#define GATE_IP_NPUPOST_QCH_CORE (CLK_GNPU_BASE + 59)
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#define GATE_LH_AST_MI_LD_GNPU_AU0_QCH (CLK_GNPU_BASE + 60)
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#define GATE_LH_AST_MI_LD_GNPU_AU1_QCH (CLK_GNPU_BASE + 61)
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#define GATE_LH_AST_MI_LD_GNPU_AU10_QCH (CLK_GNPU_BASE + 62)
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#define GATE_LH_AST_MI_LD_GNPU_AU11_QCH (CLK_GNPU_BASE + 63)
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#define GATE_LH_AST_MI_LD_GNPU_AU12_QCH (CLK_GNPU_BASE + 64)
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#define GATE_LH_AST_MI_LD_GNPU_AU13_QCH (CLK_GNPU_BASE + 65)
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#define GATE_LH_AST_MI_LD_GNPU_AU14_QCH (CLK_GNPU_BASE + 66)
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#define GATE_LH_AST_MI_LD_GNPU_AU15_QCH (CLK_GNPU_BASE + 67)
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#define GATE_LH_AST_MI_LD_GNPU_AU16_QCH (CLK_GNPU_BASE + 68)
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#define GATE_LH_AST_MI_LD_GNPU_AU17_QCH (CLK_GNPU_BASE + 69)
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#define GATE_LH_AST_MI_LD_GNPU_AU18_QCH (CLK_GNPU_BASE + 70)
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#define GATE_LH_AST_MI_LD_GNPU_AU19_QCH (CLK_GNPU_BASE + 71)
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#define GATE_LH_AST_MI_LD_GNPU_AU2_QCH (CLK_GNPU_BASE + 72)
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#define GATE_LH_AST_MI_LD_GNPU_AU20_QCH (CLK_GNPU_BASE + 73)
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#define GATE_LH_AST_MI_LD_GNPU_AU21_QCH (CLK_GNPU_BASE + 74)
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#define GATE_LH_AST_MI_LD_GNPU_AU22_QCH (CLK_GNPU_BASE + 75)
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#define GATE_LH_AST_MI_LD_GNPU_AU23_QCH (CLK_GNPU_BASE + 76)
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#define GATE_LH_AST_MI_LD_GNPU_AU24_QCH (CLK_GNPU_BASE + 77)
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#define GATE_LH_AST_MI_LD_GNPU_AU25_QCH (CLK_GNPU_BASE + 78)
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#define GATE_LH_AST_MI_LD_GNPU_AU26_QCH (CLK_GNPU_BASE + 79)
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#define GATE_LH_AST_MI_LD_GNPU_AU27_QCH (CLK_GNPU_BASE + 80)
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#define GATE_LH_AST_MI_LD_GNPU_AU28_QCH (CLK_GNPU_BASE + 81)
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#define GATE_LH_AST_MI_LD_GNPU_AU29_QCH (CLK_GNPU_BASE + 82)
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#define GATE_LH_AST_MI_LD_GNPU_AU3_QCH (CLK_GNPU_BASE + 83)
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#define GATE_LH_AST_MI_LD_GNPU_AU30_QCH (CLK_GNPU_BASE + 84)
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#define GATE_LH_AST_MI_LD_GNPU_AU31_QCH (CLK_GNPU_BASE + 85)
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#define GATE_LH_AST_MI_LD_GNPU_AU4_QCH (CLK_GNPU_BASE + 86)
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#define GATE_LH_AST_MI_LD_GNPU_AU5_QCH (CLK_GNPU_BASE + 87)
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#define GATE_LH_AST_MI_LD_GNPU_AU6_QCH (CLK_GNPU_BASE + 88)
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#define GATE_LH_AST_MI_LD_GNPU_AU7_QCH (CLK_GNPU_BASE + 89)
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#define GATE_LH_AST_MI_LD_GNPU_AU8_QCH (CLK_GNPU_BASE + 90)
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#define GATE_LH_AST_MI_LD_GNPU_AU9_QCH (CLK_GNPU_BASE + 91)
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#define GATE_LH_AST_MI_LD_GNPU_AULOADER_QCH (CLK_GNPU_BASE + 92)
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#define GATE_LH_AST_MI_LD_GNPU_CU_RDATA_QCH (CLK_GNPU_BASE + 93)
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#define GATE_LH_AST_MI_LD_GNPU_NPUC_SETREG_QCH (CLK_GNPU_BASE + 94)
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#define GATE_LH_AST_MI_LD_GNPU_SRAM_WRRESP_QCH (CLK_GNPU_BASE + 95)
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#define GATE_LH_AST_SI_LD_GNPUP_BU0_QCH (CLK_GNPU_BASE + 96)
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#define GATE_LH_AST_SI_LD_GNPUP_BU1_QCH (CLK_GNPU_BASE + 97)
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#define GATE_LH_AST_SI_LD_GNPUP_BU2_QCH (CLK_GNPU_BASE + 98)
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#define GATE_LH_AST_SI_LD_GNPUP_BU3_QCH (CLK_GNPU_BASE + 99)
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#define GATE_LH_AST_SI_LD_GNPUP_CU_WCH_QCH (CLK_GNPU_BASE + 100)
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#define GATE_LH_AST_SI_LD_GNPUP_NPUC_DONE_QCH (CLK_GNPU_BASE + 101)
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#define GATE_LH_AST_SI_LD_GNPUP_RDREQ_QCH (CLK_GNPU_BASE + 102)
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#define GATE_SLH_AXI_MI_P_GNPUP_QCH (CLK_GNPU_BASE + 103)
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#define GATE_SYSREG_GNPUP_QCH (CLK_GNPU_BASE + 104)
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#define DOUT_DIV_CLK_GNPU_NOC (CLK_GNPU_BASE + 105)
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#define DOUT_DIV_CLK_GNPUP_NOC (CLK_GNPU_BASE + 106)
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/* PERIC0 */
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#define CLK_PERIC0_BASE (1600)
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#define UMUX_CLKCMU_PERIC0_NOC (CLK_PERIC0_BASE + 0)
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#define UMUX_CLKCMU_PERIC0_IP0 (CLK_PERIC0_BASE + 1)
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#define UMUX_CLKCMU_PERIC0_IP1 (CLK_PERIC0_BASE + 2)
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#define GATE_D_TZPC_PERIC0_QCH (CLK_PERIC0_BASE + 3)
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#define GATE_GPIO_PERIC0_QCH (CLK_PERIC0_BASE + 4)
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#define GATE_PERIC0_CMU_PERIC0_QCH (CLK_PERIC0_BASE + 5)
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#define GATE_SLH_AXI_MI_P_PERIC0_QCH (CLK_PERIC0_BASE + 6)
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#define GATE_SYSREG_PERIC0_QCH (CLK_PERIC0_BASE + 7)
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#define DOUT_DIV_CLK_PERIC0_USI04 (CLK_PERIC0_BASE + 8)
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#define DOUT_DIV_CLK_PERIC0_I2C (CLK_PERIC0_BASE + 9)
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#define GATE_USI04_USI_QCH (CLK_PERIC0_BASE + 10)
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/* PERIC1 */
|
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#define CLK_PERIC1_BASE (1650)
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#define UMUX_CLKCMU_PERIC1_NOC (CLK_PERIC1_BASE + 0)
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#define UMUX_CLKCMU_PERIC1_IP0 (CLK_PERIC1_BASE + 1)
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#define UMUX_CLKCMU_PERIC1_IP1 (CLK_PERIC1_BASE + 2)
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#define GATE_D_TZPC_PERIC1_QCH (CLK_PERIC1_BASE + 3)
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#define GATE_GPIO_PERIC1_QCH (CLK_PERIC1_BASE + 4)
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#define GATE_PERIC1_CMU_PERIC1_QCH (CLK_PERIC1_BASE + 5)
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#define GATE_SLH_AXI_MI_P_CSISPERIC1_QCH (CLK_PERIC1_BASE + 6)
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#define GATE_SLH_AXI_MI_P_PERIC1_QCH (CLK_PERIC1_BASE + 7)
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#define GATE_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH (CLK_PERIC1_BASE + 8)
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#define GATE_SYSREG_PERIC1_QCH (CLK_PERIC1_BASE + 9)
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#define DOUT_DIV_CLK_PERIC1_UART_BT (CLK_PERIC1_BASE + 10)
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#define DOUT_DIV_CLK_PERIC1_I2C (CLK_PERIC1_BASE + 11)
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#define DOUT_DIV_CLK_PERIC1_USI07 (CLK_PERIC1_BASE + 12)
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#define DOUT_DIV_CLK_PERIC1_USI08 (CLK_PERIC1_BASE + 13)
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#define DOUT_DIV_CLK_PERIC1_USI09 (CLK_PERIC1_BASE + 14)
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#define DOUT_DIV_CLK_PERIC1_USI10 (CLK_PERIC1_BASE + 15)
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#define DOUT_DIV_CLK_PERIC1_SPI_MS_CTRL (CLK_PERIC1_BASE + 16)
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#define DOUT_DIV_CLK_PERIC1_USI07_SPI_I2C (CLK_PERIC1_BASE + 17)
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#define DOUT_DIV_CLK_PERIC1_USI08_SPI_I2C (CLK_PERIC1_BASE + 18)
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/* PERIC2 */
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|
#define CLK_PERIC2_BASE (1700)
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#define UMUX_CLKCMU_PERIC2_IP0 (CLK_PERIC2_BASE + 0)
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#define UMUX_CLKCMU_PERIC2_IP1 (CLK_PERIC2_BASE + 1)
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#define UMUX_CLKCMU_PERIC2_NOC (CLK_PERIC2_BASE + 2)
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#define GATE_D_TZPC_PERIC2_QCH (CLK_PERIC2_BASE + 3)
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#define GATE_GPIO_PERIC2_QCH (CLK_PERIC2_BASE + 4)
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#define GATE_PERIC2_CMU_PERIC2_QCH (CLK_PERIC2_BASE + 5)
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#define GATE_PWM_QCH (CLK_PERIC2_BASE + 6)
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#define GATE_SLH_AXI_MI_P_PERIC2_QCH (CLK_PERIC2_BASE + 7)
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#define GATE_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH (CLK_PERIC2_BASE + 8)
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#define GATE_SYSREG_PERIC2_QCH (CLK_PERIC2_BASE + 9)
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#define DOUT_DIV_CLK_PERIC2_I2C (CLK_PERIC2_BASE + 10)
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#define DOUT_DIV_CLK_PERIC2_USI00 (CLK_PERIC2_BASE + 11)
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#define DOUT_DIV_CLK_PERIC2_USI01 (CLK_PERIC2_BASE + 12)
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#define DOUT_DIV_CLK_PERIC2_USI02 (CLK_PERIC2_BASE + 13)
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#define DOUT_DIV_CLK_PERIC2_USI03 (CLK_PERIC2_BASE + 14)
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#define DOUT_DIV_CLK_PERIC2_USI05 (CLK_PERIC2_BASE + 15)
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#define DOUT_DIV_CLK_PERIC2_USI06 (CLK_PERIC2_BASE + 16)
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#define DOUT_DIV_CLK_PERIC2_SPI_MS_CTRL (CLK_PERIC2_BASE + 17)
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#define DOUT_DIV_CLK_PERIC2_USI11 (CLK_PERIC2_BASE + 18)
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#define DOUT_DIV_CLK_PERIC2_UART_DBG (CLK_PERIC2_BASE + 19)
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#define DOUT_DIV_CLK_PERIC2_USI00_SPI_I2C (CLK_PERIC2_BASE + 20)
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#define DOUT_DIV_CLK_PERIC2_USI01_SPI_I2C (CLK_PERIC2_BASE + 21)
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/* PERIS */
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#define CLK_PERIS_BASE (1750)
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#define UMUX_CLKCMU_PERIS_NOC (CLK_PERIS_BASE + 0)
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#define UMUX_CLKCMU_PERIS_GIC (CLK_PERIS_BASE + 1)
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#define GATE_BUSIF_DDD_PERIS_QCH (CLK_PERIS_BASE + 2)
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#define GATE_DFTMUX_PERIS_QCH (CLK_PERIS_BASE + 3)
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#define GATE_D_TZPC_PERIS_QCH (CLK_PERIS_BASE + 4)
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#define GATE_PERIS_CMU_PERIS_QCH (CLK_PERIS_BASE + 5)
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#define GATE_SLH_AXI_MI_P_PERIS_QCH (CLK_PERIS_BASE + 6)
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#define GATE_SLH_AXI_MI_P_PERISGIC_QCH (CLK_PERIS_BASE + 7)
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#define GATE_SYSREG_PERIS_QCH (CLK_PERIS_BASE + 8)
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#define GATE_MCT_QCH (CLK_PERIS_BASE + 9)
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#define GATE_WDT0_QCH (CLK_PERIS_BASE + 10)
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#define GATE_WDT1_QCH (CLK_PERIS_BASE + 11)
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|
|
|
/* S2D */
|
|
#define CLK_S2D_BASE (1800)
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|
#define GATE_BIS_S2D_QCH (CLK_S2D_BASE + 0)
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#define GATE_S2D_CMU_S2D_QCH (CLK_S2D_BASE + 1)
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|
|
/* SSP */
|
|
#define CLK_SSP_BASE (1820)
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#define UMUX_CLKCMU_SSP_NOC_USER (CLK_SSP_BASE + 0)
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#define GATE_D_TZPC_SSP_QCH (CLK_SSP_BASE + 1)
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#define GATE_LH_AXI_MI_L_STRONG_QCH (CLK_SSP_BASE + 2)
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#define GATE_PPMU_SSP_QCH (CLK_SSP_BASE + 3)
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#define GATE_RSTNSYNC_CLK_SSP_CM35P_QCH (CLK_SSP_BASE + 4)
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|
#define GATE_RTIC_QCH (CLK_SSP_BASE + 5)
|
|
#define GATE_SLH_ACEL_SI_D_SSP_QCH (CLK_SSP_BASE + 6)
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#define GATE_SLH_ASTL_SI_G_PPMU_SSP_QCH (CLK_SSP_BASE + 7)
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#define GATE_SLH_AXI_MI_P_SSP_QCH (CLK_SSP_BASE + 8)
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#define GATE_SSP_CMU_SSP_QCH (CLK_SSP_BASE + 9)
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|
#define GATE_SSS_QCH (CLK_SSP_BASE + 10)
|
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#define GATE_SWEEPER_D_SSP_QCH (CLK_SSP_BASE + 11)
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#define GATE_SYSMMU_SSP_QCH (CLK_SSP_BASE + 12)
|
|
#define GATE_SYSREG_SSP_QCH (CLK_SSP_BASE + 13)
|
|
#define GATE_VGEN_LITE_SSP_QCH (CLK_SSP_BASE + 14)
|
|
#define GATE_ADM_DAP_G_SSS_QCH (CLK_SSP_BASE + 15)
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|
|
|
|
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|
|
/* VTS */
|
|
#define CLK_VTS_BASE (1900)
|
|
#define UMUX_CLKCMU_VTS_DMIC_USER (CLK_VTS_BASE + 0)
|
|
#define GATE_D_TZPC_VTS_QCH (CLK_VTS_BASE + 1)
|
|
#define GATE_GPIO_VTS_QCH (CLK_VTS_BASE + 2)
|
|
#define GATE_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT (CLK_VTS_BASE + 3)
|
|
#define GATE_BAAW_C_VTS_QCH (CLK_VTS_BASE + 4)
|
|
#define GATE_MAILBOX_ABOX_VTS_QCH (CLK_VTS_BASE + 5)
|
|
#define GATE_MAILBOX_AP_VTS_QCH (CLK_VTS_BASE + 6)
|
|
#define GATE_MAILBOX_DNC_VTS_QCH (CLK_VTS_BASE + 7)
|
|
#define GATE_PDMA_VTS_QCH (CLK_VTS_BASE + 8)
|
|
#define GATE_SLH_AXI_MI_LD_AUDVTS_QCH (CLK_VTS_BASE + 9)
|
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#define GATE_SLH_AXI_MI_LD_DNCVTS_QCH (CLK_VTS_BASE + 10)
|
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#define GATE_SLH_AXI_MI_LP_VTS_QCH (CLK_VTS_BASE + 11)
|
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#define GATE_SLH_AXI_MI_P_VTS_QCH (CLK_VTS_BASE + 12)
|
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#define GATE_SLH_AXI_SI_C_VTS_QCH (CLK_VTS_BASE + 13)
|
|
#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0 (CLK_VTS_BASE + 14)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1 (CLK_VTS_BASE + 15)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2 (CLK_VTS_BASE + 16)
|
|
#define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK (CLK_VTS_BASE + 17)
|
|
#define GATE_SWEEPER_C_VTS_QCH (CLK_VTS_BASE + 18)
|
|
#define GATE_SYSREG_VTS_QCH (CLK_VTS_BASE + 19)
|
|
#define GATE_VTS_CMU_VTS_QCH (CLK_VTS_BASE + 20)
|
|
#define GATE_WDT_VTS_QCH (CLK_VTS_BASE + 21)
|
|
#define GATE_YAMIN_MCU_VTS_QCH_CLKIN (CLK_VTS_BASE + 22)
|
|
#define GATE_YAMIN_MCU_VTS_QCH_DBGCLK (CLK_VTS_BASE + 23)
|
|
#define DOUT_DIV_CLK_VTS_DMIC_IF (CLK_VTS_BASE + 24)
|
|
#define DOUT_DIV_CLK_VTS_DMIC_IF_DIV2 (CLK_VTS_BASE + 25)
|
|
#define DOUT_DIV_CLK_VTS_NOC (CLK_VTS_BASE + 26)
|
|
#define DOUT_DIV_CLK_VTS_SERIAL_LIF (CLK_VTS_BASE + 27)
|
|
#define DOUT_DIV_CLK_VTS_DMIC_AHB (CLK_VTS_BASE + 28)
|
|
#define DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE (CLK_VTS_BASE + 29)
|
|
#define DOUT_DIV_CLK_VTS_CPU (CLK_VTS_BASE + 30)
|
|
#define DOUT_DIV_CLKVTS_AUD_DMIC0 (CLK_VTS_BASE + 31)
|
|
#define DOUT_DIV_CLKVTS_AUD_DMIC1 (CLK_VTS_BASE + 32)
|
|
#define DOUT_DIV_CLK_VTS_DMAILBOX_CCLK (CLK_VTS_BASE + 33)
|
|
#define MOUT_CLK_VTS_DMIC_PAD (CLK_VTS_BASE + 34)
|
|
#define MOUT_CLK_VTS_SERIAL_LIF (CLK_VTS_BASE + 35)
|
|
#define MOUT_CLKALIVE_VTS_NOC_USER (CLK_VTS_BASE + 36)
|
|
#define MOUT_CLKALIVE_VTS_RCO_USER (CLK_VTS_BASE + 37)
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|
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|
|
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|
|
/* YUVP */
|
|
#define CLK_YUVP_BASE (1950)
|
|
#define UMUX_CLKCMU_YUVP_NOC (CLK_YUVP_BASE + 0)
|
|
#define GATE_ADD_YUVP_QCH (CLK_YUVP_BASE + 1)
|
|
#define GATE_BUSIF_ADD_YUVP_QCH (CLK_YUVP_BASE + 2)
|
|
#define GATE_BUSIF_DDD_YUVP_QCH (CLK_YUVP_BASE + 3)
|
|
#define GATE_BUSIF_HPM_YUVP_QCH (CLK_YUVP_BASE + 4)
|
|
#define GATE_D_TZPC_YUVP_QCH (CLK_YUVP_BASE + 5)
|
|
#define GATE_LH_AST_MI_OTF0_MCFPYUVP_QCH (CLK_YUVP_BASE + 6)
|
|
#define GATE_LH_AST_SI_OTF_YUVPDRCP_QCH (CLK_YUVP_BASE + 7)
|
|
#define GATE_LH_AST_SI_OTF_YUVPMCFP_QCH (CLK_YUVP_BASE + 8)
|
|
#define GATE_PPMU_YUVP_QCH (CLK_YUVP_BASE + 9)
|
|
#define GATE_SLH_ASTL_SI_G_PPMU_YUVP_QCH (CLK_YUVP_BASE + 10)
|
|
#define GATE_SLH_AXI_MI_P_YUVP_QCH (CLK_YUVP_BASE + 11)
|
|
#define GATE_SLH_AXI_SI_D_YUVP_QCH (CLK_YUVP_BASE + 12)
|
|
#define GATE_SYSMMU_D_YUVP_QCH_S1 (CLK_YUVP_BASE + 13)
|
|
#define GATE_SYSMMU_D_YUVP_QCH_S2 (CLK_YUVP_BASE + 14)
|
|
#define GATE_SYSREG_YUVP_QCH (CLK_YUVP_BASE + 15)
|
|
#define GATE_VGEN_LITE_YUVP_QCH (CLK_YUVP_BASE + 16)
|
|
#define GATE_YUVP_QCH (CLK_YUVP_BASE + 17)
|
|
#define GATE_YUVP_CMU_YUVP_QCH (CLK_YUVP_BASE + 18)
|
|
#define DOUT_DIV_CLK_YUVP_NOCP (CLK_YUVP_BASE + 19)
|
|
#define DOUT_DIV_CLK_YUVP_NOC (CLK_YUVP_BASE + 20)
|
|
|
|
|
|
/* CSTAT */
|
|
#define CLK_CSTAT_BASE (2000)
|
|
#define UMUX_CLKCMU_CSTAT_NOC (CLK_CSTAT_BASE + 0)
|
|
|
|
|
|
/* DSP */
|
|
#define CLK_DSP_BASE (2050)
|
|
#define UMUX_CLKCMU_DSP_NOC (CLK_DSP_BASE + 0)
|
|
#define GATE_DSP_CMU_DSP_QCH (CLK_DSP_BASE + 1)
|
|
#define GATE_D_TZPC_DSP_QCH (CLK_DSP_BASE + 2)
|
|
#define GATE_IP_DSP_QCH (CLK_DSP_BASE + 3)
|
|
#define GATE_LH_AST_MI_LD_STRM_SDMADSP_QCH (CLK_DSP_BASE + 4)
|
|
#define GATE_LH_AXI_MI_LD_DNCDSP_DMA_QCH (CLK_DSP_BASE + 5)
|
|
#define GATE_LH_AXI_MI_LD_DNCDSP_SFR_QCH (CLK_DSP_BASE + 6)
|
|
#define GATE_LH_AXI_SI_LD_DSPDNC_SFR_QCH (CLK_DSP_BASE + 7)
|
|
#define GATE_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH (CLK_DSP_BASE + 8)
|
|
#define GATE_SLH_AXI_MI_P_DSP_QCH (CLK_DSP_BASE + 9)
|
|
#define GATE_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH (CLK_DSP_BASE + 10)
|
|
#define GATE_SYSREG_DSP_QCH (CLK_DSP_BASE + 11)
|
|
|
|
|
|
/* SDMA */
|
|
#define CLK_SDMA_BASE (2100)
|
|
#define UMUX_CLKCMU_SDMA_NOC (CLK_SDMA_BASE + 0)
|
|
#define GATE_D_TZPC_SDMA_QCH (CLK_SDMA_BASE + 1)
|
|
#define GATE_IP_SDMA_QCH (CLK_SDMA_BASE + 2)
|
|
#define GATE_LH_AST_SI_LD_STRM_SDMADSP0_QCH (CLK_SDMA_BASE + 3)
|
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#define GATE_LH_AST_SI_LD_STRM_SDMADSP1_QCH (CLK_SDMA_BASE + 4)
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#define GATE_LH_AXI_MI_LP_DNCSDMA_QCH (CLK_SDMA_BASE + 5)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA0_QCH (CLK_SDMA_BASE + 6)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA1_QCH (CLK_SDMA_BASE + 7)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA2_QCH (CLK_SDMA_BASE + 8)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA3_QCH (CLK_SDMA_BASE + 9)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA4_QCH (CLK_SDMA_BASE + 10)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA5_QCH (CLK_SDMA_BASE + 11)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA6_QCH (CLK_SDMA_BASE + 12)
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#define GATE_LH_AXI_SI_LD_SDMADNC_DATA7_QCH (CLK_SDMA_BASE + 13)
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#define GATE_LH_AXI_SI_LD_SDMADNC_MMU0_QCH (CLK_SDMA_BASE + 14)
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#define GATE_LH_AXI_SI_LD_SDMADNC_MMU1_QCH (CLK_SDMA_BASE + 15)
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#define GATE_LH_AXI_SI_LD_SDMADNC_MMU2_QCH (CLK_SDMA_BASE + 16)
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#define GATE_LH_AXI_SI_LD_SDMADNC_MMU3_QCH (CLK_SDMA_BASE + 17)
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#define GATE_SDMA_CMU_SDMA_QCH (CLK_SDMA_BASE + 18)
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#define GATE_SLH_AXI_MI_P_SDMA_QCH (CLK_SDMA_BASE + 19)
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#define GATE_SYSREG_SDMA_QCH (CLK_SDMA_BASE + 20)
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/* UFD */
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#define CLK_UFD_BASE (2150)
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#define GATE_BAAW_D_UFDDNC_QCH (CLK_UFD_BASE + 0)
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#define GATE_D_TZPC_UFD_QCH (CLK_UFD_BASE + 1)
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#define GATE_I3C_UFD_QCH_PCLK (CLK_UFD_BASE + 2)
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#define GATE_I3C_UFD_QCH_SCLK (CLK_UFD_BASE + 3)
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#define GATE_PDMA_UFD_QCH (CLK_UFD_BASE + 4)
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#define GATE_SLH_AST_MI_OTF_CSISUFD_QCH (CLK_UFD_BASE + 5)
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#define GATE_SLH_AXI_MI_LP_CMGPUFD_QCH (CLK_UFD_BASE + 6)
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#define GATE_SLH_AXI_MI_P_UFD_QCH (CLK_UFD_BASE + 7)
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#define GATE_SLH_AXI_SI_D_UFD_QCH (CLK_UFD_BASE + 8)
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#define GATE_SLH_AXI_SI_LD_UFDDNC_QCH (CLK_UFD_BASE + 9)
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#define GATE_SLH_AXI_SI_LP_UFDCSIS_QCH (CLK_UFD_BASE + 10)
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#define GATE_SPI_UFD_QCH (CLK_UFD_BASE + 11)
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#define GATE_SRAM_MIU_UFD_QCH (CLK_UFD_BASE + 12)
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#define GATE_SYSREG_UFD_QCH (CLK_UFD_BASE + 13)
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#define GATE_SYSREG_UFD_SECURE_QCH (CLK_UFD_BASE + 14)
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#define GATE_UFD_CMU_UFD_QCH (CLK_UFD_BASE + 15)
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#define GATE_VGEN_LITE_D_UFD_QCH (CLK_UFD_BASE + 16)
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#define GATE_UFD_QCH (CLK_UFD_BASE + 17)
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/* CLKOUT */
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#define CLK_CLKOUT_BASE (2400)
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#define OSC_NFC (CLK_CLKOUT_BASE + 0)
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#define OSC_AUD (CLK_CLKOUT_BASE + 1)
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS (2600 + 1)
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#define ACPM_DVFS_MIF (0x0B040000)
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#define ACPM_DVFS_INT (0x0B040001)
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#define ACPM_DVFS_CPUCL0 (0x0B040002)
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#define ACPM_DVFS_CPUCL1 (0x0B040003)
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#define ACPM_DVFS_CPUCL2 (0x0B040004)
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#define ACPM_DVFS_NPU (0x0B040005)
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#define ACPM_DVFS_DSU (0x0B040006)
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#define ACPM_DVFS_DISP (0x0B040007)
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#define ACPM_DVFS_AUD (0x0B040008)
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#define ACPM_DVFS_CP_CPU (0x0B040009)
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#define ACPM_DVFS_CP (0x0B04000A)
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#define ACPM_DVFS_CP_EM (0x0B04000B)
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#define ACPM_DVFS_CP_MCW (0x0B04000C)
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#define ACPM_DVFS_G3D (0x0B04000D)
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#define ACPM_DVFS_INTCAM (0x0B04000E)
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#define ACPM_DVFS_CAM (0x0B04000F)
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#define ACPM_DVFS_CSIS (0x0B040010)
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#define ACPM_DVFS_ISP (0x0B040011)
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#define ACPM_DVFS_MFC0 (0x0B040012)
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#define ACPM_DVFS_MFC1 (0x0B040013)
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#define ACPM_DVFS_INTSCI (0x0B040014)
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#define ACPM_DVFS_DSP (0x0B040015)
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#define ACPM_DVFS_DNC (0x0B040016)
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#define ACPM_DVFS_GNSS (0x0B040017)
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#define ACPM_DVFS_ALIVE (0x0B040018)
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#define ACPM_DVFS_CHUB (0x0B040019)
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#define ACPM_DVFS_VTS (0x0B04001A)
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#define ACPM_DVFS_HSI0 (0x0B04001B)
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#define ACPM_DVFS_UFD (0x0B04001C)
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#define EWF_CMU_ALIVE (0)
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#define EWF_CMU_AUD (1)
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#define EWF_CMU_BUS0 (2)
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#define EWF_CMU_BUS1 (3)
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#define EWF_CMU_BUS2 (4)
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#define EWF_CMU_CMGP (6)
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#define EWF_CMU_CORE (7)
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#define EWF_CMU_CPUCL0 (8)
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#define EWF_CMU_CPUCL1 (9)
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#define EWF_CMU_CPUCL2 (10)
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#define EWF_CMU_CSIS (11)
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#define EWF_CMU_DNS (12)
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#define EWF_CMU_DPUB (13)
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#define EWF_CMU_DPUF0 (14)
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#define EWF_CMU_DPUF1 (15)
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#define EWF_CMU_G3D (17)
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#define EWF_CMU_HSI0 (18)
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#define EWF_CMU_HSI1 (19)
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#define EWF_CMU_ITP (21)
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#define EWF_CMU_LME (22)
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#define EWF_CMU_MCFP0 (23)
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#define EWF_CMU_MCFP1 (24)
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#define EWF_CMU_MCSC (25)
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#define EWF_CMU_MFC0 (26)
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#define EWF_CMU_MFC1 (27)
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#define EWF_CMU_MIF0 (28)
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#define EWF_CMU_MIF1 (29)
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#define EWF_CMU_MIF2 (30)
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#define EWF_CMU_MIF3 (31)
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#define EWF_GRP_CAM (51)
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_9830_H */
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