1046 lines
47 KiB
C
Executable file
1046 lines
47 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos9830 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_9830_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_9830_H
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#define NONE (0 + 0)
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#define OSCCLK (0 + 1)
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/* ALIVE */
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#define CLK_ALIVE_BASE (10)
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#define GATE_ALIVE_CMU_ALIVE_QCH (CLK_ALIVE_BASE + 0)
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#define GATE_APBIF_PMU_ALIVE_QCH (CLK_ALIVE_BASE + 1)
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#define GATE_APBIF_RTC_QCH (CLK_ALIVE_BASE + 2)
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#define GATE_APBIF_TOP_RTC_QCH (CLK_ALIVE_BASE + 3)
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#define GATE_CLKMON_QCH (CLK_ALIVE_BASE + 4)
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#define GATE_DBGCORE_UART_QCH (CLK_ALIVE_BASE + 5)
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#define GATE_DOUBLE_IP_BATCHER_QCH_APM (CLK_ALIVE_BASE + 6)
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#define GATE_DOUBLE_IP_BATCHER_QCH_CPU (CLK_ALIVE_BASE + 7)
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#define GATE_DOUBLE_IP_BATCHER_QCH_SEMA (CLK_ALIVE_BASE + 8)
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#define GATE_DTZPC_ALIVE_QCH (CLK_ALIVE_BASE + 9)
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#define GATE_GPIO_ALIVE_QCH (CLK_ALIVE_BASE + 10)
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#define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_ALIVE_BASE + 11)
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#define GATE_GREBEINTEGRATION_QCH_DBG (CLK_ALIVE_BASE + 12)
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#define GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH (CLK_ALIVE_BASE + 13)
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#define GATE_I3C_PMIC_QCH_P (CLK_ALIVE_BASE + 14)
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#define GATE_I3C_PMIC_QCH_S (CLK_ALIVE_BASE + 15)
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#define GATE_INTMEM_QCH (CLK_ALIVE_BASE + 16)
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#define GATE_MAILBOX_APM_AP_QCH (CLK_ALIVE_BASE + 17)
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#define GATE_MAILBOX_APM_CP_QCH (CLK_ALIVE_BASE + 18)
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#define GATE_MAILBOX_AP_CP_QCH (CLK_ALIVE_BASE + 19)
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#define GATE_MAILBOX_AP_CP_S_QCH (CLK_ALIVE_BASE + 20)
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#define GATE_MAILBOX_AP_DBGCORE_QCH (CLK_ALIVE_BASE + 21)
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#define GATE_PEM_QCH (CLK_ALIVE_BASE + 22)
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#define GATE_PMU_INTR_GEN_QCH (CLK_ALIVE_BASE + 23)
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#define GATE_ROM_CRC32_HOST_QCH (CLK_ALIVE_BASE + 24)
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#define GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH (CLK_ALIVE_BASE + 25)
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#define GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH (CLK_ALIVE_BASE + 26)
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#define GATE_SS_DBGCORE_QCH_GREBE (CLK_ALIVE_BASE + 27)
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#define GATE_SS_DBGCORE_QCH_DBG (CLK_ALIVE_BASE + 28)
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#define GATE_SWEEPER_P_ALIVE_QCH (CLK_ALIVE_BASE + 29)
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#define GATE_SYSREG_ALIVE_QCH (CLK_ALIVE_BASE + 30)
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#define GATE_APBIF_SYSREG_VGPIO2AP_QCH (CLK_ALIVE_BASE + 31)
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#define GATE_APBIF_SYSREG_VGPIO2APM_QCH (CLK_ALIVE_BASE + 32)
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#define GATE_APBIF_SYSREG_VGPIO2PMU_QCH (CLK_ALIVE_BASE + 33)
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#define GATE_VGEN_LITE_ALIVE_QCH (CLK_ALIVE_BASE + 34)
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#define GATE_WDT_ALIVE_QCH (CLK_ALIVE_BASE + 35)
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#define DOUT_CLKCMU_VTS_BUS (CLK_ALIVE_BASE + 36)
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#define DOUT_DIV_CLK_ALIVE_BUS (CLK_ALIVE_BASE + 37)
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#define DOUT_CLKCMU_CMGP_BUS (CLK_ALIVE_BASE + 38)
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#define DOUT_DIV_CLK_ALIVE_I3C_PMIC (CLK_ALIVE_BASE + 39)
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#define DOUT_CLKCMU_CMGP_PERI (CLK_ALIVE_BASE + 40)
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#define DOUT_CLKCMU_CMGP_ADC (CLK_ALIVE_BASE + 41)
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#define DOUT_DIV_CLK_ALIVE_DBGCORE_UART (CLK_ALIVE_BASE + 42)
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/* AUD */
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#define CLK_AUD_BASE (100)
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#define UMUX_CLK_AUD_UAIF6 (CLK_AUD_BASE + 0)
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#define GATE_ABOX_QCH_ACLK (CLK_AUD_BASE + 1)
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#define GATE_ABOX_QCH_BCLK_DSIF (CLK_AUD_BASE + 2)
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#define GATE_ABOX_QCH_BCLK0 (CLK_AUD_BASE + 3)
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#define GATE_ABOX_QCH_BCLK1 (CLK_AUD_BASE + 4)
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#define GATE_ABOX_QCH_BCLK2 (CLK_AUD_BASE + 5)
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#define GATE_ABOX_QCH_BCLK3 (CLK_AUD_BASE + 6)
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#define GATE_ABOX_QCH_CPU (CLK_AUD_BASE + 7)
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#define GATE_ABOX_QCH_BCLK4 (CLK_AUD_BASE + 8)
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#define GATE_ABOX_QCH_CNT (CLK_AUD_BASE + 9)
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#define GATE_ABOX_QCH_BCLK5 (CLK_AUD_BASE + 10)
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#define GATE_ABOX_QCH_CCLK_ASB (CLK_AUD_BASE + 11)
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#define GATE_ABOX_QCH_SCLK (CLK_AUD_BASE + 12)
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#define GATE_ABOX_QCH_BCLK6 (CLK_AUD_BASE + 13)
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#define GATE_ABOX_QCH_XCLK (CLK_AUD_BASE + 14)
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#define GATE_ABOX_QCH_PCMC_CLK (CLK_AUD_BASE + 15)
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#define GATE_AUD_CMU_AUD_QCH (CLK_AUD_BASE + 16)
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#define GATE_BAAW_D_AUDVTS_QCH (CLK_AUD_BASE + 17)
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#define GATE_D_TZPC_AUD_QCH (CLK_AUD_BASE + 18)
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#define GATE_MAILBOX_AUD0_QCH (CLK_AUD_BASE + 19)
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#define GATE_MAILBOX_AUD1_QCH (CLK_AUD_BASE + 20)
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#define GATE_MAILBOX_AUD2_QCH (CLK_AUD_BASE + 21)
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#define GATE_MAILBOX_AUD3_QCH (CLK_AUD_BASE + 22)
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#define GATE_PPMU_AUD_QCH (CLK_AUD_BASE + 23)
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#define GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH (CLK_AUD_BASE + 24)
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#define GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH (CLK_AUD_BASE + 25)
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#define GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH (CLK_AUD_BASE + 26)
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#define GATE_SMMU_AUD_QCH_S1 (CLK_AUD_BASE + 27)
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#define GATE_SMMU_AUD_QCH_S2 (CLK_AUD_BASE + 28)
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#define GATE_SYSREG_AUD_QCH (CLK_AUD_BASE + 29)
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#define GATE_TREX_AUD_QCH (CLK_AUD_BASE + 30)
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#define GATE_VGEN_LITE_AUD_QCH (CLK_AUD_BASE + 31)
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#define GATE_WDT_AUD_QCH (CLK_AUD_BASE + 32)
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#define DOUT_DIV_CLK_AUD_CPU (CLK_AUD_BASE + 33)
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#define DOUT_DIV_CLK_AUD_AUDIF (CLK_AUD_BASE + 34)
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#define DOUT_DIV_CLK_AUD_CPU_PCLKDBG (CLK_AUD_BASE + 35)
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#define DOUT_DIV_CLK_AUD_DSIF (CLK_AUD_BASE + 36)
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#define DOUT_DIV_CLK_AUD_UAIF0 (CLK_AUD_BASE + 37)
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#define DOUT_DIV_CLK_AUD_UAIF1 (CLK_AUD_BASE + 38)
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#define DOUT_DIV_CLK_AUD_UAIF2 (CLK_AUD_BASE + 39)
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#define DOUT_DIV_CLK_AUD_UAIF3 (CLK_AUD_BASE + 40)
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#define DOUT_DIV_CLK_AUD_CPU_ACLK (CLK_AUD_BASE + 41)
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#define DOUT_DIV_CLK_AUD_BUS (CLK_AUD_BASE + 42)
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#define DOUT_DIV_CLK_AUD_BUSP (CLK_AUD_BASE + 43)
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#define DOUT_DIV_CLK_AUD_CNT (CLK_AUD_BASE + 44)
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#define DOUT_DIV_CLK_AUD_UAIF4 (CLK_AUD_BASE + 45)
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#define DOUT_DIV_CLK_AUD_UAIF5 (CLK_AUD_BASE + 46)
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#define DOUT_DIV_CLK_AUD_SCLK (CLK_AUD_BASE + 47)
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#define DOUT_DIV_CLK_AUD_DMIC1 (CLK_AUD_BASE + 48)
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#define DOUT_DIV_CLK_AUD_UAIF6 (CLK_AUD_BASE + 49)
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#define DOUT_CLKAUD_VTS_DMIC0 (CLK_AUD_BASE + 50)
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#define DOUT_CLKAUD_HSI0_BUS (CLK_AUD_BASE + 51)
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#define DOUT_CLKAUD_HSI0_USB31DRD (CLK_AUD_BASE + 52)
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#define DOUT_DIV_CLK_AUD_PCMC (CLK_AUD_BASE + 53)
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#define PLL_OUT_AUD0 (CLK_AUD_BASE + 54)
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#define PLL_OUT_AUD1 (CLK_AUD_BASE + 55)
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#define UMUX_CP_PCMC_CLK (CLK_AUD_BASE + 56)
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#define UMUX_CLK_AUD_PCMC (CLK_AUD_BASE + 57)
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/* BUS0 */
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#define CLK_BUS0_BASE (200)
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#define GATE_ASYNCSFR_WR_SMC_QCH (CLK_BUS0_BASE + 0)
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#define GATE_BAAW_P_VPC_QCH (CLK_BUS0_BASE + 1)
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#define GATE_BUS0_CMU_BUS0_QCH (CLK_BUS0_BASE + 2)
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#define GATE_BUSIF_CMUTOPC_QCH (CLK_BUS0_BASE + 3)
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#define GATE_CACHEAID_BUS0_QCH (CLK_BUS0_BASE + 4)
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#define GATE_CMU_BUS0_CMUREF_QCH (CLK_BUS0_BASE + 5)
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#define GATE_D_TZPC_BUS0_QCH (CLK_BUS0_BASE + 6)
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#define GATE_SYSREG_BUS0_QCH (CLK_BUS0_BASE + 7)
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#define GATE_TREX_D0_BUS0_QCH (CLK_BUS0_BASE + 8)
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#define GATE_TREX_D1_BUS0_QCH (CLK_BUS0_BASE + 9)
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#define GATE_TREX_P_BUS0_QCH (CLK_BUS0_BASE + 10)
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/* BUS1 */
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#define CLK_BUS1_BASE (250)
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#define UMUX_CLKCMU_BUS1_BUS (CLK_BUS1_BASE + 0)
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#define GATE_BAAW_P_VTS_QCH (CLK_BUS1_BASE + 1)
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#define GATE_BUS1_CMU_BUS1_QCH (CLK_BUS1_BASE + 2)
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#define GATE_CMU_BUS1_CMUREF_QCH (CLK_BUS1_BASE + 3)
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#define GATE_DIT_QCH (CLK_BUS1_BASE + 4)
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#define GATE_D_TZPC_BUS1_QCH (CLK_BUS1_BASE + 5)
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#define GATE_PDMA_QCH (CLK_BUS1_BASE + 6)
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#define GATE_QE_PDMA_QCH (CLK_BUS1_BASE + 7)
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#define GATE_QE_SPDMA_QCH (CLK_BUS1_BASE + 8)
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#define GATE_SBIC_QCH (CLK_BUS1_BASE + 9)
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#define GATE_SPDMA_QCH (CLK_BUS1_BASE + 10)
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#define GATE_SYSMMU_S2_ACVPS_QCH (CLK_BUS1_BASE + 11)
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#define GATE_SYSMMU_S2_DIT_QCH (CLK_BUS1_BASE + 12)
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#define GATE_SYSMMU_S2_SBIC_QCH (CLK_BUS1_BASE + 13)
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#define GATE_SYSREG_BUS1_QCH (CLK_BUS1_BASE + 14)
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#define GATE_TREX_D_BUS1_QCH (CLK_BUS1_BASE + 15)
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#define GATE_TREX_P_BUS1_QCH (CLK_BUS1_BASE + 16)
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#define GATE_TREX_RB_BUS1_QCH (CLK_BUS1_BASE + 17)
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#define GATE_VGEN_LITE_BUS1_QCH (CLK_BUS1_BASE + 18)
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#define GATE_VGEN_PDMA_QCH (CLK_BUS1_BASE + 19)
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/* BUS2 */
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#define CLK_BUS2_BASE (300)
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#define GATE_BUS2_CMU_BUS2_QCH (CLK_BUS2_BASE + 0)
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#define GATE_CMU_BUS2_CMUREF_QCH (CLK_BUS2_BASE + 1)
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#define GATE_D_TZPC_BUS2_QCH (CLK_BUS2_BASE + 2)
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#define GATE_SYSREG_BUS2_QCH (CLK_BUS2_BASE + 3)
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#define GATE_TREX_D_BUS2_QCH (CLK_BUS2_BASE + 4)
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#define GATE_TREX_P_BUS2_QCH (CLK_BUS2_BASE + 5)
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/* CMGP */
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#define CLK_CMGP_BASE (350)
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#define UMUX_CLKCMU_CMGP_BUS (CLK_CMGP_BASE + 0)
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#define UMUX_CLKCMU_CMGP_PERI (CLK_CMGP_BASE + 1)
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#define UMUX_CLKCMU_CMGP_ADC (CLK_CMGP_BASE + 2)
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#define GATE_ADC_CMGP_QCH_S0 (CLK_CMGP_BASE + 3)
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#define GATE_ADC_CMGP_QCH_S1 (CLK_CMGP_BASE + 4)
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#define GATE_ADC_CMGP_QCH_OSC (CLK_CMGP_BASE + 5)
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#define GATE_APBIF_GPIO_CMGP_QCH (CLK_CMGP_BASE + 6)
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#define GATE_CMGP_CMU_CMGP_QCH (CLK_CMGP_BASE + 7)
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#define GATE_D_TZPC_CMGP_QCH (CLK_CMGP_BASE + 8)
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#define GATE_GPIO_CMGP_QCH (CLK_CMGP_BASE + 9)
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#define GATE_I2C_CMGP0_QCH (CLK_CMGP_BASE + 10)
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#define GATE_I2C_CMGP1_QCH (CLK_CMGP_BASE + 11)
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#define GATE_I2C_CMGP2_QCH (CLK_CMGP_BASE + 12)
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#define GATE_I2C_CMGP3_QCH (CLK_CMGP_BASE + 13)
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#define GATE_I3C_CMGP_QCH_P (CLK_CMGP_BASE + 14)
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#define GATE_I3C_CMGP_QCH_S (CLK_CMGP_BASE + 15)
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#define GATE_SYSREG_CMGP_QCH (CLK_CMGP_BASE + 16)
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#define GATE_SYSREG_CMGP2APM_QCH (CLK_CMGP_BASE + 17)
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#define GATE_SYSREG_CMGP2CP_QCH (CLK_CMGP_BASE + 18)
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#define GATE_SYSREG_CMGP2PMU_AP_QCH (CLK_CMGP_BASE + 19)
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#define GATE_USI_CMGP0_QCH (CLK_CMGP_BASE + 20)
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#define GATE_USI_CMGP1_QCH (CLK_CMGP_BASE + 21)
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#define GATE_USI_CMGP2_QCH (CLK_CMGP_BASE + 22)
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#define GATE_USI_CMGP3_QCH (CLK_CMGP_BASE + 23)
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#define DOUT_DIV_CLK_CMGP_I2C0 (CLK_CMGP_BASE + 24)
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#define DOUT_DIV_CLK_CMGP_USI1 (CLK_CMGP_BASE + 25)
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#define DOUT_DIV_CLK_CMGP_USI0 (CLK_CMGP_BASE + 26)
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#define DOUT_DIV_CLK_CMGP_USI2 (CLK_CMGP_BASE + 27)
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#define DOUT_DIV_CLK_CMGP_USI3 (CLK_CMGP_BASE + 28)
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#define DOUT_DIV_CLK_CMGP_I2C1 (CLK_CMGP_BASE + 29)
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#define DOUT_DIV_CLK_CMGP_I2C2 (CLK_CMGP_BASE + 30)
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#define DOUT_DIV_CLK_CMGP_I2C3 (CLK_CMGP_BASE + 31)
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#define DOUT_DIV_CLK_CMGP_I3C (CLK_CMGP_BASE + 32)
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/* TOP */
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#define CLK_TOP_BASE (450)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK0 (CLK_TOP_BASE + 0)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK1 (CLK_TOP_BASE + 1)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK2 (CLK_TOP_BASE + 2)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK3 (CLK_TOP_BASE + 3)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK4 (CLK_TOP_BASE + 4)
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#define GATE_DFTMUX_CMU_QCH_CIS_CLK5 (CLK_TOP_BASE + 5)
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#define CIS_CLK0 (CLK_TOP_BASE + 6)
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#define CIS_CLK1 (CLK_TOP_BASE + 7)
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#define CIS_CLK2 (CLK_TOP_BASE + 8)
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#define CIS_CLK3 (CLK_TOP_BASE + 9)
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#define CIS_CLK4 (CLK_TOP_BASE + 10)
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#define CIS_CLK5 (CLK_TOP_BASE + 11)
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#define DOUT_CLK_TOP_HSI0_BUS (CLK_TOP_BASE + 12)
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/* CORE */
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#define CLK_CORE_BASE (500)
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#define GATE_TREX_D_CORE_QCH (CLK_CORE_BASE + 0)
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#define GATE_TREX_P0_CORE_QCH (CLK_CORE_BASE + 1)
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#define GATE_TREX_P1_CORE_QCH (CLK_CORE_BASE + 2)
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/* CSIS */
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#define CLK_CSIS_BASE (550)
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#define GATE_CSISX6_QCH_VOTF0 (CLK_CSIS_BASE + 0)
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#define GATE_CSISX6_QCH_DMA (CLK_CSIS_BASE + 1)
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#define GATE_CSIS_CMU_CSIS_QCH (CLK_CSIS_BASE + 2)
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#define GATE_D_TZPC_CSIS_QCH (CLK_CSIS_BASE + 3)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0 (CLK_CSIS_BASE + 4)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1 (CLK_CSIS_BASE + 5)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2 (CLK_CSIS_BASE + 6)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3 (CLK_CSIS_BASE + 7)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4 (CLK_CSIS_BASE + 8)
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#define GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5 (CLK_CSIS_BASE + 9)
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#define GATE_OIS_MCU_TOP_QCH (CLK_CSIS_BASE + 10)
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#define GATE_PDP_TOP_QCH_PDP_TOP (CLK_CSIS_BASE + 11)
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#define GATE_PDP_TOP_QCH_C2_PDP (CLK_CSIS_BASE + 12)
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#define GATE_PPMU_D0_QCH (CLK_CSIS_BASE + 13)
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#define GATE_PPMU_D1_QCH (CLK_CSIS_BASE + 14)
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#define GATE_PPMU_D2_QCH (CLK_CSIS_BASE + 15)
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#define GATE_PPMU_D3_QCH (CLK_CSIS_BASE + 16)
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#define GATE_QE_CSIS_DMA0_QCH (CLK_CSIS_BASE + 17)
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#define GATE_QE_CSIS_DMA1_QCH (CLK_CSIS_BASE + 18)
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#define GATE_QE_CSIS_DMA2_QCH (CLK_CSIS_BASE + 19)
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#define GATE_QE_CSIS_DMA3_QCH (CLK_CSIS_BASE + 20)
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#define GATE_QE_PDP_STAT_IMG2_QCH (CLK_CSIS_BASE + 21)
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#define GATE_QE_PDP_AF1_QCH (CLK_CSIS_BASE + 22)
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#define GATE_QE_PDP_AF2_QCH (CLK_CSIS_BASE + 23)
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#define GATE_QE_PDP_IMG2_QCH (CLK_CSIS_BASE + 24)
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#define GATE_QE_PDP_STAT_IMG0_QCH (CLK_CSIS_BASE + 25)
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#define GATE_QE_PDP_STAT_IMG1_QCH (CLK_CSIS_BASE + 26)
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#define GATE_QE_STRP0_QCH (CLK_CSIS_BASE + 27)
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#define GATE_QE_STRP1_QCH (CLK_CSIS_BASE + 28)
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#define GATE_QE_STRP2_QCH (CLK_CSIS_BASE + 29)
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#define GATE_QE_ZSL0_QCH (CLK_CSIS_BASE + 30)
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#define GATE_QE_ZSL1_QCH (CLK_CSIS_BASE + 31)
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#define GATE_QE_ZSL2_QCH (CLK_CSIS_BASE + 32)
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#define GATE_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH (CLK_CSIS_BASE + 33)
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#define GATE_SYSMMU_D0_CSIS_QCH_S1 (CLK_CSIS_BASE + 34)
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#define GATE_SYSMMU_D0_CSIS_QCH_S2 (CLK_CSIS_BASE + 35)
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#define GATE_SYSMMU_D1_CSIS_QCH_S1 (CLK_CSIS_BASE + 36)
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#define GATE_SYSMMU_D1_CSIS_QCH_S2 (CLK_CSIS_BASE + 37)
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#define GATE_SYSMMU_D2_CSIS_QCH_S1 (CLK_CSIS_BASE + 38)
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#define GATE_SYSMMU_D2_CSIS_QCH_S2 (CLK_CSIS_BASE + 39)
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#define GATE_SYSMMU_D3_CSIS_QCH_S1 (CLK_CSIS_BASE + 40)
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#define GATE_SYSMMU_D3_CSIS_QCH_S2 (CLK_CSIS_BASE + 41)
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#define GATE_SYSREG_CSIS_QCH (CLK_CSIS_BASE + 42)
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#define GATE_VGEN_LITE_D0_QCH (CLK_CSIS_BASE + 43)
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#define GATE_VGEN_LITE_D1_QCH (CLK_CSIS_BASE + 44)
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#define GATE_VGEN_LITE_D2_QCH (CLK_CSIS_BASE + 45)
|
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#define UMUX_CLKCMU_CSIS_CSIS (CLK_CSIS_BASE + 46)
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#define UMUX_CLKCMU_CSIS_PDP (CLK_CSIS_BASE + 47)
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#define GATE_CSISX6_QCH_VOTF1 (CLK_CSIS_BASE + 48)
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#define GATE_CSISX6_QCH_MCB (CLK_CSIS_BASE + 49)
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#define GATE_QE_STRP3_QCH (CLK_CSIS_BASE + 50)
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#define GATE_QE_ZSL3_QCH (CLK_CSIS_BASE + 51)
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/* DNS */
|
|
#define CLK_DNS_BASE (650)
|
|
#define UMUX_CLKCMU_DNS_BUS (CLK_DNS_BASE + 0)
|
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#define GATE_DNS_QCH (CLK_DNS_BASE + 2)
|
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#define GATE_DNS_CMU_DNS_QCH (CLK_DNS_BASE + 4)
|
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#define GATE_D_TZPC_DNS_QCH (CLK_DNS_BASE + 5)
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#define GATE_PPMU_D0_DNS_QCH (CLK_DNS_BASE + 6)
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#define GATE_PPMU_D1_DNS_QCH (CLK_DNS_BASE + 7)
|
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#define GATE_SYSMMU_D0_DNS_QCH_S2 (CLK_DNS_BASE + 8)
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#define GATE_SYSMMU_D0_DNS_QCH_S1 (CLK_DNS_BASE + 9)
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#define GATE_SYSMMU_D1_DNS_QCH_S2 (CLK_DNS_BASE + 10)
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#define GATE_SYSMMU_D1_DNS_QCH_S1 (CLK_DNS_BASE + 11)
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#define GATE_SYSREG_DNS_QCH (CLK_DNS_BASE + 12)
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#define GATE_VGEN_LITE_D0_DNS_QCH (CLK_DNS_BASE + 13)
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#define GATE_VGEN_LITE_D1_DNS_QCH (CLK_DNS_BASE + 14)
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#define GATE_DNS_QCH_VOTF0 (CLK_DNS_BASE + 15)
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#define GATE_DNS_QCH_VOTF1 (CLK_DNS_BASE + 16)
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#define GATE_DNS_QCH_VOTF2 (CLK_DNS_BASE + 17)
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/* DPUB */
|
|
#define CLK_DPUB_BASE (700)
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|
#define UMUX_CLKCMU_DPUB_BUS_USER (CLK_DPUB_BASE + 0)
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#define GATE_DPUB_QCH (CLK_DPUB_BASE + 1)
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#define GATE_DPUB_CMU_DPUB_QCH (CLK_DPUB_BASE + 2)
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#define GATE_D_TZPC_DPUB_QCH (CLK_DPUB_BASE + 3)
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#define GATE_SYSREG_DPUB_QCH (CLK_DPUB_BASE + 4)
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|
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/* DPUF0 */
|
|
#define CLK_DPUF0_BASE (750)
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|
#define GATE_DPUF0_QCH_DMA (CLK_DPUF0_BASE + 7)
|
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#define GATE_DPUF0_QCH_DPP (CLK_DPUF0_BASE + 8)
|
|
#define GATE_DPUF0_QCH_C2SERV (CLK_DPUF0_BASE + 9)
|
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#define GATE_DPUF0_CMU_DPUF0_QCH (CLK_DPUF0_BASE + 10)
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#define GATE_D_TZPC_DPUF0_QCH (CLK_DPUF0_BASE + 11)
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#define GATE_PPMU_DPUF0D0_QCH (CLK_DPUF0_BASE + 12)
|
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#define GATE_PPMU_DPUF0D1_QCH (CLK_DPUF0_BASE + 13)
|
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#define GATE_SYSMMU_DPUF0D0_QCH_S1 (CLK_DPUF0_BASE + 14)
|
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#define GATE_SYSMMU_DPUF0D0_QCH_S2 (CLK_DPUF0_BASE + 15)
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|
#define GATE_SYSMMU_DPUF0D1_QCH_S1 (CLK_DPUF0_BASE + 16)
|
|
#define GATE_SYSMMU_DPUF0D1_QCH_S2 (CLK_DPUF0_BASE + 17)
|
|
#define GATE_SYSREG_DPUF0_QCH (CLK_DPUF0_BASE + 18)
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|
|
|
|
|
/* DPUF1 */
|
|
#define CLK_DPUF1_BASE (800)
|
|
#define GATE_DPUF1_QCH_DMA (CLK_DPUF1_BASE + 0)
|
|
#define GATE_DPUF1_QCH_DPP (CLK_DPUF1_BASE + 1)
|
|
#define GATE_DPUF1_QCH_C2SERV (CLK_DPUF1_BASE + 2)
|
|
#define GATE_DPUF1_CMU_DPUF1_QCH (CLK_DPUF1_BASE + 3)
|
|
#define GATE_D_TZPC_DPUF1_QCH (CLK_DPUF1_BASE + 4)
|
|
#define GATE_PPMU_DPUF1D0_QCH (CLK_DPUF1_BASE + 5)
|
|
#define GATE_PPMU_DPUF1D1_QCH (CLK_DPUF1_BASE + 6)
|
|
#define GATE_SYSMMU_DPUF1D0_QCH_S2 (CLK_DPUF1_BASE + 7)
|
|
#define GATE_SYSMMU_DPUF1D0_QCH_S1 (CLK_DPUF1_BASE + 8)
|
|
#define GATE_SYSMMU_DPUF1D1_QCH_S2 (CLK_DPUF1_BASE + 9)
|
|
#define GATE_SYSMMU_DPUF1D1_QCH_S1 (CLK_DPUF1_BASE + 10)
|
|
#define GATE_SYSREG_DPUF1_QCH (CLK_DPUF1_BASE + 11)
|
|
|
|
|
|
/* DSU */
|
|
#define CLK_DSU_BASE (850)
|
|
#define GATE_ACE_US_128TO256_D0_CLUSTER0_QCH (CLK_DSU_BASE + 0)
|
|
#define GATE_ACE_US_128TO256_D1_CLUSTER0_QCH (CLK_DSU_BASE + 1)
|
|
#define GATE_BUSIF_STR_CPUCL0_3_QCH (CLK_DSU_BASE + 2)
|
|
#define GATE_CLUSTER0_QCH_SCLK (CLK_DSU_BASE + 3)
|
|
#define GATE_CLUSTER0_QCH_ATCLK (CLK_DSU_BASE + 4)
|
|
#define GATE_CLUSTER0_QCH_PDBGCLK (CLK_DSU_BASE + 5)
|
|
#define GATE_CLUSTER0_QCH_GICCLK (CLK_DSU_BASE + 6)
|
|
#define GATE_CLUSTER0_QCH_DBG_PD (CLK_DSU_BASE + 7)
|
|
#define GATE_CLUSTER0_QCH_PCLK (CLK_DSU_BASE + 8)
|
|
#define GATE_CLUSTER0_QCH_PERIPHCLK (CLK_DSU_BASE + 9)
|
|
#define GATE_CMU_DSU_CMUREF_QCH (CLK_DSU_BASE + 10)
|
|
#define GATE_CMU_DSU_SHORTSTOP_QCH (CLK_DSU_BASE + 11)
|
|
#define GATE_DSU_CMU_DSU_QCH (CLK_DSU_BASE + 12)
|
|
#define GATE_HTU_DSU_QCH (CLK_DSU_BASE + 13)
|
|
#define GATE_PPC_INSTRRET_CLUSTER0_0_QCH (CLK_DSU_BASE + 14)
|
|
#define GATE_PPC_INSTRRET_CLUSTER0_1_QCH (CLK_DSU_BASE + 15)
|
|
#define GATE_PPC_INSTRRUN_CLUSTER0_0_QCH (CLK_DSU_BASE + 16)
|
|
#define GATE_PPC_INSTRRUN_CLUSTER0_1_QCH (CLK_DSU_BASE + 17)
|
|
|
|
|
|
/* G3D */
|
|
#define CLK_G3D_BASE (950)
|
|
#define GATE_ADD_APBIF_G3D_QCH (CLK_G3D_BASE + 0)
|
|
#define GATE_ADD_G3D_QCH (CLK_G3D_BASE + 1)
|
|
#define GATE_ASB_G3D_QCH_LH_D0_G3D (CLK_G3D_BASE + 2)
|
|
#define GATE_ASB_G3D_QCH_LH_D1_G3D (CLK_G3D_BASE + 3)
|
|
#define GATE_ASB_G3D_QCH_LH_D2_G3D (CLK_G3D_BASE + 4)
|
|
#define GATE_ASB_G3D_QCH_LH_D3_G3D (CLK_G3D_BASE + 5)
|
|
#define GATE_BUSIF_HPMG3D_QCH (CLK_G3D_BASE + 6)
|
|
#define GATE_BUSIF_STR_G3D_QCH (CLK_G3D_BASE + 7)
|
|
#define GATE_D_TZPC_G3D_QCH (CLK_G3D_BASE + 8)
|
|
#define GATE_G3D_CMU_G3D_QCH (CLK_G3D_BASE + 9)
|
|
#define GATE_GPU_QCH (CLK_G3D_BASE + 10)
|
|
#define GATE_HTU_G3D_QCH_PCLK (CLK_G3D_BASE + 11)
|
|
#define GATE_HTU_G3D_QCH_CLK (CLK_G3D_BASE + 12)
|
|
#define GATE_SYSREG_G3D_QCH (CLK_G3D_BASE + 13)
|
|
#define GATE_VGEN_LITE_G3D_QCH (CLK_G3D_BASE + 14)
|
|
#define GATE_BUSIF_STR_G3D_QCH_CORE (CLK_G3D_BASE + 15)
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|
|
|
|
|
/* HSI0 */
|
|
#define CLK_HSI0_BASE (1000)
|
|
#define UMUX_CLKCMU_HSI0_BUS (CLK_HSI0_BASE +0)
|
|
#define UMUX_CLKCMU_HSI0_USB31DRD (CLK_HSI0_BASE +1)
|
|
#define UMUX_CLKCMU_HSI0_USBDP_DEBUG (CLK_HSI0_BASE +2)
|
|
#define UMUX_CLKCMU_HSI0_DPGTC (CLK_HSI0_BASE +3)
|
|
#define GATE_DP_LINK_QCH_PCLK (CLK_HSI0_BASE +4)
|
|
#define GATE_DP_LINK_QCH_GTC_CLK (CLK_HSI0_BASE +5)
|
|
#define GATE_D_TZPC_HSI0_QCH (CLK_HSI0_BASE +6)
|
|
#define GATE_HSI0_CMU_HSI0_QCH (CLK_HSI0_BASE +7)
|
|
#define GATE_PPMU_HSI0_BUS1_QCH (CLK_HSI0_BASE +8)
|
|
#define GATE_SYSMMU_USB_QCH (CLK_HSI0_BASE +9)
|
|
#define GATE_SYSREG_HSI0_QCH (CLK_HSI0_BASE +10)
|
|
#define GATE_USB31DRD_QCH_REF (CLK_HSI0_BASE +11)
|
|
#define GATE_USB31DRD_QCH_SLV_CTRL (CLK_HSI0_BASE +12)
|
|
#define GATE_USB31DRD_QCH_SLV_LINK (CLK_HSI0_BASE +13)
|
|
#define GATE_USB31DRD_QCH_APB (CLK_HSI0_BASE +14)
|
|
#define GATE_USB31DRD_QCH_PCS (CLK_HSI0_BASE +15)
|
|
#define GATE_USB31DRD_QCH_DBG (CLK_HSI0_BASE +16)
|
|
#define GATE_VGEN_LITE_HSI0_QCH (CLK_HSI0_BASE +17)
|
|
#define USB31DRD (CLK_HSI0_BASE +18)
|
|
|
|
/* HSI1 */
|
|
#define CLK_HSI1_BASE (1050)
|
|
#define UMUX_CLKCMU_HSI1_BUS (CLK_HSI1_BASE +0)
|
|
#define UMUX_CLKCMU_HSI1_PCIE (CLK_HSI1_BASE +1)
|
|
#define GATE_D_TZPC_HSI1_QCH (CLK_HSI1_BASE +2)
|
|
#define GATE_GPIO_HSI1_QCH (CLK_HSI1_BASE +3)
|
|
#define GATE_HSI1_CMU_HSI1_QCH (CLK_HSI1_BASE +4)
|
|
#define GATE_PCIE_GEN2_QCH_MSTR (CLK_HSI1_BASE +5)
|
|
#define GATE_PCIE_GEN2_QCH_PCS (CLK_HSI1_BASE +6)
|
|
#define GATE_PCIE_GEN2_QCH_PHY (CLK_HSI1_BASE +7)
|
|
#define GATE_PCIE_GEN2_QCH_DBI (CLK_HSI1_BASE +8)
|
|
#define GATE_PCIE_GEN2_QCH_APB (CLK_HSI1_BASE +9)
|
|
#define GATE_PCIE_GEN2_QCH_REF (CLK_HSI1_BASE +10)
|
|
#define GATE_PCIE_GEN4_0_QCH_APB (CLK_HSI1_BASE +11)
|
|
#define GATE_PCIE_GEN4_0_QCH_DBI (CLK_HSI1_BASE +12)
|
|
#define GATE_PCIE_GEN4_0_QCH_AXI (CLK_HSI1_BASE +13)
|
|
#define GATE_PCIE_GEN4_0_QCH_PCS_APB (CLK_HSI1_BASE +14)
|
|
#define GATE_PCIE_GEN4_0_QCH_REF (CLK_HSI1_BASE +15)
|
|
#define GATE_PCIE_GEN4_0_QCH_PMA_APB (CLK_HSI1_BASE +16)
|
|
#define GATE_PCIE_GEN4_0_QCH_UDBG_APB (CLK_HSI1_BASE +17)
|
|
#define GATE_PCIE_IA_GEN2_QCH (CLK_HSI1_BASE +18)
|
|
#define GATE_PCIE_IA_GEN4_0_QCH (CLK_HSI1_BASE +19)
|
|
#define GATE_PPMU_HSI1_QCH (CLK_HSI1_BASE +20)
|
|
#define GATE_SYSMMU_HSI1_QCH (CLK_HSI1_BASE +21)
|
|
#define GATE_SYSREG_HSI1_QCH (CLK_HSI1_BASE +22)
|
|
#define GATE_VGEN_LITE_HSI1_QCH (CLK_HSI1_BASE +23)
|
|
#define UMUX_CLKCMU_HSI1_MMC_CARD (CLK_HSI1_BASE +24)
|
|
#define UMUX_CLKCMU_HSI1_UFS_EMBD (CLK_HSI1_BASE +25)
|
|
#define GATE_MMC_CARD_QCH (CLK_HSI1_BASE +26)
|
|
#define GATE_UFS_EMBD_QCH_FMP (CLK_HSI1_BASE +27)
|
|
#define GATE_UFS_EMBD_QCH (CLK_HSI1_BASE +28)
|
|
#define DOUT_CLKCMU_HSI1_MMC_CARD (CLK_HSI1_BASE +29)
|
|
#define UFS_EMBD (CLK_HSI1_BASE +30)
|
|
|
|
|
|
/* ITP */
|
|
#define CLK_ITP_BASE (1150)
|
|
#define GATE_D_TZPC_ITP_QCH (CLK_ITP_BASE + 0)
|
|
#define GATE_ITP_QCH (CLK_ITP_BASE + 1)
|
|
#define GATE_ITP_CMU_ITP_QCH (CLK_ITP_BASE + 2)
|
|
#define GATE_SYSREG_ITP_QCH (CLK_ITP_BASE + 3)
|
|
#define UMUX_CLKCMU_ITP_BUS (CLK_ITP_BASE + 4)
|
|
|
|
|
|
/* LME */
|
|
#define CLK_LME_BASE (1200)
|
|
#define GATE_D_TZPC_LME_QCH (CLK_LME_BASE + 0)
|
|
#define GATE_LME_QCH (CLK_LME_BASE + 1)
|
|
#define GATE_LME_QCH_C2 (CLK_LME_BASE + 2)
|
|
#define GATE_LME_CMU_LME_QCH (CLK_LME_BASE + 3)
|
|
#define GATE_PPMU_LME_QCH (CLK_LME_BASE + 4)
|
|
#define GATE_SYSMMU_D_LME_QCH_S2 (CLK_LME_BASE + 5)
|
|
#define GATE_SYSMMU_D_LME_QCH_S1 (CLK_LME_BASE + 6)
|
|
#define GATE_SYSREG_LME_QCH (CLK_LME_BASE + 7)
|
|
#define GATE_VGEN_LITE_LME_QCH (CLK_LME_BASE + 8)
|
|
#define DOUT_DIV_CLK_LME_BUSP (CLK_LME_BASE + 9)
|
|
#define UMUX_CLKCMU_LME_BUS (CLK_LME_BASE + 10)
|
|
|
|
/* M2M */
|
|
#define CLK_M2M_BASE (1250)
|
|
#define GATE_ASTC_QCH (CLK_M2M_BASE + 0)
|
|
#define GATE_D_TZPC_M2M_QCH (CLK_M2M_BASE + 1)
|
|
#define GATE_JPEG0_QCH (CLK_M2M_BASE + 2)
|
|
#define GATE_JPEG1_QCH (CLK_M2M_BASE + 3)
|
|
#define GATE_JSQZ_QCH (CLK_M2M_BASE + 4)
|
|
#define GATE_M2M_QCH (CLK_M2M_BASE + 5)
|
|
#define GATE_M2M_CMU_M2M_QCH (CLK_M2M_BASE + 6)
|
|
#define GATE_PPMU_D_M2M_QCH (CLK_M2M_BASE + 7)
|
|
#define GATE_QE_ASTC_QCH (CLK_M2M_BASE + 8)
|
|
#define GATE_QE_JPEG0_QCH (CLK_M2M_BASE + 9)
|
|
#define GATE_QE_JPEG1_QCH (CLK_M2M_BASE + 10)
|
|
#define GATE_QE_JSQZ_QCH (CLK_M2M_BASE + 11)
|
|
#define GATE_QE_M2M_QCH (CLK_M2M_BASE + 12)
|
|
#define GATE_SYSMMU_D_M2M_QCH_S2 (CLK_M2M_BASE + 13)
|
|
#define GATE_SYSMMU_D_M2M_QCH_S1 (CLK_M2M_BASE + 14)
|
|
#define GATE_SYSREG_M2M_QCH (CLK_M2M_BASE + 15)
|
|
#define GATE_VGEN_LITE_M2M_QCH (CLK_M2M_BASE + 16)
|
|
#define DOUT_DIV_CLK_M2M_BUSP (CLK_M2M_BASE + 17)
|
|
#define GATE_M2M_QCH_VOTF (CLK_M2M_BASE + 18)
|
|
|
|
/* MCFP0 */
|
|
#define CLK_MCFP0_BASE (1300)
|
|
#define GATE_D_TZPC_MCFP0_QCH (CLK_MCFP0_BASE + 0)
|
|
#define GATE_MCFP0_QCH (CLK_MCFP0_BASE + 1)
|
|
#define GATE_MCFP0_CMU_MCFP0_QCH (CLK_MCFP0_BASE + 2)
|
|
#define GATE_PPMU_D0_MCFP0_QCH (CLK_MCFP0_BASE + 3)
|
|
#define GATE_PPMU_D1_MCFP0_QCH (CLK_MCFP0_BASE + 4)
|
|
#define GATE_PPMU_D2_MCFP0_QCH (CLK_MCFP0_BASE + 5)
|
|
#define GATE_PPMU_D3_MCFP0_QCH (CLK_MCFP0_BASE + 6)
|
|
#define GATE_QE_D0_MCFP0_QCH (CLK_MCFP0_BASE + 7)
|
|
#define GATE_QE_D1_MCFP0_QCH (CLK_MCFP0_BASE + 8)
|
|
#define GATE_QE_D2_MCFP0_QCH (CLK_MCFP0_BASE + 9)
|
|
#define GATE_QE_D3_MCFP0_QCH (CLK_MCFP0_BASE + 10)
|
|
#define GATE_SYSMMU_D0_MCFP0_QCH_S1 (CLK_MCFP0_BASE + 11)
|
|
#define GATE_SYSMMU_D0_MCFP0_QCH_S2 (CLK_MCFP0_BASE + 12)
|
|
#define GATE_SYSMMU_D1_MCFP0_QCH_S1 (CLK_MCFP0_BASE + 13)
|
|
#define GATE_SYSMMU_D1_MCFP0_QCH_S2 (CLK_MCFP0_BASE + 14)
|
|
#define GATE_SYSMMU_D2_MCFP0_QCH_S1 (CLK_MCFP0_BASE + 15)
|
|
#define GATE_SYSMMU_D2_MCFP0_QCH_S2 (CLK_MCFP0_BASE + 16)
|
|
#define GATE_SYSMMU_D3_MCFP0_QCH_S1 (CLK_MCFP0_BASE + 17)
|
|
#define GATE_SYSMMU_D3_MCFP0_QCH_S2 (CLK_MCFP0_BASE + 18)
|
|
#define GATE_SYSREG_MCFP0_QCH (CLK_MCFP0_BASE + 19)
|
|
#define GATE_VGEN_LITE_MCFP0_QCH (CLK_MCFP0_BASE + 20)
|
|
#define DOUT_DIV_CLK_MCFP0_BUSP (CLK_MCFP0_BASE + 21)
|
|
#define UMUX_CLKCMU_MCFP0_BUS (CLK_MCFP0_BASE + 22)
|
|
|
|
/* MCFP1 */
|
|
#define CLK_MCFP1_BASE (1350)
|
|
#define GATE_D_TZPC_MCFP1_QCH (CLK_MCFP1_BASE + 0)
|
|
#define GATE_MCFP1_QCH (CLK_MCFP1_BASE + 1)
|
|
#define GATE_MCFP1_CMU_MCFP1_QCH (CLK_MCFP1_BASE + 2)
|
|
#define GATE_ORBMCH0_QCH_C2 (CLK_MCFP1_BASE + 3)
|
|
#define GATE_ORBMCH0_QCH (CLK_MCFP1_BASE + 4)
|
|
#define GATE_PPMU_ORBMCH_QCH (CLK_MCFP1_BASE + 5)
|
|
#define GATE_QE_D0_ORBMCH_QCH (CLK_MCFP1_BASE + 6)
|
|
#define GATE_QE_D1_ORBMCH_QCH (CLK_MCFP1_BASE + 7)
|
|
#define GATE_QE_D2_ORBMCH_QCH (CLK_MCFP1_BASE + 8)
|
|
#define GATE_QE_D3_ORBMCH_QCH (CLK_MCFP1_BASE + 9)
|
|
#define GATE_SYSMMU_D_MCFP1_QCH_S2 (CLK_MCFP1_BASE + 10)
|
|
#define GATE_SYSMMU_D_MCFP1_QCH_S1 (CLK_MCFP1_BASE + 11)
|
|
#define GATE_SYSREG_MCFP1_QCH (CLK_MCFP1_BASE + 12)
|
|
#define GATE_VGEN_LITE_D0_MCFP1_QCH (CLK_MCFP1_BASE + 13)
|
|
#define DOUT_DIV_CLK_MCFP1_BUSP (CLK_MCFP1_BASE + 14)
|
|
#define UMUX_CLKCMU_MCFP1_MCFP1 (CLK_MCFP1_BASE + 15)
|
|
#define UMUX_CLKCMU_MCFP1_ORBMCH (CLK_MCFP1_BASE + 16)
|
|
#define GATE_ORBMCH1_QCH_C2 (CLK_MCFP1_BASE + 17)
|
|
#define GATE_ORBMCH1_QCH (CLK_MCFP1_BASE + 18)
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#define GATE_QE_D4_ORBMCH_QCH (CLK_MCFP1_BASE + 19)
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#define GATE_QE_D5_ORBMCH_QCH (CLK_MCFP1_BASE + 20)
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#define GATE_VGEN_LITE_D1_MCFP1_QCH (CLK_MCFP1_BASE + 21)
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|
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/* MCSC */
|
|
#define CLK_MCSC_BASE (1400)
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#define GATE_ADD_MCSC_QCH (CLK_MCSC_BASE + 0)
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#define GATE_BUSIF_ADD_MCSC_QCH (CLK_MCSC_BASE + 1)
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#define GATE_BUSIF_HPM_MCSC_QCH (CLK_MCSC_BASE + 2)
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#define GATE_D_TZPC_MCSC_QCH (CLK_MCSC_BASE + 9)
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#define GATE_GDC_QCH (CLK_MCSC_BASE + 10)
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#define GATE_GDC_QCH_C2_M (CLK_MCSC_BASE + 11)
|
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#define GATE_GDC_QCH_C2_S (CLK_MCSC_BASE + 13)
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#define GATE_MCSC_QCH (CLK_MCSC_BASE + 14)
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#define GATE_MCSC_QCH_C2_W (CLK_MCSC_BASE + 15)
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#define GATE_MCSC_CMU_MCSC_QCH (CLK_MCSC_BASE + 16)
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#define GATE_PPMU_D0_MCSC_QCH (CLK_MCSC_BASE + 17)
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#define GATE_PPMU_D1_MCSC_QCH (CLK_MCSC_BASE + 18)
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#define GATE_PPMU_D2_MCSC_QCH (CLK_MCSC_BASE + 19)
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#define GATE_SYSMMU_D0_MCSC_QCH_S1 (CLK_MCSC_BASE + 20)
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#define GATE_SYSMMU_D0_MCSC_QCH_S2 (CLK_MCSC_BASE + 21)
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#define GATE_SYSMMU_D1_MCSC_QCH_S1 (CLK_MCSC_BASE + 22)
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#define GATE_SYSMMU_D1_MCSC_QCH_S2 (CLK_MCSC_BASE + 23)
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#define GATE_SYSMMU_D2_MCSC_QCH_S1 (CLK_MCSC_BASE + 24)
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#define GATE_SYSMMU_D2_MCSC_QCH_S2 (CLK_MCSC_BASE + 25)
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#define GATE_SYSREG_MCSC_QCH (CLK_MCSC_BASE + 26)
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#define GATE_VGEN_LITE_D0_MCSC_QCH (CLK_MCSC_BASE + 27)
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#define GATE_VGEN_LITE_D1_MCSC_QCH (CLK_MCSC_BASE + 28)
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#define UMUX_CLKCMU_MCSC_GDC (CLK_MCSC_BASE + 29)
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#define UMUX_CLKCMU_MCSC_BUS (CLK_MCSC_BASE + 30)
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#define GATE_MCSC_QCH_C2_R (CLK_MCSC_BASE + 31)
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/* MFC0 */
|
|
#define CLK_MFC0_BASE (1500)
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#define UMUX_CLKCMU_MFC0_MFC0 (CLK_MFC0_BASE + 0)
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#define UMUX_CLKCMU_MFC0_WFD (CLK_MFC0_BASE + 1)
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#define GATE_D_TZPC_MFC0_QCH (CLK_MFC0_BASE + 2)
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#define GATE_LH_ATB_MFC0_QCH_MI (CLK_MFC0_BASE + 3)
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#define GATE_LH_ATB_MFC0_QCH_SI (CLK_MFC0_BASE + 4)
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#define GATE_MFC0_QCH (CLK_MFC0_BASE + 5)
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#define GATE_MFC0_QCH_VOTF (CLK_MFC0_BASE + 6)
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|
#define GATE_MFC0_CMU_MFC0_QCH (CLK_MFC0_BASE + 7)
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#define GATE_PPMU_MFC0D0_QCH (CLK_MFC0_BASE + 8)
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#define GATE_PPMU_MFC0D1_QCH (CLK_MFC0_BASE + 9)
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#define GATE_PPMU_WFD_QCH (CLK_MFC0_BASE + 10)
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|
#define GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH (CLK_MFC0_BASE + 11)
|
|
#define GATE_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH (CLK_MFC0_BASE + 12)
|
|
#define GATE_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH (CLK_MFC0_BASE + 13)
|
|
#define GATE_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH (CLK_MFC0_BASE + 14)
|
|
#define GATE_SYSMMU_MFC0D0_QCH_S1 (CLK_MFC0_BASE + 15)
|
|
#define GATE_SYSMMU_MFC0D0_QCH_S2 (CLK_MFC0_BASE + 16)
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|
#define GATE_SYSMMU_MFC0D1_QCH_S1 (CLK_MFC0_BASE + 17)
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|
#define GATE_SYSMMU_MFC0D1_QCH_S2 (CLK_MFC0_BASE + 18)
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|
#define GATE_SYSREG_MFC0_QCH (CLK_MFC0_BASE + 19)
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|
#define GATE_VGEN_MFC0_QCH (CLK_MFC0_BASE + 20)
|
|
#define GATE_WFD_QCH (CLK_MFC0_BASE + 21)
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|
|
|
|
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/* MFC1 */
|
|
#define CLK_MFC1_BASE (1550)
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|
#define GATE_ADM_APB_MFC0MFC1_QCH (CLK_MFC1_BASE + 0)
|
|
#define GATE_D_TZPC_MFC1_QCH (CLK_MFC1_BASE + 1)
|
|
#define GATE_MFC1_QCH (CLK_MFC1_BASE + 2)
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|
#define GATE_MFC1_CMU_MFC1_QCH (CLK_MFC1_BASE + 3)
|
|
#define GATE_PPMU_MFC1D0_QCH (CLK_MFC1_BASE + 4)
|
|
#define GATE_PPMU_MFC1D1_QCH (CLK_MFC1_BASE + 5)
|
|
#define GATE_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH (CLK_MFC1_BASE + 6)
|
|
#define GATE_SYSMMU_MFC1D0_QCH_S2 (CLK_MFC1_BASE + 7)
|
|
#define GATE_SYSMMU_MFC1D0_QCH_S1 (CLK_MFC1_BASE + 8)
|
|
#define GATE_SYSMMU_MFC1D1_QCH_S2 (CLK_MFC1_BASE + 9)
|
|
#define GATE_SYSMMU_MFC1D1_QCH_S1 (CLK_MFC1_BASE + 10)
|
|
#define GATE_SYSREG_MFC1_QCH (CLK_MFC1_BASE + 11)
|
|
#define GATE_VGEN_MFC1_QCH (CLK_MFC1_BASE + 12)
|
|
|
|
|
|
/* MIF */
|
|
#define CLK_MIF_BASE (1600)
|
|
#define UMUX_MIF_DDRPHY2X (CLK_MIF_BASE + 0)
|
|
#define GATE_D_TZPC_MIF_QCH (CLK_MIF_BASE + 1)
|
|
#define GATE_MIF_CMU_MIF_QCH (CLK_MIF_BASE + 2)
|
|
#define GATE_QCH_ADAPTER_PPC_DEBUG_QCH (CLK_MIF_BASE + 3)
|
|
#define GATE_SYSREG_MIF_QCH (CLK_MIF_BASE + 4)
|
|
|
|
|
|
/* NPU */
|
|
#define CLK_NPU_BASE (1650)
|
|
#define GATE_D_TZPC_NPU_QCH (CLK_NPU_BASE + 0)
|
|
#define GATE_IP_NPUCORE_QCH_PCLK (CLK_NPU_BASE + 1)
|
|
#define GATE_IP_NPUCORE_QCH_ACLK (CLK_NPU_BASE + 2)
|
|
#define GATE_NPU_CMU_NPU_QCH (CLK_NPU_BASE + 3)
|
|
#define GATE_SYSREG_NPU_QCH (CLK_NPU_BASE + 4)
|
|
#define DOUT_DIV_CLK_NPU_BUSP (CLK_NPU_BASE + 5)
|
|
#define UMUX_CLKCMU_NPU_BUS (CLK_NPU_BASE + 6)
|
|
|
|
/* NPU01 */
|
|
#define CLK_NPU01_BASE (1670)
|
|
#define GATE_D_TZPC_NPU01_QCH (CLK_NPU01_BASE + 0)
|
|
#define GATE_IP_NPU01CORE_QCH_PCLK (CLK_NPU01_BASE + 1)
|
|
#define GATE_IP_NPU01CORE_QCH_ACLK (CLK_NPU01_BASE + 2)
|
|
#define GATE_NPU01_CMU_NPU_QCH (CLK_NPU01_BASE + 3)
|
|
#define GATE_SYSREG_NPU01_QCH (CLK_NPU01_BASE + 4)
|
|
#define DOUT_DIV_CLK_NPU01_BUSP (CLK_NPU01_BASE + 5)
|
|
#define UMUX_CLKCMU_NPU01_BUS (CLK_NPU01_BASE + 6)
|
|
|
|
/* NPU10 */
|
|
#define CLK_NPU10_BASE (1690)
|
|
#define GATE_D_TZPC_NPU10_QCH (CLK_NPU10_BASE + 0)
|
|
#define GATE_IP_NPU10CORE_QCH_PCLK (CLK_NPU10_BASE + 1)
|
|
#define GATE_IP_NPU10CORE_QCH_ACLK (CLK_NPU10_BASE + 2)
|
|
#define GATE_NPU10_CMU_NPU_QCH (CLK_NPU10_BASE + 3)
|
|
#define GATE_SYSREG_NPU10_QCH (CLK_NPU10_BASE + 4)
|
|
#define DOUT_DIV_CLK_NPU10_BUSP (CLK_NPU10_BASE + 5)
|
|
#define UMUX_CLKCMU_NPU10_BUS (CLK_NPU10_BASE + 6)
|
|
|
|
/* NPUS */
|
|
#define CLK_NPUS_BASE (1700)
|
|
#define GATE_ADD_NPUS_QCH (CLK_NPUS_BASE + 0)
|
|
#define GATE_ADM_DAP_NPUS_QCH (CLK_NPUS_BASE + 1)
|
|
#define GATE_BUSIF_ADD_NPUS_QCH (CLK_NPUS_BASE + 2)
|
|
#define GATE_BUSIF_HPM_NPUS_QCH (CLK_NPUS_BASE + 3)
|
|
#define GATE_D_TZPC_NPUS_QCH (CLK_NPUS_BASE + 4)
|
|
#define GATE_HTU_NPUS_QCH_PCLK (CLK_NPUS_BASE + 5)
|
|
#define GATE_IP_NPUS_QCH (CLK_NPUS_BASE + 6)
|
|
#define GATE_IP_NPUS_QCH_C2A0 (CLK_NPUS_BASE + 7)
|
|
#define GATE_IP_NPUS_QCH_CPU (CLK_NPUS_BASE + 8)
|
|
#define GATE_IP_NPUS_QCH_NEON (CLK_NPUS_BASE + 9)
|
|
#define GATE_IP_NPUS_QCH_C2A1 (CLK_NPUS_BASE + 11)
|
|
#define GATE_NPUS_CMU_NPUS_QCH (CLK_NPUS_BASE + 12)
|
|
#define GATE_PPMU_NPUS_0_QCH (CLK_NPUS_BASE + 13)
|
|
#define GATE_PPMU_NPUS_1_QCH (CLK_NPUS_BASE + 14)
|
|
#define GATE_PPMU_NPUS_2_QCH (CLK_NPUS_BASE + 15)
|
|
#define GATE_SYSMMU_D0_NPUS_QCH_S2 (CLK_NPUS_BASE + 16)
|
|
#define GATE_SYSMMU_D0_NPUS_QCH_S1 (CLK_NPUS_BASE + 17)
|
|
#define GATE_SYSMMU_D1_NPUS_QCH_S2 (CLK_NPUS_BASE + 18)
|
|
#define GATE_SYSMMU_D1_NPUS_QCH_S1 (CLK_NPUS_BASE + 19)
|
|
#define GATE_SYSMMU_D2_NPUS_QCH_S2 (CLK_NPUS_BASE + 20)
|
|
#define GATE_SYSMMU_D2_NPUS_QCH_S1 (CLK_NPUS_BASE + 21)
|
|
#define GATE_SYSREG_NPUS_QCH (CLK_NPUS_BASE + 22)
|
|
#define GATE_VGEN_LITE_NPUS_QCH (CLK_NPUS_BASE + 23)
|
|
#define DOUT_DIV_CLK_NPUS_BUSP (CLK_NPUS_BASE + 24)
|
|
#define UMUX_CLKCMU_NPUS_BUS (CLK_NPUS_BASE + 25)
|
|
#define GATE_HTU_NPUS_QCH_CLK (CLK_NPUS_BASE + 26)
|
|
|
|
/* PERIC0 */
|
|
#define CLK_PERIC0_BASE (1750)
|
|
#define UMUX_CLKCMU_PERIC0_BUS (CLK_PERIC0_BASE + 0)
|
|
#define GATE_D_TZPC_PERIC0_QCH (CLK_PERIC0_BASE + 1)
|
|
#define GATE_GPIO_PERIC0_QCH (CLK_PERIC0_BASE + 2)
|
|
#define GATE_PERIC0_CMU_PERIC0_QCH (CLK_PERIC0_BASE + 3)
|
|
#define GATE_PERIC0_TOP0_QCH_UART_DBG (CLK_PERIC0_BASE + 4)
|
|
#define GATE_PERIC0_TOP0_QCH_USI00_USI (CLK_PERIC0_BASE + 5)
|
|
#define GATE_PERIC0_TOP0_QCH_USI00_I2C (CLK_PERIC0_BASE + 6)
|
|
#define GATE_PERIC0_TOP0_QCH_USI01_USI (CLK_PERIC0_BASE + 7)
|
|
#define GATE_PERIC0_TOP0_QCH_USI01_I2C (CLK_PERIC0_BASE + 8)
|
|
#define GATE_PERIC0_TOP0_QCH_USI02_USI (CLK_PERIC0_BASE + 9)
|
|
#define GATE_PERIC0_TOP0_QCH_USI02_I2C (CLK_PERIC0_BASE + 10)
|
|
#define GATE_PERIC0_TOP0_QCH_USI03_USI (CLK_PERIC0_BASE + 11)
|
|
#define GATE_PERIC0_TOP0_QCH_USI03_I2C (CLK_PERIC0_BASE + 12)
|
|
#define GATE_PERIC0_TOP0_QCH_USI04_USI (CLK_PERIC0_BASE + 13)
|
|
#define GATE_PERIC0_TOP0_QCH_USI04_I2C (CLK_PERIC0_BASE + 14)
|
|
#define GATE_PERIC0_TOP0_QCH_USI05_USI (CLK_PERIC0_BASE + 15)
|
|
#define GATE_PERIC0_TOP1_QCH_USI05_I2C (CLK_PERIC0_BASE + 16)
|
|
#define GATE_PERIC0_TOP1_QCH_USI13_USI (CLK_PERIC0_BASE + 17)
|
|
#define GATE_PERIC0_TOP1_QCH_USI13_I2C (CLK_PERIC0_BASE + 18)
|
|
#define GATE_PERIC0_TOP1_QCH_USI14_USI (CLK_PERIC0_BASE + 19)
|
|
#define GATE_PERIC0_TOP1_QCH_USI14_I2C (CLK_PERIC0_BASE + 20)
|
|
#define GATE_PERIC0_TOP1_QCH_USI15_USI (CLK_PERIC0_BASE + 21)
|
|
#define GATE_PERIC0_TOP1_QCH_USI15_I2C (CLK_PERIC0_BASE + 22)
|
|
#define GATE_PERIC0_TOP1_QCH_PWM (CLK_PERIC0_BASE + 23)
|
|
#define GATE_SYSREG_PERIC0_QCH (CLK_PERIC0_BASE + 24)
|
|
#define DOUT_DIV_CLK_PERIC0_USI00_USI (CLK_PERIC0_BASE + 25)
|
|
#define DOUT_DIV_CLK_PERIC0_USI01_USI (CLK_PERIC0_BASE + 26)
|
|
#define DOUT_DIV_CLK_PERIC0_USI02_USI (CLK_PERIC0_BASE + 27)
|
|
#define DOUT_DIV_CLK_PERIC0_USI03_USI (CLK_PERIC0_BASE + 28)
|
|
#define DOUT_DIV_CLK_PERIC0_USI04_USI (CLK_PERIC0_BASE + 29)
|
|
#define DOUT_DIV_CLK_PERIC0_USI05_USI (CLK_PERIC0_BASE + 30)
|
|
#define DOUT_DIV_CLK_PERIC0_USI_I2C (CLK_PERIC0_BASE + 31)
|
|
#define UART_DBG (CLK_PERIC0_BASE + 32)
|
|
#define DOUT_DIV_CLK_PERIC0_USI13_USI (CLK_PERIC0_BASE + 33)
|
|
#define DOUT_DIV_CLK_PERIC0_USI14_USI (CLK_PERIC0_BASE + 34)
|
|
#define DOUT_DIV_CLK_PERIC0_USI15_USI (CLK_PERIC0_BASE + 35)
|
|
|
|
/* PERIC1 */
|
|
#define CLK_PERIC1_BASE (1850)
|
|
#define UMUX_CLKCMU_PERIC1_BUS (CLK_PERIC1_BASE + 0)
|
|
#define GATE_D_TZPC_PERIC1_QCH (CLK_PERIC1_BASE + 1)
|
|
#define GATE_GPIO_PERIC1_QCH (CLK_PERIC1_BASE + 2)
|
|
#define GATE_PERIC1_CMU_PERIC1_QCH (CLK_PERIC1_BASE + 3)
|
|
#define GATE_PERIC1_TOP0_QCH_UART_BT (CLK_PERIC1_BASE + 4)
|
|
#define GATE_PERIC1_TOP1_QCH_USI11_USI (CLK_PERIC1_BASE + 9)
|
|
#define GATE_PERIC1_TOP1_QCH_USI11_I2C (CLK_PERIC1_BASE + 10)
|
|
#define GATE_PERIC1_TOP1_QCH_USI16_USI (CLK_PERIC1_BASE + 11)
|
|
#define GATE_PERIC1_TOP1_QCH_USI16_I2C (CLK_PERIC1_BASE + 12)
|
|
#define GATE_PERIC1_TOP1_QCH_USI17_USI (CLK_PERIC1_BASE + 13)
|
|
#define GATE_PERIC1_TOP1_QCH_USI17_I2C (CLK_PERIC1_BASE + 14)
|
|
#define GATE_PERIC1_TOP1_QCH_USI12_USI (CLK_PERIC1_BASE + 15)
|
|
#define GATE_PERIC1_TOP1_QCH_USI12_I2C (CLK_PERIC1_BASE + 16)
|
|
#define GATE_PERIC1_TOP1_QCH_USI18_USI (CLK_PERIC1_BASE + 17)
|
|
#define GATE_PERIC1_TOP1_QCH_USI18_I2C (CLK_PERIC1_BASE + 18)
|
|
#define GATE_SYSREG_PERIC1_QCH (CLK_PERIC1_BASE + 19)
|
|
#define GATE_USI16_I3C_QCH_P (CLK_PERIC1_BASE + 20)
|
|
#define GATE_USI16_I3C_QCH_S (CLK_PERIC1_BASE + 21)
|
|
#define GATE_USI17_I3C_QCH_P (CLK_PERIC1_BASE + 22)
|
|
#define GATE_USI17_I3C_QCH_S (CLK_PERIC1_BASE + 23)
|
|
#define DOUT_DIV_CLK_PERIC1_UART_BT (CLK_PERIC1_BASE + 24)
|
|
#define DOUT_DIV_CLK_PERIC1_USI_I2C (CLK_PERIC1_BASE + 25)
|
|
#define DOUT_DIV_CLK_PERIC1_USI18_USI (CLK_PERIC1_BASE + 26)
|
|
#define DOUT_DIV_CLK_PERIC1_USI12_USI (CLK_PERIC1_BASE + 27)
|
|
#define DOUT_DIV_CLK_PERIC1_USI11_USI (CLK_PERIC1_BASE + 30)
|
|
#define DOUT_DIV_CLK_PERIC1_USI16_USI (CLK_PERIC1_BASE + 31)
|
|
#define DOUT_DIV_CLK_PERIC1_USI17_USI (CLK_PERIC1_BASE + 32)
|
|
|
|
|
|
/* PERIC2 */
|
|
#define CLK_PERIC2_BASE (1950)
|
|
#define UMUX_CLKCMU_PERIC2_BUS (CLK_PERIC2_BASE + 0)
|
|
#define GATE_D_TZPC_PERIC2_QCH (CLK_PERIC2_BASE + 1)
|
|
#define GATE_GPIO_PERIC2_QCH (CLK_PERIC2_BASE + 2)
|
|
#define GATE_PERIC2_CMU_PERIC2_QCH (CLK_PERIC2_BASE + 3)
|
|
#define GATE_PERIC2_TOP0_QCH_USI06_USI (CLK_PERIC2_BASE + 4)
|
|
#define GATE_PERIC2_TOP0_QCH_USI07_USI (CLK_PERIC2_BASE + 5)
|
|
#define GATE_PERIC2_TOP0_QCH_USI08_USI (CLK_PERIC2_BASE + 6)
|
|
#define GATE_PERIC2_TOP0_QCH_USI08_I2C (CLK_PERIC2_BASE + 7)
|
|
#define GATE_PERIC2_TOP0_QCH_USI06_I2C (CLK_PERIC2_BASE + 8)
|
|
#define GATE_PERIC2_TOP0_QCH_USI07_I2C (CLK_PERIC2_BASE + 9)
|
|
#define GATE_SYSREG_PERIC2_QCH (CLK_PERIC2_BASE + 10)
|
|
#define DOUT_DIV_CLK_PERIC2_USI08_USI (CLK_PERIC2_BASE + 11)
|
|
#define DOUT_DIV_CLK_PERIC2_USI_I2C (CLK_PERIC2_BASE + 12)
|
|
#define DOUT_DIV_CLK_PERIC2_USI06_USI (CLK_PERIC2_BASE + 13)
|
|
#define DOUT_DIV_CLK_PERIC2_USI07_USI (CLK_PERIC2_BASE + 14)
|
|
#define GATE_PERIC2_TOP1_QCH_USI09_USI (CLK_PERIC2_BASE + 15)
|
|
#define GATE_PERIC2_TOP1_QCH_USI09_I2C (CLK_PERIC2_BASE + 16)
|
|
#define GATE_PERIC2_TOP1_QCH_USI10_USI (CLK_PERIC2_BASE + 17)
|
|
#define GATE_PERIC2_TOP1_QCH_USI10_I2C (CLK_PERIC2_BASE + 18)
|
|
#define DOUT_DIV_CLK_PERIC2_USI09_USI (CLK_PERIC2_BASE + 19)
|
|
#define DOUT_DIV_CLK_PERIC2_USI10_USI (CLK_PERIC2_BASE + 20)
|
|
|
|
/* PERIS */
|
|
#define CLK_PERIS_BASE (2000)
|
|
#define UMUX_CLKCMU_PERIS_BUS (CLK_PERIS_BASE + 0)
|
|
#define GATE_BC_EMUL_QCH (CLK_PERIS_BASE + 1)
|
|
#define GATE_D_TZPC_PERIS_QCH (CLK_PERIS_BASE + 2)
|
|
#define GATE_GIC_QCH (CLK_PERIS_BASE + 3)
|
|
#define GATE_MCT_QCH (CLK_PERIS_BASE + 4)
|
|
#define GATE_OTP_QCH (CLK_PERIS_BASE + 5)
|
|
#define GATE_OTP_CON_BIRA_QCH (CLK_PERIS_BASE + 6)
|
|
#define GATE_OTP_CON_BISR_QCH (CLK_PERIS_BASE + 7)
|
|
#define GATE_OTP_CON_TOP_QCH (CLK_PERIS_BASE + 8)
|
|
#define GATE_PERIS_CMU_PERIS_QCH (CLK_PERIS_BASE + 9)
|
|
#define GATE_SYSREG_PERIS_QCH (CLK_PERIS_BASE + 10)
|
|
#define GATE_TMU_SUB_QCH (CLK_PERIS_BASE + 11)
|
|
#define GATE_TMU_TOP_QCH (CLK_PERIS_BASE + 12)
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#define GATE_WDT0_QCH (CLK_PERIS_BASE + 13)
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#define GATE_WDT1_QCH (CLK_PERIS_BASE + 14)
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/* S2D */
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#define CLK_S2D_BASE (2050)
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#define GATE_BIS_S2D_QCH (CLK_S2D_BASE + 0)
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#define GATE_S2D_CMU_S2D_QCH (CLK_S2D_BASE + 1)
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/* SSP */
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#define CLK_SSP_BASE (2100)
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#define GATE_ADM_DAP_SSS_QCH (CLK_SSP_BASE + 0)
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#define GATE_BAAW_SSS_QCH (CLK_SSP_BASE + 1)
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#define GATE_D_TZPC_SSP_QCH (CLK_SSP_BASE + 2)
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#define GATE_PPMU_SSP_QCH (CLK_SSP_BASE + 3)
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#define GATE_QE_RTIC_QCH (CLK_SSP_BASE + 4)
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#define GATE_QE_SSPCORE_QCH (CLK_SSP_BASE + 5)
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#define GATE_QE_SSS_QCH (CLK_SSP_BASE + 6)
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#define GATE_RTIC_QCH (CLK_SSP_BASE + 7)
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#define GATE_SSP_CMU_SSP_QCH (CLK_SSP_BASE + 8)
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#define GATE_SSS_QCH (CLK_SSP_BASE + 9)
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#define GATE_SWEEPER_D_SSP_QCH (CLK_SSP_BASE + 10)
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#define GATE_SYSMMU_RTIC_QCH (CLK_SSP_BASE + 11)
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#define GATE_SYSREG_SSPCTRL_QCH (CLK_SSP_BASE + 12)
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#define GATE_VGEN_LITE_RTIC_QCH (CLK_SSP_BASE + 13)
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#define GATE_USS_SSPCORE_QCH (CLK_SSP_BASE + 14)
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/* TAA */
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#define CLK_TAA_BASE (2150)
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#define GATE_ADD_TAA_QCH (CLK_TAA_BASE + 0)
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#define GATE_BUSIF_ADD_TAA_QCH (CLK_TAA_BASE + 1)
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#define GATE_BUSIF_HPM_TAA_QCH (CLK_TAA_BASE + 2)
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#define GATE_D_TZPC_TAA_QCH (CLK_TAA_BASE + 5)
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#define GATE_PPMU_TAA_QCH (CLK_TAA_BASE + 6)
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#define GATE_SIPU_TAA_QCH (CLK_TAA_BASE + 7)
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#define GATE_SIPU_TAA_QCH_C2_STAT (CLK_TAA_BASE + 8)
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#define GATE_SIPU_TAA_QCH_C2_YDS (CLK_TAA_BASE + 9)
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#define GATE_SYSMMU_D_TAA_QCH_S1 (CLK_TAA_BASE + 10)
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#define GATE_SYSMMU_D_TAA_QCH_S2 (CLK_TAA_BASE + 11)
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#define GATE_SYSREG_TAA_QCH (CLK_TAA_BASE + 12)
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#define GATE_TAA_CMU_TAA_QCH (CLK_TAA_BASE + 13)
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#define GATE_VGEN_LITE_TAA0_QCH (CLK_TAA_BASE + 14)
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#define GATE_VGEN_LITE_TAA1_QCH (CLK_TAA_BASE + 15)
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#define DOUT_DIV_CLK_TAA_BUSP (CLK_TAA_BASE + 16)
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#define UMUX_CLKCMU_TAA_BUS (CLK_TAA_BASE + 17)
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/* VPC */
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#define CLK_VPC_BASE (2200)
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#define GATE_ADD_VPC_QCH (CLK_VPC_BASE + 0)
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#define GATE_ADM_DAP_VPC_QCH (CLK_VPC_BASE + 1)
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#define GATE_BUSIF_ADD_VPC_QCH (CLK_VPC_BASE + 2)
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#define GATE_BUSIF_HPM_VPC_QCH (CLK_VPC_BASE + 3)
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#define GATE_D_TZPC_VPC_QCH (CLK_VPC_BASE + 4)
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#define GATE_HTU_VPC_QCH_PCLK (CLK_VPC_BASE + 5)
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#define GATE_IP_VPC_QCH (CLK_VPC_BASE + 6)
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#define GATE_PPMU_VPC0_QCH (CLK_VPC_BASE + 7)
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#define GATE_PPMU_VPC1_QCH (CLK_VPC_BASE + 8)
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#define GATE_PPMU_VPC2_QCH (CLK_VPC_BASE + 9)
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#define GATE_SYSMMU_VPC0_QCH_S1 (CLK_VPC_BASE + 10)
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#define GATE_SYSMMU_VPC0_QCH_S2 (CLK_VPC_BASE + 11)
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#define GATE_SYSMMU_VPC1_QCH_S1 (CLK_VPC_BASE + 12)
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#define GATE_SYSMMU_VPC1_QCH_S2 (CLK_VPC_BASE + 13)
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#define GATE_SYSMMU_VPC2_QCH_S1 (CLK_VPC_BASE + 14)
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#define GATE_SYSMMU_VPC2_QCH_S2 (CLK_VPC_BASE + 15)
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#define GATE_SYSREG_VPC_QCH (CLK_VPC_BASE + 16)
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#define GATE_VGEN_LITE_VPC_QCH (CLK_VPC_BASE + 17)
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#define GATE_VPC_CMU_VPC_QCH (CLK_VPC_BASE + 18)
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#define DOUT_DIV_CLK_VPC_BUSP (CLK_VPC_BASE + 19)
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#define DOUT_DIV_CLK_VPC_BUS (CLK_VPC_BASE + 20)
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#define UMUX_CLKCMU_VPC_BUS (CLK_VPC_BASE + 21)
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#define GATE_HTU_VPC_QCH_CLK (CLK_VPC_BASE + 22)
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/* VPD */
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#define CLK_VPD_BASE (2250)
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#define GATE_D_TZPC_VPD_QCH (CLK_VPD_BASE + 0)
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#define GATE_IP_VPD_QCH (CLK_VPD_BASE + 1)
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#define GATE_SYSREG_VPD_QCH (CLK_VPD_BASE + 2)
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#define GATE_VPD_CMU_VPD_QCH (CLK_VPD_BASE + 3)
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#define DOUT_DIV_CLK_VPD_BUSP (CLK_VPD_BASE + 4)
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#define DOUT_DIV_CLK_VPD_BUS (CLK_VPD_BASE + 5)
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#define UMUX_CLKCMU_VPD_BUS (CLK_VPD_BASE + 6)
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/* VTS */
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#define CLK_VTS_BASE (2300)
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#define GATE_BAAW_C_VTS_QCH (CLK_VTS_BASE + 0)
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#define GATE_BAAW_D_VTS_QCH (CLK_VTS_BASE + 1)
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#define GATE_CORTEXM4INTEGRATION_QCH_CPU (CLK_VTS_BASE + 2)
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#define GATE_DMIC_AHB0_QCH_PCLK (CLK_VTS_BASE + 3)
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#define GATE_DMIC_AHB1_QCH_PCLK (CLK_VTS_BASE + 4)
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#define GATE_DMIC_AHB2_QCH_PCLK (CLK_VTS_BASE + 5)
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#define GATE_DMIC_AHB3_QCH_PCLK (CLK_VTS_BASE + 6)
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#define GATE_DMIC_AHB4_QCH_PCLK (CLK_VTS_BASE + 7)
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#define GATE_DMIC_AHB5_QCH_PCLK (CLK_VTS_BASE + 8)
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#define GATE_DMIC_AUD0_QCH_PCLK (CLK_VTS_BASE + 9)
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#define GATE_DMIC_AUD0_QCH_DMIC (CLK_VTS_BASE + 10)
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#define GATE_DMIC_AUD1_QCH_PCLK (CLK_VTS_BASE + 11)
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#define GATE_DMIC_AUD1_QCH_DMIC (CLK_VTS_BASE + 12)
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#define GATE_DMIC_AUD2_QCH_PCLK (CLK_VTS_BASE + 13)
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#define GATE_DMIC_AUD2_QCH_DMIC (CLK_VTS_BASE + 14)
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#define GATE_DMIC_IF0_QCH_PCLK (CLK_VTS_BASE + 15)
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#define GATE_DMIC_IF0_QCH_DMIC (CLK_VTS_BASE + 16)
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#define GATE_DMIC_IF1_QCH_PCLK (CLK_VTS_BASE + 17)
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#define GATE_DMIC_IF1_QCH_DMIC (CLK_VTS_BASE + 18)
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#define GATE_DMIC_IF2_QCH_PCLK (CLK_VTS_BASE + 19)
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#define GATE_DMIC_IF2_QCH_DMIC (CLK_VTS_BASE + 20)
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#define GATE_D_TZPC_VTS_QCH (CLK_VTS_BASE + 21)
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#define GATE_GPIO_VTS_QCH (CLK_VTS_BASE + 22)
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#define GATE_HWACG_SYS_DMIC0_QCH (CLK_VTS_BASE + 23)
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#define GATE_HWACG_SYS_DMIC1_QCH (CLK_VTS_BASE + 24)
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#define GATE_HWACG_SYS_DMIC2_QCH (CLK_VTS_BASE + 25)
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#define GATE_HWACG_SYS_DMIC3_QCH (CLK_VTS_BASE + 26)
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#define GATE_HWACG_SYS_DMIC4_QCH (CLK_VTS_BASE + 27)
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#define GATE_HWACG_SYS_DMIC5_QCH (CLK_VTS_BASE + 28)
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#define GATE_MAILBOX_ABOX_VTS_QCH (CLK_VTS_BASE + 32)
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#define GATE_MAILBOX_APM_VTS1_QCH (CLK_VTS_BASE + 33)
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#define GATE_MAILBOX_AP_VTS_QCH (CLK_VTS_BASE + 34)
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#define GATE_PDMA_VTS_QCH (CLK_VTS_BASE + 35)
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#define GATE_SERIAL_LIF_QCH_PCLK (CLK_VTS_BASE + 36)
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#define GATE_SERIAL_LIF_QCH_LIF (CLK_VTS_BASE + 37)
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#define GATE_SERIAL_LIF_QCH_HCLK (CLK_VTS_BASE + 38)
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#define GATE_SERIAL_LIF_DEBUG_US_QCH_PCLK (CLK_VTS_BASE + 39)
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#define GATE_SERIAL_LIF_DEBUG_US_QCH_LIF (CLK_VTS_BASE + 40)
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#define GATE_SERIAL_LIF_DEBUG_VT_QCH_PCLK (CLK_VTS_BASE + 42)
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#define GATE_SERIAL_LIF_DEBUG_VT_QCH_LIF (CLK_VTS_BASE + 43)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0 (CLK_VTS_BASE + 45)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0 (CLK_VTS_BASE + 46)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1 (CLK_VTS_BASE + 47)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1 (CLK_VTS_BASE + 48)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2 (CLK_VTS_BASE + 49)
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#define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2 (CLK_VTS_BASE + 50)
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#define GATE_SWEEPER_D_VTS_QCH (CLK_VTS_BASE + 51)
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#define GATE_SYSREG_VTS_QCH (CLK_VTS_BASE + 52)
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#define GATE_TIMER_QCH (CLK_VTS_BASE + 53)
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#define GATE_TIMER1_QCH (CLK_VTS_BASE + 54)
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#define GATE_TIMER2_QCH (CLK_VTS_BASE + 55)
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#define GATE_VGEN_LITE_QCH (CLK_VTS_BASE + 56)
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#define GATE_VTS_CMU_VTS_QCH (CLK_VTS_BASE + 57)
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#define GATE_WDT_VTS_QCH (CLK_VTS_BASE + 58)
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#define DOUT_DIV_CLK_VTS_DMIC_IF (CLK_VTS_BASE + 59)
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#define DOUT_DIV_CLK_VTS_DMIC_IF_DIV2 (CLK_VTS_BASE + 60)
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#define DOUT_DIV_CLK_VTS_BUS (CLK_VTS_BASE + 61)
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#define DOUT_DIV_CLK_VTS_DMIC_AUD (CLK_VTS_BASE + 62)
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#define DOUT_DIV_CLK_VTS_DMIC_AUD_DIV2 (CLK_VTS_BASE + 63)
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#define DOUT_DIV_CLK_VTS_SERIAL_LIF (CLK_VTS_BASE + 64)
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#define DOUT_DIV_CLK_VTS_DMIC_AHB (CLK_VTS_BASE + 65)
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#define DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE (CLK_VTS_BASE + 66)
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#define UMUX_CLKCMU_VTS_BUS (CLK_VTS_BASE + 67)
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#define UMUX_CLKAUD_VTS_DMIC0 (CLK_VTS_BASE + 68)
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#define UMUX_CLKAUD_VTS_DMIC1 (CLK_VTS_BASE + 69)
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#define UMUX_CLKCMU_VTS_DMIC (CLK_VTS_BASE + 70)
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#define UMUX_CLK_RCO_VTS (CLK_VTS_BASE + 71)
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#define UMUX_CLK_VTS_DMIC_AUD (CLK_VTS_BASE + 72)
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#define UMUX_CLK_VTS_SERIAL_LIF (CLK_VTS_BASE + 73)
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#define UMUX_CLK_VTS_DMIC_IF (CLK_VTS_BASE + 74)
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#define GATE_BUSIF_HPM_VTS_QCH (CLK_VTS_BASE + 75)
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#define GATE_DMAILBOX_TEST_QCH_ACLK (CLK_VTS_BASE + 76)
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#define GATE_DMAILBOX_TEST_QCH_PCLK (CLK_VTS_BASE + 77)
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#define GATE_DMAILBOX_TEST_QCH_LIF (CLK_VTS_BASE + 78)
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#define GATE_HWACG_SYS_SERIAL_LIF_QCH (CLK_VTS_BASE + 79)
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/* YUVPP */
|
|
#define CLK_YUVPP_BASE (2400)
|
|
#define GATE_D_TZPC_YUVPP_QCH (CLK_YUVPP_BASE + 0)
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#define GATE_FRC_MC_QCH (CLK_YUVPP_BASE + 1)
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#define GATE_PPMU_YUVPP_QCH (CLK_YUVPP_BASE + 2)
|
|
#define GATE_QE_D0_YUVPP_QCH (CLK_YUVPP_BASE + 3)
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#define GATE_QE_D1_YUVPP_QCH (CLK_YUVPP_BASE + 4)
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#define GATE_QE_D2_YUVPP_QCH (CLK_YUVPP_BASE + 5)
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#define GATE_QE_D3_YUVPP_QCH (CLK_YUVPP_BASE + 6)
|
|
#define GATE_QE_D4_YUVPP_QCH (CLK_YUVPP_BASE + 7)
|
|
#define GATE_QE_D5_YUVPP_QCH (CLK_YUVPP_BASE + 8)
|
|
#define GATE_QE_D6_YUVPP_QCH (CLK_YUVPP_BASE + 9)
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|
#define GATE_QE_D7_YUVPP_QCH (CLK_YUVPP_BASE + 10)
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#define GATE_QE_D8_YUVPP_QCH (CLK_YUVPP_BASE + 11)
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|
#define GATE_QE_D9_YUVPP_QCH (CLK_YUVPP_BASE + 12)
|
|
#define GATE_SYSMMU_D_YUVPP_QCH_S1 (CLK_YUVPP_BASE + 13)
|
|
#define GATE_SYSMMU_D_YUVPP_QCH_S2 (CLK_YUVPP_BASE + 14)
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|
#define GATE_SYSREG_YUVPP_QCH (CLK_YUVPP_BASE + 15)
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|
#define GATE_VGEN_LITE_YUVPP0_QCH (CLK_YUVPP_BASE + 16)
|
|
#define GATE_VGEN_LITE_YUVPP1_QCH (CLK_YUVPP_BASE + 17)
|
|
#define GATE_YUVPP_CMU_YUVPP_QCH (CLK_YUVPP_BASE + 18)
|
|
#define GATE_YUVPP_TOP_QCH (CLK_YUVPP_BASE + 19)
|
|
#define GATE_YUVPP_TOP_QCH_C2COM (CLK_YUVPP_BASE + 20)
|
|
#define DOUT_DIV_CLK_YUVPP_BUSP (CLK_YUVPP_BASE + 21)
|
|
#define UMUX_CLKCMU_YUVPP_BUS (CLK_YUVPP_BASE + 22)
|
|
#define GATE_QE_D10_YUVPP_QCH (CLK_YUVPP_BASE + 23)
|
|
#define GATE_QE_D11_YUVPP_QCH (CLK_YUVPP_BASE + 24)
|
|
#define GATE_VGEN_LITE_YUVPP2_QCH (CLK_YUVPP_BASE + 25)
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|
|
|
/* CLKOUT */
|
|
#define CLK_CLKOUT_BASE (2450)
|
|
#define OSC_NFC (CLK_CLKOUT_BASE + 0)
|
|
#define OSC_AUD (CLK_CLKOUT_BASE + 1)
|
|
|
|
|
|
/* must be greater than maximal clock id */
|
|
#define CLK_NR_CLKS (2600 + 1)
|
|
|
|
#define ACPM_DVFS_MIF (0x0B040000)
|
|
#define ACPM_DVFS_INT (0x0B040001)
|
|
#define ACPM_DVFS_CPUCL0 (0x0B040002)
|
|
#define ACPM_DVFS_CPUCL1 (0x0B040003)
|
|
#define ACPM_DVFS_CPUCL2 (0x0B040004)
|
|
#define ACPM_DVFS_NPU (0x0B040005)
|
|
#define ACPM_DVFS_DSU (0x0B040006)
|
|
#define ACPM_DVFS_DISP (0x0B040007)
|
|
#define ACPM_DVFS_AUD (0x0B040008)
|
|
#define ACPM_DVFS_CP (0x0B040009)
|
|
#define ACPM_DVFS_MODEM (0x0B04000A)
|
|
#define ACPM_DVFS_G3D (0x0B04000B)
|
|
#define ACPM_DVFS_INTCAM (0x0B04000C)
|
|
#define ACPM_DVFS_CAM (0x0B04000D)
|
|
#define ACPM_DVFS_CSIS (0x0B04000E)
|
|
#define ACPM_DVFS_ISP (0x0B04000F)
|
|
#define ACPM_DVFS_VPC (0x0B040010)
|
|
#define ACPM_DVFS_MFC0 (0x0B040011)
|
|
#define ACPM_DVFS_MFC1 (0x0B040012)
|
|
|
|
#define EWF_CMU_ALIVE (0)
|
|
#define EWF_CMU_AUD (1)
|
|
#define EWF_CMU_BUS0 (2)
|
|
#define EWF_CMU_BUS1 (3)
|
|
#define EWF_CMU_BUS2 (4)
|
|
#define EWF_CMU_CMGP (6)
|
|
#define EWF_CMU_CORE (7)
|
|
#define EWF_CMU_CPUCL0 (8)
|
|
#define EWF_CMU_CPUCL1 (9)
|
|
#define EWF_CMU_CPUCL2 (10)
|
|
#define EWF_CMU_CSIS (11)
|
|
#define EWF_CMU_DNS (12)
|
|
#define EWF_CMU_DPUB (13)
|
|
#define EWF_CMU_DPUF0 (14)
|
|
#define EWF_CMU_DPUF1 (15)
|
|
#define EWF_CMU_G3D (17)
|
|
#define EWF_CMU_HSI0 (18)
|
|
#define EWF_CMU_HSI1 (19)
|
|
#define EWF_CMU_ITP (21)
|
|
#define EWF_CMU_LME (22)
|
|
#define EWF_CMU_MCFP0 (23)
|
|
#define EWF_CMU_MCFP1 (24)
|
|
#define EWF_CMU_MCSC (25)
|
|
#define EWF_CMU_MFC0 (26)
|
|
#define EWF_CMU_MFC1 (27)
|
|
#define EWF_CMU_MIF0 (28)
|
|
#define EWF_CMU_MIF1 (29)
|
|
#define EWF_CMU_MIF2 (30)
|
|
#define EWF_CMU_MIF3 (31)
|
|
#define EWF_GRP_CAM (51)
|
|
|
|
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_9830_H */
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