978 lines
20 KiB
Text
Executable file
978 lines
20 KiB
Text
Executable file
/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "Spreadtrum SP9863A-1H10 Board";
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compatible = "sprd,sp9863a-1h10", "sprd,sc9863a";
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soc {
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compatible = "simple-bus";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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phandle = <0x2e>;
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syscon@20e00000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x20e00000 0x00 0x4000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x20e00000 0x4000>;
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phandle = <0x2f>;
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apahb-gate {
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compatible = "sprd,sc9863a-apahb-gate";
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reg = <0x00 0x1020>;
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#clock-cells = <0x01>;
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phandle = <0x2b>;
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};
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};
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syscon@402b0000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x402b0000 0x00 0x4000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x402b0000 0x4000>;
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phandle = <0x30>;
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pmu-gate {
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compatible = "sprd,sc9863a-pmu-gate";
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reg = <0x00 0x1200>;
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clocks = <0x02>;
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clock-names = "ext-26m";
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#clock-cells = <0x01>;
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phandle = <0x31>;
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};
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};
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syscon@402e0000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x402e0000 0x00 0x4000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x402e0000 0x4000>;
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phandle = <0x32>;
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aonapb-gate {
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compatible = "sprd,sc9863a-aonapb-gate";
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reg = <0x00 0x1100>;
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#clock-cells = <0x01>;
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phandle = <0x33>;
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};
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};
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syscon@40353000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x40353000 0x00 0x3000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x40353000 0x3000>;
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phandle = <0x34>;
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pll {
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compatible = "sprd,sc9863a-pll";
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reg = <0x00 0x100>;
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clocks = <0x02>;
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clock-names = "ext-26m";
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#clock-cells = <0x01>;
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phandle = <0x35>;
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};
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};
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syscon@40359000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x40359000 0x00 0x3000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x40359000 0x3000>;
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phandle = <0x36>;
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mpll {
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compatible = "sprd,sc9863a-mpll";
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reg = <0x00 0x100>;
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#clock-cells = <0x01>;
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phandle = <0x37>;
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};
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};
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syscon@4035c000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x4035c000 0x00 0x3000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x4035c000 0x3000>;
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phandle = <0x38>;
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rpll {
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compatible = "sprd,sc9863a-rpll";
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reg = <0x00 0x100>;
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clocks = <0x02>;
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clock-names = "ext-26m";
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#clock-cells = <0x01>;
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phandle = <0x2c>;
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};
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};
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syscon@40363000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x40363000 0x00 0x3000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x40363000 0x3000>;
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phandle = <0x39>;
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dpll {
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compatible = "sprd,sc9863a-dpll";
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reg = <0x00 0x100>;
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#clock-cells = <0x01>;
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phandle = <0x3a>;
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};
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};
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syscon@60800000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x60800000 0x00 0x1000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x60800000 0x3000>;
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phandle = <0x3b>;
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mm-gate {
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compatible = "sprd,sc9863a-mm-gate";
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reg = <0x00 0x1100>;
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#clock-cells = <0x01>;
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phandle = <0x3c>;
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};
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};
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syscon@71300000 {
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compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
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reg = <0x00 0x71300000 0x00 0x4000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x71300000 0x4000>;
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phandle = <0x3d>;
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apapb-gate {
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compatible = "sprd,sc9863a-apapb-gate";
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reg = <0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "ext-26m";
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#clock-cells = <0x01>;
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phandle = <0x3e>;
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};
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};
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apb@70000000 {
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compatible = "simple-bus";
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x70000000 0x10000000>;
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serial@0 {
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compatible = "sprd,sc9863a-uart", "sprd,sc9836-uart";
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reg = <0x00 0x100>;
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interrupts = <0x00 0x02 0x04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x3f>;
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};
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serial@100000 {
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compatible = "sprd,sc9863a-uart", "sprd,sc9836-uart";
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reg = <0x100000 0x100>;
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interrupts = <0x00 0x03 0x04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x40>;
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};
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serial@200000 {
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compatible = "sprd,sc9863a-uart", "sprd,sc9836-uart";
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reg = <0x200000 0x100>;
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interrupts = <0x00 0x04 0x04>;
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clocks = <0x02>;
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status = "disabled";
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phandle = <0x41>;
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};
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serial@300000 {
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compatible = "sprd,sc9863a-uart", "sprd,sc9836-uart";
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reg = <0x300000 0x100>;
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interrupts = <0x00 0x05 0x04>;
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clocks = <0x02>;
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status = "disabled";
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phandle = <0x42>;
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};
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serial@400000 {
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compatible = "sprd,sc9863a-uart", "sprd,sc9836-uart";
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reg = <0x400000 0x100>;
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interrupts = <0x00 0x06 0x04>;
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clocks = <0x02>;
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status = "disabled";
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phandle = <0x43>;
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};
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};
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interrupt-controller@14000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <0x03>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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redistributor-stride = <0x00 0x20000>;
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#redistributor-regions = <0x01>;
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interrupt-controller;
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reg = <0x00 0x14000000 0x00 0x20000 0x00 0x14040000 0x00 0x100000>;
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interrupts = <0x01 0x09 0x04>;
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phandle = <0x01>;
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};
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clock-controller@21500000 {
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compatible = "sprd,sc9863a-ap-clk";
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reg = <0x00 0x21500000 0x00 0x1000>;
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clocks = <0x03 0x02>;
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clock-names = "ext-32k", "ext-26m";
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#clock-cells = <0x01>;
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phandle = <0x44>;
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};
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clock-controller@402d0000 {
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compatible = "sprd,sc9863a-aon-clk";
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reg = <0x00 0x402d0000 0x00 0x1000>;
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clocks = <0x02 0x04 0x03 0x05>;
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clock-names = "ext-26m", "rco-100m", "ext-32k", "ext-4m";
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#clock-cells = <0x01>;
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phandle = <0x2a>;
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};
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clock-controller@60900000 {
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compatible = "sprd,sc9863a-mm-clk";
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reg = <0x00 0x60900000 0x00 0x1000>;
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#clock-cells = <0x01>;
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phandle = <0x45>;
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};
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funnel@10001000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x00 0x10001000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x06>;
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phandle = <0x08>;
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};
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};
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};
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in-ports {
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port {
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endpoint {
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remote-endpoint = <0x07>;
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phandle = <0x12>;
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};
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};
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};
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};
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etb@10003000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x00 0x10003000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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endpoint {
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remote-endpoint = <0x08>;
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phandle = <0x06>;
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};
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};
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};
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};
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funnel@12001000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x00 0x12001000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x09>;
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phandle = <0x0f>;
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};
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};
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};
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in-ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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endpoint {
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remote-endpoint = <0x0a>;
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phandle = <0x1b>;
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};
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};
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port@1 {
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reg = <0x01>;
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endpoint {
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remote-endpoint = <0x0b>;
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phandle = <0x1d>;
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};
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};
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port@2 {
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reg = <0x02>;
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endpoint {
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remote-endpoint = <0x0c>;
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phandle = <0x1f>;
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};
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};
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port@3 {
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reg = <0x03>;
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endpoint {
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remote-endpoint = <0x0d>;
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phandle = <0x21>;
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};
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};
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};
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};
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etf@12002000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x00 0x12002000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x0e>;
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phandle = <0x13>;
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};
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};
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};
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in-port {
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port {
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endpoint {
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remote-endpoint = <0x0f>;
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phandle = <0x09>;
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};
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};
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};
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};
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etf@12003000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x00 0x12003000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x10>;
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phandle = <0x14>;
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};
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};
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};
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in-ports {
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port {
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endpoint {
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remote-endpoint = <0x11>;
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phandle = <0x15>;
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};
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};
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};
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};
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funnel@12004000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x00 0x12004000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x12>;
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phandle = <0x07>;
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};
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};
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};
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in-ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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endpoint {
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remote-endpoint = <0x13>;
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phandle = <0x0e>;
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};
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};
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port@1 {
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reg = <0x01>;
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endpoint {
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remote-endpoint = <0x14>;
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phandle = <0x10>;
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};
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};
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};
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};
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funnel@12005000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x00 0x12005000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x15>;
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phandle = <0x11>;
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};
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};
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};
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in-ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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endpoint {
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remote-endpoint = <0x16>;
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phandle = <0x23>;
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};
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};
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port@1 {
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reg = <0x01>;
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endpoint {
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remote-endpoint = <0x17>;
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phandle = <0x25>;
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};
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};
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port@2 {
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reg = <0x02>;
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endpoint {
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remote-endpoint = <0x18>;
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phandle = <0x27>;
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};
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};
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port@3 {
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reg = <0x03>;
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endpoint {
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remote-endpoint = <0x19>;
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phandle = <0x29>;
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};
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};
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};
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};
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etm@13040000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x00 0x13040000 0x00 0x1000>;
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cpu = <0x1a>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x1b>;
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phandle = <0x0a>;
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};
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};
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};
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};
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etm@13140000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x00 0x13140000 0x00 0x1000>;
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cpu = <0x1c>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x1d>;
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phandle = <0x0b>;
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};
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};
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};
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};
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etm@13240000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x00 0x13240000 0x00 0x1000>;
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cpu = <0x1e>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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|
|
|
endpoint {
|
|
remote-endpoint = <0x1f>;
|
|
phandle = <0x0c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13340000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x00 0x13340000 0x00 0x1000>;
|
|
cpu = <0x20>;
|
|
clocks = <0x02>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21>;
|
|
phandle = <0x0d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13440000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x00 0x13440000 0x00 0x1000>;
|
|
cpu = <0x22>;
|
|
clocks = <0x02>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23>;
|
|
phandle = <0x16>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13540000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x00 0x13540000 0x00 0x1000>;
|
|
cpu = <0x24>;
|
|
clocks = <0x02>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25>;
|
|
phandle = <0x17>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13640000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x00 0x13640000 0x00 0x1000>;
|
|
cpu = <0x26>;
|
|
clocks = <0x02>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x27>;
|
|
phandle = <0x18>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13740000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x00 0x13740000 0x00 0x1000>;
|
|
cpu = <0x28>;
|
|
clocks = <0x02>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x29>;
|
|
phandle = <0x19>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ap-ahb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
|
|
sdio@20300000 {
|
|
compatible = "sprd,sdhci-r11";
|
|
reg = <0x00 0x20300000 0x00 0x1000>;
|
|
interrupts = <0x00 0x39 0x04>;
|
|
clock-names = "sdio", "enable";
|
|
clocks = <0x2a 0x1e 0x2b 0x04>;
|
|
assigned-clocks = <0x2a 0x1e>;
|
|
assigned-clock-parents = <0x2c 0x02>;
|
|
bus-width = <0x04>;
|
|
no-sdio;
|
|
no-mmc;
|
|
phandle = <0x46>;
|
|
};
|
|
|
|
sdio@20600000 {
|
|
compatible = "sprd,sdhci-r11";
|
|
reg = <0x00 0x20600000 0x00 0x1000>;
|
|
interrupts = <0x00 0x3c 0x04>;
|
|
clock-names = "sdio", "enable";
|
|
clocks = <0x2a 0x21 0x2b 0x07>;
|
|
assigned-clocks = <0x2a 0x21>;
|
|
assigned-clock-parents = <0x2c 0x02>;
|
|
bus-width = <0x08>;
|
|
non-removable;
|
|
no-sdio;
|
|
no-sd;
|
|
cap-mmc-hw-reset;
|
|
phandle = <0x47>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ext-26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0x18cba80>;
|
|
clock-output-names = "ext-26m";
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
ext-32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0x8000>;
|
|
clock-output-names = "ext-32k";
|
|
phandle = <0x03>;
|
|
};
|
|
|
|
ext-4m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = "", "=\t";
|
|
clock-output-names = "ext-4m";
|
|
phandle = <0x05>;
|
|
};
|
|
|
|
rco-100m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0x5f5e100>;
|
|
clock-output-names = "rco-100m";
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
cpu-map {
|
|
|
|
cluster0 {
|
|
|
|
core0 {
|
|
cpu = <0x1a>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x1c>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x1e>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <0x20>;
|
|
};
|
|
|
|
core4 {
|
|
cpu = <0x22>;
|
|
};
|
|
|
|
core5 {
|
|
cpu = <0x24>;
|
|
};
|
|
|
|
core6 {
|
|
cpu = <0x26>;
|
|
};
|
|
|
|
core7 {
|
|
cpu = <0x28>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x00>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x100>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x1c>;
|
|
};
|
|
|
|
cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x200>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x300>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
cpu@400 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x400>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
cpu@500 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x500>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
cpu@600 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x600>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
cpu@700 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x00 0x700>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x2d>;
|
|
phandle = <0x28>;
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
core-pd {
|
|
compatible = "arm,idle-state";
|
|
entry-latency-us = <0xfa0>;
|
|
exit-latency-us = <0xfa0>;
|
|
min-residency-us = <0x2710>;
|
|
local-timer-stop;
|
|
arm,psci-suspend-param = <0x10000>;
|
|
phandle = <0x2d>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04>;
|
|
};
|
|
|
|
aliases {
|
|
serial0 = "/soc/apb@70000000/serial@0";
|
|
serial1 = "/soc/apb@70000000/serial@100000";
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x00 0x80000000 0x00 0x80000000>;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial1:115200n8";
|
|
bootargs = "earlycon";
|
|
};
|
|
|
|
__symbols__ {
|
|
soc = "/soc";
|
|
ap_ahb_regs = "/soc/syscon@20e00000";
|
|
apahb_gate = "/soc/syscon@20e00000/apahb-gate";
|
|
pmu_regs = "/soc/syscon@402b0000";
|
|
pmu_gate = "/soc/syscon@402b0000/pmu-gate";
|
|
aon_apb_regs = "/soc/syscon@402e0000";
|
|
aonapb_gate = "/soc/syscon@402e0000/aonapb-gate";
|
|
anlg_phy_g2_regs = "/soc/syscon@40353000";
|
|
pll = "/soc/syscon@40353000/pll";
|
|
anlg_phy_g4_regs = "/soc/syscon@40359000";
|
|
mpll = "/soc/syscon@40359000/mpll";
|
|
anlg_phy_g5_regs = "/soc/syscon@4035c000";
|
|
rpll = "/soc/syscon@4035c000/rpll";
|
|
anlg_phy_g7_regs = "/soc/syscon@40363000";
|
|
dpll = "/soc/syscon@40363000/dpll";
|
|
mm_ahb_regs = "/soc/syscon@60800000";
|
|
mm_gate = "/soc/syscon@60800000/mm-gate";
|
|
ap_apb_regs = "/soc/syscon@71300000";
|
|
apapb_gate = "/soc/syscon@71300000/apapb-gate";
|
|
uart0 = "/soc/apb@70000000/serial@0";
|
|
uart1 = "/soc/apb@70000000/serial@100000";
|
|
uart2 = "/soc/apb@70000000/serial@200000";
|
|
uart3 = "/soc/apb@70000000/serial@300000";
|
|
uart4 = "/soc/apb@70000000/serial@400000";
|
|
gic = "/soc/interrupt-controller@14000000";
|
|
ap_clk = "/soc/clock-controller@21500000";
|
|
aon_clk = "/soc/clock-controller@402d0000";
|
|
mm_clk = "/soc/clock-controller@60900000";
|
|
funnel_soc_out_port = "/soc/funnel@10001000/out-ports/port/endpoint";
|
|
funnel_soc_in_port = "/soc/funnel@10001000/in-ports/port/endpoint";
|
|
etb_in = "/soc/etb@10003000/in-ports/port/endpoint";
|
|
funnel_little_out_port = "/soc/funnel@12001000/out-ports/port/endpoint";
|
|
funnel_little_in_port0 = "/soc/funnel@12001000/in-ports/port@0/endpoint";
|
|
funnel_little_in_port1 = "/soc/funnel@12001000/in-ports/port@1/endpoint";
|
|
funnel_little_in_port2 = "/soc/funnel@12001000/in-ports/port@2/endpoint";
|
|
funnel_little_in_port3 = "/soc/funnel@12001000/in-ports/port@3/endpoint";
|
|
etf_little_out = "/soc/etf@12002000/out-ports/port/endpoint";
|
|
etf_little_in = "/soc/etf@12002000/in-port/port/endpoint";
|
|
etf_big_out = "/soc/etf@12003000/out-ports/port/endpoint";
|
|
etf_big_in = "/soc/etf@12003000/in-ports/port/endpoint";
|
|
funnel_ca55_out_port = "/soc/funnel@12004000/out-ports/port/endpoint";
|
|
funnel_ca55_in_port0 = "/soc/funnel@12004000/in-ports/port@0/endpoint";
|
|
funnel_ca55_in_port1 = "/soc/funnel@12004000/in-ports/port@1/endpoint";
|
|
funnel_big_out_port = "/soc/funnel@12005000/out-ports/port/endpoint";
|
|
funnel_big_in_port0 = "/soc/funnel@12005000/in-ports/port@0/endpoint";
|
|
funnel_big_in_port1 = "/soc/funnel@12005000/in-ports/port@1/endpoint";
|
|
funnel_big_in_port2 = "/soc/funnel@12005000/in-ports/port@2/endpoint";
|
|
funnel_big_in_port3 = "/soc/funnel@12005000/in-ports/port@3/endpoint";
|
|
etm0_out = "/soc/etm@13040000/out-ports/port/endpoint";
|
|
etm1_out = "/soc/etm@13140000/out-ports/port/endpoint";
|
|
etm2_out = "/soc/etm@13240000/out-ports/port/endpoint";
|
|
etm3_out = "/soc/etm@13340000/out-ports/port/endpoint";
|
|
etm4_out = "/soc/etm@13440000/out-ports/port/endpoint";
|
|
etm5_out = "/soc/etm@13540000/out-ports/port/endpoint";
|
|
etm6_out = "/soc/etm@13640000/out-ports/port/endpoint";
|
|
etm7_out = "/soc/etm@13740000/out-ports/port/endpoint";
|
|
sdio0 = "/soc/ap-ahb/sdio@20300000";
|
|
sdio3 = "/soc/ap-ahb/sdio@20600000";
|
|
ext_26m = "/ext-26m";
|
|
ext_32k = "/ext-32k";
|
|
ext_4m = "/ext-4m";
|
|
rco_100m = "/rco-100m";
|
|
CPU0 = "/cpus/cpu@0";
|
|
CPU1 = "/cpus/cpu@100";
|
|
CPU2 = "/cpus/cpu@200";
|
|
CPU3 = "/cpus/cpu@300";
|
|
CPU4 = "/cpus/cpu@400";
|
|
CPU5 = "/cpus/cpu@500";
|
|
CPU6 = "/cpus/cpu@600";
|
|
CPU7 = "/cpus/cpu@700";
|
|
CORE_PD = "/idle-states/core-pd";
|
|
};
|
|
};
|