2887 lines
65 KiB
Text
Executable file
2887 lines
65 KiB
Text
Executable file
/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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qcom,msm-id = <0x124 0x00>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "HP Envy x2";
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compatible = "hp,envy-x2", "qcom,msm8998";
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chosen {
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};
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memory {
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device_type = "memory";
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reg = <0x00 0x00 0x00 0x00>;
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};
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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memory@85800000 {
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reg = <0x00 0x85800000 0x00 0x600000>;
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no-map;
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phandle = <0x6d>;
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};
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memory@85e00000 {
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reg = <0x00 0x85e00000 0x00 0x100000>;
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no-map;
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phandle = <0x6e>;
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};
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smem-mem@86000000 {
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reg = <0x00 0x86000000 0x00 0x200000>;
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no-map;
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phandle = <0x17>;
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};
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memory@86200000 {
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reg = <0x00 0x86200000 0x00 0x2d00000>;
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no-map;
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phandle = <0x6f>;
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};
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memory@88f00000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x00 0x88f00000 0x00 0x200000>;
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no-map;
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qcom,client-id = <0x01>;
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qcom,vmid = <0x0f>;
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phandle = <0x70>;
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};
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memory@8ab00000 {
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reg = <0x00 0x8ab00000 0x00 0x700000>;
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no-map;
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phandle = <0x71>;
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};
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memory@8b200000 {
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reg = <0x00 0x8b200000 0x00 0x1a00000>;
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no-map;
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phandle = <0x68>;
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};
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memory@8cc00000 {
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reg = <0x00 0x8cc00000 0x00 0x7000000>;
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no-map;
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phandle = <0x29>;
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};
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memory@93c00000 {
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reg = <0x00 0x93c00000 0x00 0x500000>;
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no-map;
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phandle = <0x72>;
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};
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memory@94100000 {
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reg = <0x00 0x94100000 0x00 0x200000>;
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no-map;
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phandle = <0x28>;
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};
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memory@94300000 {
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reg = <0x00 0x94300000 0x00 0xf00000>;
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no-map;
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phandle = <0x2c>;
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};
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memory@95200000 {
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reg = <0x00 0x95200000 0x00 0x10000>;
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no-map;
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phandle = <0x73>;
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};
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memory@95210000 {
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reg = <0x00 0x95210000 0x00 0x5000>;
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no-map;
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phandle = <0x74>;
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};
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memory@95600000 {
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reg = <0x00 0x95600000 0x00 0x100000>;
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no-map;
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phandle = <0x75>;
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};
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memory@95700000 {
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reg = <0x00 0x95700000 0x00 0x100000>;
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no-map;
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phandle = <0x6a>;
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};
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};
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clocks {
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xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x124f800>;
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clock-output-names = "xo_board";
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phandle = <0x56>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x7ffc>;
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};
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x00>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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next-level-cache = <0x03>;
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phandle = <0x06>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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phandle = <0x03>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x76>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x77>;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x01>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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next-level-cache = <0x03>;
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phandle = <0x07>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x78>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x79>;
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};
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x02>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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next-level-cache = <0x03>;
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phandle = <0x08>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x7a>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x7b>;
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};
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x03>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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next-level-cache = <0x03>;
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phandle = <0x09>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x7c>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x7d>;
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};
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x100>;
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enable-method = "psci";
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cpu-idle-states = <0x04>;
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next-level-cache = <0x05>;
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phandle = <0x0a>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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phandle = <0x05>;
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};
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x7e>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x7f>;
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};
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x101>;
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enable-method = "psci";
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cpu-idle-states = <0x04>;
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next-level-cache = <0x05>;
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phandle = <0x0b>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x80>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x81>;
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};
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};
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cpu@102 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x102>;
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enable-method = "psci";
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cpu-idle-states = <0x04>;
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next-level-cache = <0x05>;
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phandle = <0x0c>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x82>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x83>;
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};
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};
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cpu@103 {
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device_type = "cpu";
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compatible = "qcom,kryo280";
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reg = <0x00 0x103>;
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enable-method = "psci";
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cpu-idle-states = <0x04>;
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next-level-cache = <0x05>;
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phandle = <0x0d>;
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l1-icache {
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compatible = "arm,arch-cache";
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phandle = <0x84>;
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};
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l1-dcache {
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compatible = "arm,arch-cache";
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phandle = <0x85>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x06>;
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};
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core1 {
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cpu = <0x07>;
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};
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core2 {
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cpu = <0x08>;
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};
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core3 {
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cpu = <0x09>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x0a>;
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};
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core1 {
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cpu = <0x0b>;
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};
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core2 {
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cpu = <0x0c>;
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};
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core3 {
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cpu = <0x0d>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "little-retention";
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arm,psci-suspend-param = <0x02>;
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entry-latency-us = <0x51>;
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exit-latency-us = <0x56>;
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min-residency-us = <0x1f8>;
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phandle = <0x86>;
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};
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cpu-sleep-0-1 {
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compatible = "arm,idle-state";
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idle-state-name = "little-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <0x32e>;
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exit-latency-us = <0x11d2>;
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min-residency-us = <0x23df>;
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local-timer-stop;
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phandle = <0x02>;
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};
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cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "big-retention";
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arm,psci-suspend-param = <0x02>;
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entry-latency-us = <0x4f>;
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exit-latency-us = <0x52>;
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min-residency-us = <0x516>;
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phandle = <0x87>;
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};
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cpu-sleep-1-1 {
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compatible = "arm,idle-state";
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idle-state-name = "big-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <0x2d4>;
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exit-latency-us = <0x7eb>;
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min-residency-us = <0x24cb>;
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local-timer-stop;
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phandle = <0x04>;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8998", "qcom,scm";
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};
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};
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hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <0x0e 0x00 0x1000>;
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#hwlock-cells = <0x01>;
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phandle = <0x18>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <0x00 0xa8 0x01>;
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qcom,rpm-msg-ram = <0x0f>;
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mboxes = <0x10 0x00>;
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rpm-requests {
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compatible = "qcom,rpm-msm8998";
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qcom,glink-channels = "rpm_requests";
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phandle = <0x88>;
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clock-controller {
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compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
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#clock-cells = <0x01>;
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phandle = <0x23>;
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};
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power-controller {
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compatible = "qcom,msm8998-rpmpd";
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#power-domain-cells = <0x01>;
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operating-points-v2 = <0x11>;
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phandle = <0x27>;
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opp-table {
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compatible = "operating-points-v2";
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phandle = <0x11>;
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opp1 {
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opp-level = <0x10>;
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phandle = <0x89>;
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};
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opp2 {
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opp-level = <0x20>;
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phandle = <0x8a>;
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};
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opp3 {
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opp-level = <0x30>;
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phandle = <0x8b>;
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};
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opp4 {
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opp-level = <0x40>;
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phandle = <0x8c>;
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};
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opp5 {
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opp-level = <0x80>;
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phandle = <0x8d>;
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};
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opp6 {
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opp-level = <0xc0>;
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phandle = <0x8e>;
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};
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opp7 {
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opp-level = <0x100>;
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phandle = <0x8f>;
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};
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opp8 {
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opp-level = <0x140>;
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phandle = <0x90>;
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};
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opp9 {
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opp-level = <0x180>;
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phandle = <0x91>;
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};
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opp10 {
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opp-level = <0x200>;
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phandle = <0x92>;
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};
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};
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};
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pm8998-regulators {
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compatible = "qcom,rpm-pm8998-regulators";
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vdd_s1-supply = <0x12>;
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vdd_s2-supply = <0x12>;
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vdd_s3-supply = <0x12>;
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vdd_s4-supply = <0x12>;
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vdd_s5-supply = <0x12>;
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vdd_s6-supply = <0x12>;
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vdd_s7-supply = <0x12>;
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vdd_s8-supply = <0x12>;
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vdd_s9-supply = <0x12>;
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vdd_s10-supply = <0x12>;
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vdd_s11-supply = <0x12>;
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vdd_s12-supply = <0x12>;
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vdd_s13-supply = <0x12>;
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vdd_l1_l27-supply = <0x13>;
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vdd_l2_l8_l17-supply = <0x14>;
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vdd_l3_l11-supply = <0x13>;
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vdd_l4_l5-supply = <0x13>;
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vdd_l6-supply = <0x15>;
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vdd_l7_l12_l14_l15-supply = <0x15>;
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vdd_l9-supply = <0x12>;
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vdd_l10_l23_l25-supply = <0x12>;
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vdd_l13_l19_l21-supply = <0x12>;
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vdd_l16_l28-supply = <0x12>;
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vdd_l18_l22-supply = <0x12>;
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vdd_l20_l24-supply = <0x12>;
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vdd_l26-supply = <0x14>;
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vdd_lvs1_lvs2-supply = <0x16>;
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s3 {
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regulator-min-microvolt = <0x14a140>;
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regulator-max-microvolt = <0x14a140>;
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phandle = <0x14>;
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};
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s4 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x1b7740>;
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regulator-allow-set-load;
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phandle = <0x16>;
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};
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s5 {
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regulator-min-microvolt = <0x1d0d80>;
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regulator-max-microvolt = <0x1f20c0>;
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phandle = <0x15>;
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};
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s7 {
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regulator-min-microvolt = <0xdbba0>;
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regulator-max-microvolt = <0xfafa0>;
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phandle = <0x13>;
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};
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l1 {
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regulator-min-microvolt = <0xd6d80>;
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regulator-max-microvolt = <0xd6d80>;
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regulator-allow-set-load;
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phandle = <0x20>;
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};
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l2 {
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regulator-min-microvolt = <0x124f80>;
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regulator-max-microvolt = <0x124f80>;
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regulator-allow-set-load;
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phandle = <0x21>;
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};
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l3 {
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regulator-min-microvolt = <0xf4240>;
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regulator-max-microvolt = <0xf4240>;
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phandle = <0x93>;
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};
|
|
|
|
l5 {
|
|
regulator-min-microvolt = "", "\f5";
|
|
regulator-max-microvolt = "", "\f5";
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
l6 {
|
|
regulator-min-microvolt = <0x1b9680>;
|
|
regulator-max-microvolt = <0x1b9680>;
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
l7 {
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
regulator-allow-set-load;
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
l8 {
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
l9 {
|
|
regulator-min-microvolt = <0x1b9680>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
l10 {
|
|
regulator-min-microvolt = <0x1b9680>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
l11 {
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0xf4240>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
l12 {
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
l13 {
|
|
regulator-min-microvolt = <0x1b9680>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
l14 {
|
|
regulator-min-microvolt = <0x1cafc0>;
|
|
regulator-max-microvolt = <0x1cafc0>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
l15 {
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
l16 {
|
|
regulator-min-microvolt = <0x294280>;
|
|
regulator-max-microvolt = <0x294280>;
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
l17 {
|
|
regulator-min-microvolt = <0x13e5c0>;
|
|
regulator-max-microvolt = <0x13e5c0>;
|
|
regulator-allow-set-load;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
l18 {
|
|
regulator-min-microvolt = <0x294280>;
|
|
regulator-max-microvolt = <0x294280>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
l19 {
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
l20 {
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
regulator-allow-set-load;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
l21 {
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
regulator-allow-set-load;
|
|
regulator-system-load = "", "\f5";
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
l22 {
|
|
regulator-min-microvolt = <0x2bb380>;
|
|
regulator-max-microvolt = <0x2bb380>;
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
l23 {
|
|
regulator-min-microvolt = <0x328980>;
|
|
regulator-max-microvolt = <0x328980>;
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
l24 {
|
|
regulator-min-microvolt = <0x2f1e80>;
|
|
regulator-max-microvolt = <0x2f1e80>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
l25 {
|
|
regulator-min-microvolt = "", "/]";
|
|
regulator-max-microvolt = <0x328980>;
|
|
regulator-allow-set-load;
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
l26 {
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
l28 {
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
lvs1 {
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
lvs2 {
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x2b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <0x17>;
|
|
hwlocks = <0x18 0x03>;
|
|
};
|
|
|
|
smp2p-lpass {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1bb 0x1ad>;
|
|
interrupts = <0x00 0x9e 0x01>;
|
|
mboxes = <0x10 0x0a>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x02>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x67>;
|
|
};
|
|
};
|
|
|
|
smp2p-mpss {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1b3 0x1ac>;
|
|
interrupts = <0x00 0x1c3 0x01>;
|
|
mboxes = <0x10 0x0e>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x01>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x25>;
|
|
};
|
|
};
|
|
|
|
smp2p-slpi {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1e1 0x1ae>;
|
|
interrupts = <0x00 0xb2 0x01>;
|
|
mboxes = <0x10 0x1a>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x03>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2a>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
cpu0-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x01>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xa5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x02>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xa7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x03>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xa9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x04>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xab>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x07>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xad>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x08>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xaf>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x09>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xb1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x0a>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xb3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-bottom {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x0c>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-top {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x0d>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
clust0-mhm-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x05>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
clust1-mhm-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x06>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster1-l2-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x19 0x0b>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
modem-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x01>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xb9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mem-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x02>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xba>;
|
|
};
|
|
};
|
|
};
|
|
|
|
wlan-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x03>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
q6-dsp-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x04>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbc>;
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x05>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
multimedia-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1a 0x06>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm8998 {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x1b>;
|
|
|
|
trips {
|
|
|
|
pm8998-alert0 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
pm8998-crit {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xc0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x01 0x08 0x01 0x02 0x08 0x01 0x03 0x08 0x01 0x00 0x08>;
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
phandle = <0xc1>;
|
|
|
|
clock-controller@100000 {
|
|
compatible = "qcom,gcc-msm8998";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
#power-domain-cells = <0x01>;
|
|
reg = <0x100000 0xb0000>;
|
|
phandle = <0x1d>;
|
|
};
|
|
|
|
memory@778000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x778000 0x7000>;
|
|
phandle = <0x0f>;
|
|
};
|
|
|
|
qfprom@780000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x780000 0x621c>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
phandle = <0xc2>;
|
|
|
|
hstx-trim@423a {
|
|
reg = <0x423a 0x01>;
|
|
bits = <0x00 0x04>;
|
|
phandle = <0x53>;
|
|
};
|
|
};
|
|
|
|
thermal@10ab000 {
|
|
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
|
reg = <0x10ab000 0x1000 0x10aa000 0x1000>;
|
|
#qcom,sensors = <0x0e>;
|
|
interrupts = <0x00 0x1ca 0x04 0x00 0x1bd 0x04>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
thermal@10ae000 {
|
|
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
|
reg = <0x10ae000 0x1000 0x10ad000 0x1000>;
|
|
#qcom,sensors = <0x08>;
|
|
interrupts = <0x00 0xb8 0x04 0x00 0x1ae 0x04>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
iommu@1680000 {
|
|
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
|
reg = <0x1680000 0x10000>;
|
|
#iommu-cells = <0x01>;
|
|
#global-interrupts = <0x00>;
|
|
interrupts = <0x00 0x16c 0x01 0x00 0x16d 0x01 0x00 0x16e 0x01 0x00 0x16f 0x01 0x00 0x170 0x01 0x00 0x171 0x01>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
iommu@16c0000 {
|
|
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
|
reg = <0x16c0000 0x40000>;
|
|
#iommu-cells = <0x01>;
|
|
#global-interrupts = <0x00>;
|
|
interrupts = <0x00 0x175 0x01 0x00 0x176 0x01 0x00 0x177 0x01 0x00 0x178 0x01 0x00 0x179 0x01 0x00 0x17a 0x01 0x00 0x1ce 0x01 0x00 0x1cf 0x01 0x00 0x1d0 0x01 0x00 0x1d1 0x01>;
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
pci@1c00000 {
|
|
compatible = "qcom,pcie-msm8996";
|
|
reg = <0x1c00000 0x2000 0x1b000000 0xf1d 0x1b000f20 0xa8 0x1b100000 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0x00>;
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
num-lanes = <0x01>;
|
|
phys = <0x1c>;
|
|
phy-names = "pciephy";
|
|
ranges = <0x1000000 0x00 0x00 0x1b200000 0x00 0x100000 0x2000000 0x00 0x1b300000 0x1b300000 0x00 0xd00000>;
|
|
#interrupt-cells = <0x01>;
|
|
interrupts = <0x00 0x195 0x04>;
|
|
interrupt-names = "msi";
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x87 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x88 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x8a 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x8b 0x04>;
|
|
clocks = <0x1d 0x5e 0x1d 0x5d 0x1d 0x5f 0x1d 0x5c 0x1d 0x5b>;
|
|
clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
|
|
power-domains = <0x1d 0x00>;
|
|
iommu-map = <0x100 0x1e 0x1480 0x01>;
|
|
perst-gpios = <0x1f 0x23 0x01>;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
phy@1c06000 {
|
|
compatible = "qcom,msm8998-qmp-pcie-phy";
|
|
reg = <0x1c06000 0x18c>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x1d 0x60 0x1d 0x5c 0x1d 0xa9>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
resets = <0x1d 0x4c 0x1d 0x4e>;
|
|
reset-names = "phy", "common";
|
|
vdda-phy-supply = <0x20>;
|
|
vdda-pll-supply = <0x21>;
|
|
|
|
lane@1c06800 {
|
|
reg = <0x1c06200 0x128 0x1c06400 0x1fc 0x1c06800 0x20c>;
|
|
#phy-cells = <0x00>;
|
|
clocks = <0x1d 0x5e>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "pcie_0_pipe_clk_src";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x1c>;
|
|
};
|
|
};
|
|
|
|
ufshc@1da4000 {
|
|
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
|
reg = <0x1da4000 0x2500>;
|
|
interrupts = <0x00 0x109 0x04>;
|
|
phys = <0x22>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <0x02>;
|
|
power-domains = <0x1d 0x01>;
|
|
#reset-cells = <0x01>;
|
|
clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk";
|
|
clocks = <0x1d 0x6d 0x1d 0x1f 0x1d 0x6c 0x1d 0x73 0x23 0x50 0x1d 0x72 0x1d 0x70 0x1d 0x71>;
|
|
freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
resets = <0x1d 0x11>;
|
|
reset-names = "rst";
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
phy@1da7000 {
|
|
compatible = "qcom,msm8998-qmp-ufs-phy";
|
|
reg = <0x1da7000 0x18c>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clock-names = "ref", "ref_aux";
|
|
clocks = <0x1d 0xa8 0x1d 0x6f>;
|
|
reset-names = "ufsphy";
|
|
resets = <0x24 0x00>;
|
|
phandle = <0xc4>;
|
|
|
|
lanes@1da7400 {
|
|
reg = <0x1da7400 0x128 0x1da7600 0x1fc 0x1da7c00 0x1dc 0x1da7800 0x128 0x1da7a00 0x1fc>;
|
|
#phy-cells = <0x00>;
|
|
phandle = <0x22>;
|
|
};
|
|
};
|
|
|
|
syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x40000>;
|
|
phandle = <0x0e>;
|
|
};
|
|
|
|
pinctrl@3400000 {
|
|
compatible = "qcom,msm8998-pinctrl";
|
|
reg = <0x3400000 0xc00000>;
|
|
interrupts = <0x00 0xd0 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
gpio-reserved-ranges = <0x00 0x04 0x51 0x04>;
|
|
phandle = <0x1f>;
|
|
|
|
sdc2_clk_on {
|
|
phandle = <0x59>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
sdc2_clk_off {
|
|
phandle = <0x5d>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_on {
|
|
phandle = <0x5a>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_off {
|
|
phandle = <0x5e>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_on {
|
|
phandle = <0x5b>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_off {
|
|
phandle = <0x5f>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_cd_on {
|
|
phandle = <0x5c>;
|
|
|
|
mux {
|
|
pins = "gpio95";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio95";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_cd_off {
|
|
phandle = <0x60>;
|
|
|
|
mux {
|
|
pins = "gpio95";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio95";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
blsp1_uart3_on {
|
|
phandle = <0x62>;
|
|
|
|
tx {
|
|
pins = "gpio45";
|
|
function = "blsp_uart3_a";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
|
|
rx {
|
|
pins = "gpio46";
|
|
function = "blsp_uart3_a";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
cts {
|
|
pins = "gpio47";
|
|
function = "blsp_uart3_a";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
rfr {
|
|
pins = "gpio48";
|
|
function = "blsp_uart3_a";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
touchpad {
|
|
phandle = <0x66>;
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc@4080000 {
|
|
compatible = "qcom,msm8998-mss-pil";
|
|
reg = <0x4080000 0x100 0x4180000 0x20>;
|
|
reg-names = "qdsp6", "rmb";
|
|
interrupts-extended = <0x01 0x00 0x1c0 0x01 0x25 0x00 0x01 0x25 0x01 0x01 0x25 0x02 0x01 0x25 0x03 0x01 0x25 0x07 0x01>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack";
|
|
clocks = <0x1d 0xab 0x1d 0x24 0x1d 0xac 0x1d 0xad 0x1d 0xae 0x1d 0xaf 0x23 0x08 0x23 0x00>;
|
|
clock-names = "iface", "bus", "mem", "gpll0_mss", "snoc_axi", "mnoc_axi", "qdss", "xo";
|
|
qcom,smem-states = <0x26 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
resets = <0x1d 0x6c>;
|
|
reset-names = "mss_restart";
|
|
qcom,halt-regs = <0x0e 0x23000 0x25000 0x24000>;
|
|
power-domains = <0x27 0x00 0x27 0x03>;
|
|
power-domain-names = "cx", "mx";
|
|
phandle = <0xc5>;
|
|
|
|
mba {
|
|
memory-region = <0x28>;
|
|
};
|
|
|
|
mpss {
|
|
memory-region = <0x29>;
|
|
};
|
|
|
|
glink-edge {
|
|
interrupts = <0x00 0x1c4 0x01>;
|
|
label = "modem";
|
|
qcom,remote-pid = <0x01>;
|
|
mboxes = <0x10 0x0f>;
|
|
};
|
|
};
|
|
|
|
clock-controller@5065000 {
|
|
compatible = "qcom,msm8998-gpucc";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
#power-domain-cells = <0x01>;
|
|
reg = <0x5065000 0x9000>;
|
|
clocks = <0x23 0x00 0x1d 0x7f>;
|
|
clock-names = "xo", "gpll0";
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
remoteproc@5800000 {
|
|
compatible = "qcom,msm8998-slpi-pas";
|
|
reg = <0x5800000 0x4040>;
|
|
interrupts-extended = <0x01 0x00 0x186 0x01 0x2a 0x00 0x01 0x2a 0x01 0x01 0x2a 0x02 0x01 0x2a 0x03 0x01>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
|
|
px-supply = <0x2b>;
|
|
clocks = <0x23 0x00 0x23 0x40>;
|
|
clock-names = "xo", "aggre2";
|
|
memory-region = <0x2c>;
|
|
qcom,smem-states = <0x2d 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
power-domains = <0x27 0x06>;
|
|
power-domain-names = "ssc_cx";
|
|
status = "disabled";
|
|
phandle = <0xc7>;
|
|
|
|
glink-edge {
|
|
interrupts = <0x00 0xb3 0x01>;
|
|
label = "dsps";
|
|
qcom,remote-pid = <0x03>;
|
|
mboxes = <0x10 0x1b>;
|
|
};
|
|
};
|
|
|
|
stm@6002000 {
|
|
compatible = "arm,coresight-stm", "arm,primecell";
|
|
reg = <0x6002000 0x1000 0x16280000 0x180000>;
|
|
reg-names = "stm-base", "stm-stimulus-base";
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xc8>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2e>;
|
|
phandle = <0x30>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6041000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x6041000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xc9>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2f>;
|
|
phandle = <0x34>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x30>;
|
|
phandle = <0x2e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6042000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x6042000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xca>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x31>;
|
|
phandle = <0x35>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x32>;
|
|
phandle = <0x48>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6045000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x6045000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xcb>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x33>;
|
|
phandle = <0x39>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x34>;
|
|
phandle = <0x2f>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x35>;
|
|
phandle = <0x31>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@6046000 {
|
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
|
reg = <0x6046000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xcc>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x36>;
|
|
phandle = <0x3a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x37>;
|
|
phandle = <0x38>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf@6047000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x6047000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xcd>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x38>;
|
|
phandle = <0x37>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x39>;
|
|
phandle = <0x33>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@6048000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x6048000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
arm,scatter-gather;
|
|
phandle = <0xce>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3a>;
|
|
phandle = <0x36>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7840000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7840000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x06>;
|
|
phandle = <0xcf>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3b>;
|
|
phandle = <0x40>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7940000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7940000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x07>;
|
|
phandle = <0xd0>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3c>;
|
|
phandle = <0x41>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7a40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7a40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x08>;
|
|
phandle = <0xd1>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3d>;
|
|
phandle = <0x42>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7b40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7b40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x09>;
|
|
phandle = <0xd2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3e>;
|
|
phandle = <0x43>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7b60000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7b60000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xd3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3f>;
|
|
phandle = <0x49>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x40>;
|
|
phandle = <0x3b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x41>;
|
|
phandle = <0x3c>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x42>;
|
|
phandle = <0x3d>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x43>;
|
|
phandle = <0x3e>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x44>;
|
|
phandle = <0x4a>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x45>;
|
|
phandle = <0x4b>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x46>;
|
|
phandle = <0x4c>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x47>;
|
|
phandle = <0x4d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7b70000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x7b70000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
phandle = <0xd4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x48>;
|
|
phandle = <0x32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x49>;
|
|
phandle = <0x3f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7c40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7c40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x0a>;
|
|
phandle = <0xd5>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4a>;
|
|
phandle = <0x44>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7d40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7d40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x0b>;
|
|
phandle = <0xd6>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4b>;
|
|
phandle = <0x45>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7e40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7e40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x0c>;
|
|
phandle = <0xd7>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4c>;
|
|
phandle = <0x46>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7f40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x7f40000 0x1000>;
|
|
status = "disabled";
|
|
clocks = <0x23 0x08 0x23 0x09>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
cpu = <0x0d>;
|
|
phandle = <0xd8>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4d>;
|
|
phandle = <0x47>;
|
|
};
|
|
};
|
|
};
|
|
|
|
spmi@800f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x800f000 0x1000 0x8400000 0x1000000 0x9400000 0x1000000 0xa400000 0x220000 0x800a000 0x3000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <0x00 0x146 0x04>;
|
|
qcom,ee = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
cell-index = <0x00>;
|
|
phandle = <0xd9>;
|
|
|
|
pmic@0 {
|
|
compatible = "qcom,pm8998", "qcom,spmi-pmic";
|
|
reg = <0x00 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xda>;
|
|
|
|
pon@800 {
|
|
compatible = "qcom,pm8998-pon";
|
|
reg = <0x800>;
|
|
mode-bootloader = <0x02>;
|
|
mode-recovery = <0x01>;
|
|
phandle = <0xdb>;
|
|
|
|
pwrkey {
|
|
compatible = "qcom,pm8941-pwrkey";
|
|
interrupts = <0x00 0x08 0x00 0x03>;
|
|
debounce = <0x3d09>;
|
|
bias-pull-up;
|
|
linux,code = <0x74>;
|
|
phandle = <0xdc>;
|
|
};
|
|
};
|
|
|
|
temp-alarm@2400 {
|
|
compatible = "qcom,spmi-temp-alarm";
|
|
reg = <0x2400>;
|
|
interrupts = <0x00 0x24 0x00 0x01>;
|
|
io-channels = <0x4e 0x06>;
|
|
io-channel-names = "thermal";
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
coincell@2800 {
|
|
compatible = "qcom,pm8941-coincell";
|
|
reg = <0x2800>;
|
|
status = "disabled";
|
|
phandle = <0xdd>;
|
|
};
|
|
|
|
adc@3100 {
|
|
compatible = "qcom,spmi-adc-rev2";
|
|
reg = <0x3100>;
|
|
interrupts = <0x00 0x31 0x00 0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#io-channel-cells = <0x01>;
|
|
phandle = <0x4e>;
|
|
|
|
adc-chan@6 {
|
|
reg = <0x06>;
|
|
label = "die_temp";
|
|
};
|
|
};
|
|
|
|
rtc@6000 {
|
|
compatible = "qcom,pm8941-rtc";
|
|
reg = <0x6000 0x6100>;
|
|
reg-names = "rtc", "alarm";
|
|
interrupts = <0x00 0x61 0x01 0x01>;
|
|
};
|
|
|
|
gpios@c000 {
|
|
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
|
|
reg = <0xc000>;
|
|
gpio-controller;
|
|
gpio-ranges = <0x4f 0x00 0x00 0x1a>;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x4f>;
|
|
};
|
|
};
|
|
|
|
pmic@1 {
|
|
compatible = "qcom,pm8998", "qcom,spmi-pmic";
|
|
reg = <0x01 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
pmic@4 {
|
|
compatible = "qcom,pm8005", "qcom,spmi-pmic";
|
|
reg = <0x04 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xdf>;
|
|
|
|
gpios@c000 {
|
|
compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio";
|
|
reg = <0xc000>;
|
|
gpio-controller;
|
|
gpio-ranges = <0x50 0x00 0x00 0x04>;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x50>;
|
|
};
|
|
};
|
|
|
|
pmic@5 {
|
|
compatible = "qcom,pm8005", "qcom,spmi-pmic";
|
|
reg = <0x05 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xe0>;
|
|
|
|
pm8005-regulators {
|
|
compatible = "qcom,pm8005-regulators";
|
|
vdd_s1-supply = <0x12>;
|
|
|
|
s1 {
|
|
regulator-min-microvolt = <0x7fee0>;
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
regulator-enable-ramp-delay = <0x1f4>;
|
|
regulator-always-on;
|
|
phandle = <0xe1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
usb@a8f8800 {
|
|
compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
|
|
reg = <0xa8f8800 0x400>;
|
|
status = "okay";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x1d 0x47 0x1d 0x74 0x1d 0x20 0x1d 0x75 0x1d 0x76>;
|
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", "sleep";
|
|
assigned-clocks = <0x1d 0x75 0x1d 0x74>;
|
|
assigned-clock-rates = <0x124f800 0x7270e00>;
|
|
interrupts = <0x00 0x15b 0x04 0x00 0xf3 0x04>;
|
|
interrupt-names = "hs_phy_irq", "ss_phy_irq";
|
|
power-domains = <0x1d 0x02>;
|
|
resets = <0x1d 0x12>;
|
|
phandle = <0xe2>;
|
|
|
|
dwc3@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xa800000 0xcd00>;
|
|
interrupts = <0x00 0x83 0x04>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <0x51 0x52>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = [10];
|
|
dr_mode = "host";
|
|
phandle = <0xe3>;
|
|
};
|
|
};
|
|
|
|
phy@c010000 {
|
|
compatible = "qcom,msm8998-qmp-usb3-phy";
|
|
reg = <0xc010000 0x18c>;
|
|
status = "okay";
|
|
#clock-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x1d 0x77 0x1d 0x79 0x1d 0xa6>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
resets = <0x1d 0x45 0x1d 0x46>;
|
|
reset-names = "phy", "common";
|
|
vdda-phy-supply = <0x20>;
|
|
vdda-pll-supply = <0x21>;
|
|
phandle = <0xe4>;
|
|
|
|
lane@c010200 {
|
|
reg = <0xc010200 0x128 0xc010400 0x200 0xc010c00 0x20c 0xc010600 0x128 0xc010800 0x200>;
|
|
#phy-cells = <0x00>;
|
|
clocks = <0x1d 0x78>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "usb3_phy_pipe_clk_src";
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
|
|
phy@c012000 {
|
|
compatible = "qcom,msm8998-qusb2-phy";
|
|
reg = <0xc012000 0x2a8>;
|
|
status = "okay";
|
|
#phy-cells = <0x00>;
|
|
clocks = <0x1d 0x79 0x1d 0xaa>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
resets = <0x1d 0x6a>;
|
|
nvmem-cells = <0x53>;
|
|
vdda-pll-supply = <0x54>;
|
|
vdda-phy-dpdm-supply = <0x55>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
sdhci@c0a4900 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0xc0a4900 0x314 0xc0a4000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
interrupts = <0x00 0x7d 0x04 0x00 0xdd 0x04>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
clock-names = "iface", "core", "xo";
|
|
clocks = <0x1d 0x65 0x1d 0x66 0x56>;
|
|
bus-width = <0x04>;
|
|
status = "okay";
|
|
vmmc-supply = <0x57>;
|
|
vqmmc-supply = <0x58>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <0x59 0x5a 0x5b 0x5c>;
|
|
pinctrl-1 = <0x5d 0x5e 0x5f 0x60>;
|
|
cd-gpios = <0x1f 0x5f 0x01>;
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
dma@c144000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0xc144000 0x25000>;
|
|
interrupts = <0x00 0xee 0x04>;
|
|
clocks = <0x1d 0x25>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <0x01>;
|
|
qcom,ee = <0x00>;
|
|
qcom,controlled-remotely;
|
|
num-channels = <0x12>;
|
|
qcom,num-ees = <0x04>;
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
serial@c171000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0xc171000 0x1000>;
|
|
interrupts = <0x00 0x6d 0x04>;
|
|
clocks = <0x1d 0x35 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
dmas = <0x61 0x04 0x61 0x05>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x62>;
|
|
status = "okay";
|
|
phandle = <0xe6>;
|
|
|
|
bluetooth {
|
|
compatible = "qcom,wcn3990-bt";
|
|
vddio-supply = <0x16>;
|
|
vddxo-supply = <0x63>;
|
|
vddrf-supply = <0x64>;
|
|
vddch0-supply = <0x65>;
|
|
max-speed = <0x30d400>;
|
|
};
|
|
};
|
|
|
|
i2c@c175000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc175000 0x600>;
|
|
interrupts = <0x00 0x5f 0x04>;
|
|
clocks = <0x1d 0x26 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
i2c@c176000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc176000 0x600>;
|
|
interrupts = <0x00 0x60 0x04>;
|
|
clocks = <0x1d 0x28 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
i2c@c177000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc177000 0x600>;
|
|
interrupts = <0x00 0x61 0x04>;
|
|
clocks = <0x1d 0x2a 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
i2c@c178000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc178000 0x600>;
|
|
interrupts = <0x00 0x62 0x04>;
|
|
clocks = <0x1d 0x2c 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
i2c@c179000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc179000 0x600>;
|
|
interrupts = <0x00 0x63 0x04>;
|
|
clocks = <0x1d 0x2e 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
i2c@c17a000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc17a000 0x600>;
|
|
interrupts = <0x00 0x64 0x04>;
|
|
clocks = <0x1d 0x30 0x1d 0x25>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "okay";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xec>;
|
|
|
|
keyboard@3a {
|
|
compatible = "hid-over-i2c";
|
|
interrupt-parent = <0x1f>;
|
|
interrupts = <0x79 0x08>;
|
|
reg = <0x3a>;
|
|
hid-descr-addr = <0x01>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x66>;
|
|
};
|
|
};
|
|
|
|
serial@c1b0000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0xc1b0000 0x1000>;
|
|
interrupts = <0x00 0x72 0x04>;
|
|
clocks = <0x1d 0x45 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
phandle = <0xed>;
|
|
};
|
|
|
|
i2c@c1b5000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1b5000 0x600>;
|
|
interrupts = <0x00 0x65 0x04>;
|
|
clocks = <0x1d 0x37 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xee>;
|
|
};
|
|
|
|
i2c@c1b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1b6000 0x600>;
|
|
interrupts = <0x00 0x66 0x04>;
|
|
clocks = <0x1d 0x39 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xef>;
|
|
};
|
|
|
|
i2c@c1b7000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1b7000 0x600>;
|
|
interrupts = <0x00 0x67 0x04>;
|
|
clocks = <0x1d 0x3b 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xf0>;
|
|
};
|
|
|
|
i2c@c1b8000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1b8000 0x600>;
|
|
interrupts = <0x00 0x68 0x04>;
|
|
clocks = <0x1d 0x3d 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xf1>;
|
|
};
|
|
|
|
i2c@c1b9000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1b9000 0x600>;
|
|
interrupts = <0x00 0x69 0x04>;
|
|
clocks = <0x1d 0x3f 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xf2>;
|
|
};
|
|
|
|
i2c@c1ba000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xc1ba000 0x600>;
|
|
interrupts = <0x00 0x6a 0x04>;
|
|
clocks = <0x1d 0x41 0x1d 0x36>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <0x61a80>;
|
|
status = "disabled";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
remoteproc@17300000 {
|
|
compatible = "qcom,msm8998-adsp-pas";
|
|
reg = <0x17300000 0x4040>;
|
|
interrupts-extended = <0x01 0x00 0xa2 0x01 0x67 0x00 0x01 0x67 0x01 0x01 0x67 0x02 0x01 0x67 0x03 0x01>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
|
|
clocks = <0x23 0x00>;
|
|
clock-names = "xo";
|
|
memory-region = <0x68>;
|
|
qcom,smem-states = <0x69 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
power-domains = <0x27 0x00>;
|
|
power-domain-names = "cx";
|
|
status = "disabled";
|
|
phandle = <0xf4>;
|
|
|
|
glink-edge {
|
|
interrupts = <0x00 0x9d 0x01>;
|
|
label = "lpass";
|
|
qcom,remote-pid = <0x02>;
|
|
mboxes = <0x10 0x09>;
|
|
};
|
|
};
|
|
|
|
mailbox@17911000 {
|
|
compatible = "qcom,msm8998-apcs-hmss-global";
|
|
reg = <0x17911000 0x1000>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x10>;
|
|
};
|
|
|
|
timer@17920000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17920000 0x1000>;
|
|
|
|
frame@17921000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>;
|
|
reg = <0x17921000 0x1000 0x17922000 0x1000>;
|
|
};
|
|
|
|
frame@17923000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
reg = <0x17923000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17924000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0x17924000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17925000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
reg = <0x17925000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17926000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
reg = <0x17926000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17927000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
reg = <0x17927000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17928000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
reg = <0x17928000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x17a00000 0x10000 0x17b00000 0x100000>;
|
|
#interrupt-cells = <0x03>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
interrupt-controller;
|
|
#redistributor-regions = <0x01>;
|
|
redistributor-stride = <0x00 0x20000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
phandle = <0x01>;
|
|
};
|
|
|
|
wifi@18800000 {
|
|
compatible = "qcom,wcn3990-wifi";
|
|
status = "okay";
|
|
reg = <0x18800000 0x800000>;
|
|
reg-names = "membase";
|
|
memory-region = <0x6a>;
|
|
clocks = <0x23 0x18>;
|
|
clock-names = "cxo_ref_clk_pin";
|
|
interrupts = <0x00 0x19d 0x04 0x00 0x19e 0x04 0x00 0x19f 0x04 0x00 0x1a0 0x04 0x00 0x1a1 0x04 0x00 0x1a2 0x04 0x00 0x1a4 0x04 0x00 0x1a5 0x04 0x00 0x1a6 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04>;
|
|
iommus = <0x6b 0x1900 0x6b 0x1901>;
|
|
qcom,snoc-host-cap-8bit-quirk;
|
|
vdd-0.8-cx-mx-supply = <0x6c>;
|
|
vdd-1.8-xo-supply = <0x63>;
|
|
vdd-1.3-rfa-supply = <0x64>;
|
|
vdd-3.3-ch0-supply = <0x65>;
|
|
phandle = <0xf5>;
|
|
};
|
|
};
|
|
|
|
vph-pwr-regulator {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vph_pwr";
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
__symbols__ {
|
|
hyp_mem = "/reserved-memory/memory@85800000";
|
|
xbl_mem = "/reserved-memory/memory@85e00000";
|
|
smem_mem = "/reserved-memory/smem-mem@86000000";
|
|
tz_mem = "/reserved-memory/memory@86200000";
|
|
rmtfs_mem = "/reserved-memory/memory@88f00000";
|
|
spss_mem = "/reserved-memory/memory@8ab00000";
|
|
adsp_mem = "/reserved-memory/memory@8b200000";
|
|
mpss_mem = "/reserved-memory/memory@8cc00000";
|
|
venus_mem = "/reserved-memory/memory@93c00000";
|
|
mba_mem = "/reserved-memory/memory@94100000";
|
|
slpi_mem = "/reserved-memory/memory@94300000";
|
|
ipa_fw_mem = "/reserved-memory/memory@95200000";
|
|
ipa_gsi_mem = "/reserved-memory/memory@95210000";
|
|
gpu_mem = "/reserved-memory/memory@95600000";
|
|
wlan_msa_mem = "/reserved-memory/memory@95700000";
|
|
xo = "/clocks/xo-board";
|
|
CPU0 = "/cpus/cpu@0";
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
|
L1_I_0 = "/cpus/cpu@0/l1-icache";
|
|
L1_D_0 = "/cpus/cpu@0/l1-dcache";
|
|
CPU1 = "/cpus/cpu@1";
|
|
L1_I_1 = "/cpus/cpu@1/l1-icache";
|
|
L1_D_1 = "/cpus/cpu@1/l1-dcache";
|
|
CPU2 = "/cpus/cpu@2";
|
|
L1_I_2 = "/cpus/cpu@2/l1-icache";
|
|
L1_D_2 = "/cpus/cpu@2/l1-dcache";
|
|
CPU3 = "/cpus/cpu@3";
|
|
L1_I_3 = "/cpus/cpu@3/l1-icache";
|
|
L1_D_3 = "/cpus/cpu@3/l1-dcache";
|
|
CPU4 = "/cpus/cpu@100";
|
|
L2_1 = "/cpus/cpu@100/l2-cache";
|
|
L1_I_100 = "/cpus/cpu@100/l1-icache";
|
|
L1_D_100 = "/cpus/cpu@100/l1-dcache";
|
|
CPU5 = "/cpus/cpu@101";
|
|
L1_I_101 = "/cpus/cpu@101/l1-icache";
|
|
L1_D_101 = "/cpus/cpu@101/l1-dcache";
|
|
CPU6 = "/cpus/cpu@102";
|
|
L1_I_102 = "/cpus/cpu@102/l1-icache";
|
|
L1_D_102 = "/cpus/cpu@102/l1-dcache";
|
|
CPU7 = "/cpus/cpu@103";
|
|
L1_I_103 = "/cpus/cpu@103/l1-icache";
|
|
L1_D_103 = "/cpus/cpu@103/l1-dcache";
|
|
LITTLE_CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0-0";
|
|
LITTLE_CPU_SLEEP_1 = "/cpus/idle-states/cpu-sleep-0-1";
|
|
BIG_CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-1-0";
|
|
BIG_CPU_SLEEP_1 = "/cpus/idle-states/cpu-sleep-1-1";
|
|
tcsr_mutex = "/hwlock";
|
|
rpm_requests = "/rpm-glink/rpm-requests";
|
|
rpmcc = "/rpm-glink/rpm-requests/clock-controller";
|
|
rpmpd = "/rpm-glink/rpm-requests/power-controller";
|
|
rpmpd_opp_table = "/rpm-glink/rpm-requests/power-controller/opp-table";
|
|
rpmpd_opp_ret = "/rpm-glink/rpm-requests/power-controller/opp-table/opp1";
|
|
rpmpd_opp_ret_plus = "/rpm-glink/rpm-requests/power-controller/opp-table/opp2";
|
|
rpmpd_opp_min_svs = "/rpm-glink/rpm-requests/power-controller/opp-table/opp3";
|
|
rpmpd_opp_low_svs = "/rpm-glink/rpm-requests/power-controller/opp-table/opp4";
|
|
rpmpd_opp_svs = "/rpm-glink/rpm-requests/power-controller/opp-table/opp5";
|
|
rpmpd_opp_svs_plus = "/rpm-glink/rpm-requests/power-controller/opp-table/opp6";
|
|
rpmpd_opp_nom = "/rpm-glink/rpm-requests/power-controller/opp-table/opp7";
|
|
rpmpd_opp_nom_plus = "/rpm-glink/rpm-requests/power-controller/opp-table/opp8";
|
|
rpmpd_opp_turbo = "/rpm-glink/rpm-requests/power-controller/opp-table/opp9";
|
|
rpmpd_opp_turbo_plus = "/rpm-glink/rpm-requests/power-controller/opp-table/opp10";
|
|
vreg_s3a_1p35 = "/rpm-glink/rpm-requests/pm8998-regulators/s3";
|
|
vreg_s4a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/s4";
|
|
vreg_s5a_2p04 = "/rpm-glink/rpm-requests/pm8998-regulators/s5";
|
|
vreg_s7a_1p025 = "/rpm-glink/rpm-requests/pm8998-regulators/s7";
|
|
vreg_l1a_0p875 = "/rpm-glink/rpm-requests/pm8998-regulators/l1";
|
|
vreg_l2a_1p2 = "/rpm-glink/rpm-requests/pm8998-regulators/l2";
|
|
vreg_l3a_1p0 = "/rpm-glink/rpm-requests/pm8998-regulators/l3";
|
|
vreg_l5a_0p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l5";
|
|
vreg_l6a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l6";
|
|
vreg_l7a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l7";
|
|
vreg_l8a_1p2 = "/rpm-glink/rpm-requests/pm8998-regulators/l8";
|
|
vreg_l9a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l9";
|
|
vreg_l10a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l10";
|
|
vreg_l11a_1p0 = "/rpm-glink/rpm-requests/pm8998-regulators/l11";
|
|
vreg_l12a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l12";
|
|
vreg_l13a_2p95 = "/rpm-glink/rpm-requests/pm8998-regulators/l13";
|
|
vreg_l14a_1p88 = "/rpm-glink/rpm-requests/pm8998-regulators/l14";
|
|
vreg_l15a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/l15";
|
|
vreg_l16a_2p7 = "/rpm-glink/rpm-requests/pm8998-regulators/l16";
|
|
vreg_l17a_1p3 = "/rpm-glink/rpm-requests/pm8998-regulators/l17";
|
|
vreg_l18a_2p7 = "/rpm-glink/rpm-requests/pm8998-regulators/l18";
|
|
vreg_l19a_3p0 = "/rpm-glink/rpm-requests/pm8998-regulators/l19";
|
|
vreg_l20a_2p95 = "/rpm-glink/rpm-requests/pm8998-regulators/l20";
|
|
vreg_l21a_2p95 = "/rpm-glink/rpm-requests/pm8998-regulators/l21";
|
|
vreg_l22a_2p85 = "/rpm-glink/rpm-requests/pm8998-regulators/l22";
|
|
vreg_l23a_3p3 = "/rpm-glink/rpm-requests/pm8998-regulators/l23";
|
|
vreg_l24a_3p075 = "/rpm-glink/rpm-requests/pm8998-regulators/l24";
|
|
vreg_l25a_3p3 = "/rpm-glink/rpm-requests/pm8998-regulators/l25";
|
|
vreg_l26a_1p2 = "/rpm-glink/rpm-requests/pm8998-regulators/l26";
|
|
vreg_l28_3p0 = "/rpm-glink/rpm-requests/pm8998-regulators/l28";
|
|
vreg_lvs1a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/lvs1";
|
|
vreg_lvs2a_1p8 = "/rpm-glink/rpm-requests/pm8998-regulators/lvs2";
|
|
adsp_smp2p_out = "/smp2p-lpass/master-kernel";
|
|
adsp_smp2p_in = "/smp2p-lpass/slave-kernel";
|
|
modem_smp2p_out = "/smp2p-mpss/master-kernel";
|
|
modem_smp2p_in = "/smp2p-mpss/slave-kernel";
|
|
slpi_smp2p_out = "/smp2p-slpi/master-kernel";
|
|
slpi_smp2p_in = "/smp2p-slpi/slave-kernel";
|
|
cpu0_alert0 = "/thermal-zones/cpu0-thermal/trips/trip-point0";
|
|
cpu0_crit = "/thermal-zones/cpu0-thermal/trips/cpu_crit";
|
|
cpu1_alert0 = "/thermal-zones/cpu1-thermal/trips/trip-point0";
|
|
cpu1_crit = "/thermal-zones/cpu1-thermal/trips/cpu_crit";
|
|
cpu2_alert0 = "/thermal-zones/cpu2-thermal/trips/trip-point0";
|
|
cpu2_crit = "/thermal-zones/cpu2-thermal/trips/cpu_crit";
|
|
cpu3_alert0 = "/thermal-zones/cpu3-thermal/trips/trip-point0";
|
|
cpu3_crit = "/thermal-zones/cpu3-thermal/trips/cpu_crit";
|
|
cpu4_alert0 = "/thermal-zones/cpu4-thermal/trips/trip-point0";
|
|
cpu4_crit = "/thermal-zones/cpu4-thermal/trips/cpu_crit";
|
|
cpu5_alert0 = "/thermal-zones/cpu5-thermal/trips/trip-point0";
|
|
cpu5_crit = "/thermal-zones/cpu5-thermal/trips/cpu_crit";
|
|
cpu6_alert0 = "/thermal-zones/cpu6-thermal/trips/trip-point0";
|
|
cpu6_crit = "/thermal-zones/cpu6-thermal/trips/cpu_crit";
|
|
cpu7_alert0 = "/thermal-zones/cpu7-thermal/trips/trip-point0";
|
|
cpu7_crit = "/thermal-zones/cpu7-thermal/trips/cpu_crit";
|
|
gpu1_alert0 = "/thermal-zones/gpu-thermal-bottom/trips/trip-point0";
|
|
gpu2_alert0 = "/thermal-zones/gpu-thermal-top/trips/trip-point0";
|
|
cluster0_mhm_alert0 = "/thermal-zones/clust0-mhm-thermal/trips/trip-point0";
|
|
cluster1_mhm_alert0 = "/thermal-zones/clust1-mhm-thermal/trips/trip-point0";
|
|
cluster1_l2_alert0 = "/thermal-zones/cluster1-l2-thermal/trips/trip-point0";
|
|
modem_alert0 = "/thermal-zones/modem-thermal/trips/trip-point0";
|
|
mem_alert0 = "/thermal-zones/mem-thermal/trips/trip-point0";
|
|
wlan_alert0 = "/thermal-zones/wlan-thermal/trips/trip-point0";
|
|
q6_dsp_alert0 = "/thermal-zones/q6-dsp-thermal/trips/trip-point0";
|
|
camera_alert0 = "/thermal-zones/camera-thermal/trips/trip-point0";
|
|
multimedia_alert0 = "/thermal-zones/multimedia-thermal/trips/trip-point0";
|
|
pm8998_alert0 = "/thermal-zones/pm8998/trips/pm8998-alert0";
|
|
pm8998_crit = "/thermal-zones/pm8998/trips/pm8998-crit";
|
|
soc = "/soc";
|
|
gcc = "/soc/clock-controller@100000";
|
|
rpm_msg_ram = "/soc/memory@778000";
|
|
qfprom = "/soc/qfprom@780000";
|
|
qusb2_hstx_trim = "/soc/qfprom@780000/hstx-trim@423a";
|
|
tsens0 = "/soc/thermal@10ab000";
|
|
tsens1 = "/soc/thermal@10ae000";
|
|
anoc1_smmu = "/soc/iommu@1680000";
|
|
anoc2_smmu = "/soc/iommu@16c0000";
|
|
pcie0 = "/soc/pci@1c00000";
|
|
pciephy = "/soc/phy@1c06000/lane@1c06800";
|
|
ufshc = "/soc/ufshc@1da4000";
|
|
ufsphy = "/soc/phy@1da7000";
|
|
ufsphy_lanes = "/soc/phy@1da7000/lanes@1da7400";
|
|
tcsr_mutex_regs = "/soc/syscon@1f40000";
|
|
tlmm = "/soc/pinctrl@3400000";
|
|
sdc2_clk_on = "/soc/pinctrl@3400000/sdc2_clk_on";
|
|
sdc2_clk_off = "/soc/pinctrl@3400000/sdc2_clk_off";
|
|
sdc2_cmd_on = "/soc/pinctrl@3400000/sdc2_cmd_on";
|
|
sdc2_cmd_off = "/soc/pinctrl@3400000/sdc2_cmd_off";
|
|
sdc2_data_on = "/soc/pinctrl@3400000/sdc2_data_on";
|
|
sdc2_data_off = "/soc/pinctrl@3400000/sdc2_data_off";
|
|
sdc2_cd_on = "/soc/pinctrl@3400000/sdc2_cd_on";
|
|
sdc2_cd_off = "/soc/pinctrl@3400000/sdc2_cd_off";
|
|
blsp1_uart3_on = "/soc/pinctrl@3400000/blsp1_uart3_on";
|
|
touchpad = "/soc/pinctrl@3400000/touchpad";
|
|
remoteproc_mss = "/soc/remoteproc@4080000";
|
|
gpucc = "/soc/clock-controller@5065000";
|
|
remoteproc_slpi = "/soc/remoteproc@5800000";
|
|
stm = "/soc/stm@6002000";
|
|
stm_out = "/soc/stm@6002000/out-ports/port/endpoint";
|
|
funnel1 = "/soc/funnel@6041000";
|
|
funnel0_out = "/soc/funnel@6041000/out-ports/port/endpoint";
|
|
funnel0_in7 = "/soc/funnel@6041000/in-ports/port@7/endpoint";
|
|
funnel2 = "/soc/funnel@6042000";
|
|
funnel1_out = "/soc/funnel@6042000/out-ports/port/endpoint";
|
|
funnel1_in6 = "/soc/funnel@6042000/in-ports/port@6/endpoint";
|
|
funnel3 = "/soc/funnel@6045000";
|
|
merge_funnel_out = "/soc/funnel@6045000/out-ports/port/endpoint";
|
|
merge_funnel_in0 = "/soc/funnel@6045000/in-ports/port@0/endpoint";
|
|
merge_funnel_in1 = "/soc/funnel@6045000/in-ports/port@1/endpoint";
|
|
replicator1 = "/soc/replicator@6046000";
|
|
replicator_out = "/soc/replicator@6046000/out-ports/port/endpoint";
|
|
replicator_in = "/soc/replicator@6046000/in-ports/port/endpoint";
|
|
etf = "/soc/etf@6047000";
|
|
etf_out = "/soc/etf@6047000/out-ports/port/endpoint";
|
|
etf_in = "/soc/etf@6047000/in-ports/port/endpoint";
|
|
etr = "/soc/etr@6048000";
|
|
etr_in = "/soc/etr@6048000/in-ports/port/endpoint";
|
|
etm1 = "/soc/etm@7840000";
|
|
etm0_out = "/soc/etm@7840000/out-ports/port/endpoint";
|
|
etm2 = "/soc/etm@7940000";
|
|
etm1_out = "/soc/etm@7940000/out-ports/port/endpoint";
|
|
etm3 = "/soc/etm@7a40000";
|
|
etm2_out = "/soc/etm@7a40000/out-ports/port/endpoint";
|
|
etm4 = "/soc/etm@7b40000";
|
|
etm3_out = "/soc/etm@7b40000/out-ports/port/endpoint";
|
|
funnel4 = "/soc/funnel@7b60000";
|
|
apss_funnel_out = "/soc/funnel@7b60000/out-ports/port/endpoint";
|
|
apss_funnel_in0 = "/soc/funnel@7b60000/in-ports/port@0/endpoint";
|
|
apss_funnel_in1 = "/soc/funnel@7b60000/in-ports/port@1/endpoint";
|
|
apss_funnel_in2 = "/soc/funnel@7b60000/in-ports/port@2/endpoint";
|
|
apss_funnel_in3 = "/soc/funnel@7b60000/in-ports/port@3/endpoint";
|
|
apss_funnel_in4 = "/soc/funnel@7b60000/in-ports/port@4/endpoint";
|
|
apss_funnel_in5 = "/soc/funnel@7b60000/in-ports/port@5/endpoint";
|
|
apss_funnel_in6 = "/soc/funnel@7b60000/in-ports/port@6/endpoint";
|
|
apss_funnel_in7 = "/soc/funnel@7b60000/in-ports/port@7/endpoint";
|
|
funnel5 = "/soc/funnel@7b70000";
|
|
apss_merge_funnel_out = "/soc/funnel@7b70000/out-ports/port/endpoint";
|
|
apss_merge_funnel_in = "/soc/funnel@7b70000/in-ports/port/endpoint";
|
|
etm5 = "/soc/etm@7c40000";
|
|
etm4_out = "/soc/etm@7c40000/port/endpoint";
|
|
etm6 = "/soc/etm@7d40000";
|
|
etm5_out = "/soc/etm@7d40000/port/endpoint";
|
|
etm7 = "/soc/etm@7e40000";
|
|
etm6_out = "/soc/etm@7e40000/port/endpoint";
|
|
etm8 = "/soc/etm@7f40000";
|
|
etm7_out = "/soc/etm@7f40000/port/endpoint";
|
|
spmi_bus = "/soc/spmi@800f000";
|
|
pm8998_lsid0 = "/soc/spmi@800f000/pmic@0";
|
|
pm8998_pon = "/soc/spmi@800f000/pmic@0/pon@800";
|
|
pm8998_pwrkey = "/soc/spmi@800f000/pmic@0/pon@800/pwrkey";
|
|
pm8998_temp = "/soc/spmi@800f000/pmic@0/temp-alarm@2400";
|
|
pm8998_coincell = "/soc/spmi@800f000/pmic@0/coincell@2800";
|
|
pm8998_adc = "/soc/spmi@800f000/pmic@0/adc@3100";
|
|
pm8998_gpio = "/soc/spmi@800f000/pmic@0/gpios@c000";
|
|
pm8998_lsid1 = "/soc/spmi@800f000/pmic@1";
|
|
pm8005_lsid0 = "/soc/spmi@800f000/pmic@4";
|
|
pm8005_gpio = "/soc/spmi@800f000/pmic@4/gpios@c000";
|
|
pm8005_lsid1 = "/soc/spmi@800f000/pmic@5";
|
|
pm8005_s1 = "/soc/spmi@800f000/pmic@5/pm8005-regulators/s1";
|
|
usb3 = "/soc/usb@a8f8800";
|
|
usb3_dwc3 = "/soc/usb@a8f8800/dwc3@a800000";
|
|
usb3phy = "/soc/phy@c010000";
|
|
usb1_ssphy = "/soc/phy@c010000/lane@c010200";
|
|
qusb2phy = "/soc/phy@c012000";
|
|
sdhc2 = "/soc/sdhci@c0a4900";
|
|
blsp1_dma = "/soc/dma@c144000";
|
|
blsp1_uart3 = "/soc/serial@c171000";
|
|
blsp1_i2c1 = "/soc/i2c@c175000";
|
|
blsp1_i2c2 = "/soc/i2c@c176000";
|
|
blsp1_i2c3 = "/soc/i2c@c177000";
|
|
blsp1_i2c4 = "/soc/i2c@c178000";
|
|
blsp1_i2c5 = "/soc/i2c@c179000";
|
|
blsp1_i2c6 = "/soc/i2c@c17a000";
|
|
blsp2_uart1 = "/soc/serial@c1b0000";
|
|
blsp2_i2c0 = "/soc/i2c@c1b5000";
|
|
blsp2_i2c1 = "/soc/i2c@c1b6000";
|
|
blsp2_i2c2 = "/soc/i2c@c1b7000";
|
|
blsp2_i2c3 = "/soc/i2c@c1b8000";
|
|
blsp2_i2c4 = "/soc/i2c@c1b9000";
|
|
blsp2_i2c5 = "/soc/i2c@c1ba000";
|
|
remoteproc_adsp = "/soc/remoteproc@17300000";
|
|
apcs_glb = "/soc/mailbox@17911000";
|
|
intc = "/soc/interrupt-controller@17a00000";
|
|
wifi = "/soc/wifi@18800000";
|
|
vph_pwr = "/vph-pwr-regulator";
|
|
};
|
|
};
|