324 lines
9 KiB
C
Executable file
324 lines
9 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019-2020 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos CP interface
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*/
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#ifndef _DT_BINDINGS_EXYNOS_CPIF_H
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#define _DT_BINDINGS_EXYNOS_CPIF_H
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/* CP model */
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#define SEC_S5000AP 0
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#define SEC_S5100 1
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#define MODEM_TYPE_DUMMY 2
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#define MAX_MODEM_TYPE 3
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/* CP protocol */
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#define PROTOCOL_SIPC 0
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#define PROTOCOL_SIT 1
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#define MAX_PROTOCOL 2
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/* SIPC version */
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#define NO_SIPC_VER 0
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#define SIPC_VER_40 40
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#define SIPC_VER_41 41
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#define SIPC_VER_42 42
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#define SIPC_VER_50 50
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#define MAX_SIPC_VER 51
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/* IPC device format */
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#define IPC_FMT 0
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#define IPC_RAW 1
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#define IPC_RFS 2
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#define IPC_MULTI_RAW 3
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#define IPC_BOOT 4
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#define IPC_DUMP 5
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#define IPC_CMD 6
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#define IPC_DEBUG 7
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#define MAX_DEV_FORMAT 8
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/* Link device type */
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#define LINKDEV_SHMEM 0
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#define LINKDEV_PCIE 1
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#define LINKDEV_UNDEFINED 2
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#define LINKDEV_MAX 3
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/* Interrupt type */
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#define INTERRUPT_MAILBOX 0
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#define INTERRUPT_GPIO 1
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#define INTERRUPT_MAX 2
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/* Control msg type */
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#define CMSG_TYPE_NONE 0
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#define MAILBOX_SR 1
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#define DRAM_V1 2
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#define DRAM_V2 3
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#define GPIO 4
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#define MAX_CMSG_TYPE 5
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/* Mailbox interrupt */
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#define CP_MBOX_IRQ_IDX_0 0
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#define CP_MBOX_IRQ_IDX_1 1
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#define CP_MBOX_IRQ_IDX_2 2
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#define CP_MBOX_IRQ_IDX_3 3
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#define CP_MBOX_IRQ_IDX_4 4
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#define MAX_CP_MBOX_IRQ_IDX 5
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/* PCIe MSI interrupt */
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#define PCIE_CP_IRQ_IDX_0 0
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#define PCIE_CP_IRQ_IDX_1 1
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#define PCIE_CP_IRQ_IDX_2 2
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#define PCIE_CP_IRQ_IDX_3 3
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#define PCIE_CP_IRQ_IDX_4 4
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#define PCIE_CP_IRQ_IDX_5 5
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#define MAX_PCIE_CP_IRQ_IDX 6
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/* IO device type */
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#define IODEV_BOOTDUMP 0
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#define IODEV_IPC 1
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#define IODEV_NET 2
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#define IODEV_DUMMY 3
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/* Shared memory index */
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#define SHMEM_CP 0
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#define SHMEM_VSS 1
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#define SHMEM_L2B 2
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#define SHMEM_IPC 3
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#define SHMEM_VPA 4
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#define SHMEM_BTL 5
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#define SHMEM_BTL_EXT 6
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#define SHMEM_PKTPROC 7
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#define SHMEM_PKTPROC_UL 8
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#define SHMEM_ZMC 9
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#define SHMEM_C2C 10
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#define SHMEM_MSI 11
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#define SHMEM_DDM 12
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#define MAX_CP_SHMEM 13
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/* TPMON measure */
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#define TPMON_MEASURE_TP 0
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#define TPMON_MEASURE_NETDEV_Q 1
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#define TPMON_MEASURE_PKTPROC_DL_Q 2
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#define TPMON_MEASURE_DIT_SRC_Q 3
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/* TPMON target */
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#define TPMON_TARGET_RPS 0
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#define TPMON_TARGET_GRO 1
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#define TPMON_TARGET_MIF 2
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#define TPMON_TARGET_PCIE_LOW_POWER 3
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#define TPMON_TARGET_IRQ_MBOX 4
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#define TPMON_TARGET_IRQ_PCIE 5
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#define TPMON_TARGET_IRQ_DIT 6
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#define TPMON_TARGET_INT_FREQ 7
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#define TPMON_TARGET_BTS 8
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#define TPMON_TARGET_CPU_CL0 9
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#define TPMON_TARGET_CPU_CL1 10
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#define TPMON_TARGET_CPU_CL2 11
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#define TPMON_TARGET_MIF_MAX 12
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#define TPMON_TARGET_INT_FREQ_MAX 13
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#define TPMON_TARGET_CPU_CL0_MAX 14
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#define TPMON_TARGET_CPU_CL1_MAX 15
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#define TPMON_TARGET_CPU_CL2_MAX 16
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#define MAX_TPMON_TARGET 17
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/* Protocol for TPMON */
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#define TPMON_PROTO_ALL 0
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#define TPMON_PROTO_TCP 1
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#define TPMON_PROTO_UDP 2
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#define TPMON_PROTO_OTHERS 3
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/* SRINFO */
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#define SRINFO_OFFSET 0x200 /* TODO: remove this offset */
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#define SRINFO_SBD_OFFSET 0xF800
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#define SRINFO_SIZE 0x800
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/* Link device attr */
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#define LINK_ATTR_SBD_IPC (0x1 << 0) /* IPC over SBD (from MIPI-LLI) */
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#define LINK_ATTR_IPC_ALIGNED (0x1 << 1) /* IPC with 4-bytes alignment */
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#define LINK_ATTR_IOSM_MESSAGE (0x1 << 2) /* IOSM message */
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#define LINK_ATTR_DPRAM_MAGIC (0x1 << 3) /* DPRAM-style magic code validation */
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#define LINK_ATTR_SBD_BOOT (0x1 << 4) /* BOOT over SBD */
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#define LINK_ATTR_SBD_DUMP (0x1 << 5) /* DUMP over SBD */
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#define LINK_ATTR_MEM_BOOT (0x1 << 6) /* BOOT over legacy memory-type I/F */
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#define LINK_ATTR_MEM_DUMP (0x1 << 7) /* DUMP over legacy memory-type I/F */
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#define LINK_ATTR_BOOT_ALIGNED (0x1 << 8) /* BOOT with 4-bytes alignment */
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#define LINK_ATTR_DUMP_ALIGNED (0x1 << 9) /* DUMP with 4-bytes alignment */
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#define LINK_ATTR_XMIT_BTDLR (0x1 << 10) /* Used to download CP bootloader */
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#define LINK_ATTR_XMIT_BTDLR_SPI (0x1 << 11) /* Download CP bootloader by SPI */
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#define LINK_ATTR_XMIT_BTDLR_PCIE (0x1 << 12) /* CP ROM booting via PCIe */
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/* IO device attr */
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#define IO_ATTR_SIPC4 (0x1 << 0)
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#define IO_ATTR_SIPC5 (0x1 << 1)
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#define IO_ATTR_CDC_NCM (0x1 << 2)
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#define IO_ATTR_MULTIFMT (0x1 << 3)
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#define IO_ATTR_HANDOVER (0x1 << 4)
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#define IO_ATTR_LEGACY_RFS (0x1 << 5)
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#define IO_ATTR_RX_FRAGMENT (0x1 << 6)
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#define IO_ATTR_SBD_IPC (0x1 << 7) /* IPC using SBD designed from MIPI-LLI */
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#define IO_ATTR_NO_LINK_HEADER (0x1 << 8) /* Link-layer header is not needed */
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#define IO_ATTR_NO_CHECK_MAXQ (0x1 << 9) /* no need to check rxq overflow condition */
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#define IO_ATTR_DUALSIM (0x1 << 10) /* support Dual SIM */
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#define IO_ATTR_OPTION_REGION (0x1 << 11) /* region & operator info */
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/* Deprecated */
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#define IO_ATTR_ZEROCOPY (0x1 << 12) /* support SW zerocopy on SBD */
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#define IO_ATTR_MULTI_CH (0x1 << 13) /* Multi channel IO device */
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/* SIPC channel ID */
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#define SIPC_CH_ID_RAW_0 0
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#define SIPC_CH_ID_CS_VT_DATA 1
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#define SIPC_CH_ID_CS_VT_CONTROL 2
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#define SIPC_CH_ID_CS_VT_AUDIO 3
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#define SIPC_CH_ID_CS_VT_VIDEO 4
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#define SIPC_CH_ID_RAW_5 5
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#define SIPC_CH_ID_RAW_6 6
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#define SIPC_CH_ID_CDMA_DATA 7
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#define SIPC_CH_ID_PCM_DATA 8
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#define SIPC_CH_ID_TRANSFER_SCREEN 9
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#define SIPC_CH_ID_PDP_0 10
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#define SIPC_CH_ID_PDP_1 11
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#define SIPC_CH_ID_PDP_2 12
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#define SIPC_CH_ID_PDP_3 13
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#define SIPC_CH_ID_PDP_4 14
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#define SIPC_CH_ID_PDP_5 15
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#define SIPC_CH_ID_PDP_6 16
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#define SIPC_CH_ID_PDP_7 17
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#define SIPC_CH_ID_PDP_8 18
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#define SIPC_CH_ID_PDP_9 19
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#define SIPC_CH_ID_PDP_10 20
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#define SIPC_CH_ID_PDP_11 21
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#define SIPC_CH_ID_PDP_12 22
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#define SIPC_CH_ID_PDP_13 23
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#define SIPC_CH_ID_PDP_14 24
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#define SIPC_CH_ID_BT_DUN 25
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#define SIPC_CH_ID_CIQ_DATA 26
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#define SIPC_CH_ID_PDP_17 27
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#define SIPC_CH_ID_CPLOG1 28
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#define SIPC_CH_ID_CPLOG2 29
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#define SIPC_CH_ID_LOOPBACK1 30
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#define SIPC_CH_ID_LOOPBACK2 31
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#define SIPC_CH_ID_SMD4 33
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#define SIPC_CH_ID_CASS 35
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/* 0 ... 30 */
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#define SIPC_CH_EX_ID_PDP_0 181
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#define SIPC_CH_EX_ID_PDP_30 (SIPC_CH_EX_ID_PDP_0 + 30)
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#define SIPC_CH_EX_ID_PDP_MAX SIPC_CH_EX_ID_PDP_30
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#define SIPC5_CH_ID_BOOT_0 215
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#define SIPC5_CH_ID_BOOT_1 216
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#define SIPC5_CH_ID_BOOT_2 217
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#define SIPC5_CH_ID_BOOT_3 218
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#define SIPC5_CH_ID_BOOT_4 219
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#define SIPC5_CH_ID_BOOT_5 220
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#define SIPC5_CH_ID_BOOT_6 221
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#define SIPC5_CH_ID_BOOT_7 222
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#define SIPC5_CH_ID_BOOT_8 223
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#define SIPC5_CH_ID_BOOT_9 224
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#define SIPC5_CH_ID_DUMP_0 225
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#define SIPC5_CH_ID_DUMP_1 226
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#define SIPC5_CH_ID_DUMP_2 227
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#define SIPC5_CH_ID_DUMP_3 228
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#define SIPC5_CH_ID_DUMP_4 229
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#define SIPC5_CH_ID_DUMP_5 230
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#define SIPC5_CH_ID_DUMP_6 231
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#define SIPC5_CH_ID_DUMP_7 232
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#define SIPC5_CH_ID_DUMP_8 233
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#define SIPC5_CH_ID_DUMP_9 234
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#define SIPC5_CH_ID_FMT_0 235
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#define SIPC5_CH_ID_FMT_1 236
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#define SIPC5_CH_ID_FMT_2 237
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#define SIPC5_CH_ID_FMT_3 238
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#define SIPC5_CH_ID_FMT_4 239
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#define SIPC5_CH_ID_FMT_5 240
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#define SIPC5_CH_ID_FMT_6 241
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#define SIPC5_CH_ID_FMT_7 242
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#define SIPC5_CH_ID_FMT_8 243
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#define SIPC5_CH_ID_FMT_9 244
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#define SIPC5_CH_ID_RFS_0 245
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#define SIPC5_CH_ID_RFS_1 246
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#define SIPC5_CH_ID_RFS_2 247
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#define SIPC5_CH_ID_RFS_3 248
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#define SIPC5_CH_ID_RFS_4 249
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#define SIPC5_CH_ID_RFS_5 250
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#define SIPC5_CH_ID_RFS_6 251
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#define SIPC5_CH_ID_RFS_7 252
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#define SIPC5_CH_ID_RFS_8 253
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#define SIPC5_CH_ID_RFS_9 254
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#define SIPC5_CH_ID_MAX 255
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/* SIT channel ID */
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#define EXYNOS_CH_ID_MULTIPDP 0
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#define EXYNOS_CH_ID_PDP_0 1
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#define EXYNOS_CH_ID_PDP_1 2
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#define EXYNOS_CH_ID_PDP_2 3
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#define EXYNOS_CH_ID_PDP_3 4
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#define EXYNOS_CH_ID_PDP_4 5
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#define EXYNOS_CH_ID_PDP_5 6
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#define EXYNOS_CH_ID_PDP_6 7
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#define EXYNOS_CH_ID_PDP_7 8
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#define EXYNOS_CH_ID_PDP_8 9
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#define EXYNOS_CH_ID_PDP_9 10
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#define EXYNOS_CH_ID_PDP_10 11
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#define EXYNOS_CH_ID_PDP_11 12
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#define EXYNOS_CH_ID_PDP_12 13
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#define EXYNOS_CH_ID_PDP_13 14
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#define EXYNOS_CH_ID_PDP_14 15
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#define EXYNOS_CH_ID_PDP_15 16
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#define EXYNOS_CH_ID_BT_DUN 21 /* umts_router */
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#define EXYNOS_CH_ID_UTS 23 /* umts_atc0 */
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#define EXYNOS_CH_ID_EMBMS_0 30
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#define EXYNOS_CH_ID_EMBMS_1 31
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#define EXYNOS_CH_ID_RFS_0 41 /*umts_rfs0 */
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#define EXYNOS_CH_ID_RFS_1 42
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#define EXYNOS_CH_ID_RFS_2 43
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#define EXYNOS_CH_ID_RFS_3 44
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#define EXYNOS_CH_ID_RFS_4 45
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#define EXYNOS_CH_ID_RFS_5 46
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#define EXYNOS_CH_ID_RFS_6 47
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#define EXYNOS_CH_ID_RFS_7 48
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#define EXYNOS_CH_ID_RFS_8 49
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#define EXYNOS_CH_ID_RFS_9 50
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#define EXYNOS_CH_ID_CPLOG 81 /* umts_dm0 */
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#define EXYNOS_CH_ID_LOOPBACK 82 /* umts_loopback */
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#define EXYNOS_CH_ID_RCS_0 91
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#define EXYNOS_CH_ID_RCS_1 92
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#define EXYNOS_CH_ID_WFS_0 93 /* umts_wfc0 */
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#define EXYNOS_CH_ID_WFS_1 94 /* umts_wfc1 */
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/* 0 ... 30 */
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#define EXYNOS_CH_EX_ID_PDP_0 181
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#define EXYNOS_CH_EX_ID_PDP_30 (EXYNOS_CH_EX_ID_PDP_0 + 30)
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#define EXYNOS_CH_EX_ID_PDP_MAX EXYNOS_CH_EX_ID_PDP_30
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#define EXYNOS_CH_ID_BOOT 241
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#define EXYNOS_CH_ID_DUMP 242
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#define EXYNOS_CH_ID_FMT_0 245 /* umts_ipc0 */
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#define EXYNOS_CH_ID_FMT_1 246 /* umts_ipc1 */
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#define EXYNOS_CH_ID_MAX 255
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/* SIPC/SIT common */
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#define IOD_CH_ID_MAX 256
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#endif /* _DT_BINDINGS_EXYNOS_CPIF_H */
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