10169 lines
1,023 KiB
C
Executable file
10169 lines
1,023 KiB
C
Executable file
#include "../../cmucal.h"
|
|
#include "cmucal-sfr.h"
|
|
|
|
unsigned int cmucal_sfr_block_size = 31;
|
|
struct sfr_block cmucal_sfr_block_list[] = {
|
|
SFR_BLOCK(CMU_AUD, 0x14e00000, 0x8000),
|
|
SFR_BLOCK(CMU_TOP, 0x12900000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL0, 0x10820000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL1, 0x10830000, 0x8000),
|
|
SFR_BLOCK(CMU_DSU, 0x108a0000, 0x8000),
|
|
SFR_BLOCK(CMU_MIF, 0x10400000, 0x8000),
|
|
SFR_BLOCK(CMU_S2D, 0x11b30000, 0x8000),
|
|
SFR_BLOCK(CMU_ALIVE, 0x11800000, 0x8000),
|
|
SFR_BLOCK(CMU_BUSC, 0x14500000, 0x8000),
|
|
SFR_BLOCK(CMU_CHUB, 0x11000000, 0x8000),
|
|
SFR_BLOCK(CMU_CHUBVTS, 0x11600000, 0x8000),
|
|
SFR_BLOCK(CMU_CMGP, 0x11400000, 0x8000),
|
|
SFR_BLOCK(CMU_CORE, 0x12800000, 0x8000),
|
|
SFR_BLOCK(CMU_USB, 0x13000000, 0x8000),
|
|
SFR_BLOCK(CMU_VTS, 0x11700000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL0_GLB, 0x108b0000, 0x8000),
|
|
SFR_BLOCK(CMU_CSIS, 0x15000000, 0x8000),
|
|
SFR_BLOCK(CMU_DPU, 0x14800000, 0x8000),
|
|
SFR_BLOCK(CMU_G3D, 0x10200000, 0x8000),
|
|
SFR_BLOCK(CMU_HSI, 0x13400000, 0x8000),
|
|
SFR_BLOCK(CMU_ISP, 0x15400000, 0x8000),
|
|
SFR_BLOCK(CMU_M2M, 0x12c00000, 0x8000),
|
|
SFR_BLOCK(CMU_MCSC, 0x15600000, 0x8000),
|
|
SFR_BLOCK(CMU_MFC, 0x12e00000, 0x8000),
|
|
SFR_BLOCK(CMU_NPU0, 0x10a00000, 0x8000),
|
|
SFR_BLOCK(CMU_NPUS, 0x10b00000, 0x8000),
|
|
SFR_BLOCK(CMU_PERI, 0x10030000, 0x8000),
|
|
SFR_BLOCK(CMU_TAA, 0x15500000, 0x8000),
|
|
SFR_BLOCK(CMU_TNR, 0x15300000, 0x8000),
|
|
SFR_BLOCK(CMU_GNSS, 0x13e00000, 0x7000),
|
|
SFR_BLOCK(CMU_MODEM, 0x0, 0x7000),
|
|
};
|
|
|
|
unsigned int dbg_offset = 0x4000;
|
|
unsigned int cmucal_sfr_size = 2458;
|
|
struct sfr cmucal_sfr_list[] = {
|
|
SFR(PLL_LOCKTIME_PLL_AUD, 0x0, CMU_AUD),
|
|
SFR(PLL_CON3_PLL_AUD, 0x10c, CMU_AUD),
|
|
SFR(PLL_CON9_PLL_AUD, 0x124, CMU_AUD),
|
|
SFR(PLL_CON8_PLL_AUD, 0x120, CMU_AUD),
|
|
SFR(PLL_CON4_PLL_AUD, 0x110, CMU_AUD),
|
|
SFR(PLL_CON5_PLL_AUD, 0x114, CMU_AUD),
|
|
SFR(DBG_NFO_PLL_AUD, 0x4100, CMU_AUD),
|
|
SFR(PLL_CON0_PLL_AUD, 0x100, CMU_AUD),
|
|
SFR(PLL_CON1_PLL_AUD, 0x104, CMU_AUD),
|
|
SFR(PLL_CON2_PLL_AUD, 0x108, CMU_AUD),
|
|
SFR(PLL_CON6_PLL_AUD, 0x118, CMU_AUD),
|
|
SFR(PLL_LOCKTIME_REG_PLL_AUD, 0x80, CMU_AUD),
|
|
SFR(PLL_CON7_PLL_AUD, 0x11c, CMU_AUD),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED1, 0xc, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED1, 0x1cc, CMU_TOP),
|
|
SFR(PLL_CON9_PLL_SHARED1, 0x1e4, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_SHARED1, 0x1e0, CMU_TOP),
|
|
SFR(PLL_CON4_PLL_SHARED1, 0x1d0, CMU_TOP),
|
|
SFR(PLL_CON5_PLL_SHARED1, 0x1d4, CMU_TOP),
|
|
SFR(DBG_NFO_PLL_SHARED1, 0x41c0, CMU_TOP),
|
|
SFR(PLL_CON0_PLL_SHARED1, 0x1c0, CMU_TOP),
|
|
SFR(PLL_CON1_PLL_SHARED1, 0x1c4, CMU_TOP),
|
|
SFR(PLL_CON2_PLL_SHARED1, 0x1c8, CMU_TOP),
|
|
SFR(PLL_CON6_PLL_SHARED1, 0x1d8, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_REG_PLL_SHARED1, 0x8c, CMU_TOP),
|
|
SFR(PLL_CON7_PLL_SHARED1, 0x1dc, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED0, 0x8, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED0, 0x18c, CMU_TOP),
|
|
SFR(PLL_CON9_PLL_SHARED0, 0x1a4, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_SHARED0, 0x1a0, CMU_TOP),
|
|
SFR(PLL_CON4_PLL_SHARED0, 0x190, CMU_TOP),
|
|
SFR(PLL_CON5_PLL_SHARED0, 0x194, CMU_TOP),
|
|
SFR(PLL_CON1_PLL_SHARED0, 0x184, CMU_TOP),
|
|
SFR(DBG_NFO_PLL_SHARED0, 0x4180, CMU_TOP),
|
|
SFR(PLL_CON0_PLL_SHARED0, 0x180, CMU_TOP),
|
|
SFR(PLL_CON2_PLL_SHARED0, 0x188, CMU_TOP),
|
|
SFR(PLL_CON6_PLL_SHARED0, 0x198, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_REG_PLL_SHARED0, 0x88, CMU_TOP),
|
|
SFR(PLL_CON7_PLL_SHARED0, 0x19c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_G3D, 0x0, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_G3D, 0x10c, CMU_TOP),
|
|
SFR(PLL_CON9_PLL_G3D, 0x124, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_G3D, 0x120, CMU_TOP),
|
|
SFR(PLL_CON4_PLL_G3D, 0x110, CMU_TOP),
|
|
SFR(PLL_CON5_PLL_G3D, 0x114, CMU_TOP),
|
|
SFR(DBG_NFO_PLL_G3D, 0x4100, CMU_TOP),
|
|
SFR(PLL_CON0_PLL_G3D, 0x100, CMU_TOP),
|
|
SFR(PLL_CON1_PLL_G3D, 0x104, CMU_TOP),
|
|
SFR(PLL_CON2_PLL_G3D, 0x108, CMU_TOP),
|
|
SFR(PLL_CON6_PLL_G3D, 0x118, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_REG_PLL_G3D, 0x80, CMU_TOP),
|
|
SFR(PLL_CON7_PLL_G3D, 0x11c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_MMC, 0x4, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_MMC, 0x14c, CMU_TOP),
|
|
SFR(PLL_CON9_PLL_MMC, 0x164, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_MMC, 0x160, CMU_TOP),
|
|
SFR(PLL_CON4_PLL_MMC, 0x150, CMU_TOP),
|
|
SFR(PLL_CON5_PLL_MMC, 0x154, CMU_TOP),
|
|
SFR(DBG_NFO_PLL_MMC, 0x4140, CMU_TOP),
|
|
SFR(PLL_CON0_PLL_MMC, 0x140, CMU_TOP),
|
|
SFR(PLL_CON1_PLL_MMC, 0x144, CMU_TOP),
|
|
SFR(PLL_CON2_PLL_MMC, 0x148, CMU_TOP),
|
|
SFR(PLL_CON6_PLL_MMC, 0x158, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_REG_PLL_MMC, 0x84, CMU_TOP),
|
|
SFR(PLL_CON7_PLL_MMC, 0x15c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED2, 0x10, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED2, 0x20c, CMU_TOP),
|
|
SFR(PLL_CON9_PLL_SHARED2, 0x224, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_SHARED2, 0x220, CMU_TOP),
|
|
SFR(PLL_CON4_PLL_SHARED2, 0x210, CMU_TOP),
|
|
SFR(PLL_CON5_PLL_SHARED2, 0x214, CMU_TOP),
|
|
SFR(DBG_NFO_PLL_SHARED2, 0x4200, CMU_TOP),
|
|
SFR(PLL_CON0_PLL_SHARED2, 0x200, CMU_TOP),
|
|
SFR(PLL_CON1_PLL_SHARED2, 0x204, CMU_TOP),
|
|
SFR(PLL_CON2_PLL_SHARED2, 0x208, CMU_TOP),
|
|
SFR(PLL_CON6_PLL_SHARED2, 0x218, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_REG_PLL_SHARED2, 0x90, CMU_TOP),
|
|
SFR(PLL_CON7_PLL_SHARED2, 0x21c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0, CMU_CPUCL0),
|
|
SFR(PLL_CON3_PLL_CPUCL0, 0x10c, CMU_CPUCL0),
|
|
SFR(PLL_CON9_PLL_CPUCL0, 0x124, CMU_CPUCL0),
|
|
SFR(PLL_CON8_PLL_CPUCL0, 0x120, CMU_CPUCL0),
|
|
SFR(PLL_CON4_PLL_CPUCL0, 0x110, CMU_CPUCL0),
|
|
SFR(PLL_CON5_PLL_CPUCL0, 0x114, CMU_CPUCL0),
|
|
SFR(DBG_NFO_PLL_CPUCL0, 0x4100, CMU_CPUCL0),
|
|
SFR(PLL_CON0_PLL_CPUCL0, 0x100, CMU_CPUCL0),
|
|
SFR(PLL_CON1_PLL_CPUCL0, 0x104, CMU_CPUCL0),
|
|
SFR(PLL_CON2_PLL_CPUCL0, 0x108, CMU_CPUCL0),
|
|
SFR(PLL_CON6_PLL_CPUCL0, 0x118, CMU_CPUCL0),
|
|
SFR(PLL_LOCKTIME_REG_PLL_CPUCL0, 0x80, CMU_CPUCL0),
|
|
SFR(PLL_CON7_PLL_CPUCL0, 0x11c, CMU_CPUCL0),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0, CMU_CPUCL1),
|
|
SFR(PLL_CON3_PLL_CPUCL1, 0x10c, CMU_CPUCL1),
|
|
SFR(PLL_CON4_PLL_CPUCL1, 0x110, CMU_CPUCL1),
|
|
SFR(DBG_NFO_PLL_CPUCL1, 0x4100, CMU_CPUCL1),
|
|
SFR(PLL_CON0_PLL_CPUCL1, 0x100, CMU_CPUCL1),
|
|
SFR(PLL_CON1_PLL_CPUCL1, 0x104, CMU_CPUCL1),
|
|
SFR(PLL_CON2_PLL_CPUCL1, 0x108, CMU_CPUCL1),
|
|
SFR(PLL_CON6_PLL_CPUCL1, 0x118, CMU_CPUCL1),
|
|
SFR(PLL_LOCKTIME_REG_PLL_CPUCL1, 0x80, CMU_CPUCL1),
|
|
SFR(PLL_LOCKTIME_PLL_DSU, 0x0, CMU_DSU),
|
|
SFR(PLL_CON3_PLL_DSU, 0x10c, CMU_DSU),
|
|
SFR(PLL_CON9_PLL_DSU, 0x124, CMU_DSU),
|
|
SFR(PLL_CON8_PLL_DSU, 0x120, CMU_DSU),
|
|
SFR(PLL_CON4_PLL_DSU, 0x110, CMU_DSU),
|
|
SFR(PLL_CON5_PLL_DSU, 0x114, CMU_DSU),
|
|
SFR(DBG_NFO_PLL_DSU, 0x4100, CMU_DSU),
|
|
SFR(PLL_CON0_PLL_DSU, 0x100, CMU_DSU),
|
|
SFR(PLL_CON1_PLL_DSU, 0x104, CMU_DSU),
|
|
SFR(PLL_CON2_PLL_DSU, 0x108, CMU_DSU),
|
|
SFR(PLL_CON6_PLL_DSU, 0x118, CMU_DSU),
|
|
SFR(PLL_LOCKTIME_REG_PLL_DSU, 0x80, CMU_DSU),
|
|
SFR(PLL_CON7_PLL_DSU, 0x11c, CMU_DSU),
|
|
SFR(PLL_LOCKTIME_PLL_MIF, 0x0, CMU_MIF),
|
|
SFR(PLL_CON3_PLL_MIF, 0x10c, CMU_MIF),
|
|
SFR(PLL_CON4_PLL_MIF, 0x110, CMU_MIF),
|
|
SFR(DBG_NFO_PLL_MIF, 0x4100, CMU_MIF),
|
|
SFR(PLL_CON0_PLL_MIF, 0x100, CMU_MIF),
|
|
SFR(PLL_CON1_PLL_MIF, 0x104, CMU_MIF),
|
|
SFR(PLL_CON2_PLL_MIF, 0x108, CMU_MIF),
|
|
SFR(PLL_LOCKTIME_PLL_MIF_S2D, 0x0, CMU_S2D),
|
|
SFR(PLL_CON3_PLL_MIF_S2D, 0x10c, CMU_S2D),
|
|
SFR(PLL_CON4_PLL_MIF_S2D, 0x110, CMU_S2D),
|
|
SFR(DBG_NFO_PLL_MIF_S2D, 0x4100, CMU_S2D),
|
|
SFR(PLL_CON0_PLL_MIF_S2D, 0x100, CMU_S2D),
|
|
SFR(PLL_CON1_PLL_MIF_S2D, 0x104, CMU_S2D),
|
|
SFR(PLL_CON2_PLL_MIF_S2D, 0x108, CMU_S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS, 0x1010, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMGP_BUS, 0x5010, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_BUS, 0x101c, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_BUS, 0x501c, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI, 0x1014, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMGP_PERI, 0x5014, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC, 0x1028, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_I3C_PMIC, 0x5028, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS, 0x1004, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS, 0x5004, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART, 0x1020, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_DBGCORE_UART, 0x5020, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AP2GNSS, 0x1000, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_AP2GNSS, 0x5000, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI, 0x1008, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUB_PERI, 0x5008, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_USI0, 0x102c, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_USI0, 0x502c, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_I2C, 0x1024, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_I2C, 0x5024, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0x102c, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF3, 0x502c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x1028, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF2, 0x5028, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0x1024, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF1, 0x5024, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x1020, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF0, 0x5020, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x100c, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_CPU, 0x500c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_FM, 0x1018, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_FM, 0x5018, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0x1030, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF4, 0x5030, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0x1034, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF5, 0x5034, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0x1038, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_UAIF6, 0x5038, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_DSIF, 0x1014, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_DSIF, 0x5014, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL, 0x1010, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_CPU_PLL, 0x5010, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_BUS, 0x1004, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_BUS, 0x5004, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_PCMC, 0x101c, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_PCMC, 0x501c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_BUSC_CMUREF, 0x1000, CMU_BUSC),
|
|
SFR(DBG_NFO_MUX_BUSC_CMUREF, 0x5000, CMU_BUSC),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_TIMER, 0x1008, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_TIMER, 0x5008, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI0, 0x100c, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_USI0, 0x500c, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI1, 0x1010, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_USI1, 0x5010, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI2, 0x1014, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_USI2, 0x5014, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_I2C, 0x1004, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_I2C, 0x5004, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI3, 0x1018, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_USI3, 0x5018, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_BUS, 0x1000, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_BUS, 0x5000, CMU_CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS, 0x1000, CMU_CHUBVTS),
|
|
SFR(DBG_NFO_MUX_CLK_CHUBVTS_BUS, 0x5000, CMU_CHUBVTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0x1004, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_I2C, 0x5004, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI0, 0x100c, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_USI0, 0x500c, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI4, 0x101c, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_USI4, 0x501c, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I3C, 0x1008, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_I3C, 0x5008, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_BUS, 0x1000, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_BUS, 0x5000, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI1, 0x1010, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_USI1, 0x5010, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI2, 0x1014, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_USI2, 0x5014, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI3, 0x1018, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLK_CMGP_USI3, 0x5018, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0x1080, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MFC_MFC, 0x5080, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0x1030, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_BUS, 0x5030, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x1044, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH, 0x5044, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x1088, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MIF_SWITCH, 0x5088, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS, 0x10a0, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_TAA_BUS, 0x50a0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, 0x1068, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_ISP_BUS, 0x5068, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0x100c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_AUD_CPU, 0x500c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL, 0x106c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_M2M_MSCL, 0x506c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS, 0x1040, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS, 0x5040, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1014, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK0, 0x5014, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x1018, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK1, 0x5018, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x101c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK2, 0x501c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD, 0x1064, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD, 0x5064, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x10b0, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CMU_CMUREF, 0x50b0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0x1094, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_BUS, 0x5094, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS, 0x108c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_NPU0_BUS, 0x508c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS, 0x1004, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_ALIVE_BUS, 0x5004, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0x1060, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_HSI_BUS, 0x5060, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0x1084, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MIF_BUSP, 0x5084, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0x1098, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_IP, 0x5098, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0x1050, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DPU_BUS, 0x5050, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x1048, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH, 0x5048, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_USB_BUS, 0x10a8, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_USB_BUS, 0x50a8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0x10a4, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_TNR_BUS, 0x50a4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD, 0x109c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD, 0x509c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0x102c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMU_BOOST, 0x502c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0x1034, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_G3D, 0x5034, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0x104c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CSIS_BUS, 0x504c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0x1070, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_BUS, 0x5070, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0x1074, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_GDC, 0x5074, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD, 0x10ac, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_USB_USB20DRD, 0x50ac, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS, 0x1090, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_NPUS_BUS, 0x5090, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0x105c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_G3D_SWITCH, 0x505c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0x1038, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_SSS, 0x5038, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0x1010, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_BUSC_BUS, 0x5010, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x1020, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK3, 0x5020, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0x1024, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK4, 0x5024, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_G3D_BUS, 0x1000, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_G3D_BUS, 0x5000, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0x1028, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK5, 0x5028, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, 0x1058, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DSU_SWITCH, 0x5058, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP, 0x103c, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP, 0x503c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM, 0x1054, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DPU_DSIM, 0x5054, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0x1078, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_MCSC, 0x5078, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0x1008, CMU_TOP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_AUD_BUS, 0x5008, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CORE_CMUREF, 0x1004, CMU_CORE),
|
|
SFR(DBG_NFO_MUX_CORE_CMUREF, 0x5004, CMU_CORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CORE_GIC, 0x1000, CMU_CORE),
|
|
SFR(DBG_NFO_MUX_CLK_CORE_GIC, 0x5000, CMU_CORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x1000, CMU_CPUCL0),
|
|
SFR(DBG_NFO_MUX_CLK_CPUCL0_PLL, 0x5000, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL0_CMUREF, 0x1008, CMU_CPUCL0),
|
|
SFR(DBG_NFO_MUX_CPUCL0_CMUREF, 0x5008, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CMU_CPUCL1),
|
|
SFR(DBG_NFO_MUX_CLK_CPUCL1_PLL, 0x5000, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL1_CMUREF, 0x1008, CMU_CPUCL1),
|
|
SFR(DBG_NFO_MUX_CPUCL1_CMUREF, 0x5008, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_DSU_CMUREF, 0x1008, CMU_DSU),
|
|
SFR(DBG_NFO_MUX_DSU_CMUREF, 0x5008, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_PLL, 0x1000, CMU_DSU),
|
|
SFR(DBG_NFO_MUX_CLK_DSU_PLL, 0x5000, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1008, CMU_MIF),
|
|
SFR(DBG_NFO_MUX_MIF_CMUREF, 0x5008, CMU_MIF),
|
|
SFR(CLK_CON_MUX_MUX_CLK_S2D_CORE, 0x1004, CMU_S2D),
|
|
SFR(DBG_NFO_MUX_CLK_S2D_CORE, 0x5004, CMU_S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USB_BUS, 0x1000, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLK_USB_BUS, 0x5000, CMU_USB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USB_USB20DRD, 0x1004, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLK_USB_USB20DRD, 0x5004, CMU_USB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_BUS, 0x1000, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_CLK_VTS_BUS, 0x5000, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_VTS_DMIC_AUD, 0x1008, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_VTS_DMIC_AUD, 0x5008, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_VTS_SERIAL_LIF, 0x100c, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_VTS_SERIAL_LIF, 0x500c, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF, 0x1004, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_CLK_VTS_DMIC_IF, 0x5004, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER, 0x600, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER, 0x604, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_ALIVE_BUS_USER, 0x4600, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLK_RCO_ALIVE_USER, 0x630, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLK_RCO_ALIVE_USER, 0x634, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_RCO_ALIVE_USER, 0x4630, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, 0x610, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, 0x614, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, 0x4610, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLK_ALIVE_TIMER, 0x620, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLK_ALIVE_TIMER, 0x624, CMU_ALIVE),
|
|
SFR(DBG_NFO_MUX_CLK_ALIVE_TIMER, 0x4620, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0x610, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER, 0x614, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLKCMU_AUD_CPU_USER, 0x4610, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER, 0x600, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER, 0x604, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CLKCMU_AUD_BUS_USER, 0x4600, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CP_PCMC_CLK_USER, 0x620, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CP_PCMC_CLK_USER, 0x624, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_CP_PCMC_CLK_USER, 0x4620, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER, 0x600, CMU_BUSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER, 0x604, CMU_BUSC),
|
|
SFR(DBG_NFO_MUX_CLKCMU_BUSC_BUS_USER, 0x4600, CMU_BUSC),
|
|
SFR(PLL_CON0_MUX_CLK_CHUB_BUS_USER, 0x620, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLK_CHUB_BUS_USER, 0x624, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLK_CHUB_BUS_USER, 0x4620, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER, 0x600, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER, 0x604, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUB_PERI_USER, 0x4600, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER, 0x610, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER, 0x614, CMU_CHUB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUB_RCO_USER, 0x4610, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER, 0x600, CMU_CHUBVTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER, 0x604, CMU_CHUBVTS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_USER, 0x4600, CMU_CHUBVTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER, 0x610, CMU_CHUBVTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER, 0x614, CMU_CHUBVTS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CHUBVTS_RCO_USER, 0x4610, CMU_CHUBVTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER, 0x610, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER, 0x614, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMGP_BUS_USER, 0x4610, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER, 0x620, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER, 0x624, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMGP_PERI_USER, 0x4620, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER, 0x630, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER, 0x634, CMU_CMGP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CMGP_RCO_USER, 0x4630, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0x600, CMU_CORE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER, 0x604, CMU_CORE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_BUS_USER, 0x4600, CMU_CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 0x620, CMU_CORE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CORE_G3D_USER, 0x624, CMU_CORE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_G3D_USER, 0x4620, CMU_CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 0x630, CMU_CORE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CORE_SSS_USER, 0x634, CMU_CORE),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CORE_SSS_USER, 0x4630, CMU_CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x610, CMU_CPUCL0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x614, CMU_CPUCL0),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x4610, CMU_CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x610, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x614, CMU_CPUCL0_GLB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x4610, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER, 0x600, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER, 0x604, CMU_CPUCL0_GLB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_USER, 0x4600, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x600, CMU_CPUCL1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x604, CMU_CPUCL1),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x4600, CMU_CPUCL1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER, 0x600, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER, 0x604, CMU_CSIS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_CSIS_BUS_USER, 0x4600, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 0x600, CMU_DPU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPU_BUS_USER, 0x604, CMU_DPU),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DPU_BUS_USER, 0x4600, CMU_DPU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER, 0x610, CMU_DPU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER, 0x614, CMU_DPU),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DPU_DSIM_USER, 0x4610, CMU_DPU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER, 0x600, CMU_DSU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER, 0x604, CMU_DSU),
|
|
SFR(DBG_NFO_MUX_CLKCMU_DSU_SWITCH_USER, 0x4600, CMU_DSU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER, 0x610, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER, 0x614, CMU_G3D),
|
|
SFR(DBG_NFO_MUX_CLKCMU_G3D_BUS_USER, 0x4610, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 0x600, CMU_HSI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI_BUS_USER, 0x604, CMU_HSI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_HSI_BUS_USER, 0x4600, CMU_HSI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, 0x630, CMU_HSI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER, 0x634, CMU_HSI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_USER, 0x4630, CMU_HSI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER, 0x600, CMU_ISP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_ISP_BUS_USER, 0x604, CMU_ISP),
|
|
SFR(DBG_NFO_MUX_CLKCMU_ISP_BUS_USER, 0x4600, CMU_ISP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER, 0x600, CMU_M2M),
|
|
SFR(PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER, 0x604, CMU_M2M),
|
|
SFR(DBG_NFO_MUX_CLKCMU_M2M_MSCL_USER, 0x4600, CMU_M2M),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER, 0x600, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER, 0x604, CMU_MCSC),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_BUS_USER, 0x4600, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER, 0x610, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER, 0x614, CMU_MCSC),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_GDC_USER, 0x4610, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER, 0x620, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER, 0x624, CMU_MCSC),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER, 0x4620, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 0x600, CMU_MFC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER, 0x604, CMU_MFC),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MFC_MFC_USER, 0x4600, CMU_MFC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, 0x610, CMU_MIF),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER, 0x614, CMU_MIF),
|
|
SFR(DBG_NFO_MUX_CLKCMU_MIF_BUSP_USER, 0x4610, CMU_MIF),
|
|
SFR(PLL_CON0_CLKMUX_MIF_DDRPHY2X, 0x600, CMU_MIF),
|
|
SFR(PLL_CON1_CLKMUX_MIF_DDRPHY2X, 0x604, CMU_MIF),
|
|
SFR(DBG_NFO_CLKMUX_MIF_DDRPHY2X, 0x4600, CMU_MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER, 0x600, CMU_NPU0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER, 0x604, CMU_NPU0),
|
|
SFR(DBG_NFO_MUX_CLKCMU_NPU0_BUS_USER, 0x4600, CMU_NPU0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER, 0x600, CMU_NPUS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER, 0x604, CMU_NPUS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_NPUS_BUS_USER, 0x4600, CMU_NPUS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 0x600, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_BUS_USER, 0x604, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_BUS_USER, 0x4600, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER, 0x640, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER, 0x644, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI00_USI_USER, 0x4640, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER, 0x650, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER, 0x654, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI01_USI_USER, 0x4650, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER, 0x660, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER, 0x664, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI02_USI_USER, 0x4660, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER, 0x670, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER, 0x674, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI03_USI_USER, 0x4670, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER, 0x680, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER, 0x684, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI04_USI_USER, 0x4680, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER, 0x690, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER, 0x694, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI05_USI_USER, 0x4690, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER, 0x6b0, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER, 0x6b4, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI_I2C_USER, 0x46b0, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_UART_DBG, 0x630, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_UART_DBG, 0x634, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_UART_DBG, 0x4630, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER, 0x610, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER, 0x614, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_USER, 0x4610, CMU_PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER, 0x6a0, CMU_PERI),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER, 0x6a4, CMU_PERI),
|
|
SFR(DBG_NFO_MUX_CLKCMU_PERI_USI06_USI_USER, 0x46a0, CMU_PERI),
|
|
SFR(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, 0x600, CMU_S2D),
|
|
SFR(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, 0x604, CMU_S2D),
|
|
SFR(DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D, 0x4600, CMU_S2D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER, 0x600, CMU_TAA),
|
|
SFR(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER, 0x604, CMU_TAA),
|
|
SFR(DBG_NFO_MUX_CLKCMU_TAA_BUS_USER, 0x4600, CMU_TAA),
|
|
SFR(PLL_CON0_MUX_CLKCMU_TNR_BUS_USER, 0x600, CMU_TNR),
|
|
SFR(PLL_CON1_MUX_CLKCMU_TNR_BUS_USER, 0x604, CMU_TNR),
|
|
SFR(DBG_NFO_MUX_CLKCMU_TNR_BUS_USER, 0x4600, CMU_TNR),
|
|
SFR(PLL_CON0_MUX_CLKCMU_USB_BUS_USER, 0x620, CMU_USB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_USB_BUS_USER, 0x624, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_USB_BUS_USER, 0x4620, CMU_USB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, 0x630, CMU_USB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER, 0x634, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLKCMU_USB_USB20DRD_USER, 0x4630, CMU_USB),
|
|
SFR(PLL_CON0_MUX_CLKAUD_USB_BUS_USER, 0x600, CMU_USB),
|
|
SFR(PLL_CON1_MUX_CLKAUD_USB_BUS_USER, 0x604, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLKAUD_USB_BUS_USER, 0x4600, CMU_USB),
|
|
SFR(PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER, 0x610, CMU_USB),
|
|
SFR(PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER, 0x614, CMU_USB),
|
|
SFR(DBG_NFO_MUX_CLKAUD_USB_USB20DRD_USER, 0x4610, CMU_USB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER, 0x600, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER, 0x604, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_VTS_BUS_USER, 0x4600, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_RCO_USER, 0x610, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VTS_RCO_USER, 0x614, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_CLKCMU_VTS_RCO_USER, 0x4610, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER, 0x620, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER, 0x624, CMU_VTS),
|
|
SFR(DBG_NFO_MUX_CLK_AUD_DMIC_BUS_USER, 0x4620, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU, 0x103c, CMU_AUD),
|
|
SFR(DBG_NFO_MUX_HCHGEN_CLK_AUD_CPU, 0x503c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_PERI, 0x1810, CMU_ALIVE),
|
|
SFR(DBG_NFO_CLKCMU_CMGP_PERI, 0x5810, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_BUS, 0x1818, CMU_ALIVE),
|
|
SFR(DBG_NFO_DIV_CLK_ALIVE_BUS, 0x5818, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_BUS, 0x180c, CMU_ALIVE),
|
|
SFR(DBG_NFO_CLKCMU_CMGP_BUS, 0x580c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC, 0x1824, CMU_ALIVE),
|
|
SFR(DBG_NFO_DIV_CLK_ALIVE_I3C_PMIC, 0x5824, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, 0x181c, CMU_ALIVE),
|
|
SFR(DBG_NFO_DIV_CLK_ALIVE_DBGCORE_UART, 0x581c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CHUBVTS_BUS, 0x1800, CMU_ALIVE),
|
|
SFR(DBG_NFO_CLKCMU_CHUBVTS_BUS, 0x5800, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CHUB_PERI, 0x1804, CMU_ALIVE),
|
|
SFR(DBG_NFO_CLKCMU_CHUB_PERI, 0x5804, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_USI0, 0x1828, CMU_ALIVE),
|
|
SFR(DBG_NFO_DIV_CLK_ALIVE_USI0, 0x5828, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_I2C, 0x1820, CMU_ALIVE),
|
|
SFR(DBG_NFO_DIV_CLK_ALIVE_I2C, 0x5820, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x182c, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_CPU_PCLKDBG, 0x582c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0x1838, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_FM_SPDY, 0x5838, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x1844, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF0, 0x5844, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0x1848, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF1, 0x5848, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x184c, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF2, 0x584c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0x1850, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF3, 0x5850, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x1824, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_CPU_ACLK, 0x5824, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0x1818, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_BUSP, 0x5818, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CNT, 0x181c, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_CNT, 0x581c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0x1854, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF4, 0x5854, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0x1830, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_DSIF, 0x5830, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_FM, 0x1834, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_FM, 0x5834, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0x1858, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF5, 0x5858, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0x185c, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_UAIF6, 0x585c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0x183c, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_MCLK, 0x583c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x1810, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_AUDIF, 0x5810, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0x1814, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_BUSD, 0x5814, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_PCMC, 0x1840, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_PCMC, 0x5840, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_USB_BUS, 0x1800, CMU_AUD),
|
|
SFR(DBG_NFO_CLKAUD_USB_BUS, 0x5800, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_USB_USB20DRD, 0x1804, CMU_AUD),
|
|
SFR(DBG_NFO_CLKAUD_USB_USB20DRD, 0x5804, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU, 0x1820, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_CPU, 0x5820, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP, 0x1828, CMU_AUD),
|
|
SFR(DBG_NFO_DIV_CLK_AUD_CPU_ACP, 0x5828, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLK_AUD_DMIC, 0x1808, CMU_AUD),
|
|
SFR(DBG_NFO_CLK_AUD_DMIC, 0x5808, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BUSC_BUSP, 0x1800, CMU_BUSC),
|
|
SFR(DBG_NFO_DIV_CLK_BUSC_BUSP, 0x5800, CMU_BUSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI0, 0x1808, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_USI0, 0x5808, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI1, 0x180c, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_USI1, 0x580c, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI2, 0x1810, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_USI2, 0x5810, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_I2C, 0x1804, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_I2C, 0x5804, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI3, 0x1814, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_USI3, 0x5814, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_BUS, 0x1800, CMU_CHUB),
|
|
SFR(DBG_NFO_DIV_CLK_CHUB_BUS, 0x5800, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS, 0x1800, CMU_CHUBVTS),
|
|
SFR(DBG_NFO_DIV_CLK_CHUBVTS_BUS, 0x5800, CMU_CHUBVTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0x1800, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_I2C, 0x5800, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI0, 0x1808, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_USI0, 0x5808, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI4, 0x1818, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_USI4, 0x5818, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I3C, 0x1804, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_I3C, 0x5804, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI1, 0x180c, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_USI1, 0x580c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI2, 0x1810, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_USI2, 0x5810, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI3, 0x1814, CMU_CMGP),
|
|
SFR(DBG_NFO_DIV_CLK_CMGP_USI3, 0x5814, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ALIVE_BUS, 0x1800, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_ALIVE_BUS, 0x5800, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x1858, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_G3D_SWITCH, 0x5858, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_BUS, 0x1890, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_PERI_BUS, 0x5890, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DPU_BUS, 0x184c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_DPU_BUS, 0x584c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC_MFC, 0x187c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_MFC_MFC, 0x587c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_BUS, 0x182c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CORE_BUS, 0x582c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1840, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CPUCL0_SWITCH, 0x5840, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_TAA_BUS, 0x189c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_TAA_BUS, 0x589c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISP_BUS, 0x1864, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_ISP_BUS, 0x5864, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_CPU, 0x1808, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_AUD_CPU, 0x5808, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_M2M_MSCL, 0x1868, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_M2M_MSCL, 0x5868, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, 0x183c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CPUCL0_DBG_BUS, 0x583c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1810, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK0, 0x5810, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1814, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK1, 0x5814, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x1818, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK2, 0x5818, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD, 0x1860, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_HSI_UFS_EMBD, 0x5860, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_NPU0_BUS, 0x1884, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_NPU0_BUS, 0x5884, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MIF_BUSP, 0x1880, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_MIF_BUSP, 0x5880, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_IP, 0x1894, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_PERI_IP, 0x5894, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x1844, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CPUCL1_SWITCH, 0x5844, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_USB_BUS, 0x18a4, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_USB_BUS, 0x58a4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_TNR_BUS, 0x18a0, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_TNR_BUS, 0x58a0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST, 0x1828, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CMU_BOOST, 0x5828, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_G3D, 0x1830, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CORE_G3D, 0x5830, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_BUS, 0x1848, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CSIS_BUS, 0x5848, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCSC_BUS, 0x186c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_MCSC_BUS, 0x586c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI_BUS, 0x185c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_HSI_BUS, 0x585c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_MMC_CARD, 0x1898, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_PERI_MMC_CARD, 0x5898, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCSC_GDC, 0x1870, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_MCSC_GDC, 0x5870, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_USB_USB20DRD, 0x18a8, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_USB_USB20DRD, 0x58a8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_NPUS_BUS, 0x1888, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_NPUS_BUS, 0x5888, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_SSS, 0x1834, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CORE_SSS, 0x5834, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUSC_BUS, 0x180c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_BUSC_BUS, 0x580c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x181c, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK3, 0x581c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK4, 0x1820, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK4, 0x5820, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK5, 0x1824, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CIS_CLK5, 0x5824, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DSU_SWITCH, 0x1854, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_DSU_SWITCH, 0x5854, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP, 0x1838, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_CPUCL0_BUSP, 0x5838, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DPU_DSIM, 0x1850, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_DPU_DSIM, 0x5850, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0x1874, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_MCSC_MCSC, 0x5874, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_BUS, 0x1804, CMU_TOP),
|
|
SFR(DBG_NFO_CLKCMU_AUD_BUS, 0x5804, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0x1800, CMU_CORE),
|
|
SFR(DBG_NFO_DIV_CLK_CORE_BUSP, 0x5800, CMU_CORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP, 0x181c, CMU_CPUCL0),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL0_SHORTSTOP, 0x581c, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x1800, CMU_CPUCL0_GLB),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x5800, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP, 0x1808, CMU_CPUCL1),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL1_SHORTSTOP, 0x5808, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU, 0x1804, CMU_CPUCL1),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL1_HTU, 0x5804, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_BUSP, 0x1800, CMU_CSIS),
|
|
SFR(DBG_NFO_DIV_CLK_CSIS_BUSP, 0x5800, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0x1800, CMU_DPU),
|
|
SFR(DBG_NFO_DIV_CLK_DPU_BUSP, 0x5800, CMU_DPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP, 0x1814, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_DSU_SHORTSTOP, 0x5814, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0x1800, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_CLUSTER0_ACLK, 0x5800, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0x1804, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK, 0x5804, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0x1808, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_CLUSTER0_PCLK, 0x5808, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0x180c, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK, 0x580c, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1808, CMU_G3D),
|
|
SFR(DBG_NFO_DIV_CLK_G3D_BUSP, 0x5808, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ISP_BUSP, 0x1800, CMU_ISP),
|
|
SFR(DBG_NFO_DIV_CLK_ISP_BUSP, 0x5800, CMU_ISP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_M2M_BUSP, 0x1800, CMU_M2M),
|
|
SFR(DBG_NFO_DIV_CLK_M2M_BUSP, 0x5800, CMU_M2M),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_BUSP, 0x1800, CMU_MCSC),
|
|
SFR(DBG_NFO_DIV_CLK_MCSC_BUSP, 0x5800, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC_BUSP, 0x1800, CMU_MFC),
|
|
SFR(DBG_NFO_DIV_CLK_MFC_BUSP, 0x5800, CMU_MFC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU0_BUSP, 0x1804, CMU_NPU0),
|
|
SFR(DBG_NFO_DIV_CLK_NPU0_BUSP, 0x5804, CMU_NPU0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPUS_BUSP, 0x1804, CMU_NPUS),
|
|
SFR(DBG_NFO_DIV_CLK_NPUS_BUSP, 0x5804, CMU_NPUS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI00_USI, 0x1808, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI00_USI, 0x5808, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI01_USI, 0x180c, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI01_USI, 0x580c, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI02_USI, 0x1810, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI02_USI, 0x5810, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI03_USI, 0x1814, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI03_USI, 0x5814, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI04_USI, 0x1818, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI04_USI, 0x5818, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI05_USI, 0x181c, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI05_USI, 0x581c, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, 0x1824, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI_I2C, 0x5824, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_UART_DBG, 0x1804, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_UART_DBG, 0x5804, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI06_USI, 0x1820, CMU_PERI),
|
|
SFR(DBG_NFO_DIV_CLK_PERI_USI06_USI, 0x5820, CMU_PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_TAA_BUSP, 0x1800, CMU_TAA),
|
|
SFR(DBG_NFO_DIV_CLK_TAA_BUSP, 0x5800, CMU_TAA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_TNR_BUSP, 0x1800, CMU_TNR),
|
|
SFR(DBG_NFO_DIV_CLK_TNR_BUSP, 0x5800, CMU_TNR),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0x1804, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_CLK_VTS_DMIC_IF, 0x5804, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, 0x1808, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_CLK_VTS_DMIC_IF_DIV2, 0x5808, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_BUS, 0x1800, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_CLK_VTS_BUS, 0x5800, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_VTS_DMIC_AUD, 0x180c, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_VTS_DMIC_AUD, 0x580c, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2, 0x1810, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_VTS_DMIC_AUD_DIV2, 0x5810, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE, 0x1818, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_VTS_SERIAL_LIF_CORE, 0x5818, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_VTS_SERIAL_LIF, 0x1814, CMU_VTS),
|
|
SFR(DBG_NFO_DIV_VTS_SERIAL_LIF, 0x5814, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x1814, CMU_CPUCL0),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL0_CPU, 0x5814, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x1800, CMU_CPUCL1),
|
|
SFR(DBG_NFO_DIV_CLK_CPUCL1_CPU, 0x5800, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER, 0x1810, CMU_DSU),
|
|
SFR(DBG_NFO_DIV_CLK_DSU_CLUSTER, 0x5810, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0x1804, CMU_G3D),
|
|
SFR(DBG_NFO_DIV_CLK_G3D_BUSD, 0x5804, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU0_BUS, 0x1800, CMU_NPU0),
|
|
SFR(DBG_NFO_DIV_CLK_NPU0_BUS, 0x5800, CMU_NPU0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPUS_BUS, 0x1800, CMU_NPUS),
|
|
SFR(DBG_NFO_DIV_CLK_NPUS_BUS, 0x5800, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK, 0x213c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, 0x2134, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, 0x201c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK, 0x20fc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, 0x217c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, 0x2154, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 0x2094, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI, 0x202c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2038, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK, 0x208c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK, 0x2090, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2144, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x20f0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, 0x2180, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, 0x2014, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x2058, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2034, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, 0x204c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 0x214c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK, 0x2054, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, 0x20a4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 0x20b8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2140, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK, 0x203c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK, 0x2138, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS, 0x2028, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, 0x2178, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, 0x2050, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 0x20f8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 0x20f4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK, 0x2128, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK, 0x212c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK, 0x2124, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK, 0x2130, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, 0x2148, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, 0x2098, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK, 0x20ec, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK, 0x20e8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK, 0x20c4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK, 0x20a8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK, 0x20dc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, 0x20d8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, 0x20bc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, 0x20a0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, 0x20cc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK, 0x20d4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, 0x20c8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, 0x20b4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, 0x20b0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, 0x209c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK, 0x20e4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, 0x20ac, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK, 0x2080, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK, 0x2084, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK, 0x2110, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, 0x2018, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK, 0x2044, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK, 0x2040, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK, 0x2048, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, 0x2100, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK, 0x2030, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKCMU_VTS_RCO, 0x2010, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 0x2020, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_AP2GNSS_CLK, 0x2000, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK, 0x20c0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK, 0x20d0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI, 0x2024, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, 0x205c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, 0x2150, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, 0x2108, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK, 0x2104, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK, 0x2060, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK, 0x2064, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK, 0x2158, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK, 0x215c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK, 0x210c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK, 0x2114, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKCMU_CHUB_RCO, 0x2008, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKCMU_CMGP_RCO, 0x200c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, 0x20e0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKCMU_CHUBVTS_RCO, 0x2004, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK, 0x20d4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, 0x2000, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK, 0x2088, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, 0x209c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x2028, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, 0x202c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, 0x2034, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK, 0x20a4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, 0x20c4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x20e0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x20e4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x20e8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x20ec, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x20b4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2030, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK, 0x2100, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, 0x20a8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, 0x2098, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, 0x2114, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1, 0x2104, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK, 0x20c0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM, 0x2070, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, 0x2014, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM, 0x2078, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, 0x2058, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, 0x2018, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, 0x201c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK, 0x20d8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, 0x2094, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, 0x2038, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM, 0x2074, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK, 0x20f0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, 0x2050, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, 0x2054, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2, 0x2108, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, 0x20ac, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, 0x20b0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x2008, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, 0x2020, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK, 0x20cc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, 0x203c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, 0x2040, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK, 0x20f4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK, 0x20f8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, 0x2080, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, 0x208c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, 0x2090, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, 0x2084, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK, 0x20fc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, 0x2060, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, 0x20d0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, 0x2044, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, 0x2048, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK, 0x20c8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK, 0x20bc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_USB_BUS, 0x200c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD, 0x2010, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, 0x2110, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0, 0x2064, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1, 0x2068, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2, 0x206c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM, 0x207c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, 0x20b8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP, 0x204c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY, 0x205c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, 0x2024, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, 0x20a0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, 0x210c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK, 0x20dc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, 0x2000, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, 0x2004, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS, 0x2008, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK, 0x205c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK, 0x2058, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK, 0x2030, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK, 0x2034, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK, 0x2014, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK, 0x202c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0, 0x2018, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1, 0x203c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2, 0x2040, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, 0x2044, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, 0x2048, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK, 0x204c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK, 0x2050, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, 0x201c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, 0x2020, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK, 0x2024, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK, 0x2038, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK, 0x200c, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK, 0x2010, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK, 0x2054, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK, 0x2028, CMU_BUSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK, 0x2010, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK, 0x2008, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK, 0x2018, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0, 0x2040, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, 0x2070, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK, 0x2080, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK, 0x20a4, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK, 0x2044, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, 0x2050, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK, 0x204c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK, 0x2054, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK, 0x2028, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK, 0x202c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK, 0x2084, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK, 0x2088, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK, 0x208c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK, 0x2090, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK, 0x2094, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK, 0x2098, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, 0x2048, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK, 0x2058, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK, 0x205c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK, 0x2060, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK, 0x2078, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK, 0x2074, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK, 0x207c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK, 0x200c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK, 0x2038, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK, 0x203c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK, 0x209c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK, 0x20a0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK, 0x2064, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK, 0x2004, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK, 0x206c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK, 0x2068, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, 0x2000, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK, 0x2000, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, 0x2008, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK, 0x2010, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK, 0x2014, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK, 0x2020, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK, 0x201c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK, 0x2024, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK, 0x2028, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK, 0x202c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK, 0x2030, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK, 0x2034, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK, 0x2038, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK, 0x203c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK, 0x2040, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK, 0x200c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK, 0x2004, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK, 0x2018, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, 0x2000, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, 0x2018, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK, 0x2020, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, 0x207c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, 0x2084, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, 0x2050, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, 0x204c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK, 0x2058, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK, 0x201c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, 0x2080, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, 0x2078, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, 0x2014, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK, 0x206c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, 0x2070, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, 0x2004, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, 0x2074, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK, 0x2048, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK, 0x2044, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK, 0x2054, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, 0x2008, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, 0x200c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, 0x2010, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, 0x203c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, 0x2040, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, 0x20a4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, 0x20a0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK, 0x2068, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK, 0x2024, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK, 0x2028, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, 0x202c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, 0x2030, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, 0x2034, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, 0x2038, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, 0x2088, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, 0x208c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, 0x2090, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, 0x2094, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, 0x2098, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, 0x209c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK, 0x205c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK, 0x2060, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK, 0x2064, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS, 0x2014, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF_SWITCH, 0x2010, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 0x2090, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 0x2074, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD, 0x20a8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 0x205c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x2070, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 0x20a0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 0x203c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2050, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS, 0x20ac, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, 0x207c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 0x201c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL, 0x2068, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 0x204c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2024, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x2028, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x202c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD, 0x2078, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS, 0x2098, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 0x2094, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 0x20a4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2054, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_USB_BUS, 0x20b4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 0x20b0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 0x2040, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 0x2058, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 0x2080, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 0x2084, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS, 0x206c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD, 0x20b8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_AP2CP_SHARED0_CLK, 0x2004, CMU_TOP),
|
|
SFR(CLK_CON_GAT_AP2CP_SHARED1_CLK, 0x2008, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS, 0x209c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 0x2044, CMU_TOP),
|
|
SFR(CLK_CON_GAT_AP2CP_SHARED2_CLK, 0x200c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_AP2CP_HISPEEDY_CLK, 0x2000, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 0x2020, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x2030, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 0x2034, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 0x2038, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH, 0x2064, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP, 0x2048, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM, 0x2060, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 0x2088, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 0x2018, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 0x2000, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, 0x2154, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK, 0x20c0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, 0x216c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK, 0x2170, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, 0x2098, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x209c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A, 0x2040, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK, 0x2168, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, 0x20fc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20f0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, 0x20f4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK, 0x20d4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x2160, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, 0x2174, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK, 0x20e4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, 0x2158, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK, 0x2044, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK, 0x20d8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK, 0x2140, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK, 0x20c8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK, 0x20cc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK, 0x20d0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK, 0x2078, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, 0x20a0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS, 0x2010, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 0x200c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS, 0x2024, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, 0x2020, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, 0x215c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, 0x2164, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK, 0x20c4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK, 0x213c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK, 0x2124, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, 0x211c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, 0x2120, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, 0x2118, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK, 0x2100, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK, 0x2048, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK, 0x2064, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK, 0x2080, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK, 0x2084, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK, 0x20e8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, 0x20f8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK, 0x2104, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK, 0x2134, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, 0x202c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, 0x2030, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, 0x2034, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, 0x20bc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK, 0x2108, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, 0x2110, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, 0x2138, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK, 0x2128, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK, 0x2130, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK, 0x2070, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK, 0x20a8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2, 0x2150, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK, 0x208c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, 0x20dc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK, 0x2074, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK, 0x2148, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK, 0x2144, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK, 0x2094, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, 0x20a4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS, 0x2018, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 0x2014, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK, 0x212c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK, 0x207c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK, 0x2088, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK, 0x20ec, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK, 0x2114, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK, 0x2068, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK, 0x2028, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, 0x2038, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK, 0x217c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK, 0x2090, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, 0x2054, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK, 0x2058, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK, 0x2060, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2, 0x214c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, 0x203c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, 0x2008, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, 0x205c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK, 0x20ac, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK, 0x210c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK, 0x2050, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK, 0x20e0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK, 0x2178, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM, 0x201c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK, 0x206c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK, 0x204c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK, 0x20b0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x20b4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK, 0x20b8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, 0x2018, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK, 0x2034, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK, 0x202c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x200c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN, 0x2028, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, 0x2030, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, 0x2004, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, 0x2014, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, 0x2068, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, 0x2018, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x2020, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, 0x2024, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2044, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK, 0x2048, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK, 0x204c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2050, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, 0x2054, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK, 0x2058, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK, 0x205c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, 0x2040, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x2060, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, 0x2064, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK, 0x202c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x2038, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK, 0x2034, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK, 0x203c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, 0x2000, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK, 0x2030, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2004, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC, 0x2008, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK, 0x2040, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK, 0x2038, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK, 0x203c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, 0x2048, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, 0x2000, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, 0x2048, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, 0x204c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK, 0x2110, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK, 0x2114, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, 0x2020, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB, 0x200c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA, 0x2008, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK, 0x201c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK, 0x2070, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK, 0x2078, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, 0x2120, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, 0x2128, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK, 0x2074, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK, 0x207c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, 0x2140, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, 0x211c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK, 0x203c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2030, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x2034, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, 0x2004, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, 0x2150, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, 0x2154, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK, 0x2040, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2024, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x2028, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, 0x2124, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, 0x212c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK, 0x2084, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK, 0x2080, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, 0x2090, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, 0x2094, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, 0x209c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, 0x2098, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, 0x20f8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, 0x20fc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, 0x20e0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, 0x20e4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK, 0x20c8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK, 0x20cc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0, 0x2058, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1, 0x205c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2, 0x2060, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3, 0x2064, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4, 0x2068, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5, 0x206c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK, 0x2050, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, 0x2100, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, 0x2104, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, 0x20e8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, 0x20ec, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK, 0x20d0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK, 0x20d4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, 0x20a0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, 0x20a4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, 0x20a8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, 0x20ac, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK, 0x20b0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK, 0x20b4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK, 0x20b8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK, 0x20bc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0, 0x2010, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1, 0x2014, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK, 0x2018, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, 0x2158, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK, 0x215c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, 0x2130, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, 0x2134, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK, 0x2160, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK, 0x2088, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK, 0x208c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1, 0x2138, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2, 0x213c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK, 0x2054, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK, 0x20c4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK, 0x20c0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, 0x20f0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, 0x20f4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, 0x2108, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, 0x210c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK, 0x20d8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK, 0x20dc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK, 0x2044, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2038, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x202c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK, 0x2144, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK, 0x2148, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK, 0x214c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK, 0x2118, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 0x2000, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 0x205c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1, 0x204c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, 0x2048, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK, 0x202c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK, 0x2030, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, 0x203c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, 0x2040, CMU_DPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, 0x2008, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, 0x2024, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON, 0x2014, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA, 0x2018, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP, 0x201c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 0x2020, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2, 0x2050, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, 0x200c, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV, 0x2010, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, 0x2028, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK, 0x2034, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK, 0x2038, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1, 0x2054, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2, 0x2058, CMU_DPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK, 0x2004, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK, 0x2044, CMU_DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK, 0x2088, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK, 0x208c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, 0x2014, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK, 0x2040, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK, 0x2044, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, 0x2058, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, 0x205c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, 0x2060, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, 0x2064, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, 0x2048, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, 0x204c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, 0x2050, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, 0x2054, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, 0x2078, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, 0x207c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, 0x2008, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, 0x200c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, 0x2010, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, 0x201c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, 0x2024, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK, 0x2038, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, 0x2018, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK, 0x2084, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK, 0x2080, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, 0x2034, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, 0x2020, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK, 0x2068, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK, 0x206c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK, 0x2070, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK, 0x2074, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK, 0x203c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, 0x2054, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x205c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x2048, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, 0x2008, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2000, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, 0x2004, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, 0x2018, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, 0x2044, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK, 0x2034, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK, 0x2030, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK, 0x2038, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK, 0x202c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK, 0x2040, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK, 0x203c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM, 0x2010, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2, 0x2058, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK, 0x2028, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK, 0x204c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, 0x2024, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK, 0x2064, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, 0x201c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, 0x2020, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM, 0x2014, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK, 0x2060, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK, 0x2050, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK, 0x2004, CMU_GNSS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK, 0x2040, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK, 0x200c, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, 0x2030, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK, 0x2004, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK, 0x202c, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK, 0x2028, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK, 0x2010, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK, 0x2014, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK, 0x2018, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK, 0x201c, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK, 0x2000, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x2034, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x203c, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x2038, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2, 0x2024, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK, 0x2008, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK, 0x2020, CMU_HSI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, 0x2050, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, 0x2000, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, 0x2010, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, 0x2014, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK, 0x2024, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK, 0x200c, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK, 0x2004, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK, 0x2008, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, 0x201c, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK, 0x202c, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK, 0x2028, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1, 0x2048, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2, 0x204c, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK, 0x2038, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK, 0x203c, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK, 0x2030, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK, 0x2034, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK, 0x2054, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM, 0x2020, CMU_ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK, 0x2018, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK, 0x2044, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK, 0x2040, CMU_ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, 0x2020, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, 0x2000, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, 0x2044, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK, 0x2038, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1, 0x203c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, 0x2024, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, 0x2028, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, 0x204c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK, 0x2030, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, 0x202c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM, 0x2004, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, 0x2010, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, 0x200c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2, 0x2040, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK, 0x2014, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, 0x2018, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, 0x201c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM, 0x2008, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, 0x2048, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, 0x2034, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, 0x2000, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK, 0x2064, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK, 0x2068, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, 0x2078, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, 0x208c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK, 0x2060, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, 0x201c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK, 0x206c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM, 0x2004, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK, 0x2054, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK, 0x2058, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, 0x2084, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, 0x2088, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK, 0x2020, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, 0x2048, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM, 0x2014, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM, 0x2010, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK, 0x2090, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK, 0x2094, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, 0x2028, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, 0x202c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, 0x2030, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, 0x2034, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK, 0x2038, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK, 0x203c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK, 0x2040, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK, 0x2044, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK, 0x2024, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, 0x2008, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK, 0x205c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, 0x207c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, 0x2080, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, 0x2070, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK, 0x20a0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK, 0x204c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK, 0x2050, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM, 0x200c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK, 0x209c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK, 0x2098, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS, 0x2018, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK, 0x2074, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK, 0x2028, CMU_MFC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, 0x2000, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, 0x2004, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, 0x2038, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK, 0x200c, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, 0x202c, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1, 0x2030, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK, 0x2014, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK, 0x2018, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, 0x201c, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, 0x2010, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK, 0x2020, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, 0x2008, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2, 0x2034, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, 0x2024, CMU_MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK, 0x203c, CMU_MFC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2004, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK, 0x2050, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2068, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, 0x2064, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, 0x2018, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, 0x204c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, 0x2008, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, 0x2014, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, 0x2054, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, 0x2028, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, 0x2048, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, 0x203c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, 0x2000, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, 0x2058, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, 0x2060, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, 0x205c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, 0x2044, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, 0x2040, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, 0x2024, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, 0x2020, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, 0x201c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK, 0x202c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK, 0x2038, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK, 0x2034, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK, 0x2030, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK, 0x2014, CMU_MODEM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK, 0x2028, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK, 0x202c, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK, 0x200c, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK, 0x2010, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK, 0x2034, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK, 0x2030, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, 0x2008, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK, 0x2004, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK, 0x201c, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK, 0x2014, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK, 0x2024, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, 0x2020, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK, 0x2018, CMU_NPU0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK, 0x209c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK, 0x2044, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK, 0x2058, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK, 0x2048, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK, 0x204c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK, 0x2054, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK, 0x206c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1, 0x208c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2, 0x2090, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK, 0x2038, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK, 0x205c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK, 0x2008, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK, 0x2074, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, 0x2040, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1, 0x2094, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2, 0x2098, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK, 0x2050, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK, 0x2064, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK, 0x2024, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK, 0x2028, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK, 0x2078, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK, 0x2030, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK, 0x2034, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK, 0x2004, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK, 0x2060, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK, 0x2068, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK, 0x2080, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK, 0x2088, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK, 0x202c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK, 0x203c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK, 0x2070, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS, 0x2020, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM, 0x201c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK, 0x2014, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK, 0x2084, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM, 0x2018, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK, 0x207c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK, 0x200c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK, 0x2010, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, 0x2018, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, 0x2070, CMU_PERI),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, 0x2008, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK, 0x2038, CMU_PERI),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, 0x2040, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK, 0x205c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK, 0x2044, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK, 0x2048, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK, 0x204c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK, 0x2050, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK, 0x2054, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK, 0x203c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK, 0x2068, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK, 0x2010, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK, 0x2104, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, 0x201c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x2028, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK, 0x20fc, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK, 0x2100, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK, 0x2074, CMU_PERI),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 0x2004, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0, 0x2034, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK, 0x2078, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK, 0x207c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, 0x2088, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, 0x208c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, 0x2080, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, 0x2084, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK, 0x2098, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK, 0x209c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK, 0x2090, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK, 0x2094, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK, 0x20a8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK, 0x20a0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK, 0x20a4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK, 0x20b8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK, 0x20bc, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK, 0x20b0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK, 0x20b4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK, 0x20c8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK, 0x20cc, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK, 0x20c0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK, 0x20c4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK, 0x20d8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK, 0x20dc, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK, 0x20d0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK, 0x20d4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK, 0x20ac, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK, 0x20f8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2, 0x2064, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2020, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2024, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK, 0x202c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK, 0x2030, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK, 0x206c, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK, 0x2014, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK, 0x2058, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK, 0x20e8, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK, 0x20ec, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK, 0x20e0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK, 0x20e4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK, 0x20f0, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK, 0x20f4, CMU_PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK, 0x2060, CMU_PERI),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, 0x2004, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, 0x2010, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, 0x200c, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, 0x2000, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2018, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, 0x2014, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK, 0x2034, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK, 0x205c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK, 0x2068, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK, 0x2040, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK, 0x2044, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK, 0x2000, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK, 0x2018, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK, 0x2008, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK, 0x200c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK, 0x2048, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK, 0x2050, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2028, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x202c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK, 0x2038, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK, 0x203c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK, 0x2010, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x201c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x2020, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT, 0x2054, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM, 0x2004, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1, 0x2060, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2, 0x2064, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK, 0x2074, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS, 0x2058, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK, 0x2014, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2030, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2024, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK, 0x206c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK, 0x2070, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK, 0x204c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, 0x2000, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, 0x200c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM, 0x2004, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, 0x2010, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, 0x2014, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, 0x2040, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, 0x2008, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, 0x204c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, 0x2024, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, 0x2020, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, 0x202c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, 0x2028, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, 0x2030, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, 0x2034, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, 0x2038, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, 0x203c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0, 0x2044, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK, 0x2048, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK, 0x2050, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK, 0x2018, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, 0x2060, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK, 0x201c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1, 0x2058, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK, 0x205c, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK, 0x2054, CMU_TNR),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26, 0x203c, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, 0x200c, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK, 0x2028, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK, 0x2014, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK, 0x2040, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK, 0x2008, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK, 0x2020, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, 0x2010, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2, 0x201c, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, 0x202c, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL, 0x2034, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY, 0x2038, CMU_USB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, 0x2000, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK, 0x2044, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK, 0x2024, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK, 0x2030, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK, 0x2018, CMU_USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK, 0x2010, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK, 0x2000, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, 0x2048, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, 0x20c4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, 0x2008, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, 0x2060, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, 0x20cc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK, 0x2024, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, 0x2050, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, 0x2014, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, 0x20b0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK, 0x201c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, 0x2084, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, 0x207c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK, 0x202c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, 0x2080, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK, 0x20c8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, 0x2054, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, 0x205c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, 0x208c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK, 0x20a8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK, 0x20ac, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK, 0x2020, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK, 0x2028, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK, 0x2064, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, 0x2068, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK, 0x206c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS, 0x2070, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0, 0x2004, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK, 0x2018, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK, 0x200c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x204c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2058, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK, 0x20a4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK, 0x20a0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK, 0x2038, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK, 0x2044, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS, 0x2078, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK, 0x2074, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2040, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, 0x2030, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2034, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, 0x203c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK, 0x2098, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK, 0x209c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0, 0x20b4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1, 0x20b8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, 0x20bc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, 0x20c0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK, 0x2088, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, 0x2090, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, 0x2094, CMU_VTS),
|
|
SFR(CLK_CON_DIV_CLKCMU_OTP, 0x188c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MIF_BUSD, 0x1800, CMU_MIF),
|
|
SFR(CLK_CON_DIV_CLK_MIF_BUSD_S2D, 0x1800, CMU_S2D),
|
|
SFR(QCH_CON_ALIVE_CMU_ALIVE_QCH, 0x3034, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_CHUB_RTC_QCH, 0x3038, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x303c, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3040, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_RTC_QCH, 0x3044, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH, 0x304c, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH, 0x3048, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH, 0x3050, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_TOP_RTC_QCH, 0x3054, CMU_ALIVE),
|
|
SFR(QCH_CON_DBGCORE_UART_QCH, 0x3058, CMU_ALIVE),
|
|
SFR(QCH_CON_D_TZPC_ALIVE_QCH, 0x305c, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x3064, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x3060, CMU_ALIVE),
|
|
SFR(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH, 0x3068, CMU_ALIVE),
|
|
SFR(QCH_CON_I2C_ALIVE0_QCH, 0x306c, CMU_ALIVE),
|
|
SFR(QCH_CON_I3C_APM_PMIC_QCH_P, 0x307c, CMU_ALIVE),
|
|
SFR(QCH_CON_I3C_APM_PMIC_QCH_S, 0x3080, CMU_ALIVE),
|
|
SFR(QCH_CON_INTMEM_QCH, 0x3084, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_AP_QCH, 0x3088, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CHUB_QCH, 0x308c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CP_QCH, 0x3090, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_GNSS_QCH, 0x3094, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_VTS_QCH, 0x3098, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_WLBT_QCH, 0x309c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CHUB_QCH, 0x30a0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_QCH, 0x30a4, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_S_QCH, 0x30a8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_DBGCORE_QCH, 0x30ac, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_GNSS_QCH, 0x30b0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_WLBT_BT_QCH, 0x30b4, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_WLBT_WL_QCH, 0x30b8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_CHUB_QCH, 0x30bc, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_GNSS_QCH, 0x30c0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_WLBT_BT_QCH, 0x30c4, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_WLBT_WL_QCH, 0x30c8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_GNSS_CHUB_QCH, 0x30cc, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_GNSS_WLBT_QCH, 0x30d0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_SHARED_SRAM_QCH, 0x30d4, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_VTS_CHUB_QCH, 0x30d8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_WLBT_ABOX_QCH, 0x30dc, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_WLBT_CHUB_QCH, 0x30e0, CMU_ALIVE),
|
|
SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x30e4, CMU_ALIVE),
|
|
SFR(QCH_CON_ROM_CRC32_HOST_QCH, 0x30e8, CMU_ALIVE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH, 0x30f0, CMU_ALIVE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, 0x30ec, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH, 0x30f4, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_C_GNSS_QCH, 0x30f8, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_C_MODEM_QCH, 0x30fc, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_C_WLBT_QCH, 0x3100, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_APM_QCH, 0x3104, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_C_CMGP_QCH, 0x3108, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_APM_QCH, 0x310c, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH, 0x3110, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH, 0x3114, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH, 0x3118, CMU_ALIVE),
|
|
SFR(QCH_CON_SS_DBGCORE_QCH_GREBE, 0x3120, CMU_ALIVE),
|
|
SFR(QCH_CON_SS_DBGCORE_QCH_DBG, 0x311c, CMU_ALIVE),
|
|
SFR(QCH_CON_SYSREG_ALIVE_QCH, 0x3124, CMU_ALIVE),
|
|
SFR(QCH_CON_USI_ALIVE0_QCH, 0x3128, CMU_ALIVE),
|
|
SFR(QCH_CON_VGEN_LITE_ALIVE_QCH, 0x3138, CMU_ALIVE),
|
|
SFR(QCH_CON_WDT_ALIVE_QCH, 0x313c, CMU_ALIVE),
|
|
SFR(QCH_CON_ABOX_QCH_ACLK, 0x3030, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK_DSIF, 0x3050, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK0, 0x3034, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK1, 0x3038, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK2, 0x303c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK3, 0x3040, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK4, 0x3044, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CNT, 0x3064, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CCLK_ASB, 0x3060, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK5, 0x3048, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK6, 0x304c, CMU_AUD),
|
|
SFR(DMYQCH_CON_ABOX_QCH_CPU, 0x3000, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_PCMC_CLK, 0x307c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A0, 0x3054, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A1, 0x3058, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK0, 0x3080, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK1, 0x3084, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK2, 0x3088, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CPU0, 0x3068, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CPU1, 0x306c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_NEON0, 0x3074, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_NEON1, 0x3078, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_L2, 0x3070, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CCLK_ACP, 0x305c, CMU_AUD),
|
|
SFR(QCH_CON_AUD_CMU_AUD_QCH, 0x308c, CMU_AUD),
|
|
SFR(DMYQCH_CON_DFTMUX_AUD_QCH, 0x3004, CMU_AUD),
|
|
SFR(QCH_CON_D_TZPC_AUD_QCH, 0x3090, CMU_AUD),
|
|
SFR(QCH_CON_LH_AXI_SI_D_AUD_QCH, 0x3094, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD0_QCH, 0x3098, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD1_QCH, 0x309c, CMU_AUD),
|
|
SFR(QCH_CON_PPMU_AUD_QCH, 0x30a0, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, 0x30a4, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, 0x30a8, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, 0x30ac, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_USBAUD_QCH, 0x30b0, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_AUD_QCH, 0x30b4, CMU_AUD),
|
|
SFR(QCH_CON_SYSMMU_AUD_QCH_S1, 0x30b8, CMU_AUD),
|
|
SFR(QCH_CON_SYSMMU_AUD_QCH_S2, 0x30bc, CMU_AUD),
|
|
SFR(QCH_CON_SYSREG_AUD_QCH, 0x30c0, CMU_AUD),
|
|
SFR(QCH_CON_VGEN_LITE_AUD_QCH, 0x30c4, CMU_AUD),
|
|
SFR(QCH_CON_WDT_AUD_QCH, 0x30c8, CMU_AUD),
|
|
SFR(QCH_CON_BUSC_CMU_BUSC_QCH, 0x3020, CMU_BUSC),
|
|
SFR(DMYQCH_CON_CMU_BUSC_CMUREF_QCH, 0x3000, CMU_BUSC),
|
|
SFR(QCH_CON_D_TZPC_BUSC_QCH, 0x3024, CMU_BUSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH, 0x3028, CMU_BUSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D_MFC_QCH, 0x302c, CMU_BUSC),
|
|
SFR(QCH_CON_PDMA_BUSC_QCH, 0x3030, CMU_BUSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_APM_QCH, 0x3034, CMU_BUSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_PERI_QCH, 0x3038, CMU_BUSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_USB_QCH, 0x303c, CMU_BUSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_BUSC_QCH, 0x3040, CMU_BUSC),
|
|
SFR(QCH_CON_SPDMA_BUSC_QCH, 0x3044, CMU_BUSC),
|
|
SFR(QCH_CON_SYSMMU_AXI_D_BUSC_QCH, 0x3048, CMU_BUSC),
|
|
SFR(QCH_CON_SYSREG_BUSC_QCH, 0x304c, CMU_BUSC),
|
|
SFR(QCH_CON_TREX_D_BUSC_QCH, 0x3050, CMU_BUSC),
|
|
SFR(QCH_CON_VGEN_PDMA_QCH, 0x3054, CMU_BUSC),
|
|
SFR(QCH_CON_VGEN_SPDMA_QCH, 0x3058, CMU_BUSC),
|
|
SFR(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, 0x3020, CMU_CHUB),
|
|
SFR(QCH_CON_APBIF_GPIO_CHUB_QCH, 0x3028, CMU_CHUB),
|
|
SFR(QCH_CON_APBIF_GPIO_CHUBEINT_QCH, 0x3024, CMU_CHUB),
|
|
SFR(QCH_CON_CHUB_CMU_CHUB_QCH, 0x302c, CMU_CHUB),
|
|
SFR(QCH_CON_CM4_CHUB_QCH_CPU, 0x3030, CMU_CHUB),
|
|
SFR(QCH_CON_I2C_CHUB1_QCH, 0x303c, CMU_CHUB),
|
|
SFR(QCH_CON_I2C_CHUB3_QCH, 0x3044, CMU_CHUB),
|
|
SFR(QCH_CON_PWM_CHUB_QCH, 0x3048, CMU_CHUB),
|
|
SFR(QCH_CON_SLH_AXI_MI_S_CHUB_QCH, 0x304c, CMU_CHUB),
|
|
SFR(QCH_CON_SLH_AXI_SI_M_CHUB_QCH, 0x3050, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_CHUB_QCH, 0x3054, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH, 0x305c, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH, 0x3058, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH, 0x3060, CMU_CHUB),
|
|
SFR(QCH_CON_TIMER_CHUB_QCH, 0x3064, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB0_QCH, 0x3068, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB1_QCH, 0x306c, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB2_QCH, 0x3070, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB3_QCH, 0x3074, CMU_CHUB),
|
|
SFR(QCH_CON_WDT_CHUB_QCH, 0x3078, CMU_CHUB),
|
|
SFR(QCH_CON_BAAW_CHUB_QCH, 0x301c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_BAAW_VTS_QCH, 0x3020, CMU_CHUBVTS),
|
|
SFR(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH, 0x3024, CMU_CHUBVTS),
|
|
SFR(QCH_CON_D_TZPC_CHUBVTS_QCH, 0x3028, CMU_CHUBVTS),
|
|
SFR(QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH, 0x302c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH, 0x3030, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_M_CHUB_QCH, 0x3034, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_M_VTS_QCH, 0x3038, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH, 0x303c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_SI_S_CHUB_QCH, 0x3040, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_SI_S_VTS_QCH, 0x3044, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SWEEPER_C_CHUBVTS_QCH, 0x3048, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SYSREG_CHUBVTS_QCH, 0x304c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_VGEN_LITE_CHUBVTS_QCH, 0x3050, CMU_CHUBVTS),
|
|
SFR(QCH_CON_CMGP_CMU_CMGP_QCH, 0x3004, CMU_CMGP),
|
|
SFR(QCH_CON_D_TZPC_CMGP_QCH, 0x3008, CMU_CMGP),
|
|
SFR(QCH_CON_GPIO_CMGP_QCH, 0x300c, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP0_QCH, 0x3010, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP1_QCH, 0x3014, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP2_QCH, 0x3018, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP3_QCH, 0x301c, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP4_QCH, 0x3020, CMU_CMGP),
|
|
SFR(QCH_CON_I3C_CMGP_QCH_P, 0x3024, CMU_CMGP),
|
|
SFR(QCH_CON_I3C_CMGP_QCH_S, 0x3028, CMU_CMGP),
|
|
SFR(QCH_CON_SLH_AXI_MI_C_CMGP_QCH, 0x302c, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP_QCH, 0x3048, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2APM_QCH, 0x3030, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CHUB_QCH, 0x3034, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CP_QCH, 0x3038, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2GNSS_QCH, 0x303c, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_AP_QCH, 0x3040, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2WLBT_QCH, 0x3044, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP0_QCH, 0x304c, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP1_QCH, 0x3050, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP2_QCH, 0x3054, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP3_QCH, 0x3058, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP4_QCH, 0x305c, CMU_CMGP),
|
|
SFR(DMYQCH_CON_CMU_CMU_CMUREF_QCH, 0x3000, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0, 0x3004, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1, 0x3008, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2, 0x300c, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3, 0x3010, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4, 0x3014, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5, 0x3018, CMU_TOP),
|
|
SFR(DMYQCH_CON_OTP_QCH, 0x301c, CMU_TOP),
|
|
SFR(DMYQCH_CON_ADM_APB_G_BDU_QCH, 0x3000, CMU_CORE),
|
|
SFR(QCH_CON_BAAW_D_SSS_QCH, 0x30d4, CMU_CORE),
|
|
SFR(QCH_CON_BAAW_P_GNSS_QCH, 0x30d8, CMU_CORE),
|
|
SFR(QCH_CON_BAAW_P_MODEM_QCH, 0x30dc, CMU_CORE),
|
|
SFR(QCH_CON_BAAW_P_WLBT_QCH, 0x30e0, CMU_CORE),
|
|
SFR(QCH_CON_BDU_QCH, 0x30e4, CMU_CORE),
|
|
SFR(DMYQCH_CON_CMU_CORE_CMUREF_QCH, 0x3008, CMU_CORE),
|
|
SFR(QCH_CON_CORE_CMU_CORE_QCH, 0x30e8, CMU_CORE),
|
|
SFR(QCH_CON_DIT_QCH, 0x30ec, CMU_CORE),
|
|
SFR(QCH_CON_D_TZPC_CORE_QCH, 0x30f0, CMU_CORE),
|
|
SFR(QCH_CON_GIC_QCH, 0x30f4, CMU_CORE),
|
|
SFR(QCH_CON_HW_APBSEMA_MEC_QCH, 0x30f8, CMU_CORE),
|
|
SFR(QCH_CON_LH_AST_MI_G_CPU_QCH, 0x30fc, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_DPU_QCH, 0x3100, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_NPUS_QCH, 0x3104, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_DPU_QCH, 0x3108, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_NPUS_QCH, 0x310c, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D_AUD_QCH, 0x3110, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D_G3D_QCH, 0x3114, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D_M2M_QCH, 0x3118, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_MI_D_SSS_QCH, 0x311c, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH, 0x3120, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH, 0x3124, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH, 0x3128, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH, 0x312c, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH, 0x3130, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH, 0x3134, CMU_CORE),
|
|
SFR(QCH_CON_LH_AXI_SI_D_SSS_QCH, 0x3138, CMU_CORE),
|
|
SFR(DMYQCH_CON_PUF_QCH, 0x300c, CMU_CORE),
|
|
SFR(QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH, 0x313c, CMU_CORE),
|
|
SFR(QCH_CON_SFR_APBIF_CMU_TOPC_QCH, 0x3140, CMU_CORE),
|
|
SFR(QCH_CON_SIREX_QCH, 0x3144, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH, 0x3148, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH, 0x314c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_GNSS_QCH, 0x3150, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_HSI_QCH, 0x3154, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_WLBT_QCH, 0x3158, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH, 0x315c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH, 0x3160, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_APM_QCH, 0x3164, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_AUD_QCH, 0x3168, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_BUSC_QCH, 0x316c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH, 0x3170, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CSIS_QCH, 0x3174, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_DPU_QCH, 0x3178, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_G3D_QCH, 0x317c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_GNSS_QCH, 0x3180, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_HSI_QCH, 0x3184, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_ISP_QCH, 0x3188, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_M2M_QCH, 0x318c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MCSC_QCH, 0x3190, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MCW_QCH, 0x3194, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MFC_QCH, 0x3198, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF0_QCH, 0x319c, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF1_QCH, 0x31a0, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MODEM_QCH, 0x31a4, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_NPU0_QCH, 0x31a8, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_NPUS_QCH, 0x31ac, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERI_QCH, 0x31b0, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_TAA_QCH, 0x31b4, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_TNR_QCH, 0x31b8, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_USB_QCH, 0x31bc, CMU_CORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_WLBT_QCH, 0x31c0, CMU_CORE),
|
|
SFR(QCH_CON_SSS_QCH, 0x31c4, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH, 0x31c8, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_ACEL_D_DIT_QCH, 0x31cc, CMU_CORE),
|
|
SFR(QCH_CON_SYSREG_CORE_QCH, 0x31d0, CMU_CORE),
|
|
SFR(QCH_CON_TREX_D_CORE_QCH, 0x31d4, CMU_CORE),
|
|
SFR(QCH_CON_TREX_D_NRT_QCH, 0x31d8, CMU_CORE),
|
|
SFR(QCH_CON_TREX_P_CORE_QCH, 0x31dc, CMU_CORE),
|
|
SFR(QCH_CON_VGEN_LITE_CORE_QCH, 0x31e0, CMU_CORE),
|
|
SFR(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, 0x3000, CMU_CPUCL0),
|
|
SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3014, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_CPUCL0_QCH, 0x3004, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x3018, CMU_CPUCL0),
|
|
SFR(QCH_CON_HTU_CPUCL0_QCH_PCLK, 0x3020, CMU_CPUCL0),
|
|
SFR(QCH_CON_HTU_CPUCL0_QCH_CLK, 0x301c, CMU_CPUCL0),
|
|
SFR(QCH_CON_BPS_CPUCL0_QCH, 0x3028, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, 0x302c, CMU_CPUCL0_GLB),
|
|
SFR(DMYQCH_CON_CSSYS_QCH, 0x3000, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_D_TZPC_CPUCL0_QCH, 0x3030, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH, 0x3034, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SECJTAG_QCH, 0x3038, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH, 0x303c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH, 0x3040, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH, 0x3044, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH, 0x3048, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH, 0x304c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH, 0x3050, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH, 0x3054, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x3058, CMU_CPUCL0_GLB),
|
|
SFR(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, 0x3000, CMU_CPUCL1),
|
|
SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3018, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_BIG, 0x3004, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_DDD_HC0, 0x3008, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_DDD_HC1, 0x300c, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x301c, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_QCH_PCLK, 0x3024, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_QCH_CLK, 0x3020, CMU_CPUCL1),
|
|
SFR(QCH_CON_CSIS_CMU_CSIS_QCH, 0x3064, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_VOTF0, 0x3078, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_DMA, 0x306c, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_PDP_TOP, 0x3074, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_MCB, 0x3070, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_VOTF1, 0x307c, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_C2_PDP, 0x3068, CMU_CSIS),
|
|
SFR(QCH_CON_D_TZPC_CSIS_QCH, 0x3080, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH, 0x3084, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH, 0x3088, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH, 0x308c, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH, 0x3090, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH, 0x3094, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH, 0x3098, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH, 0x309c, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH, 0x30a0, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH, 0x30a4, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_CSIS_QCH, 0x30a8, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_CSIS_QCH, 0x30ac, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D2_CSIS_QCH, 0x30b0, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D3_CSIS_QCH, 0x30b4, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0, 0x30b8, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1, 0x30bc, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2, 0x30c0, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3, 0x30c4, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4, 0x30c8, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5, 0x30cc, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_CSIS_D0_QCH, 0x30d0, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_CSIS_D1_QCH, 0x30d4, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_CSIS_D2_QCH, 0x30d8, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_CSIS_D3_QCH, 0x30dc, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA0_QCH, 0x30e0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA1_QCH, 0x30e4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA2_QCH, 0x30e8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA3_QCH, 0x30ec, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_AF0_QCH, 0x30f0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_AF1_QCH, 0x30f4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_AF2_QCH, 0x30f8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG0_QCH, 0x30fc, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG1_QCH, 0x3100, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG2_QCH, 0x3104, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP0_QCH, 0x3108, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP1_QCH, 0x310c, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP2_QCH, 0x3110, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL0_QCH, 0x3114, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL1_QCH, 0x3118, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL2_QCH, 0x311c, CMU_CSIS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CSIS_QCH, 0x3120, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S1, 0x3124, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S2, 0x3128, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S1, 0x312c, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S2, 0x3130, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S1, 0x3134, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S2, 0x3138, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D3_CSIS_QCH_S2, 0x3140, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D3_CSIS_QCH_S1, 0x313c, CMU_CSIS),
|
|
SFR(QCH_CON_SYSREG_CSIS_QCH, 0x3144, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE0_CSIS_QCH, 0x3148, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE1_CSIS_QCH, 0x314c, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE2_CSIS_QCH, 0x3150, CMU_CSIS),
|
|
SFR(QCH_CON_DPU_QCH_DPU, 0x3030, CMU_DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_DMA, 0x3038, CMU_DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_DPP, 0x303c, CMU_DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_C2SERV, 0x3034, CMU_DPU),
|
|
SFR(DMYQCH_CON_DPU_QCH, 0x3000, CMU_DPU),
|
|
SFR(QCH_CON_DPU_CMU_DPU_QCH, 0x302c, CMU_DPU),
|
|
SFR(QCH_CON_D_TZPC_DPU_QCH, 0x3040, CMU_DPU),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_DPU_QCH, 0x3044, CMU_DPU),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_DPU_QCH, 0x3048, CMU_DPU),
|
|
SFR(QCH_CON_PPMU_D0_DPU_QCH, 0x304c, CMU_DPU),
|
|
SFR(QCH_CON_PPMU_D1_DPU_QCH, 0x3050, CMU_DPU),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DPU_QCH, 0x3054, CMU_DPU),
|
|
SFR(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1, 0x3058, CMU_DPU),
|
|
SFR(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2, 0x305c, CMU_DPU),
|
|
SFR(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1, 0x3060, CMU_DPU),
|
|
SFR(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2, 0x3064, CMU_DPU),
|
|
SFR(QCH_CON_SYSREG_DPU_QCH, 0x3068, CMU_DPU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_SCLK, 0x3034, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_ATCLK, 0x3020, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_GIC, 0x3028, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_DBG_PD, 0x3024, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PCLK, 0x302c, CMU_DSU),
|
|
SFR(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, 0x3000, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PDBGCLK, 0x3030, CMU_DSU),
|
|
SFR(DMYQCH_CON_CMU_DSU_CMUREF_QCH, 0x3004, CMU_DSU),
|
|
SFR(QCH_CON_CMU_DSU_SHORTSTOP_QCH, 0x3038, CMU_DSU),
|
|
SFR(QCH_CON_DSU_CMU_DSU_QCH, 0x303c, CMU_DSU),
|
|
SFR(QCH_CON_HTU_DSU_QCH_PCLK, 0x3044, CMU_DSU),
|
|
SFR(QCH_CON_HTU_DSU_QCH_CLK, 0x3040, CMU_DSU),
|
|
SFR(QCH_CON_LH_AST_SI_G_CPU_QCH, 0x3048, CMU_DSU),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH, 0x304c, CMU_DSU),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH, 0x3050, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH, 0x3054, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH, 0x3058, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH, 0x305c, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH, 0x3060, CMU_DSU),
|
|
SFR(QCH_CON_PPMU_CPUCL0_QCH, 0x3064, CMU_DSU),
|
|
SFR(QCH_CON_PPMU_CPUCL1_QCH, 0x3068, CMU_DSU),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH, 0x306c, CMU_DSU),
|
|
SFR(QCH_CON_D_TZPC_G3D_QCH, 0x3020, CMU_G3D),
|
|
SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x3024, CMU_G3D),
|
|
SFR(QCH_CON_GPU_QCH, 0x3028, CMU_G3D),
|
|
SFR(QCH_CON_HTU_G3D_QCH_CLK, 0x302c, CMU_G3D),
|
|
SFR(QCH_CON_HTU_G3D_QCH_PCLK, 0x3030, CMU_G3D),
|
|
SFR(QCH_CON_LHM_AXI_P_INT_G3D_QCH, 0x3034, CMU_G3D),
|
|
SFR(QCH_CON_LHS_AXI_P_INT_G3D_QCH, 0x3038, CMU_G3D),
|
|
SFR(QCH_CON_LH_AXI_SI_D_G3D_QCH, 0x303c, CMU_G3D),
|
|
SFR(QCH_CON_PPMU_D_G3D_QCH, 0x3040, CMU_G3D),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_G3D_QCH, 0x3044, CMU_G3D),
|
|
SFR(QCH_CON_SYSMMU_D_G3D_QCH, 0x3048, CMU_G3D),
|
|
SFR(QCH_CON_SYSREG_G3D_QCH, 0x304c, CMU_G3D),
|
|
SFR(QCH_CON_VGEN_LITE_G3D_QCH, 0x3050, CMU_G3D),
|
|
SFR(QCH_CON_GNSS_CMU_GNSS_QCH, 0x3000, CMU_GNSS),
|
|
SFR(QCH_CON_D_TZPC_HSI_QCH, 0x3010, CMU_HSI),
|
|
SFR(QCH_CON_GPIO_HSI_QCH, 0x3014, CMU_HSI),
|
|
SFR(QCH_CON_GPIO_HSI_UFS_QCH, 0x3018, CMU_HSI),
|
|
SFR(QCH_CON_HSI_CMU_HSI_QCH, 0x301c, CMU_HSI),
|
|
SFR(QCH_CON_PPMU_HSI_QCH, 0x3020, CMU_HSI),
|
|
SFR(QCH_CON_S2MPU_D_HSI_QCH_S2, 0x3024, CMU_HSI),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_HSI_QCH, 0x3028, CMU_HSI),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_HSI_QCH, 0x302c, CMU_HSI),
|
|
SFR(QCH_CON_SYSREG_HSI_QCH, 0x3030, CMU_HSI),
|
|
SFR(QCH_CON_UFS_EMBD_QCH, 0x3034, CMU_HSI),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x3038, CMU_HSI),
|
|
SFR(QCH_CON_VGEN_LITE_HSI_QCH, 0x303c, CMU_HSI),
|
|
SFR(QCH_CON_D_TZPC_ISP_QCH, 0x3028, CMU_ISP),
|
|
SFR(QCH_CON_ISP_CMU_ISP_QCH, 0x302c, CMU_ISP),
|
|
SFR(QCH_CON_ITP_DNS_QCH_S00, 0x3030, CMU_ISP),
|
|
SFR(QCH_CON_ITP_DNS_QCH_S01, 0x3034, CMU_ISP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH, 0x3038, CMU_ISP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH, 0x303c, CMU_ISP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_TAAISP_QCH, 0x3040, CMU_ISP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH, 0x3044, CMU_ISP),
|
|
SFR(QCH_CON_LH_AXI_SI_D_ISP_QCH, 0x3048, CMU_ISP),
|
|
SFR(QCH_CON_PPMU_ISP_QCH, 0x304c, CMU_ISP),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_ISP_QCH, 0x3050, CMU_ISP),
|
|
SFR(QCH_CON_SYSMMU_D_ISP_QCH_S1, 0x3054, CMU_ISP),
|
|
SFR(QCH_CON_SYSMMU_D_ISP_QCH_S2, 0x3058, CMU_ISP),
|
|
SFR(QCH_CON_SYSREG_ISP_QCH, 0x305c, CMU_ISP),
|
|
SFR(QCH_CON_VGEN_LITE_ISP_QCH, 0x3060, CMU_ISP),
|
|
SFR(QCH_CON_D_TZPC_M2M_QCH, 0x301c, CMU_M2M),
|
|
SFR(QCH_CON_JPEG0_QCH, 0x3020, CMU_M2M),
|
|
SFR(QCH_CON_LH_AXI_SI_D_M2M_QCH, 0x3028, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH_S2, 0x3034, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH_S1, 0x3030, CMU_M2M),
|
|
SFR(QCH_CON_M2M_CMU_M2M_QCH, 0x302c, CMU_M2M),
|
|
SFR(QCH_CON_PPMU_D_M2M_QCH, 0x3038, CMU_M2M),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_M2M_QCH, 0x303c, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_QCH_S1, 0x3040, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_QCH_S2, 0x3044, CMU_M2M),
|
|
SFR(QCH_CON_SYSREG_M2M_QCH, 0x3048, CMU_M2M),
|
|
SFR(QCH_CON_VGEN_LITE_M2M_QCH, 0x304c, CMU_M2M),
|
|
SFR(QCH_CON_D_TZPC_MCSC_QCH, 0x304c, CMU_MCSC),
|
|
SFR(QCH_CON_GDC_QCH, 0x3050, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH, 0x3054, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_CSIS_QCH, 0x3058, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_TNR_QCH, 0x305c, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_CSIS_QCH, 0x3060, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_TNR_QCH, 0x3064, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D2_CSIS_QCH, 0x3068, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D3_CSIS_QCH, 0x306c, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D_ISP_QCH, 0x3070, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_D_TAA_QCH, 0x3074, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH, 0x307c, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_CMU_MCSC_QCH, 0x3078, CMU_MCSC),
|
|
SFR(QCH_CON_ORBMCH_QCH_ACLK, 0x3080, CMU_MCSC),
|
|
SFR(QCH_CON_ORBMCH_QCH_C2CLK, 0x3084, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_GDC_QCH, 0x3088, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_MCSC_QCH, 0x308c, CMU_MCSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MCSC_QCH, 0x3090, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S1, 0x3094, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S2, 0x3098, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S1, 0x309c, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S2, 0x30a0, CMU_MCSC),
|
|
SFR(QCH_CON_SYSREG_MCSC_QCH, 0x30a4, CMU_MCSC),
|
|
SFR(QCH_CON_TREX_D_CAM_QCH, 0x30a8, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_GDC_QCH, 0x30ac, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_MCSC_QCH, 0x30b0, CMU_MCSC),
|
|
SFR(QCH_CON_D_TZPC_MFC_QCH, 0x3014, CMU_MFC),
|
|
SFR(QCH_CON_LH_AXI_SI_D_MFC_QCH, 0x3018, CMU_MFC),
|
|
SFR(QCH_CON_MFC_QCH, 0x3020, CMU_MFC),
|
|
SFR(QCH_CON_MFC_CMU_MFC_QCH, 0x301c, CMU_MFC),
|
|
SFR(QCH_CON_PPMU_MFC_QCH, 0x3024, CMU_MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH, 0x3028, CMU_MFC),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MFC_QCH, 0x302c, CMU_MFC),
|
|
SFR(QCH_CON_SYSMMU_MFC_QCH_S1, 0x3030, CMU_MFC),
|
|
SFR(QCH_CON_SYSMMU_MFC_QCH_S2, 0x3034, CMU_MFC),
|
|
SFR(QCH_CON_SYSREG_MFC_QCH, 0x3038, CMU_MFC),
|
|
SFR(QCH_CON_VGEN_LITE_MFC_QCH, 0x303c, CMU_MFC),
|
|
SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, CMU_MIF),
|
|
SFR(QCH_CON_DMC_QCH, 0x3018, CMU_MIF),
|
|
SFR(QCH_CON_D_TZPC_MIF_QCH, 0x301c, CMU_MIF),
|
|
SFR(QCH_CON_LH_AXI_MI_D_MIF_CP_QCH, 0x3024, CMU_MIF),
|
|
SFR(QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH, 0x3020, CMU_MIF),
|
|
SFR(QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH, 0x3028, CMU_MIF),
|
|
SFR(QCH_CON_LH_AXI_MI_D_MIF_RT_QCH, 0x302c, CMU_MIF),
|
|
SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3030, CMU_MIF),
|
|
SFR(QCH_CON_PPMU_DMC_CPU_QCH, 0x3034, CMU_MIF),
|
|
SFR(QCH_CON_QE_DMC_CPU_QCH, 0x3038, CMU_MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH, 0x303c, CMU_MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_QCH, 0x3048, CMU_MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH, 0x3040, CMU_MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH, 0x3044, CMU_MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH, 0x304c, CMU_MIF),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MIF_QCH, 0x3050, CMU_MIF),
|
|
SFR(QCH_CON_SYSREG_MIF_QCH, 0x3054, CMU_MIF),
|
|
SFR(QCH_CON_MODEM_CMU_MODEM_QCH, 0x3000, CMU_MODEM),
|
|
SFR(QCH_CON_D_TZPC_NPU0_QCH, 0x301c, CMU_NPU0),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_ACLK, 0x3020, CMU_NPU0),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_PCLK, 0x3024, CMU_NPU0),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_NPU0_QCH, 0x3028, CMU_NPU0),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_NPU0_QCH, 0x302c, CMU_NPU0),
|
|
SFR(QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH, 0x3030, CMU_NPU0),
|
|
SFR(QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH, 0x3034, CMU_NPU0),
|
|
SFR(QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH, 0x3038, CMU_NPU0),
|
|
SFR(QCH_CON_NPU0_CMU_NPU0_QCH, 0x303c, CMU_NPU0),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_NPU0_QCH, 0x3040, CMU_NPU0),
|
|
SFR(QCH_CON_SYSREG_NPU0_QCH, 0x3044, CMU_NPU0),
|
|
SFR(DMYQCH_CON_ADM_DAP_NPUS_QCH, 0x3000, CMU_NPUS),
|
|
SFR(QCH_CON_D_TZPC_NPUS_QCH, 0x3040, CMU_NPUS),
|
|
SFR(QCH_CON_HTU_NPUS_QCH_PCLK, 0x3048, CMU_NPUS),
|
|
SFR(QCH_CON_HTU_NPUS_QCH_CLK, 0x3044, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH, 0x304c, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_C2A0CLK, 0x3050, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_C2A1CLK, 0x3054, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_CPU, 0x3058, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_NEON, 0x305c, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH, 0x3060, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH, 0x3064, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_NPU0_QCH, 0x3068, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_NPUS_QCH, 0x306c, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_NPU0_QCH, 0x3070, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_NPUS_QCH, 0x3074, CMU_NPUS),
|
|
SFR(QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH, 0x3078, CMU_NPUS),
|
|
SFR(QCH_CON_NPUS_CMU_NPUS_QCH, 0x307c, CMU_NPUS),
|
|
SFR(QCH_CON_PPMU_NPUS_0_QCH, 0x3080, CMU_NPUS),
|
|
SFR(QCH_CON_PPMU_NPUS_1_QCH, 0x3084, CMU_NPUS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH, 0x3088, CMU_NPUS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_NPUS_QCH, 0x308c, CMU_NPUS),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH, 0x3090, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D0_NPUS_QCH_S1, 0x3094, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D0_NPUS_QCH_S2, 0x3098, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D1_NPUS_QCH_S1, 0x309c, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D1_NPUS_QCH_S2, 0x30a0, CMU_NPUS),
|
|
SFR(QCH_CON_SYSREG_NPUS_QCH, 0x30a4, CMU_NPUS),
|
|
SFR(QCH_CON_VGEN_LITE_NPUS_QCH, 0x30a8, CMU_NPUS),
|
|
SFR(QCH_CON_D_TZPC_PERI_QCH, 0x3014, CMU_PERI),
|
|
SFR(QCH_CON_GPIO_PERI_QCH, 0x301c, CMU_PERI),
|
|
SFR(QCH_CON_GPIO_PERIMMC_QCH_GPIO, 0x3018, CMU_PERI),
|
|
SFR(QCH_CON_MCT_QCH, 0x3020, CMU_PERI),
|
|
SFR(QCH_CON_MMC_CARD_QCH, 0x3024, CMU_PERI),
|
|
SFR(QCH_CON_OTP_CON_TOP_QCH, 0x302c, CMU_PERI),
|
|
SFR(QCH_CON_PERI_CMU_PERI_QCH, 0x3030, CMU_PERI),
|
|
SFR(QCH_CON_PPMU_PERI_QCH, 0x3034, CMU_PERI),
|
|
SFR(QCH_CON_PWM_QCH, 0x3038, CMU_PERI),
|
|
SFR(QCH_CON_S2MPU_D_PERI_QCH, 0x303c, CMU_PERI),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERI_QCH, 0x3040, CMU_PERI),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_PERI_QCH, 0x3044, CMU_PERI),
|
|
SFR(QCH_CON_SYSREG_PERI_QCH, 0x3048, CMU_PERI),
|
|
SFR(QCH_CON_TMU_QCH, 0x304c, CMU_PERI),
|
|
SFR(QCH_CON_UART_DBG_QCH, 0x3050, CMU_PERI),
|
|
SFR(QCH_CON_USI00_I2C_QCH, 0x3054, CMU_PERI),
|
|
SFR(QCH_CON_USI00_USI_QCH, 0x3058, CMU_PERI),
|
|
SFR(QCH_CON_USI01_I2C_QCH, 0x305c, CMU_PERI),
|
|
SFR(QCH_CON_USI01_USI_QCH, 0x3060, CMU_PERI),
|
|
SFR(QCH_CON_USI02_I2C_QCH, 0x3064, CMU_PERI),
|
|
SFR(QCH_CON_USI02_USI_QCH, 0x3068, CMU_PERI),
|
|
SFR(QCH_CON_USI03_I2C_QCH, 0x306c, CMU_PERI),
|
|
SFR(QCH_CON_USI03_USI_QCH, 0x3070, CMU_PERI),
|
|
SFR(QCH_CON_USI04_I2C_QCH, 0x3074, CMU_PERI),
|
|
SFR(QCH_CON_USI04_USI_QCH, 0x3078, CMU_PERI),
|
|
SFR(QCH_CON_USI05_I2C_QCH, 0x307c, CMU_PERI),
|
|
SFR(QCH_CON_USI05_USI_QCH, 0x3080, CMU_PERI),
|
|
SFR(QCH_CON_USI06_I2C_QCH, 0x3084, CMU_PERI),
|
|
SFR(QCH_CON_USI06_USI_QCH, 0x3088, CMU_PERI),
|
|
SFR(QCH_CON_USI07_I2C_QCH, 0x308c, CMU_PERI),
|
|
SFR(QCH_CON_VGEN_LITE_PERI_QCH, 0x3090, CMU_PERI),
|
|
SFR(QCH_CON_WDT0_QCH, 0x3094, CMU_PERI),
|
|
SFR(QCH_CON_WDT1_QCH, 0x3098, CMU_PERI),
|
|
SFR(QCH_CON_S2D_CMU_S2D_QCH, 0x3004, CMU_S2D),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH, 0x3008, CMU_S2D),
|
|
SFR(QCH_CON_D_TZPC_TAA_QCH, 0x303c, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH, 0x3040, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH, 0x3044, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH, 0x3048, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_TAAISP_QCH, 0x304c, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH, 0x3050, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH, 0x3054, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH, 0x3058, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH, 0x305c, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH, 0x3060, CMU_TAA),
|
|
SFR(QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH, 0x3064, CMU_TAA),
|
|
SFR(QCH_CON_LH_AXI_SI_D_TAA_QCH, 0x3068, CMU_TAA),
|
|
SFR(QCH_CON_PPMU_TAA_QCH, 0x306c, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH, 0x3070, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH_C2_STAT, 0x3074, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH_C2_YDS, 0x3078, CMU_TAA),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_TAA_QCH, 0x307c, CMU_TAA),
|
|
SFR(QCH_CON_SYSMMU_TAA_QCH_S1, 0x3080, CMU_TAA),
|
|
SFR(QCH_CON_SYSMMU_TAA_QCH_S2, 0x3084, CMU_TAA),
|
|
SFR(QCH_CON_SYSREG_TAA_QCH, 0x3088, CMU_TAA),
|
|
SFR(QCH_CON_TAA_CMU_TAA_QCH, 0x308c, CMU_TAA),
|
|
SFR(QCH_CON_VGEN_LITE0_TAA_QCH, 0x3090, CMU_TAA),
|
|
SFR(QCH_CON_VGEN_LITE1_TAA_QCH, 0x3094, CMU_TAA),
|
|
SFR(QCH_CON_D_TZPC_TNR_QCH, 0x300c, CMU_TNR),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH, 0x3060, CMU_TNR),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH, 0x3064, CMU_TNR),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_TNR_QCH, 0x3014, CMU_TNR),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_TNR_QCH, 0x3018, CMU_TNR),
|
|
SFR(QCH_CON_PPMU_D0_TNR_QCH, 0x3020, CMU_TNR),
|
|
SFR(QCH_CON_PPMU_D1_TNR_QCH, 0x3024, CMU_TNR),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_TNR_QCH, 0x3010, CMU_TNR),
|
|
SFR(QCH_CON_SYSMMU_D0_TNR_QCH_S1, 0x3028, CMU_TNR),
|
|
SFR(QCH_CON_SYSMMU_D0_TNR_QCH_S2, 0x302c, CMU_TNR),
|
|
SFR(QCH_CON_SYSMMU_D1_TNR_QCH_S1, 0x3030, CMU_TNR),
|
|
SFR(QCH_CON_SYSMMU_D1_TNR_QCH_S2, 0x3034, CMU_TNR),
|
|
SFR(QCH_CON_SYSREG_TNR_QCH, 0x3038, CMU_TNR),
|
|
SFR(QCH_CON_TNR_QCH_MCFP0, 0x3040, CMU_TNR),
|
|
SFR(QCH_CON_TNR_QCH_MCFP1, 0x3068, CMU_TNR),
|
|
SFR(QCH_CON_TNR_CMU_TNR_QCH, 0x303c, CMU_TNR),
|
|
SFR(QCH_CON_VGEN_LITE_D_TNR_QCH, 0x3044, CMU_TNR),
|
|
SFR(QCH_CON_D_TZPC_USB_QCH, 0x3018, CMU_USB),
|
|
SFR(QCH_CON_PPMU_USB_QCH, 0x301c, CMU_USB),
|
|
SFR(QCH_CON_S2MPU_D_USB_QCH, 0x3020, CMU_USB),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_USB_QCH, 0x3024, CMU_USB),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_USB_QCH, 0x302c, CMU_USB),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_USBAUD_QCH, 0x3028, CMU_USB),
|
|
SFR(QCH_CON_SYSREG_USB_QCH, 0x3030, CMU_USB),
|
|
SFR(QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL, 0x3034, CMU_USB),
|
|
SFR(QCH_CON_USB20DRD_TOP_QCH_SLV_LINK, 0x3038, CMU_USB),
|
|
SFR(QCH_CON_USB_CMU_USB_QCH, 0x303c, CMU_USB),
|
|
SFR(QCH_CON_VGEN_LITE_USB_QCH, 0x3040, CMU_USB),
|
|
SFR(QCH_CON_CM4_VTS_QCH_CPU, 0x303c, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB0_QCH_PCLK, 0x3040, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB2_QCH_PCLK, 0x3044, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AUD0_QCH_PCLK, 0x3048, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_AUD0_QCH_DMIC, 0x3000, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AUD1_QCH_PCLK, 0x304c, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_AUD1_QCH_DMIC, 0x3004, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF0_QCH_PCLK, 0x3050, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF0_QCH_DMIC, 0x3008, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF1_QCH_PCLK, 0x3054, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF1_QCH_DMIC, 0x300c, CMU_VTS),
|
|
SFR(QCH_CON_GPIO_VTS_QCH, 0x3058, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC0_QCH, 0x305c, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC2_QCH, 0x3060, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH, 0x3064, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_ABOX_VTS_QCH, 0x3068, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_AP_VTS_QCH, 0x306c, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_AUD_QCH_PCLK, 0x3070, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB, 0x3010, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF, 0x3014, CMU_VTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_S_VTS_QCH, 0x3074, CMU_VTS),
|
|
SFR(QCH_CON_SLH_AXI_SI_M_VTS_QCH, 0x3078, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, 0x3018, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, 0x301c, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, 0x3020, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, 0x3024, CMU_VTS),
|
|
SFR(QCH_CON_SYSREG_VTS_QCH, 0x307c, CMU_VTS),
|
|
SFR(QCH_CON_TIMER_VTS_QCH, 0x3080, CMU_VTS),
|
|
SFR(QCH_CON_VTS_CMU_VTS_QCH, 0x3084, CMU_VTS),
|
|
SFR(QCH_CON_WDT_VTS_QCH, 0x3088, CMU_VTS),
|
|
SFR(ALIVE_CMU_ALIVE_CONTROLLER_OPTION, 0x800, CMU_ALIVE),
|
|
SFR(AUD_CMU_AUD_CONTROLLER_OPTION, 0x800, CMU_AUD),
|
|
SFR(BUSC_CMU_BUSC_CONTROLLER_OPTION, 0x800, CMU_BUSC),
|
|
SFR(CHUB_CMU_CHUB_CONTROLLER_OPTION, 0x800, CMU_CHUB),
|
|
SFR(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION, 0x800, CMU_CHUBVTS),
|
|
SFR(CMGP_CMU_CMGP_CONTROLLER_OPTION, 0x800, CMU_CMGP),
|
|
SFR(CMU_CMU_TOP_CONTROLLER_OPTION, 0x800, CMU_TOP),
|
|
SFR(CORE_CMU_CORE_CONTROLLER_OPTION, 0x800, CMU_CORE),
|
|
SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x800, CMU_CPUCL0),
|
|
SFR(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION, 0x800, CMU_CPUCL0_GLB),
|
|
SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x800, CMU_CPUCL1),
|
|
SFR(CSIS_CMU_CSIS_CONTROLLER_OPTION, 0x800, CMU_CSIS),
|
|
SFR(DPU_CMU_DPU_CONTROLLER_OPTION, 0x800, CMU_DPU),
|
|
SFR(DSU_CMU_DSU_CONTROLLER_OPTION, 0x800, CMU_DSU),
|
|
SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x800, CMU_G3D),
|
|
SFR(GNSS_CMU_GNSS_CONTROLLER_OPTION, 0x800, CMU_GNSS),
|
|
SFR(HSI_CMU_HSI_CONTROLLER_OPTION, 0x800, CMU_HSI),
|
|
SFR(ISP_CMU_ISP_CONTROLLER_OPTION, 0x800, CMU_ISP),
|
|
SFR(M2M_CMU_M2M_CONTROLLER_OPTION, 0x800, CMU_M2M),
|
|
SFR(MCSC_CMU_MCSC_CONTROLLER_OPTION, 0x800, CMU_MCSC),
|
|
SFR(MFC_CMU_MFC_CONTROLLER_OPTION, 0x800, CMU_MFC),
|
|
SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x800, CMU_MIF),
|
|
SFR(MODEM_CMU_MODEM_CONTROLLER_OPTION, 0x800, CMU_MODEM),
|
|
SFR(NPU0_CMU_NPU0_CONTROLLER_OPTION, 0x800, CMU_NPU0),
|
|
SFR(NPUS_CMU_NPUS_CONTROLLER_OPTION, 0x800, CMU_NPUS),
|
|
SFR(PERI_CMU_PERI_CONTROLLER_OPTION, 0x800, CMU_PERI),
|
|
SFR(S2D_CMU_S2D_CONTROLLER_OPTION, 0x800, CMU_S2D),
|
|
SFR(TAA_CMU_TAA_CONTROLLER_OPTION, 0x800, CMU_TAA),
|
|
SFR(TNR_CMU_TNR_CONTROLLER_OPTION, 0x800, CMU_TNR),
|
|
SFR(USB_CMU_USB_CONTROLLER_OPTION, 0x800, CMU_USB),
|
|
SFR(VTS_CMU_VTS_CONTROLLER_OPTION, 0x800, CMU_VTS),
|
|
};
|
|
|
|
unsigned int cmucal_sfr_access_size = 7665;
|
|
struct sfr_access cmucal_sfr_access_list[] = {
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_ENABLE, 31, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_STABLE, 29, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_P, 8, 6, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_M, 16, 10, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_S, 0, 3, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON9_PLL_AUD_K, 0, 32, PLL_CON9_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON8_PLL_AUD_F, 0, 32, PLL_CON8_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_SSCGEN, 16, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON5_PLL_AUD_MFR, 16, 8, PLL_CON5_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON5_PLL_AUD_MRR, 24, 6, PLL_CON5_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON5_PLL_AUD_SEL_PF, 30, 2, PLL_CON5_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_AFC_ENB, 20, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(DBG_NFO_PLL_AUD_AFC_CODE, 16, 6, DBG_NFO_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_BYPASS, 22, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_MUX_SEL, 4, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_MUX_BUSY, 16, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_LOCK_FAIL, 27, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(DBG_NFO_PLL_AUD_DEBUG_INFO, 0, 16, DBG_NFO_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON2_PLL_AUD_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON2_PLL_AUD_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON1_PLL_AUD_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_LOCK_EN, 26, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON6_PLL_AUD_RESETB_REG, 31, 1, PLL_CON6_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON6_PLL_AUD_STABLE_REG, 29, 1, PLL_CON6_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_AUD_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON4_PLL_AUD_MASK_SEL, 18, 1, PLL_CON4_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON6_PLL_AUD_LDO_SEL, 23, 1, PLL_CON6_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON6_PLL_AUD_LDO_CON, 20, 3, PLL_CON6_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_REV, 24, 6, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_R_CON, 20, 4, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_C_CON, 16, 4, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_ICP, 8, 4, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_EXT_AFC, 0, 6, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_EN_FOUT, 15, 1, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_EN_FOUT2, 14, 1, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_EN_FOUT3, 13, 1, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON7_PLL_AUD_EN_FOUT4, 12, 1, PLL_CON7_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_ENABLE, 31, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_STABLE, 29, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_P, 8, 6, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_M, 16, 10, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_S, 0, 3, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON9_PLL_SHARED1_K, 0, 32, PLL_CON9_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED1_F, 0, 32, PLL_CON8_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_SSCGEN, 16, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED1_MFR, 16, 8, PLL_CON5_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED1_MRR, 24, 6, PLL_CON5_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED1_SEL_PF, 30, 2, PLL_CON5_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED1_AFC_CODE, 16, 6, DBG_NFO_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_BYPASS, 22, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED1_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED1_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED1_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED1_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED1_RESETB_REG, 31, 1, PLL_CON6_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED1_STABLE_REG, 29, 1, PLL_CON6_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_SHARED1_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED1_MASK_SEL, 18, 1, PLL_CON4_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED1_LDO_SEL, 23, 1, PLL_CON6_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED1_LDO_CON, 20, 3, PLL_CON6_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_REV, 24, 6, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_R_CON, 20, 4, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_C_CON, 16, 4, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_ICP, 8, 4, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_EXT_AFC, 0, 6, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_EN_FOUT, 15, 1, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_EN_FOUT2, 14, 1, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_EN_FOUT3, 13, 1, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED1_EN_FOUT4, 12, 1, PLL_CON7_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_ENABLE, 31, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_STABLE, 29, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_P, 8, 6, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_M, 16, 10, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_S, 0, 3, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON9_PLL_SHARED0_K, 0, 32, PLL_CON9_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED0_F, 0, 32, PLL_CON8_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_SSCGEN, 16, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED0_MFR, 16, 8, PLL_CON5_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED0_MRR, 24, 6, PLL_CON5_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED0_SEL_PF, 30, 2, PLL_CON5_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_LOCK_CON_IN, 12, 2, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED0_AFC_CODE, 16, 6, DBG_NFO_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_BYPASS, 22, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED0_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED0_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED0_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED0_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED0_RESETB_REG, 31, 1, PLL_CON6_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED0_STABLE_REG, 29, 1, PLL_CON6_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_SHARED0_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED0_MASK_SEL, 18, 1, PLL_CON4_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED0_LDO_SEL, 23, 1, PLL_CON6_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED0_LDO_CON, 20, 3, PLL_CON6_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_REV, 24, 6, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_R_CON, 20, 4, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_C_CON, 16, 4, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_ICP, 8, 4, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_EXT_AFC, 0, 6, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_EN_FOUT, 15, 1, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_EN_FOUT2, 14, 1, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_EN_FOUT3, 13, 1, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED0_EN_FOUT4, 12, 1, PLL_CON7_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_ENABLE, 31, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_STABLE, 29, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_P, 8, 6, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_M, 16, 10, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_S, 0, 3, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON9_PLL_G3D_K, 0, 32, PLL_CON9_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON8_PLL_G3D_F, 0, 32, PLL_CON8_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_SSCGEN, 16, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON5_PLL_G3D_MFR, 16, 8, PLL_CON5_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON5_PLL_G3D_MRR, 24, 6, PLL_CON5_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON5_PLL_G3D_SEL_PF, 30, 2, PLL_CON5_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_AFC_ENB, 20, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(DBG_NFO_PLL_G3D_AFC_CODE, 16, 6, DBG_NFO_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_BYPASS, 22, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_MUX_SEL, 4, 1, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_MUX_BUSY, 16, 1, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_LOCK_FAIL, 27, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(DBG_NFO_PLL_G3D_DEBUG_INFO, 0, 16, DBG_NFO_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON2_PLL_G3D_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON2_PLL_G3D_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON1_PLL_G3D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_LOCK_EN, 26, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON6_PLL_G3D_RESETB_REG, 31, 1, PLL_CON6_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON6_PLL_G3D_STABLE_REG, 29, 1, PLL_CON6_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_G3D_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON4_PLL_G3D_MASK_SEL, 18, 1, PLL_CON4_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON6_PLL_G3D_LDO_SEL, 23, 1, PLL_CON6_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON6_PLL_G3D_LDO_CON, 20, 3, PLL_CON6_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_REV, 24, 6, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_R_CON, 20, 4, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_C_CON, 16, 4, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_ICP, 8, 4, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_EXT_AFC, 0, 6, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_EN_FOUT, 15, 1, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_EN_FOUT2, 14, 1, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_EN_FOUT3, 13, 1, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON7_PLL_G3D_EN_FOUT4, 12, 1, PLL_CON7_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_ENABLE, 31, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_STABLE, 29, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_P, 8, 6, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_M, 16, 10, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_S, 0, 3, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON9_PLL_MMC_K, 0, 32, PLL_CON9_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON8_PLL_MMC_F, 0, 32, PLL_CON8_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_SSCGEN, 16, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON5_PLL_MMC_MFR, 16, 8, PLL_CON5_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON5_PLL_MMC_MRR, 24, 6, PLL_CON5_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON5_PLL_MMC_SEL_PF, 30, 2, PLL_CON5_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_AFC_ENB, 20, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(DBG_NFO_PLL_MMC_AFC_CODE, 16, 6, DBG_NFO_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_BYPASS, 22, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_MUX_SEL, 4, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_MUX_BUSY, 16, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(DBG_NFO_PLL_MMC_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON2_PLL_MMC_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON2_PLL_MMC_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON1_PLL_MMC_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_LOCK_EN, 26, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON6_PLL_MMC_RESETB_REG, 31, 1, PLL_CON6_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON6_PLL_MMC_STABLE_REG, 29, 1, PLL_CON6_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_MMC_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON4_PLL_MMC_MASK_SEL, 18, 1, PLL_CON4_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON6_PLL_MMC_LDO_SEL, 23, 1, PLL_CON6_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON6_PLL_MMC_LDO_CON, 20, 3, PLL_CON6_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_REV, 24, 6, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_R_CON, 20, 4, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_C_CON, 16, 4, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_ICP, 8, 4, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_EXT_AFC, 0, 6, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_EN_FOUT, 15, 1, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_EN_FOUT2, 14, 1, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_EN_FOUT3, 13, 1, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON7_PLL_MMC_EN_FOUT4, 12, 1, PLL_CON7_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_ENABLE, 31, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_STABLE, 29, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_P, 8, 6, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_M, 16, 10, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_S, 0, 3, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON9_PLL_SHARED2_K, 0, 32, PLL_CON9_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED2_F, 0, 32, PLL_CON8_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_SSCGEN, 16, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED2_MFR, 16, 8, PLL_CON5_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED2_MRR, 24, 6, PLL_CON5_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON5_PLL_SHARED2_SEL_PF, 30, 2, PLL_CON5_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED2_AFC_CODE, 16, 6, DBG_NFO_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_BYPASS, 22, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(DBG_NFO_PLL_SHARED2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED2_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON2_PLL_SHARED2_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON1_PLL_SHARED2_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED2_RESETB_REG, 31, 1, PLL_CON6_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED2_STABLE_REG, 29, 1, PLL_CON6_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_SHARED2_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON4_PLL_SHARED2_MASK_SEL, 18, 1, PLL_CON4_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED2_LDO_SEL, 23, 1, PLL_CON6_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON6_PLL_SHARED2_LDO_CON, 20, 3, PLL_CON6_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_REV, 24, 6, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_R_CON, 20, 4, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_C_CON, 16, 4, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_ICP, 8, 4, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_EXT_AFC, 0, 6, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_EN_FOUT, 15, 1, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_EN_FOUT2, 14, 1, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_EN_FOUT3, 13, 1, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON7_PLL_SHARED2_EN_FOUT4, 12, 1, PLL_CON7_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_STABLE, 29, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON9_PLL_CPUCL0_K, 0, 32, PLL_CON9_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON8_PLL_CPUCL0_F, 0, 32, PLL_CON8_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_SSCGEN, 16, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON5_PLL_CPUCL0_MFR, 16, 8, PLL_CON5_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON5_PLL_CPUCL0_MRR, 24, 6, PLL_CON5_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON5_PLL_CPUCL0_SEL_PF, 30, 2, PLL_CON5_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_AFC_ENB, 20, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(DBG_NFO_PLL_CPUCL0_AFC_CODE, 16, 6, DBG_NFO_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_BYPASS, 22, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL0_MUX_SEL, 4, 1, PLL_CON0_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL0_MUX_BUSY, 16, 1, PLL_CON0_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_LOCK_FAIL, 27, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(DBG_NFO_PLL_CPUCL0_DEBUG_INFO, 0, 16, DBG_NFO_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON2_PLL_CPUCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON2_PLL_CPUCL0_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL0_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_LOCK_EN, 26, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL0_RESETB_REG, 31, 1, PLL_CON6_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL0_STABLE_REG, 29, 1, PLL_CON6_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_CPUCL0_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL0_MASK_SEL, 18, 1, PLL_CON4_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL0_LDO_SEL, 23, 1, PLL_CON6_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL0_LDO_CON, 20, 3, PLL_CON6_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_REV, 24, 6, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_R_CON, 20, 4, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_C_CON, 16, 4, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_ICP, 8, 4, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_EXT_AFC, 0, 6, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_EN_FOUT, 15, 1, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_EN_FOUT2, 14, 1, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_EN_FOUT3, 13, 1, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON7_PLL_CPUCL0_EN_FOUT4, 12, 1, PLL_CON7_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_STABLE, 29, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_ICP, 6, 2, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_AFC_ENB, 20, 1, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_EXT_AFC, 0, 5, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(DBG_NFO_PLL_CPUCL1_AFC_CODE, 16, 5, DBG_NFO_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_FOUT_MASK, 25, 1, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_RSEL, 28, 4, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_BYPASS, 22, 1, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_MUX_SEL, 4, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_MUX_BUSY, 16, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON4_PLL_CPUCL1_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_LOCK_FAIL, 27, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(DBG_NFO_PLL_CPUCL1_DEBUG_INFO, 0, 16, DBG_NFO_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON2_PLL_CPUCL1_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON2_PLL_CPUCL1_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON1_PLL_CPUCL1_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_LOCK_EN, 26, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL1_RESETB_REG, 31, 1, PLL_CON6_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL1_VREG_CON, 8, 3, PLL_CON6_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL1_VBGR_CON, 0, 8, PLL_CON6_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON6_PLL_CPUCL1_STABLE_REG, 29, 1, PLL_CON6_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_CPUCL1_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_ENABLE, 31, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_STABLE, 29, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_P, 8, 6, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_M, 16, 10, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_S, 0, 3, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON9_PLL_DSU_K, 0, 32, PLL_CON9_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON8_PLL_DSU_F, 0, 32, PLL_CON8_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_SSCGEN, 16, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON5_PLL_DSU_MFR, 16, 8, PLL_CON5_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON5_PLL_DSU_MRR, 24, 6, PLL_CON5_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON5_PLL_DSU_SEL_PF, 30, 2, PLL_CON5_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_AFC_ENB, 20, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(DBG_NFO_PLL_DSU_AFC_CODE, 16, 6, DBG_NFO_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_BYPASS, 22, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON0_PLL_DSU_MUX_SEL, 4, 1, PLL_CON0_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON0_PLL_DSU_MUX_BUSY, 16, 1, PLL_CON0_PLL_DSU),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_DSU_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_LOCK_FAIL, 27, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(DBG_NFO_PLL_DSU_DEBUG_INFO, 0, 16, DBG_NFO_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON2_PLL_DSU_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON2_PLL_DSU_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON1_PLL_DSU_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_LOCK_EN, 26, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON6_PLL_DSU_RESETB_REG, 31, 1, PLL_CON6_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON6_PLL_DSU_STABLE_REG, 29, 1, PLL_CON6_PLL_DSU),
|
|
SFR_ACCESS(PLL_LOCKTIME_REG_PLL_DSU_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_AFCINIT_SEL, 19, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON4_PLL_DSU_MASK_SEL, 18, 1, PLL_CON4_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON6_PLL_DSU_LDO_SEL, 23, 1, PLL_CON6_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON6_PLL_DSU_LDO_CON, 20, 3, PLL_CON6_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_REV, 24, 6, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_R_CON, 20, 4, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_C_CON, 16, 4, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_ICP, 8, 4, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_EXT_AFC, 0, 6, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_EN_FOUT, 15, 1, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_EN_FOUT2, 14, 1, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_EN_FOUT3, 13, 1, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON7_PLL_DSU_EN_FOUT4, 12, 1, PLL_CON7_PLL_DSU),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_ENABLE, 31, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_STABLE, 29, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_DIV_P, 8, 6, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_DIV_M, 16, 10, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_DIV_S, 0, 3, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_ICP, 6, 2, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_AFC_ENB, 20, 1, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_EXT_AFC, 0, 5, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(DBG_NFO_PLL_MIF_AFC_CODE, 16, 6, DBG_NFO_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_FOUT_MASK, 25, 1, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_RSEL, 28, 4, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_BYPASS, 22, 1, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_MUX_SEL, 4, 1, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_MUX_BUSY, 16, 1, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(DBG_NFO_PLL_MIF_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON2_PLL_MIF_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON2_PLL_MIF_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_LOCK_EN, 26, 1, PLL_CON3_PLL_MIF),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_ENABLE, 31, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_STABLE, 29, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_P, 8, 6, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_M, 16, 10, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_S, 0, 3, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_ICP, 6, 2, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_AFC_ENB, 20, 1, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_EXT_AFC, 0, 5, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(DBG_NFO_PLL_MIF_S2D_AFC_CODE, 16, 5, DBG_NFO_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_FOUT_MASK, 25, 1, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_RSEL, 28, 4, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_BYPASS, 22, 1, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_MUX_SEL, 4, 1, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_MUX_BUSY, 16, 1, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(DBG_NFO_PLL_MIF_S2D_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON2_PLL_MIF_S2D_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON2_PLL_MIF_S2D_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_LOCK_EN, 26, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMGP_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMGP_PERI_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_I3C_PMIC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_DBGCORE_UART_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AP2GNSS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AP2GNSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUB_PERI_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_USI0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_I2C_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF3_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF2_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_CPU_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_FM_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF4_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF5_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_UAIF6_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_DSIF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_CPU_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_CPU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_PCMC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUSC_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_BUSC_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUSC_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_BUSC_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUSC_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_BUSC_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUSC_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_BUSC_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_BUSC_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_BUSC_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_TIMER_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_TIMER_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_TIMER_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_TIMER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_TIMER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_USI0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_USI1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_USI2_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_I2C_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_USI3_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUBVTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_I2C_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_USI0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_USI4_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_I3C_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_USI1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_USI2_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CMGP_USI3_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MFC_MFC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TAA_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ISP_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUD_CPU_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_M2M_MSCL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK2_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CMU_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NPU0_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ALIVE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_IP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_USB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TNR_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMU_BOOST_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_G3D_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CSIS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_GDC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_USB_USB20DRD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NPUS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_SSS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_BUSC_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK3_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK4_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_BUS_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_BUS_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_G3D_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK5_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DSU_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_DSIM_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUD_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CORE_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CORE_GIC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CPUCL0_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CPUCL0_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CPUCL0_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CPUCL1_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CPUCL1_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_DSU_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_DSU_PLL),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_DSU_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_DSU_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(DBG_NFO_MUX_MIF_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_S2D_CORE_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_USB_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_USB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_USB20DRD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_USB20DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USB_USB20DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_USB_USB20DRD),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_USB_USB20DRD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_VTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_DMIC_AUD_SELECT, 0, 1, CLK_CON_MUX_MUX_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_DMIC_AUD_BUSY, 16, 1, CLK_CON_MUX_MUX_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_DMIC_AUD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_VTS_DMIC_AUD),
|
|
SFR_ACCESS(DBG_NFO_MUX_VTS_DMIC_AUD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_SERIAL_LIF_SELECT, 0, 1, CLK_CON_MUX_MUX_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_SERIAL_LIF_BUSY, 16, 1, CLK_CON_MUX_MUX_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_VTS_SERIAL_LIF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(DBG_NFO_MUX_VTS_SERIAL_LIF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_VTS_DMIC_IF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ALIVE_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_ALIVE_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_RCO_ALIVE_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_ALIVE_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_ALIVE_TIMER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_ALIVE_TIMER_BUSY, 16, 1, PLL_CON0_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_ALIVE_TIMER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_ALIVE_TIMER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_ALIVE_TIMER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUD_CPU_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUD_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, 16, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_PCMC_CLK_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CP_PCMC_CLK_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_PCMC_CLK_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_BUSC_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_CHUB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_CHUB_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_CHUB_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_CHUB_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_CHUB_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLK_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUB_PERI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUB_RCO_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CHUBVTS_RCO_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMGP_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMGP_PERI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMGP_RCO_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_G3D_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CORE_SSS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CSIS_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_DSIM_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DSU_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ISP_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_M2M_MSCL_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_GDC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MFC_MFC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_BUSP_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, 4, 2, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(DBG_NFO_CLKMUX_MIF_DDRPHY2X_DEBUG_INFO, 0, 16, DBG_NFO_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NPU0_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NPUS_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI00_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI01_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI02_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI03_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI04_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI05_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI_I2C_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_UART_DBG_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERI_USI06_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, 4, 2, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, 16, 1, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TAA_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TNR_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_USB_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_USB_USB20DRD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_USB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_USB_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKAUD_USB_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKAUD_USB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKAUD_USB_USB20DRD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_VTS_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLKCMU_VTS_RCO_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(DBG_NFO_MUX_CLK_AUD_DMIC_BUS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(DBG_NFO_MUX_HCHGEN_CLK_AUD_CPU_DEBUG_INFO, 0, 16, DBG_NFO_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CMGP_PERI_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ALIVE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CMGP_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ALIVE_I3C_PMIC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ALIVE_DBGCORE_UART_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CHUBVTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_PERI_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_PERI_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_PERI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CHUB_PERI_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ALIVE_USI0_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ALIVE_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ALIVE_I2C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ALIVE_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_CPU_PCLKDBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_FM_SPDY_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_FM_SPDY),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF0_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF1_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF2_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF3_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_CPU_ACLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_CNT_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF4_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_DSIF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, 0, 10, CLK_CON_DIV_DIV_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_FM),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_FM_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_FM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF5_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_UAIF6_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_MCLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_MCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_MCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_MCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_AUDIF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSD_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSD),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_BUSD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_PCMC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKAUD_USB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_USB20DRD_DIVRATIO, 0, 5, CLK_CON_DIV_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_USB20DRD_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_USB_USB20DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(DBG_NFO_CLKAUD_USB_USB20DRD_DEBUG_INFO, 0, 16, DBG_NFO_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_AUD_CPU_ACP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_DMIC_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_AUD_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_DMIC_BUSY, 16, 1, CLK_CON_DIV_CLK_AUD_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_AUD_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_DMIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLK_AUD_DMIC),
|
|
SFR_ACCESS(DBG_NFO_CLK_AUD_DMIC_DEBUG_INFO, 0, 16, DBG_NFO_CLK_AUD_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_BUSC_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_BUSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_USI0_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_USI1_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_USI2_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_I2C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_USI3_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CHUBVTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CHUBVTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_I2C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_USI0_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_USI4_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_I3C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_USI1_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_USI2_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CMGP_USI3_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_ALIVE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_G3D_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_PERI_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_DPU_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MFC_MFC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CORE_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_TAA_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_ISP_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_AUD_CPU_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_MSCL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_MSCL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_MSCL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_M2M_MSCL_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL0_DBG_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK0_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK1_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK2_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_HSI_UFS_EMBD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU0_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_NPU0_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MIF_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_PERI_IP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_USB_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_TNR_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CMU_BOOST_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CORE_G3D_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CSIS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MCSC_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_HSI_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_PERI_MMC_CARD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MCSC_GDC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB20DRD_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB20DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB20DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_USB_USB20DRD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_NPUS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_SSS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_SSS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_SSS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CORE_SSS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_BUSC_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK3_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK4_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK5_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_DSU_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL0_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_DSIM_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_DSIM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_DSIM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_DPU_DSIM_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_MCSC_MCSC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(DBG_NFO_CLKCMU_AUD_BUS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CORE_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_SHORTSTOP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL1_SHORTSTOP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL1_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL1_HTU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CSIS_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_DPU_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_DSU_SHORTSTOP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DSU_SHORTSTOP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_ACLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_PCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_ISP_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ISP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_M2M_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_MCSC_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_MFC_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MFC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_NPU0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_NPU0_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NPU0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_NPUS_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI00_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI01_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI02_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI03_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI04_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI05_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI_I2C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_UART_DBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_PERI_USI06_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERI_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_TAA_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TNR_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TNR_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TNR_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_BUSP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TNR_BUSP),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_TNR_BUSP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TNR_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_VTS_DMIC_IF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_VTS_DMIC_IF_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_VTS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_BUSY, 16, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD),
|
|
SFR_ACCESS(DBG_NFO_DIV_VTS_DMIC_AUD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(DBG_NFO_DIV_VTS_DMIC_AUD_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_DIV_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(DBG_NFO_DIV_VTS_SERIAL_LIF_CORE_DEBUG_INFO, 0, 16, DBG_NFO_DIV_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_BUSY, 16, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_VTS_SERIAL_LIF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(DBG_NFO_DIV_VTS_SERIAL_LIF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL1_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_DSU_CLUSTER_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_BUSD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU0_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NPU0_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_NPU0_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(DBG_NFO_DIV_CLK_NPUS_BUS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_VTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_VTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_VTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2GNSS_CLK_CG_VAL, 21, 1, CLK_CON_GAT_AP2GNSS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2GNSS_CLK_MANUAL, 20, 1, CLK_CON_GAT_AP2GNSS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2GNSS_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_AP2GNSS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUB_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CHUB_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUB_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CHUB_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUB_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CHUB_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CMGP_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CMGP_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CMGP_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_AP2CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED0_CLK_MANUAL, 20, 1, CLK_CON_GAT_AP2CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_AP2CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_AP2CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED1_CLK_MANUAL, 20, 1, CLK_CON_GAT_AP2CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_AP2CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_AP2CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED2_CLK_MANUAL, 20, 1, CLK_CON_GAT_AP2CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_AP2CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_HISPEEDY_CLK_CG_VAL, 21, 1, CLK_CON_GAT_AP2CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_HISPEEDY_CLK_MANUAL, 20, 1, CLK_CON_GAT_AP2CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_AP2CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_AP2CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD_S2D),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_CHUB_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_CHUB_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_CHUB_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_CHUB_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_ENABLE, 0, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, 0, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_ALIVE0_QCH_ENABLE, 0, 1, QCH_CON_I2C_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_ALIVE0_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_ALIVE0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_ALIVE0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_P_ENABLE, 0, 1, QCH_CON_I3C_APM_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C_APM_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_I3C_APM_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_APM_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_S_ENABLE, 0, 1, QCH_CON_I3C_APM_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C_APM_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_S_EXPIRE_VAL, 16, 10, QCH_CON_I3C_APM_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_APM_PMIC_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_APM_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_BT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_BT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_BT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_WL_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_WL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_WL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_BT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_BT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_BT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_WLBT_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_WL_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_WL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_WL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_WLBT_WL_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSS_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSS_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GNSS_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GNSS_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_ABOX_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_WLBT_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_WLBT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, 0, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_C_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_C_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_C_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_C_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_WLBT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_C_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_C_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_C_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_C_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_ALIVE0_QCH_ENABLE, 0, 1, QCH_CON_USI_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_ALIVE0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_ALIVE0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_ALIVE0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_ALIVE0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_ENABLE, 0, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, 0, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSC_CMU_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUSC_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_BUSC_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUSC_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_BUSC_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUSC_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_BUSC_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUSC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_BUSC_QCH_ENABLE, 0, 1, QCH_CON_PDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_PERI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_AXI_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AXI_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AXI_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AXI_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUBEINT_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_CHUBEINT_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUBEINT_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_CHUBEINT_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUBEINT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_CHUBEINT_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUBEINT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_CHUBEINT_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, 0, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_ENABLE, 0, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB1_QCH_ENABLE, 0, 1, QCH_CON_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB1_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB3_QCH_ENABLE, 0, 1, QCH_CON_I2C_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_ENABLE, 0, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_ENABLE, 0, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_M_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_VTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_M_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_S_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_VTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_S_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_C_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_C_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_C_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_C_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, 0, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_ENABLE, 0, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_S_ENABLE, 0, 1, QCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_S_EXPIRE_VAL, 16, 10, QCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_ENABLE, 0, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_BDU_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_G_BDU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_BDU_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_G_BDU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_G_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_SSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_ENABLE, 0, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE, 0, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ, 1, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_CPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_SSS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_SSS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_SSS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PUF_QCH_ENABLE, 0, 1, DMYQCH_CON_PUF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PUF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PUF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PUF_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, 0, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_ENABLE, 0, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_HSI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_WLBT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ISP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPU0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TAA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_USB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_WLBT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D_DIT_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_ACEL_D_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_ACEL_D_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_ACEL_D_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_ACEL_D_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_ACEL_D_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CORE_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_CORE_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_ENABLE, 0, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CSSYS_QCH_ENABLE, 0, 1, DMYQCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_BIG_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_BIG),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_BIG_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_BIG),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_BIG_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_BIG),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_TOP_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_TOP_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_TOP_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_C2_PDP_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_C2_PDP_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_C2_PDP_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_PDP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_C2_PDP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_ENABLE, 0, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, 1, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CSIS_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CSIS_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CSIS_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CSIS_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CSIS_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CSIS_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CSIS_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CSIS_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CSIS_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CSIS_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CSIS_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CSIS_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CSIS_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CSIS_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CSIS_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSIS_D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CSIS_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE2_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_DMA),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_DMA),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_DMA),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_DMA),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_DPP),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_DPP),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_DPP),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_DPP),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_C2SERV_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_C2SERV_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_C2SERV_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPU_QCH_DPU_C2SERV_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_C2SERV),
|
|
SFR_ACCESS(DMYQCH_CON_DPU_QCH_ENABLE, 0, 1, DMYQCH_CON_DPU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DPU_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DPU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_DPU_CMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU_CMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU_CMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_CMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_ENABLE, 0, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_CPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_ENABLE, 0, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE, 0, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_UFS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_UFS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI_CMU_HSI_QCH_ENABLE, 0, 1, QCH_CON_HSI_CMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI_CMU_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI_CMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI_CMU_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI_CMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI_CMU_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI_CMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_HSI_QCH_S2_ENABLE, 0, 1, QCH_CON_S2MPU_D_HSI_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_HSI_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_S2MPU_D_HSI_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_HSI_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_S2MPU_D_HSI_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_HSI_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2MPU_D_HSI_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_HSI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_HSI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ISP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_ENABLE, 0, 1, QCH_CON_ISP_CMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISP_CMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISP_CMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ISP_CMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S00_ENABLE, 0, 1, QCH_CON_ITP_DNS_QCH_S00),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S00_CLOCK_REQ, 1, 1, QCH_CON_ITP_DNS_QCH_S00),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S00_EXPIRE_VAL, 16, 10, QCH_CON_ITP_DNS_QCH_S00),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S00_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_DNS_QCH_S00),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S01_ENABLE, 0, 1, QCH_CON_ITP_DNS_QCH_S01),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S01_CLOCK_REQ, 1, 1, QCH_CON_ITP_DNS_QCH_S01),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S01_EXPIRE_VAL, 16, 10, QCH_CON_ITP_DNS_QCH_S01),
|
|
SFR_ACCESS(QCH_CON_ITP_DNS_QCH_S01_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_DNS_QCH_S01),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_ISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ISP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ISP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_ISP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_ISP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_ISP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_ISP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_ISP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_ISP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_ISP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_ISP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_ISP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ISP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_ENABLE, 0, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S2_ENABLE, 0, 1, QCH_CON_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S1_ENABLE, 0, 1, QCH_CON_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_ENABLE, 0, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_ENABLE, 0, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_ISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_TAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ORBMCH_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_C2CLK_ENABLE, 0, 1, QCH_CON_ORBMCH_QCH_C2CLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_C2CLK_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH_QCH_C2CLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_C2CLK_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH_QCH_C2CLK),
|
|
SFR_ACCESS(QCH_CON_ORBMCH_QCH_C2CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH_QCH_C2CLK),
|
|
SFR_ACCESS(QCH_CON_PPMU_GDC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CAM_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_GDC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MFC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MFC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_ENABLE, 0, 1, QCH_CON_QE_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_DMC_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MODEM_CMU_MODEM_QCH_ENABLE, 0, 1, QCH_CON_MODEM_CMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_MODEM_CMU_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_MODEM_CMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_MODEM_CMU_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MODEM_CMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_MODEM_CMU_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MODEM_CMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU0_CMU_NPU0_QCH_ENABLE, 0, 1, QCH_CON_NPU0_CMU_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU0_CMU_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPU0_CMU_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU0_CMU_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPU0_CMU_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU0_CMU_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPU0_CMU_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPU0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPU0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0CLK_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_C2A0CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0CLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_C2A0CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0CLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_C2A0CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_C2A0CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1CLK_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_C2A1CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1CLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_C2A1CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1CLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_C2A1CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_C2A1CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE, 0, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERI_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIMMC_QCH_GPIO_ENABLE, 0, 1, QCH_CON_GPIO_PERIMMC_QCH_GPIO),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIMMC_QCH_GPIO_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIMMC_QCH_GPIO),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIMMC_QCH_GPIO_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIMMC_QCH_GPIO),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIMMC_QCH_GPIO_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIMMC_QCH_GPIO),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_ENABLE, 0, 1, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_PERI_QCH_ENABLE, 0, 1, QCH_CON_PPMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_ENABLE, 0, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_PERI_QCH_ENABLE, 0, 1, QCH_CON_S2MPU_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2MPU_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2MPU_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2MPU_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_PERI_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_QCH_ENABLE, 0, 1, QCH_CON_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_DBG_QCH_ENABLE, 0, 1, QCH_CON_UART_DBG_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_DBG_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_DBG_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UART_DBG_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_ENABLE, 0, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI01_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI01_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_ENABLE, 0, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_ENABLE, 0, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_ENABLE, 0, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_ENABLE, 0, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_ENABLE, 0, 1, QCH_CON_USI05_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI05_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_ENABLE, 0, 1, QCH_CON_USI06_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI06_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI07_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI07_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI07_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_PERI_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_ENABLE, 0, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_ENABLE, 0, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_ENABLE, 0, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_TAA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TAA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_TAA_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_ENABLE, 0, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_TAA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE0_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE0_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE0_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE0_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE0_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_TAA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE1_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE1_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE1_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE1_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE1_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP0_ENABLE, 0, 1, QCH_CON_TNR_QCH_MCFP0),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP0_CLOCK_REQ, 1, 1, QCH_CON_TNR_QCH_MCFP0),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP0_EXPIRE_VAL, 16, 10, QCH_CON_TNR_QCH_MCFP0),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_QCH_MCFP0),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP1_ENABLE, 0, 1, QCH_CON_TNR_QCH_MCFP1),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP1_CLOCK_REQ, 1, 1, QCH_CON_TNR_QCH_MCFP1),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP1_EXPIRE_VAL, 16, 10, QCH_CON_TNR_QCH_MCFP1),
|
|
SFR_ACCESS(QCH_CON_TNR_QCH_MCFP1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_QCH_MCFP1),
|
|
SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_ENABLE, 0, 1, QCH_CON_TNR_CMU_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_TNR_CMU_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TNR_CMU_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_CMU_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_TNR_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D_TNR_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_USB_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_USB_QCH_ENABLE, 0, 1, QCH_CON_PPMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_USB_QCH_ENABLE, 0, 1, QCH_CON_S2MPU_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2MPU_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2MPU_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_S2MPU_D_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2MPU_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_USB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_ENABLE, 0, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_EXPIRE_VAL, 16, 10, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_ENABLE, 0, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_CLOCK_REQ, 1, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_EXPIRE_VAL, 16, 10, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_ENABLE, 0, 1, QCH_CON_USB_CMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_USB_CMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USB_CMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB_CMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_USB_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_CM4_VTS_QCH_CPU_ENABLE, 0, 1, QCH_CON_CM4_VTS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_VTS_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_CM4_VTS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_VTS_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_CM4_VTS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_VTS_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CM4_VTS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_VTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_S_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_S_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_VTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_M_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_M_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_M_VTS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_VTS_QCH_ENABLE, 0, 1, QCH_CON_TIMER_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_ENABLE, 0, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_ENABLE, 0, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BUSC_CMU_BUSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUSC_CMU_BUSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPU_CMU_DPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPU_CMU_DPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GNSS_CMU_GNSS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GNSS_CMU_GNSS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI_CMU_HSI_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI_CMU_HSI_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ISP_CMU_ISP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISP_CMU_ISP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MODEM_CMU_MODEM_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MODEM_CMU_MODEM_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPU0_CMU_NPU0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPU0_CMU_NPU0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPUS_CMU_NPUS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPUS_CMU_NPUS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERI_CMU_PERI_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERI_CMU_PERI_CONTROLLER_OPTION),
|
|
SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, TAA_CMU_TAA_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, TAA_CMU_TAA_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, TNR_CMU_TNR_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, TNR_CMU_TNR_CONTROLLER_OPTION),
|
|
SFR_ACCESS(USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, USB_CMU_USB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, USB_CMU_USB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
|
|
};
|