414 lines
9.7 KiB
C
Executable file
414 lines
9.7 KiB
C
Executable file
#include "../pmucal_common.h"
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#include "../pmucal_cpu.h"
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#include "../pmucal_local.h"
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#include "../pmucal_rae.h"
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#include "../pmucal_system.h"
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#include "../pmucal_powermode.h"
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#include "flexpmu_cal_cpu_exynos2100.h"
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#include "flexpmu_cal_local_exynos2100.h"
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#include "flexpmu_cal_p2vmap_exynos2100.h"
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#include "flexpmu_cal_system_exynos2100.h"
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#include "flexpmu_cal_powermode_exynos2100.h"
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#include "flexpmu_cal_define_exynos2100.h"
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#if IS_ENABLED(CONFIG_CP_PMUCAL)
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#include "../pmucal_cp.h"
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#include "pmucal_cp_exynos2100.h"
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#endif
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#include "cmucal-node.c"
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#include "cmucal-qch.c"
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#include "cmucal-sfr.c"
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#include "cmucal-vclk.c"
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#include "cmucal-vclklut.c"
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#include "clkout_exynos2100.c"
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#include "acpm_dvfs_exynos2100.h"
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#include "asv_exynos2100.h"
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#include "../ra.h"
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//#include "cmu-pmu_map.h"
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#include <linux/smc.h>
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#include <soc/samsung/exynos-cpupm.h>
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/* defines for EWF WA */
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#define EXYNOS2100_CMU_BUS0_BASE (0x1A300000)
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#define QCH_CON_TREX_D0_BUS0_QCH_OFFSET (0x30f0)
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#define IGNORE_FORCE_PM_EN (2)
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/* defines for PLL_MMC SSC settings */
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#define EXYNOS2100_CMU_TOP_BASE (0x1a330000)
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#define PLL_CON0_PLL_MMC (0x140)
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#define PLL_CON1_PLL_MMC (0x144)
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#define PLL_CON2_PLL_MMC (0x148)
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#define PLL_CON3_PLL_MMC (0x14c)
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#define PLL_CON4_PLL_MMC (0x150)
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#define PLL_CON5_PLL_MMC (0x154)
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#define PLL_ENABLE_SHIFT (31)
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#define MANUAL_MODE (0x2)
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#define PLL_MMC_MUX_BUSY_SHIFT (16)
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#define MFR_MASK (0xff)
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#define MRR_MASK (0x3f)
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#define MFR_SHIFT (16)
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#define MRR_SHIFT (24)
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#define SSCG_EN (16)
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/* defines for RCO_400 off settings */
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#define EXYNOS2100_CMU_ALIVE_BASE (0x15800000)
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#define OSC_CON0_RCO_400 (0x100)
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#define OSC_CON3_RCO_400 (0x10C)
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#define MUX_CLKCMU_VTS_BUS (0x1004)
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#define MUX_CLKCMU_CMGP_ADC (0x101c)
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#define DIV_CLKCMU_CMGP_ADC (0x1818)
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#define RCO_400_ENABLE (31)
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#define RCO_400_STABLE (29)
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#define RCO_400_MUX_SEL (4)
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/* defines for CPUCL2 smpl_warn SW release */
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//#define EXYNOS9830_CCMU_CPUCL2_BASE (0x1d200000)
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//#define CCMU_SMPL_WARN_CFG (0x9c)
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//#define SW_RELEASE (1 << 26)
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void __iomem *cmu_top;
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void __iomem *cmu_bus0;
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void __iomem *ccmu_cpucl2;
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void __iomem *cmu_alive;
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#define NUM_SKIP_CMU_SFR (4)
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u32 skip_cmu_sfr[NUM_SKIP_CMU_SFR] = {0x1a331054, 0x1a331860, 0x1a3318fc, 0x1a33194c};
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unsigned int frac_rpll_list[10];
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unsigned int frac_rpll_size;
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unsigned int exynos2100_frac_rpll_list[] = {
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PLL_AUD0,
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PLL_AUD1,
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PLL_MMC,
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};
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void cmu_adc_rco_400_contorl(void)
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{
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unsigned int reg;
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reg = __raw_readl(cmu_alive + MUX_CLKCMU_CMGP_ADC);
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reg &= ~(1 << 0);
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__raw_writel(reg, cmu_alive + MUX_CLKCMU_CMGP_ADC);
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reg = __raw_readl(cmu_alive + DIV_CLKCMU_CMGP_ADC);
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reg &= ~(0xf << 0);
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reg |= (1 << 0);
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__raw_writel(reg, cmu_alive + DIV_CLKCMU_CMGP_ADC);
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}
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int cmu_vts_rco_400_control(bool on)
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{
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unsigned int reg, tmp;
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unsigned int timeout = 0;
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if (on == 1) {
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reg = __raw_readl(cmu_alive + OSC_CON3_RCO_400);
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reg |= (1 << RCO_400_ENABLE);
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__raw_writel(reg, cmu_alive + OSC_CON3_RCO_400);
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while (1) {
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tmp = __raw_readl(cmu_alive + OSC_CON3_RCO_400);
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if (((tmp >> RCO_400_STABLE) & 0x1) == 1)
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break;
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timeout++;
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udelay(1);
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if (timeout > 10000) {
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pr_err("RCO_400 %s:timed out OSC_CON3_RCO_400 : 0x%x\n", __func__, tmp);
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return -ETIMEDOUT;
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}
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}
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reg = __raw_readl(cmu_alive + OSC_CON0_RCO_400);
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reg |= (1 << RCO_400_MUX_SEL);
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__raw_writel(reg, cmu_alive + OSC_CON0_RCO_400);
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reg = __raw_readl(cmu_alive + MUX_CLKCMU_VTS_BUS);
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reg |= (1 << 0);
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__raw_writel(reg, cmu_alive + MUX_CLKCMU_VTS_BUS);
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} else {
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reg = __raw_readl(cmu_alive + MUX_CLKCMU_VTS_BUS);
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reg &= ~(1 << 0);
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__raw_writel(reg, cmu_alive + MUX_CLKCMU_VTS_BUS);
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reg = __raw_readl(cmu_alive + OSC_CON0_RCO_400);
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reg &= ~(1 << RCO_400_MUX_SEL);
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__raw_writel(reg, cmu_alive + OSC_CON0_RCO_400);
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reg = __raw_readl(cmu_alive + OSC_CON3_RCO_400);
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reg &= ~(1 << RCO_400_ENABLE);
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__raw_writel(reg, cmu_alive + OSC_CON3_RCO_400);
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}
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return 0;
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} EXPORT_SYMBOL(cmu_vts_rco_400_control);
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static int cmu_stable_done(void __iomem *cmu,
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unsigned char shift,
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unsigned int done,
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int usec)
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{
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unsigned int result;
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do {
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result = get_bit(cmu, shift);
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if (result == done)
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return 0;
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udelay(1);
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} while (--usec > 0);
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return -EVCLKTIMEOUT;
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}
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int pll_mmc_enable(int enable)
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{
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unsigned int reg;
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unsigned int cmu_mode;
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int ret;
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if (!cmu_top) {
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pr_err("%s: cmu_top cmuioremap failed\n", __func__);
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return -1;
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}
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/* set PLL to manual mode */
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cmu_mode = readl(cmu_top + PLL_CON1_PLL_MMC);
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writel(MANUAL_MODE, cmu_top + PLL_CON1_PLL_MMC);
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if (!enable) {
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/* select oscclk */
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reg = readl(cmu_top + PLL_CON0_PLL_MMC);
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reg &= ~(PLL_MUX_SEL);
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writel(reg, cmu_top + PLL_CON0_PLL_MMC);
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ret = cmu_stable_done(cmu_top + PLL_CON0_PLL_MMC, PLL_MMC_MUX_BUSY_SHIFT, 0, 100);
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if (ret)
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pr_err("pll mux change time out, \'PLL_MMC\'\n");
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}
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/* setting ENABLE of PLL */
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reg = readl(cmu_top + PLL_CON3_PLL_MMC);
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if (enable)
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reg |= 1 << PLL_ENABLE_SHIFT;
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else
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reg &= ~(1 << PLL_ENABLE_SHIFT);
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writel(reg, cmu_top + PLL_CON3_PLL_MMC);
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if (enable) {
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/* wait for PLL stable */
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ret = cmu_stable_done(cmu_top + PLL_CON3_PLL_MMC, PLL_STABLE_SHIFT, 1, 100);
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if (ret)
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pr_err("pll time out, \'PLL_MMC\' %d\n", enable);
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/* select FOUT_PLL_MMC */
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reg = readl(cmu_top + PLL_CON0_PLL_MMC);
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reg |= PLL_MUX_SEL;
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writel(reg, cmu_top + PLL_CON0_PLL_MMC);
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ret = cmu_stable_done(cmu_top + PLL_CON0_PLL_MMC, PLL_MMC_MUX_BUSY_SHIFT, 0, 100);
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if (ret)
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pr_err("pll mux change time out, \'PLL_MMC\'\n");
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}
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/* restore PLL mode */
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writel(cmu_mode, cmu_top + PLL_CON1_PLL_MMC);
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return ret;
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}
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int cal_pll_mmc_check(void)
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{
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unsigned int reg;
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bool ret = false;
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reg = readl(cmu_top + PLL_CON4_PLL_MMC);
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if (reg & (1 << SSCG_EN))
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ret = true;
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return ret;
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}EXPORT_SYMBOL(cal_pll_mmc_check);
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int cal_pll_mmc_set_ssc(unsigned int mfr, unsigned int mrr, unsigned int ssc_on)
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{
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unsigned int reg;
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int ret = 0;
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/* disable PLL_MMC */
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ret = pll_mmc_enable(0);
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if (ret) {
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pr_err("%s: pll_mmc_disable failed\n", __func__);
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return ret;
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}
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/* setting MFR, MRR */
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reg = readl(cmu_top + PLL_CON5_PLL_MMC);
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reg &= ~((MFR_MASK << MFR_SHIFT) | (MRR_MASK << MRR_SHIFT));
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if (ssc_on)
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reg |= ((mfr & MFR_MASK) << MFR_SHIFT) | ((mrr & MRR_MASK) << MRR_SHIFT);
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writel(reg, cmu_top + PLL_CON5_PLL_MMC);
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/* setting SSCG_EN */
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reg = readl(cmu_top + PLL_CON4_PLL_MMC);
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if (ssc_on)
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reg |= 1 << SSCG_EN;
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else
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reg &= ~(1 << SSCG_EN);
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writel(reg, cmu_top + PLL_CON4_PLL_MMC);
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/* enable PLL_MMC */
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ret = pll_mmc_enable(1);
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if (ret)
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pr_err("%s: pll_mmc_enable failed\n", __func__);
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return ret;
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}EXPORT_SYMBOL(cal_pll_mmc_set_ssc);
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void exynos2100_cal_data_init(void)
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{
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int i;
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pr_info("%s: cal data init\n", __func__);
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/* cpu inform sfr initialize */
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pmucal_sys_powermode[SYS_SICD] = CPU_INFORM_SICD;
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pmucal_sys_powermode[SYS_SLEEP] = CPU_INFORM_SLEEP;
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pmucal_sys_powermode[SYS_SLEEP_HSI1ON] = CPU_INFORM_SLEEP_HSI1ON;
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cpu_inform_c2 = CPU_INFORM_C2;
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cpu_inform_cpd = CPU_INFORM_CPD;
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cmu_top = ioremap(EXYNOS2100_CMU_TOP_BASE, SZ_4K);
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if (!cmu_top)
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pr_err("%s: cmu_top ioremap failed\n", __func__);
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cmu_bus0 = ioremap(EXYNOS2100_CMU_BUS0_BASE, SZ_16K);
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if (!cmu_bus0)
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pr_err("%s: cmu_bus0 ioremap failed\n", __func__);
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cmu_alive = ioremap(EXYNOS2100_CMU_ALIVE_BASE, SZ_8K);
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if (!cmu_alive)
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pr_err("%s: cmu_alive ioremap failed\n", __func__);
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// ccmu_cpucl2 = ioremap(EXYNOS2100_CCMU_CPUCL2_BASE, SZ_4K);
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// if (!ccmu_cpucl2)
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// pr_err("%s: ccmu_cpucl2 ioremap failed\n", __func__);
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frac_rpll_size = ARRAY_SIZE(exynos2100_frac_rpll_list);
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for (i = 0; i < frac_rpll_size; i++)
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frac_rpll_list[i] = exynos2100_frac_rpll_list[i];
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cmu_adc_rco_400_contorl();
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}
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void (*cal_data_init)(void) = exynos2100_cal_data_init;
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/*
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static void __exynos2100_set_cmuewf(unsigned int index, unsigned int en, void *cmu_cmu)
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{
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unsigned int reg;
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unsigned int reg_idx;
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if (index >= 32) {
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reg_idx = EARLY_WAKEUP_FORCED_ENABLE1;
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index = index - 32;
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} else {
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reg_idx = EARLY_WAKEUP_FORCED_ENABLE0;
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}
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if (en) {
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reg = __raw_readl(cmu_cmu + reg_idx);
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reg |= 1 << index;
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__raw_writel(reg, cmu_cmu + reg_idx);
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} else {
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reg = __raw_readl(cmu_cmu + reg_idx);
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reg &= ~(1 << index);
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__raw_writel(reg, cmu_cmu + reg_idx);
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}
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}
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int exynos2100_set_cmuewf(unsigned int index, unsigned int en, void *cmu_cmu, int *ewf_refcnt)
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{
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unsigned int reg;
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int ret = 0;
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int tmp;
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if (en) {
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__exynos2100_set_cmuewf(index, en, cmu_cmu);
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reg = __raw_readl(cmu_bus0 + QCH_CON_TREX_D0_BUS0_QCH_OFFSET);
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reg |= 1 << IGNORE_FORCE_PM_EN;
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__raw_writel(reg, cmu_bus0 + QCH_CON_TREX_D0_BUS0_QCH_OFFSET);
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ewf_refcnt[index] += 1;
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} else {
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tmp = ewf_refcnt[index] - 1;
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if (tmp == 0) {
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reg = __raw_readl(cmu_bus0 + QCH_CON_TREX_D0_BUS0_QCH_OFFSET);
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reg &= ~(1 << IGNORE_FORCE_PM_EN);
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__raw_writel(reg, cmu_bus0 + QCH_CON_TREX_D0_BUS0_QCH_OFFSET);
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__exynos2100_set_cmuewf(index, en, cmu_cmu);
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} else if (tmp < 0) {
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pr_err("[EWF]%s ref count mismatch. ewf_index:%u\n",__func__, index);
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ret = -EINVAL;
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goto exit;
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}
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ewf_refcnt[index] -= 1;
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}
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exit:
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return ret;
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}
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int (*wa_set_cmuewf)(unsigned int index, unsigned int en, void *cmu_cmu, int *ewf_refcnt) = exynos2100_set_cmuewf;
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*/
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void exynos2100_set_cmu_smpl_warn(void)
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{
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}
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void (*cal_set_cmu_smpl_warn)(void) = exynos2100_set_cmu_smpl_warn;
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bool is_ignore_cmu_dbg(u32 addr)
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{
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int i;
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for (i = 0; i < NUM_SKIP_CMU_SFR; i++) {
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if (addr == skip_cmu_sfr[i])
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return true;
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}
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return false;
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}
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/*
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char *exynos2100_get_pd_name_by_cmu(unsigned int addr)
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{
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int i, map_size;
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map_size = (sizeof(cmu_pmu_map) / sizeof(struct cmu_pmu));
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for (i = 0; i < map_size; i++) {
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if (cmu_pmu_map[i].cmu == addr)
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break;
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}
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if (i < map_size)
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return cmu_pmu_map[i].pmu;
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else
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return NULL;
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}
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char *(*cal_get_pd_name_by_cmu)(unsigned int addr) = exynos2100_get_pd_name_by_cmu;
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*/
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