347 lines
6.5 KiB
Text
Executable file
347 lines
6.5 KiB
Text
Executable file
/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "sprd,sc9836-openphone\0sprd,sc9836";
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model = "Spreadtrum SC9836 Openphone Board";
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soc {
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compatible = "simple-bus";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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ap-apb {
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compatible = "simple-bus";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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serial@70000000 {
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compatible = "sprd,sc9836-uart";
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reg = <0x00 0x70000000 0x00 0x100>;
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interrupts = <0x00 0x02 0xf04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x13>;
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};
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serial@70100000 {
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compatible = "sprd,sc9836-uart";
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reg = <0x00 0x70100000 0x00 0x100>;
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interrupts = <0x00 0x03 0xf04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x14>;
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};
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serial@70200000 {
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compatible = "sprd,sc9836-uart";
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reg = <0x00 0x70200000 0x00 0x100>;
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interrupts = <0x00 0x04 0xf04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x15>;
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};
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serial@70300000 {
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compatible = "sprd,sc9836-uart";
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reg = <0x00 0x70300000 0x00 0x100>;
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interrupts = <0x00 0x05 0xf04>;
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clocks = <0x02>;
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status = "okay";
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phandle = <0x16>;
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};
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};
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};
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clk26mhz {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x18cba80>;
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phandle = <0x02>;
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x00>;
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enable-method = "psci";
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phandle = <0x0a>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x01>;
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enable-method = "psci";
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phandle = <0x0c>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x02>;
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enable-method = "psci";
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phandle = <0x0e>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x03>;
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enable-method = "psci";
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phandle = <0x10>;
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};
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};
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etf@10003000 {
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compatible = "arm,coresight-tmc\0arm,primecell";
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reg = <0x00 0x10003000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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endpoint {
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remote-endpoint = <0x03>;
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phandle = <0x04>;
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};
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};
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};
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};
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funnel@10001000 {
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compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
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reg = <0x00 0x10001000 0x00 0x1000>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x04>;
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phandle = <0x03>;
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};
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};
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};
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in-ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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endpoint {
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remote-endpoint = <0x05>;
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phandle = <0x0b>;
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};
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};
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port@1 {
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reg = <0x01>;
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endpoint {
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remote-endpoint = <0x06>;
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phandle = <0x0d>;
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};
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};
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port@2 {
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reg = <0x02>;
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endpoint {
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remote-endpoint = <0x07>;
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phandle = <0x0f>;
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};
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};
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port@3 {
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reg = <0x03>;
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endpoint {
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remote-endpoint = <0x08>;
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phandle = <0x11>;
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};
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};
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port@4 {
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reg = <0x04>;
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endpoint {
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remote-endpoint = <0x09>;
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phandle = <0x12>;
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};
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};
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};
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};
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etm@10440000 {
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compatible = "arm,coresight-etm4x\0arm,primecell";
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reg = <0x00 0x10440000 0x00 0x1000>;
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cpu = <0x0a>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x0b>;
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phandle = <0x05>;
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};
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};
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};
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};
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etm@10540000 {
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compatible = "arm,coresight-etm4x\0arm,primecell";
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reg = <0x00 0x10540000 0x00 0x1000>;
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cpu = <0x0c>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x0d>;
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phandle = <0x06>;
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};
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};
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};
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};
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etm@10640000 {
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compatible = "arm,coresight-etm4x\0arm,primecell";
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reg = <0x00 0x10640000 0x00 0x1000>;
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cpu = <0x0e>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x0f>;
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phandle = <0x07>;
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};
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};
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};
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};
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etm@10740000 {
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compatible = "arm,coresight-etm4x\0arm,primecell";
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reg = <0x00 0x10740000 0x00 0x1000>;
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cpu = <0x10>;
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x11>;
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phandle = <0x08>;
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};
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};
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};
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};
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stm@10006000 {
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compatible = "arm,coresight-stm\0arm,primecell";
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reg = <0x00 0x10006000 0x00 0x1000 0x00 0x1000000 0x00 0x180000>;
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reg-names = "stm-base\0stm-stimulus-base";
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clocks = <0x02>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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endpoint {
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remote-endpoint = <0x12>;
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phandle = <0x09>;
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};
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};
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};
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};
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interrupt-controller@12001000 {
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compatible = "arm,gic-400";
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reg = <0x00 0x12001000 0x00 0x1000 0x00 0x12002000 0x00 0x2000 0x00 0x12004000 0x00 0x2000 0x00 0x12006000 0x00 0x2000>;
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#interrupt-cells = <0x03>;
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interrupt-controller;
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interrupts = <0x01 0x09 0xf04>;
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phandle = <0x01>;
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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cpu_suspend = <0xc4000001>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
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};
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aliases {
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serial0 = "/soc/ap-apb/serial@70000000";
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serial1 = "/soc/ap-apb/serial@70100000";
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serial2 = "/soc/ap-apb/serial@70200000";
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serial3 = "/soc/ap-apb/serial@70300000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x20000000>;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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__symbols__ {
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uart0 = "/soc/ap-apb/serial@70000000";
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uart1 = "/soc/ap-apb/serial@70100000";
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uart2 = "/soc/ap-apb/serial@70200000";
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uart3 = "/soc/ap-apb/serial@70300000";
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clk26mhz = "/clk26mhz";
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cpu0 = "/cpus/cpu@0";
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cpu1 = "/cpus/cpu@1";
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cpu2 = "/cpus/cpu@2";
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cpu3 = "/cpus/cpu@3";
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etf_in = "/etf@10003000/in-ports/port/endpoint";
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funnel_out_port0 = "/funnel@10001000/out-ports/port/endpoint";
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funnel_in_port0 = "/funnel@10001000/in-ports/port@0/endpoint";
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funnel_in_port1 = "/funnel@10001000/in-ports/port@1/endpoint";
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funnel_in_port2 = "/funnel@10001000/in-ports/port@2/endpoint";
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funnel_in_port3 = "/funnel@10001000/in-ports/port@3/endpoint";
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funnel_in_port4 = "/funnel@10001000/in-ports/port@4/endpoint";
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etm0_out = "/etm@10440000/out-ports/port/endpoint";
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etm1_out = "/etm@10540000/out-ports/port/endpoint";
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etm2_out = "/etm@10640000/out-ports/port/endpoint";
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etm3_out = "/etm@10740000/out-ports/port/endpoint";
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stm_out = "/stm@10006000/out-ports/port/endpoint";
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gic = "/interrupt-controller@12001000";
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};
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};
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