3116 lines
68 KiB
Text
Executable file
3116 lines
68 KiB
Text
Executable file
/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "Qualcomm Technologies, Inc. MSM 8996 MTP";
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compatible = "qcom,msm8996-mtp";
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chosen {
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stdout-path = "serial0";
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};
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clocks {
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xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x124f800>;
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clock-output-names = "xo_board";
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phandle = <0x58>;
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};
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sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x7ffc>;
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clock-output-names = "sleep_clk";
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phandle = <0x6e>;
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};
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x00 0x00>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x03>;
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phandle = <0x05>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x03>;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x00 0x01>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x03>;
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phandle = <0x06>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x00 0x100>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x04>;
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phandle = <0x07>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x04>;
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};
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x00 0x101>;
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enable-method = "psci";
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cpu-idle-states = <0x02>;
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x04>;
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phandle = <0x08>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x05>;
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};
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core1 {
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cpu = <0x06>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x07>;
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};
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core1 {
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cpu = <0x08>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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cpu-sleep-0 {
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compatible = "arm,idle-state";
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idle-state-name = "standalone-power-collapse";
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arm,psci-suspend-param = <0x04>;
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entry-latency-us = <0x82>;
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exit-latency-us = <0x50>;
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min-residency-us = <0x12c>;
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phandle = <0x02>;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8996";
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qcom,dload-mode = <0x09 0x13000>;
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};
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};
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hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <0x0a 0x00 0x1000>;
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#hwlock-cells = <0x01>;
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phandle = <0x0f>;
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};
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memory {
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device_type = "memory";
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reg = <0x00 0x00 0x00 0x00>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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mba@91500000 {
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reg = <0x00 0x91500000 0x00 0x200000>;
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no-map;
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phandle = <0x6f>;
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};
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slpi@90b00000 {
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reg = <0x00 0x90b00000 0x00 0xa00000>;
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no-map;
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phandle = <0x70>;
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};
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venus@90400000 {
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reg = <0x00 0x90400000 0x00 0x700000>;
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no-map;
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phandle = <0x35>;
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};
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adsp@8ea00000 {
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reg = <0x00 0x8ea00000 0x00 0x1a00000>;
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no-map;
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phandle = <0x69>;
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};
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mpss@88800000 {
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reg = <0x00 0x88800000 0x00 0x6200000>;
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no-map;
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phandle = <0x71>;
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};
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smem-mem@86000000 {
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reg = <0x00 0x86000000 0x00 0x200000>;
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no-map;
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phandle = <0x0e>;
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};
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memory@85800000 {
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reg = <0x00 0x85800000 0x00 0x800000>;
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no-map;
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};
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memory@86200000 {
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reg = <0x00 0x86200000 0x00 0x2600000>;
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no-map;
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};
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rmtfs@86700000 {
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compatible = "qcom,rmtfs-mem";
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size = <0x00 0x200000>;
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alloc-ranges = <0x00 0xa0000000 0x00 0x2000000>;
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no-map;
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qcom,client-id = <0x01>;
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qcom,vmid = <0x0f>;
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};
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gpu@8f200000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x90b00000 0x00 0xa00000>;
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no-map;
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phandle = <0x1b>;
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};
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <0x00 0xa8 0x01>;
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qcom,rpm-msg-ram = <0x0b>;
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mboxes = <0x0c 0x00>;
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rpm-requests {
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compatible = "qcom,rpm-msm8996";
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qcom,glink-channels = "rpm_requests";
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phandle = <0x72>;
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qcom,rpmcc {
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compatible = "qcom,rpmcc-msm8996";
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#clock-cells = <0x01>;
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phandle = <0x11>;
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};
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power-controller {
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compatible = "qcom,msm8996-rpmpd";
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#power-domain-cells = <0x01>;
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operating-points-v2 = <0x0d>;
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phandle = <0x73>;
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opp-table {
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compatible = "operating-points-v2";
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phandle = <0x0d>;
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opp1 {
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opp-level = <0x01>;
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phandle = <0x74>;
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};
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opp2 {
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opp-level = <0x02>;
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phandle = <0x75>;
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};
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opp3 {
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opp-level = <0x03>;
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phandle = <0x76>;
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};
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opp4 {
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opp-level = <0x04>;
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phandle = <0x77>;
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};
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opp5 {
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opp-level = <0x05>;
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phandle = <0x78>;
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};
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opp6 {
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opp-level = <0x06>;
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phandle = <0x79>;
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};
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};
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <0x0e>;
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hwlocks = <0x0f 0x03>;
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};
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smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <0x1bb 0x1ad>;
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interrupts = <0x00 0x9e 0x01>;
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mboxes = <0x0c 0x0a>;
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qcom,local-pid = <0x00>;
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qcom,remote-pid = <0x02>;
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master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <0x01>;
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phandle = <0x6a>;
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};
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slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <0x02>;
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phandle = <0x68>;
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};
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};
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smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <0x1b3 0x1ac>;
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interrupts = <0x00 0x1c3 0x01>;
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mboxes = <0x0c 0x0e>;
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qcom,local-pid = <0x00>;
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qcom,remote-pid = <0x01>;
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master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <0x01>;
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phandle = <0x7a>;
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};
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slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <0x02>;
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phandle = <0x7b>;
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};
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};
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smp2p-slpi {
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compatible = "qcom,smp2p";
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qcom,smem = <0x1e1 0x1ae>;
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interrupts = <0x00 0xb2 0x01>;
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mboxes = <0x0c 0x1a>;
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qcom,local-pid = <0x00>;
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qcom,remote-pid = <0x03>;
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slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <0x02>;
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phandle = <0x7c>;
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};
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master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <0x01>;
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phandle = <0x7d>;
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};
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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phandle = <0x7e>;
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phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#clock-cells = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x10 0xc0 0x10 0xbf 0x10 0xd8>;
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clock-names = "aux\0cfg_ahb\0ref";
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resets = <0x10 0x55 0x10 0x65 0x10 0x66>;
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reset-names = "phy\0common\0cfg";
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status = "disabled";
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phandle = <0x7f>;
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lane@35000 {
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reg = <0x35000 0x130 0x35200 0x200 0x35400 0x1dc>;
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#phy-cells = <0x00>;
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clock-output-names = "pcie_0_pipe_clk_src";
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clocks = <0x10 0xb4>;
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clock-names = "pipe0";
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resets = <0x10 0x50>;
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reset-names = "lane0";
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phandle = <0x1d>;
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};
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lane@36000 {
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reg = <0x36000 0x130 0x36200 0x200 0x36400 0x1dc>;
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#phy-cells = <0x00>;
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clock-output-names = "pcie_1_pipe_clk_src";
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clocks = <0x10 0xb9>;
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clock-names = "pipe1";
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resets = <0x10 0x52>;
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reset-names = "lane1";
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phandle = <0x23>;
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};
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lane@37000 {
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reg = <0x37000 0x130 0x37200 0x200 0x37400 0x1dc>;
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#phy-cells = <0x00>;
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clock-output-names = "pcie_2_pipe_clk_src";
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clocks = <0x10 0xbe>;
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clock-names = "pipe2";
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resets = <0x10 0x54>;
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reset-names = "lane2";
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phandle = <0x29>;
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};
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};
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memory@68000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x68000 0x6000>;
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phandle = <0x0b>;
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};
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qfprom@74000 {
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compatible = "qcom,qfprom";
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reg = <0x74000 0x8ff>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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hstx_trim@24e {
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reg = <0x24e 0x02>;
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bits = <0x05 0x04>;
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phandle = <0x56>;
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};
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hstx_trim@24f {
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reg = <0x24f 0x01>;
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bits = <0x01 0x04>;
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phandle = <0x57>;
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};
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gpu_speed_bin@133 {
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reg = <0x133 0x01>;
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bits = <0x05 0x03>;
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phandle = <0x19>;
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};
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};
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rng@83000 {
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compatible = "qcom,prng-ee";
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reg = <0x83000 0x1000>;
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clocks = <0x10 0x98>;
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clock-names = "core";
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phandle = <0x80>;
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};
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clock-controller@300000 {
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compatible = "qcom,gcc-msm8996";
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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#power-domain-cells = <0x01>;
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reg = <0x300000 0x90000>;
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clocks = <0x11 0x4a>;
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clock-names = "cxo2";
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phandle = <0x10>;
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};
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thermal-sensor@4a9000 {
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compatible = "qcom,msm8996-tsens\0qcom,tsens-v2";
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reg = <0x4a9000 0x1000 0x4a8000 0x1000>;
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#qcom,sensors = <0x0d>;
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interrupts = <0x00 0x1ca 0x04 0x00 0x1bd 0x04>;
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interrupt-names = "uplow\0critical";
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#thermal-sensor-cells = <0x01>;
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phandle = <0x6c>;
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};
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thermal-sensor@4ad000 {
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compatible = "qcom,msm8996-tsens\0qcom,tsens-v2";
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reg = <0x4ad000 0x1000 0x4ac000 0x1000>;
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#qcom,sensors = <0x08>;
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interrupts = <0x00 0xb8 0x04 0x00 0x1ae 0x04>;
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interrupt-names = "uplow\0critical";
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#thermal-sensor-cells = <0x01>;
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phandle = <0x6d>;
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};
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syscon@740000 {
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compatible = "syscon";
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reg = <0x740000 0x20000>;
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phandle = <0x0a>;
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};
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syscon@7a0000 {
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compatible = "qcom,tcsr-msm8996\0syscon";
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reg = <0x7a0000 0x18000>;
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phandle = <0x09>;
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};
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clock-controller@8c0000 {
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compatible = "qcom,mmcc-msm8996";
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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#power-domain-cells = <0x01>;
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reg = <0x8c0000 0x40000>;
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assigned-clocks = <0x12 0x0f 0x12 0x03 0x12 0x07 0x12 0x09 0x12 0x0b>;
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assigned-clock-rates = <0x25317c00 0x30479e80 0x3a699d00 0x39387000 0x312c8040>;
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phandle = <0x12>;
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};
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mdss@900000 {
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compatible = "qcom,mdss";
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reg = <0x900000 0x1000 0x9b0000 0x1040 0x9b8000 0x1040>;
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reg-names = "mdss_phys\0vbif_phys\0vbif_nrt_phys";
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power-domains = <0x12 0x0d>;
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interrupts = <0x00 0x53 0x04>;
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interrupt-controller;
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#interrupt-cells = <0x01>;
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clocks = <0x12 0x74>;
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clock-names = "iface";
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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phandle = <0x13>;
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mdp@901000 {
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compatible = "qcom,mdp5";
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reg = <0x901000 0x90000>;
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reg-names = "mdp_phys";
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interrupt-parent = <0x13>;
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interrupts = <0x00 0x04>;
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clocks = <0x12 0x74 0x12 0x76 0x12 0x79 0x12 0x5c 0x12 0x7b>;
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clock-names = "iface\0bus\0core\0iommu\0vsync";
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iommus = <0x14 0x00>;
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phandle = <0x81>;
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ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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endpoint {
|
|
remote-endpoint = <0x15>;
|
|
phandle = <0x17>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi-tx@9a0000 {
|
|
compatible = "qcom,hdmi-tx-8996";
|
|
reg = <0x9a0000 0x50c 0x70000 0x6158 0x9e0000 0xfff>;
|
|
reg-names = "core_physical\0qfprom_physical\0hdcp_physical";
|
|
interrupt-parent = <0x13>;
|
|
interrupts = <0x08 0x04>;
|
|
clocks = <0x12 0x79 0x12 0x74 0x12 0x7c 0x12 0x75 0x12 0x7a>;
|
|
clock-names = "mdp_core\0iface\0core\0alt_iface\0extp";
|
|
phys = <0x16>;
|
|
phy-names = "hdmi_phy";
|
|
#sound-dai-cells = <0x01>;
|
|
phandle = <0x82>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17>;
|
|
phandle = <0x15>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi-phy@9a0600 {
|
|
#phy-cells = <0x00>;
|
|
compatible = "qcom,hdmi-phy-8996";
|
|
reg = <0x9a0600 0x1c4 0x9a0a00 0x124 0x9a0c00 0x124 0x9a0e00 0x124 0x9a1000 0x124 0x9a1200 0xc8>;
|
|
reg-names = "hdmi_pll\0hdmi_tx_l0\0hdmi_tx_l1\0hdmi_tx_l2\0hdmi_tx_l3\0hdmi_phy";
|
|
clocks = <0x12 0x74 0x10 0xd6>;
|
|
clock-names = "iface\0ref";
|
|
phandle = <0x16>;
|
|
};
|
|
};
|
|
|
|
gpu@b00000 {
|
|
compatible = "qcom,adreno-530.2\0qcom,adreno";
|
|
#stream-id-cells = <0x10>;
|
|
reg = <0xb00000 0x3f000>;
|
|
reg-names = "kgsl_3d0_reg_memory";
|
|
interrupts = <0x00 0x12c 0x04>;
|
|
clocks = <0x12 0x66 0x12 0x68 0x12 0x67 0x10 0xa8 0x10 0x5a>;
|
|
clock-names = "core\0iface\0rbbmtimer\0mem\0mem_iface";
|
|
power-domains = <0x12 0x0e>;
|
|
iommus = <0x18 0x00>;
|
|
nvmem-cells = <0x19>;
|
|
nvmem-cell-names = "speed_bin";
|
|
operating-points-v2 = <0x1a>;
|
|
|
|
opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0x1a>;
|
|
|
|
opp-624000000 {
|
|
opp-hz = <0x00 0x25317c00>;
|
|
opp-supported-hw = <0x09>;
|
|
};
|
|
|
|
opp-560000000 {
|
|
opp-hz = <0x00 0x2160ec00>;
|
|
opp-supported-hw = <0x0d>;
|
|
};
|
|
|
|
opp-510000000 {
|
|
opp-hz = <0x00 0x1e65fb80>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-401800000 {
|
|
opp-hz = <0x00 0x17f2fb40>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-315000000 {
|
|
opp-hz = <0x00 0x12c684c0>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-214000000 {
|
|
opp-hz = <0x00 0xcc16180>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
|
|
opp-133000000 {
|
|
opp-hz = <0x00 0x7ed6b40>;
|
|
opp-supported-hw = <0xff>;
|
|
};
|
|
};
|
|
|
|
zap-shader {
|
|
memory-region = <0x1b>;
|
|
};
|
|
};
|
|
|
|
pinctrl@1010000 {
|
|
compatible = "qcom,msm8996-pinctrl";
|
|
reg = <0x1010000 0x300000>;
|
|
interrupts = <0x00 0xd0 0x04>;
|
|
gpio-controller;
|
|
gpio-ranges = <0x1c 0x00 0x00 0x96>;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1c>;
|
|
|
|
wcd9xxx_intr {
|
|
|
|
wcd_intr_default {
|
|
phandle = <0x66>;
|
|
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
cdc_reset_ctrl {
|
|
|
|
cdc_reset_sleep {
|
|
phandle = <0x83>;
|
|
|
|
mux {
|
|
pins = "gpio64";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cdc_reset_active {
|
|
phandle = <0x65>;
|
|
|
|
mux {
|
|
pins = "gpio64";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64";
|
|
drive-strength = <0x10>;
|
|
bias-pull-down;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
blsp1_spi0_default {
|
|
phandle = <0x59>;
|
|
|
|
pinmux {
|
|
function = "blsp_spi1";
|
|
pins = "gpio0\0gpio1\0gpio3";
|
|
};
|
|
|
|
pinmux_cs {
|
|
function = "gpio";
|
|
pins = "gpio2";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio0\0gpio1\0gpio3";
|
|
drive-strength = <0x0c>;
|
|
bias-disable;
|
|
};
|
|
|
|
pinconf_cs {
|
|
pins = "gpio2";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
blsp1_spi0_sleep {
|
|
phandle = <0x5a>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
blsp1_i2c2_default {
|
|
phandle = <0x5b>;
|
|
|
|
pinmux {
|
|
function = "blsp_i2c3";
|
|
pins = "gpio47\0gpio48";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio47\0gpio48";
|
|
drive-strength = <0x10>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
blsp1_i2c2_sleep {
|
|
phandle = <0x5c>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio47\0gpio48";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio47\0gpio48";
|
|
drive-strength = <0x02>;
|
|
bias-disable = <0x00>;
|
|
};
|
|
};
|
|
|
|
blsp2_i2c0 {
|
|
phandle = <0x5d>;
|
|
|
|
pinmux {
|
|
function = "blsp_i2c7";
|
|
pins = "gpio55\0gpio56";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio55\0gpio56";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_i2c0_sleep {
|
|
phandle = <0x5e>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio55\0gpio56";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio55\0gpio56";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart1_2pins {
|
|
phandle = <0x84>;
|
|
|
|
pinmux {
|
|
function = "blsp_uart8";
|
|
pins = "gpio4\0gpio5";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio4\0gpio5";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart1_2pins_sleep {
|
|
phandle = <0x85>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio4\0gpio5";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio4\0gpio5";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart1_4pins {
|
|
phandle = <0x86>;
|
|
|
|
pinmux {
|
|
function = "blsp_uart8";
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart1_4pins_sleep {
|
|
phandle = <0x87>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_i2c1 {
|
|
phandle = <0x5f>;
|
|
|
|
pinmux {
|
|
function = "blsp_i2c8";
|
|
pins = "gpio6\0gpio7";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio6\0gpio7";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_i2c1_sleep {
|
|
phandle = <0x60>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio6\0gpio7";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart2_2pins {
|
|
phandle = <0x88>;
|
|
|
|
pinmux {
|
|
function = "blsp_uart9";
|
|
pins = "gpio49\0gpio50";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart2_2pins_sleep {
|
|
phandle = <0x89>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio49\0gpio50";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio49\0gpio50";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart2_4pins {
|
|
phandle = <0x8a>;
|
|
|
|
pinmux {
|
|
function = "blsp_uart9";
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_uart2_4pins_sleep {
|
|
phandle = <0x8b>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio49\0gpio50\0gpio51\0gpio52";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_spi5_default {
|
|
phandle = <0x61>;
|
|
|
|
pinmux {
|
|
function = "blsp_spi12";
|
|
pins = "gpio85\0gpio86\0gpio88";
|
|
};
|
|
|
|
pinmux_cs {
|
|
function = "gpio";
|
|
pins = "gpio87";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio85\0gpio86\0gpio88";
|
|
drive-strength = <0x0c>;
|
|
bias-disable;
|
|
};
|
|
|
|
pinconf_cs {
|
|
pins = "gpio87";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
blsp2_spi5_sleep {
|
|
phandle = <0x62>;
|
|
|
|
pinmux {
|
|
function = "gpio";
|
|
pins = "gpio85\0gpio86\0gpio87\0gpio88";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio85\0gpio86\0gpio87\0gpio88";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc2_clk_on {
|
|
phandle = <0x8c>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
};
|
|
|
|
sdc2_clk_off {
|
|
phandle = <0x8d>;
|
|
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_on {
|
|
phandle = <0x8e>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_off {
|
|
phandle = <0x8f>;
|
|
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_on {
|
|
phandle = <0x90>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
};
|
|
|
|
sdc2_data_off {
|
|
phandle = <0x91>;
|
|
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_default {
|
|
phandle = <0x1e>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "pci_e0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_perst_default {
|
|
phandle = <0x1f>;
|
|
|
|
mux {
|
|
pins = "gpio35";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_default {
|
|
phandle = <0x20>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_sleep {
|
|
phandle = <0x21>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_sleep {
|
|
phandle = <0x22>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_default {
|
|
phandle = <0x24>;
|
|
|
|
mux {
|
|
pins = "gpio131";
|
|
function = "pci_e1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio131";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_perst_default {
|
|
phandle = <0x25>;
|
|
|
|
mux {
|
|
pins = "gpio130";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio130";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie1_wake_default {
|
|
phandle = <0x26>;
|
|
|
|
mux {
|
|
pins = "gpio132";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio132";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_sleep {
|
|
phandle = <0x27>;
|
|
|
|
mux {
|
|
pins = "gpio131";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio131";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie1_wake_sleep {
|
|
phandle = <0x28>;
|
|
|
|
mux {
|
|
pins = "gpio132";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio132";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie2_clkreq_default {
|
|
phandle = <0x2a>;
|
|
|
|
mux {
|
|
pins = "gpio115";
|
|
function = "pci_e2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio115";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie2_perst_default {
|
|
phandle = <0x2b>;
|
|
|
|
mux {
|
|
pins = "gpio114";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio114";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie2_wake_default {
|
|
phandle = <0x2c>;
|
|
|
|
mux {
|
|
pins = "gpio116";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie2_clkreq_sleep {
|
|
phandle = <0x2d>;
|
|
|
|
mux {
|
|
pins = "gpio115";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio115";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pcie2_wake_sleep {
|
|
phandle = <0x2e>;
|
|
|
|
mux {
|
|
pins = "gpio116";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
cci0_default {
|
|
phandle = <0x32>;
|
|
|
|
pinmux {
|
|
function = "cci_i2c";
|
|
pins = "gpio17\0gpio18";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio17\0gpio18";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
cci1_default {
|
|
phandle = <0x33>;
|
|
|
|
pinmux {
|
|
function = "cci_i2c";
|
|
pins = "gpio19\0gpio20";
|
|
};
|
|
|
|
pinconf {
|
|
pins = "gpio19\0gpio20";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
camera_board_default {
|
|
phandle = <0x92>;
|
|
|
|
mux_pwdn {
|
|
function = "gpio";
|
|
pins = "gpio98";
|
|
};
|
|
|
|
config_pwdn {
|
|
pins = "gpio98";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_rst {
|
|
function = "gpio";
|
|
pins = "gpio104";
|
|
};
|
|
|
|
config_rst {
|
|
pins = "gpio104";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_mclk1 {
|
|
function = "cam_mclk";
|
|
pins = "gpio14";
|
|
};
|
|
|
|
config_mclk1 {
|
|
pins = "gpio14";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
camera_front_default {
|
|
phandle = <0x93>;
|
|
|
|
mux_pwdn {
|
|
function = "gpio";
|
|
pins = "gpio133";
|
|
};
|
|
|
|
config_pwdn {
|
|
pins = "gpio133";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_rst {
|
|
function = "gpio";
|
|
pins = "gpio23";
|
|
};
|
|
|
|
config_rst {
|
|
pins = "gpio23";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_mclk2 {
|
|
function = "cam_mclk";
|
|
pins = "gpio15";
|
|
};
|
|
|
|
config_mclk2 {
|
|
pins = "gpio15";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
camera_rear_default {
|
|
phandle = <0x94>;
|
|
|
|
mux_pwdn {
|
|
function = "gpio";
|
|
pins = "gpio26";
|
|
};
|
|
|
|
config_pwdn {
|
|
pins = "gpio26";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_rst {
|
|
function = "gpio";
|
|
pins = "gpio25";
|
|
};
|
|
|
|
config_rst {
|
|
pins = "gpio25";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux_mclk0 {
|
|
function = "cam_mclk";
|
|
pins = "gpio13";
|
|
};
|
|
|
|
config_mclk0 {
|
|
pins = "gpio13";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,spmi@400f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x400f000 0x1000 0x4400000 0x800000 0x4c00000 0x800000 0x5800000 0x200000 0x400a000 0x2100>;
|
|
reg-names = "core\0chnls\0obsrvr\0intr\0cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <0x00 0x146 0x04>;
|
|
qcom,ee = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
agnoc@0 {
|
|
power-domains = <0x10 0x00>;
|
|
compatible = "simple-pm-bus";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
pcie@600000 {
|
|
compatible = "qcom,pcie-msm8996\0snps,dw-pcie";
|
|
status = "disabled";
|
|
power-domains = <0x10 0x05>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <0x01>;
|
|
reg = <0x600000 0x2000 0xc000000 0xf1d 0xc000f20 0xa8 0xc100000 0x100000>;
|
|
reg-names = "parf\0dbi\0elbi\0config";
|
|
phys = <0x1d>;
|
|
phy-names = "pciephy";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x00 0xc200000 0x00 0x100000 0x2000000 0x00 0xc300000 0xc300000 0x00 0xd00000>;
|
|
interrupts = <0x00 0x195 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0xf4 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0xf5 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0xf7 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0xf8 0x04>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x1e 0x1f 0x20>;
|
|
pinctrl-1 = <0x21 0x1f 0x22>;
|
|
linux,pci-domain = <0x00>;
|
|
clocks = <0x10 0xb4 0x10 0xb3 0x10 0xb2 0x10 0xb1 0x10 0xb0>;
|
|
clock-names = "pipe\0aux\0cfg\0bus_master\0bus_slave";
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
pcie@608000 {
|
|
compatible = "qcom,pcie-msm8996\0snps,dw-pcie";
|
|
power-domains = <0x10 0x06>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <0x01>;
|
|
status = "disabled";
|
|
reg = <0x608000 0x2000 0xd000000 0xf1d 0xd000f20 0xa8 0xd100000 0x100000>;
|
|
reg-names = "parf\0dbi\0elbi\0config";
|
|
phys = <0x23>;
|
|
phy-names = "pciephy";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x00 0xd200000 0x00 0x100000 0x2000000 0x00 0xd300000 0xd300000 0x00 0xd00000>;
|
|
interrupts = <0x00 0x19d 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x110 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x111 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x112 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x113 0x04>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x24 0x25 0x26>;
|
|
pinctrl-1 = <0x27 0x25 0x28>;
|
|
linux,pci-domain = <0x01>;
|
|
clocks = <0x10 0xb9 0x10 0xb8 0x10 0xb7 0x10 0xb6 0x10 0xb5>;
|
|
clock-names = "pipe\0aux\0cfg\0bus_master\0bus_slave";
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
pcie@610000 {
|
|
compatible = "qcom,pcie-msm8996\0snps,dw-pcie";
|
|
power-domains = <0x10 0x07>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <0x01>;
|
|
status = "disabled";
|
|
reg = <0x610000 0x2000 0xe000000 0xf1d 0xe000f20 0xa8 0xe100000 0x100000>;
|
|
reg-names = "parf\0dbi\0elbi\0config";
|
|
phys = <0x29>;
|
|
phy-names = "pciephy";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x00 0xe200000 0x00 0x100000 0x2000000 0x00 0xe300000 0xe300000 0x00 0x1d00000>;
|
|
device_type = "pci";
|
|
interrupts = <0x00 0x1a5 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x8e 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x8f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x90 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x91 0x04>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2a 0x2b 0x2c>;
|
|
pinctrl-1 = <0x2d 0x2b 0x2e>;
|
|
linux,pci-domain = <0x02>;
|
|
clocks = <0x10 0xbe 0x10 0xbd 0x10 0xbc 0x10 0xbb 0x10 0xba>;
|
|
clock-names = "pipe\0aux\0cfg\0bus_master\0bus_slave";
|
|
phandle = <0x98>;
|
|
};
|
|
};
|
|
|
|
ufshc@624000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x624000 0x2500>;
|
|
interrupts = <0x00 0x109 0x04>;
|
|
phys = <0x2f>;
|
|
phy-names = "ufsphy";
|
|
power-domains = <0x10 0x08>;
|
|
clock-names = "core_clk_src\0core_clk\0bus_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro_src\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk";
|
|
clocks = <0x10 0x49 0x10 0xc1 0x10 0x52 0x10 0xd1 0x10 0xc2 0x10 0x4a 0x10 0xc8 0x10 0xc9 0x11 0x4a 0x10 0xc5 0x10 0xc6>;
|
|
freq-table-hz = <0x5f5e100 0xbebc200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8f0d180 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
lanes-per-direction = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
status = "disabled";
|
|
phandle = <0x30>;
|
|
|
|
ufs_variant {
|
|
compatible = "qcom,ufs_variant";
|
|
};
|
|
};
|
|
|
|
phy@627000 {
|
|
compatible = "qcom,msm8996-qmp-ufs-phy";
|
|
reg = <0x627000 0x1c4>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x10 0xd7>;
|
|
clock-names = "ref";
|
|
resets = <0x30 0x00>;
|
|
reset-names = "ufsphy";
|
|
status = "disabled";
|
|
phandle = <0x99>;
|
|
|
|
lanes@627400 {
|
|
reg = <0x627400 0x12c 0x627600 0x200 0x627c00 0x1b4>;
|
|
#phy-cells = <0x00>;
|
|
phandle = <0x2f>;
|
|
};
|
|
};
|
|
|
|
camss@a34000 {
|
|
compatible = "qcom,msm8996-camss";
|
|
reg = <0xa34000 0x1000 0xa00030 0x04 0xa35000 0x1000 0xa00038 0x04 0xa36000 0x1000 0xa00040 0x04 0xa30000 0x100 0xa30400 0x100 0xa30800 0x100 0xa30c00 0x100 0xa31000 0x500 0xa00020 0x10 0xa10000 0x1000 0xa14000 0x1000>;
|
|
reg-names = "csiphy0\0csiphy0_clk_mux\0csiphy1\0csiphy1_clk_mux\0csiphy2\0csiphy2_clk_mux\0csid0\0csid1\0csid2\0csid3\0ispif\0csi_clk_mux\0vfe0\0vfe1";
|
|
interrupts = <0x00 0x4e 0x01 0x00 0x4f 0x01 0x00 0x50 0x01 0x00 0x128 0x01 0x00 0x129 0x01 0x00 0x12a 0x01 0x00 0x12b 0x01 0x00 0x135 0x01 0x00 0x13a 0x01 0x00 0x13b 0x01>;
|
|
interrupt-names = "csiphy0\0csiphy1\0csiphy2\0csid0\0csid1\0csid2\0csid3\0ispif\0vfe0\0vfe1";
|
|
power-domains = <0x12 0x08 0x12 0x09>;
|
|
clocks = <0x12 0x81 0x12 0xb9 0x12 0x8c 0x12 0x8d 0x12 0x8e 0x12 0xa6 0x12 0xa5 0x12 0xa7 0x12 0xa9 0x12 0xa8 0x12 0xab 0x12 0xaa 0x12 0xac 0x12 0xae 0x12 0xad 0x12 0xb0 0x12 0xaf 0x12 0xb1 0x12 0xb3 0x12 0xb2 0x12 0xb5 0x12 0xb4 0x12 0xb6 0x12 0xb8 0x12 0xb7 0x12 0x82 0x12 0x99 0x12 0x9f 0x12 0x9b 0x12 0x9a 0x12 0x9c 0x12 0xa0 0x12 0x9e 0x12 0x9d 0x12 0x97 0x12 0x98>;
|
|
clock-names = "top_ahb\0ispif_ahb\0csiphy0_timer\0csiphy1_timer\0csiphy2_timer\0csi0_ahb\0csi0\0csi0_phy\0csi0_pix\0csi0_rdi\0csi1_ahb\0csi1\0csi1_phy\0csi1_pix\0csi1_rdi\0csi2_ahb\0csi2\0csi2_phy\0csi2_pix\0csi2_rdi\0csi3_ahb\0csi3\0csi3_phy\0csi3_pix\0csi3_rdi\0ahb\0vfe0\0csi_vfe0\0vfe0_ahb\0vfe0_stream\0vfe1\0csi_vfe1\0vfe1_ahb\0vfe1_stream\0vfe_ahb\0vfe_axi";
|
|
iommus = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>;
|
|
status = "disabled";
|
|
phandle = <0x9a>;
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
};
|
|
|
|
cci@a0c000 {
|
|
compatible = "qcom,msm8996-cci";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0xa0c000 0x1000>;
|
|
interrupts = <0x00 0x127 0x01>;
|
|
power-domains = <0x12 0x07>;
|
|
clocks = <0x12 0x81 0x12 0x8b 0x12 0x8a 0x12 0x82>;
|
|
clock-names = "camss_top_ahb\0cci_ahb\0cci\0camss_ahb";
|
|
assigned-clocks = <0x12 0x8b 0x12 0x8a>;
|
|
assigned-clock-rates = <0x4c4b400 0x23c3460>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x32 0x33>;
|
|
status = "disabled";
|
|
phandle = <0x9b>;
|
|
|
|
i2c-bus@0 {
|
|
reg = <0x00>;
|
|
clock-frequency = <0x61a80>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
i2c-bus@1 {
|
|
reg = <0x01>;
|
|
clock-frequency = <0x61a80>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x9d>;
|
|
};
|
|
};
|
|
|
|
iommu@b40000 {
|
|
compatible = "qcom,msm8996-smmu-v2\0qcom,smmu-v2";
|
|
reg = <0xb40000 0x10000>;
|
|
#global-interrupts = <0x01>;
|
|
interrupts = <0x00 0x14e 0x04 0x00 0x149 0x04 0x00 0x14a 0x04>;
|
|
#iommu-cells = <0x01>;
|
|
clocks = <0x12 0x68 0x10 0x5a>;
|
|
clock-names = "iface\0bus";
|
|
power-domains = <0x12 0x03>;
|
|
phandle = <0x18>;
|
|
};
|
|
|
|
video-codec@c00000 {
|
|
compatible = "qcom,msm8996-venus";
|
|
reg = <0xc00000 0xff000>;
|
|
interrupts = <0x00 0x11f 0x04>;
|
|
power-domains = <0x12 0x04>;
|
|
clocks = <0x12 0x6e 0x12 0x71 0x12 0x6f 0x12 0x70>;
|
|
clock-names = "core\0iface\0bus\0mbus";
|
|
iommus = <0x34 0x00 0x34 0x01 0x34 0x0a 0x34 0x07 0x34 0x0e 0x34 0x0f 0x34 0x08 0x34 0x09 0x34 0x0b 0x34 0x0c 0x34 0x0d 0x34 0x10 0x34 0x11 0x34 0x21 0x34 0x28 0x34 0x29 0x34 0x2b 0x34 0x2c 0x34 0x2d 0x34 0x31>;
|
|
memory-region = <0x35>;
|
|
status = "okay";
|
|
|
|
video-decoder {
|
|
compatible = "venus-decoder";
|
|
clocks = <0x12 0x72>;
|
|
clock-names = "core";
|
|
power-domains = <0x12 0x05>;
|
|
};
|
|
|
|
video-encoder {
|
|
compatible = "venus-encoder";
|
|
clocks = <0x12 0x73>;
|
|
clock-names = "core";
|
|
power-domains = <0x12 0x06>;
|
|
};
|
|
};
|
|
|
|
iommu@d00000 {
|
|
compatible = "qcom,msm8996-smmu-v2\0qcom,smmu-v2";
|
|
reg = <0xd00000 0x10000>;
|
|
#global-interrupts = <0x01>;
|
|
interrupts = <0x00 0x49 0x04 0x00 0x140 0x04 0x00 0x141 0x04>;
|
|
#iommu-cells = <0x01>;
|
|
clocks = <0x12 0x5b 0x12 0x5c>;
|
|
clock-names = "iface\0bus";
|
|
power-domains = <0x12 0x0d>;
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
iommu@d40000 {
|
|
compatible = "qcom,msm8996-smmu-v2\0qcom,smmu-v2";
|
|
reg = <0xd40000 0x20000>;
|
|
#global-interrupts = <0x01>;
|
|
interrupts = <0x00 0x11e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04>;
|
|
power-domains = <0x12 0x00>;
|
|
clocks = <0x12 0x62 0x12 0x63>;
|
|
clock-names = "iface\0bus";
|
|
#iommu-cells = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
iommu@da0000 {
|
|
compatible = "qcom,msm8996-smmu-v2\0qcom,smmu-v2";
|
|
reg = <0xda0000 0x10000>;
|
|
#global-interrupts = <0x01>;
|
|
interrupts = <0x00 0x4c 0x04 0x00 0x157 0x04 0x00 0x158 0x04>;
|
|
power-domains = <0x12 0x02>;
|
|
clocks = <0x12 0x4e 0x12 0x4f>;
|
|
clock-names = "iface\0bus";
|
|
#iommu-cells = <0x01>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
iommu@1600000 {
|
|
compatible = "qcom,msm8996-smmu-v2\0qcom,smmu-v2";
|
|
reg = <0x1600000 0x20000>;
|
|
#iommu-cells = <0x01>;
|
|
power-domains = <0x10 0x03>;
|
|
#global-interrupts = <0x01>;
|
|
interrupts = <0x00 0x194 0x04 0x00 0xe2 0x04 0x00 0x189 0x04 0x00 0x18a 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04>;
|
|
clocks = <0x10 0xdb 0x10 0xdc>;
|
|
clock-names = "iface\0bus";
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
stm@3002000 {
|
|
compatible = "arm,coresight-stm\0arm,primecell";
|
|
reg = <0x3002000 0x1000 0x8280000 0x180000>;
|
|
reg-names = "stm-base\0stm-stimulus-base";
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x36>;
|
|
phandle = <0x38>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpiu@3020000 {
|
|
compatible = "arm,coresight-tpiu\0arm,primecell";
|
|
reg = <0x3020000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x37>;
|
|
phandle = <0x43>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3021000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3021000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x38>;
|
|
phandle = <0x36>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x39>;
|
|
phandle = <0x3d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3022000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3022000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3a>;
|
|
phandle = <0x53>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3b>;
|
|
phandle = <0x3e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3023000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3023000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3c>;
|
|
phandle = <0x3f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3025000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3025000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3d>;
|
|
phandle = <0x39>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3e>;
|
|
phandle = <0x3b>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x3f>;
|
|
phandle = <0x3c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x40>;
|
|
phandle = <0x44>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@3026000 {
|
|
compatible = "arm,coresight-dynamic-replicator\0arm,primecell";
|
|
reg = <0x3026000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x41>;
|
|
phandle = <0x45>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x42>;
|
|
phandle = <0x46>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x43>;
|
|
phandle = <0x37>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf@3027000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
reg = <0x3027000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x44>;
|
|
phandle = <0x40>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x45>;
|
|
phandle = <0x41>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@3028000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
reg = <0x3028000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
arm,scatter-gather;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x46>;
|
|
phandle = <0x42>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
debug@3810000 {
|
|
compatible = "arm,coresight-cpu-debug\0arm,primecell";
|
|
reg = <0x3810000 0x1000>;
|
|
clocks = <0x11 0x08>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x05>;
|
|
};
|
|
|
|
etm@3840000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
reg = <0x3840000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
cpu = <0x05>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x47>;
|
|
phandle = <0x49>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
debug@3910000 {
|
|
compatible = "arm,coresight-cpu-debug\0arm,primecell";
|
|
reg = <0x3910000 0x1000>;
|
|
clocks = <0x11 0x08>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x06>;
|
|
};
|
|
|
|
etm@3940000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
reg = <0x3940000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
cpu = <0x06>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x48>;
|
|
phandle = <0x4a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@39b0000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x39b0000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x49>;
|
|
phandle = <0x47>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4a>;
|
|
phandle = <0x48>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4b>;
|
|
phandle = <0x51>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
debug@3a10000 {
|
|
compatible = "arm,coresight-cpu-debug\0arm,primecell";
|
|
reg = <0x3a10000 0x1000>;
|
|
clocks = <0x11 0x08>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x07>;
|
|
};
|
|
|
|
etm@3a40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
reg = <0x3a40000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
cpu = <0x07>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4c>;
|
|
phandle = <0x4e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
debug@3b10000 {
|
|
compatible = "arm,coresight-cpu-debug\0arm,primecell";
|
|
reg = <0x3b10000 0x1000>;
|
|
clocks = <0x11 0x08>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x08>;
|
|
};
|
|
|
|
etm@3b40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
reg = <0x3b40000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
cpu = <0x08>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4d>;
|
|
phandle = <0x4f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3bb0000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3bb0000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4e>;
|
|
phandle = <0x4c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x4f>;
|
|
phandle = <0x4d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x50>;
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@3bc0000 {
|
|
compatible = "arm,coresight-dynamic-funnel\0arm,primecell";
|
|
reg = <0x3bc0000 0x1000>;
|
|
clocks = <0x11 0x08 0x11 0x09>;
|
|
clock-names = "apb_pclk\0atclk";
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x51>;
|
|
phandle = <0x4b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x52>;
|
|
phandle = <0x50>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x53>;
|
|
phandle = <0x3a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
clock-controller@6400000 {
|
|
compatible = "qcom,apcc-msm8996";
|
|
reg = <0x6400000 0x90000>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
usb@6af8800 {
|
|
compatible = "qcom,msm8996-dwc3\0qcom,dwc3";
|
|
reg = <0x6af8800 0x400>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x10 0x51 0x10 0x5b 0x10 0xd2 0x10 0x5d 0x10 0x5c 0x10 0x63>;
|
|
assigned-clocks = <0x10 0x5d 0x10 0x5b>;
|
|
assigned-clock-rates = <0x124f800 0x7270e00>;
|
|
power-domains = <0x10 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x9f>;
|
|
|
|
dwc3@6a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x6a00000 0xcc00>;
|
|
interrupts = <0x00 0x83 0x04>;
|
|
phys = <0x54 0x55>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
snps,hird-threshold = [00];
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
snps,is-utmi-l1-suspend;
|
|
tx-fifo-resize;
|
|
};
|
|
};
|
|
|
|
phy@7410000 {
|
|
compatible = "qcom,msm8996-qmp-usb3-phy";
|
|
reg = <0x7410000 0x1c4>;
|
|
#clock-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
clocks = <0x10 0x5e 0x10 0x63 0x10 0xd5>;
|
|
clock-names = "aux\0cfg_ahb\0ref";
|
|
resets = <0x10 0x67 0x10 0x68>;
|
|
reset-names = "phy\0common";
|
|
status = "disabled";
|
|
phandle = <0xa0>;
|
|
|
|
lane@7410200 {
|
|
reg = <0x7410200 0x200 0x7410400 0x130 0x7410600 0x1a8>;
|
|
#phy-cells = <0x00>;
|
|
clock-output-names = "usb3_phy_pipe_clk_src";
|
|
clocks = <0x10 0x5f>;
|
|
clock-names = "pipe0";
|
|
phandle = <0x55>;
|
|
};
|
|
};
|
|
|
|
phy@7411000 {
|
|
compatible = "qcom,msm8996-qusb2-phy";
|
|
reg = <0x7411000 0x180>;
|
|
#phy-cells = <0x00>;
|
|
clocks = <0x10 0x63 0x10 0xda>;
|
|
clock-names = "cfg_ahb\0ref";
|
|
resets = <0x10 0x09>;
|
|
nvmem-cells = <0x56>;
|
|
status = "disabled";
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
phy@7412000 {
|
|
compatible = "qcom,msm8996-qusb2-phy";
|
|
reg = <0x7412000 0x180>;
|
|
#phy-cells = <0x00>;
|
|
clocks = <0x10 0x63 0x10 0xd9>;
|
|
clock-names = "cfg_ahb\0ref";
|
|
resets = <0x10 0x0a>;
|
|
nvmem-cells = <0x57>;
|
|
status = "disabled";
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
sdhci@74a4900 {
|
|
status = "disabled";
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x74a4900 0x314 0x74a4000 0x800>;
|
|
reg-names = "hc_mem\0core_mem";
|
|
interrupts = <0x00 0x7d 0x04 0x00 0xdd 0x04>;
|
|
interrupt-names = "hc_irq\0pwr_irq";
|
|
clock-names = "iface\0core\0xo";
|
|
clocks = <0x10 0x68 0x10 0x67 0x58>;
|
|
bus-width = <0x04>;
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
serial@7570000 {
|
|
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
|
|
reg = <0x7570000 0x1000>;
|
|
interrupts = <0x00 0x6c 0x04>;
|
|
clocks = <0x10 0x74 0x10 0x6d>;
|
|
clock-names = "core\0iface";
|
|
status = "disabled";
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
spi@7575000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x7575000 0x600>;
|
|
interrupts = <0x00 0x5f 0x04>;
|
|
clocks = <0x10 0x6f 0x10 0x6d>;
|
|
clock-names = "core\0iface";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x59>;
|
|
pinctrl-1 = <0x5a>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
i2c@7577000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x7577000 0x1000>;
|
|
interrupts = <0x00 0x61 0x04>;
|
|
clocks = <0x10 0x6d 0x10 0x76>;
|
|
clock-names = "iface\0core";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x5b>;
|
|
pinctrl-1 = <0x5c>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
serial@75b0000 {
|
|
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
|
|
reg = <0x75b0000 0x1000>;
|
|
interrupts = <0x00 0x72 0x04>;
|
|
clocks = <0x10 0x88 0x10 0x81>;
|
|
clock-names = "core\0iface";
|
|
status = "okay";
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
serial@75b1000 {
|
|
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
|
|
reg = <0x75b1000 0x1000>;
|
|
interrupts = <0x00 0x73 0x04>;
|
|
clocks = <0x10 0x8b 0x10 0x81>;
|
|
clock-names = "core\0iface";
|
|
status = "disabled";
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
i2c@75b5000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x75b5000 0x1000>;
|
|
interrupts = <0x00 0x65 0x04>;
|
|
clocks = <0x10 0x81 0x10 0x84>;
|
|
clock-names = "iface\0core";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x5d>;
|
|
pinctrl-1 = <0x5e>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
i2c@75b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x75b6000 0x1000>;
|
|
interrupts = <0x00 0x66 0x04>;
|
|
clocks = <0x10 0x81 0x10 0x87>;
|
|
clock-names = "iface\0core";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x5f>;
|
|
pinctrl-1 = <0x60>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
spi@75ba000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x75ba000 0x600>;
|
|
interrupts = <0x00 0x6a 0x04>;
|
|
clocks = <0x10 0x92 0x10 0x81>;
|
|
clock-names = "core\0iface";
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x61>;
|
|
pinctrl-1 = <0x62>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
usb@76f8800 {
|
|
compatible = "qcom,msm8996-dwc3\0qcom,dwc3";
|
|
reg = <0x76f8800 0x400>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
interrupts = <0x00 0x160 0x04>;
|
|
interrupt-names = "hs_phy_irq";
|
|
clocks = <0x10 0x55 0x10 0x60 0x10 0x62 0x10 0x61 0x10 0x63>;
|
|
assigned-clocks = <0x10 0x62 0x10 0x60>;
|
|
assigned-clock-rates = <0x124f800 0x3938700>;
|
|
power-domains = <0x10 0x04>;
|
|
status = "disabled";
|
|
phandle = <0xaa>;
|
|
|
|
dwc3@7600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x7600000 0xcc00>;
|
|
interrupts = <0x00 0x8a 0x04>;
|
|
phys = <0x63>;
|
|
phy-names = "usb2-phy";
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
};
|
|
};
|
|
|
|
dma@9184000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x9184000 0x32000>;
|
|
num-channels = <0x1f>;
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
#dma-cells = <0x01>;
|
|
qcom,ee = <0x01>;
|
|
qcom,num-ees = <0x02>;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
slim@91c0000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x91c0000 0x2c000>;
|
|
reg-names = "ctrl";
|
|
interrupts = <0x00 0xa3 0x04>;
|
|
dmas = <0x64 0x03 0x64 0x04 0x64 0x05 0x64 0x06>;
|
|
dma-names = "rx\0tx\0tx2\0rx2";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0xab>;
|
|
|
|
ngd@1 {
|
|
reg = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
tas-ifd {
|
|
compatible = "slim217,1a0";
|
|
reg = <0x00 0x00>;
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
codec@1 {
|
|
pinctrl-0 = <0x65 0x66>;
|
|
pinctrl-names = "default";
|
|
compatible = "slim217,1a0";
|
|
reg = <0x01 0x00>;
|
|
interrupt-parent = <0x1c>;
|
|
interrupts = <0x36 0x04 0x35 0x04>;
|
|
interrupt-names = "intr1\0intr2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
reset-gpios = <0x1c 0x40 0x00>;
|
|
slim-ifc-dev = <0x67>;
|
|
#sound-dai-cells = <0x01>;
|
|
phandle = <0xac>;
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc@9300000 {
|
|
compatible = "qcom,msm8996-adsp-pil";
|
|
reg = <0x9300000 0x80000>;
|
|
interrupts-extended = <0x01 0x00 0xa2 0x01 0x68 0x00 0x01 0x68 0x01 0x01 0x68 0x02 0x01 0x68 0x03 0x01>;
|
|
interrupt-names = "wdog\0fatal\0ready\0handover\0stop-ack";
|
|
clocks = <0x58>;
|
|
clock-names = "xo";
|
|
memory-region = <0x69>;
|
|
qcom,smem-states = <0x6a 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0xad>;
|
|
|
|
smd-edge {
|
|
interrupts = <0x00 0x9c 0x01>;
|
|
label = "lpass";
|
|
mboxes = <0x0c 0x08>;
|
|
qcom,smd-edge = <0x01>;
|
|
qcom,remote-pid = <0x02>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
apr {
|
|
power-domains = <0x10 0x02>;
|
|
compatible = "qcom,apr-v2";
|
|
qcom,smd-channels = "apr_audio_svc";
|
|
qcom,apr-domain = <0x04>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
q6core {
|
|
reg = <0x03>;
|
|
compatible = "qcom,q6core";
|
|
};
|
|
|
|
q6afe {
|
|
compatible = "qcom,q6afe";
|
|
reg = <0x04>;
|
|
phandle = <0xae>;
|
|
|
|
dais {
|
|
compatible = "qcom,q6afe-dais";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#sound-dai-cells = <0x01>;
|
|
phandle = <0xaf>;
|
|
|
|
hdmi@1 {
|
|
reg = <0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
q6asm {
|
|
compatible = "qcom,q6asm";
|
|
reg = <0x07>;
|
|
phandle = <0xb0>;
|
|
|
|
dais {
|
|
compatible = "qcom,q6asm-dais";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#sound-dai-cells = <0x01>;
|
|
iommus = <0x6b 0x01>;
|
|
phandle = <0xb1>;
|
|
};
|
|
};
|
|
|
|
q6adm {
|
|
compatible = "qcom,q6adm";
|
|
reg = <0x08>;
|
|
phandle = <0xb2>;
|
|
|
|
routing {
|
|
compatible = "qcom,q6adm-routing";
|
|
#sound-dai-cells = <0x00>;
|
|
phandle = <0xb3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mailbox@9820000 {
|
|
compatible = "qcom,msm8996-apcs-hmss-global";
|
|
reg = <0x9820000 0x1000>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x0c>;
|
|
};
|
|
|
|
timer@9840000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x9840000 0x1000>;
|
|
clock-frequency = <0x124f800>;
|
|
|
|
frame@9850000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x1f 0x04 0x00 0x1e 0x04>;
|
|
reg = <0x9850000 0x1000 0x9860000 0x1000>;
|
|
};
|
|
|
|
frame@9870000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x20 0x04>;
|
|
reg = <0x9870000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@9880000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x21 0x04>;
|
|
reg = <0x9880000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@9890000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x22 0x04>;
|
|
reg = <0x9890000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98a0000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x23 0x04>;
|
|
reg = <0x98a0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98b0000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x24 0x04>;
|
|
reg = <0x98b0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98c0000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x25 0x04>;
|
|
reg = <0x98c0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
syscon@9a10000 {
|
|
compatible = "syscon";
|
|
reg = <0x9a10000 0x1000>;
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
interrupt-controller@9bc0000 {
|
|
compatible = "qcom,msm8996-gic-v3\0arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <0x01>;
|
|
redistributor-stride = <0x00 0x40000>;
|
|
reg = <0x9bc0000 0x10000 0x9c00000 0x100000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
phandle = <0x01>;
|
|
};
|
|
};
|
|
|
|
sound {
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
cpu0-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x03>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xb6>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xb7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x05>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xb9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x08>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xbb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x0a>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x124f8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
phandle = <0xbd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-top {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x06>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbe>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-bottom {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x07>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xbf>;
|
|
};
|
|
};
|
|
};
|
|
|
|
m4m-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x01>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
l3-or-venus-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x02>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster0-l2-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x07>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster1-l2-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6c 0x0c>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x01>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
q6-dsp-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x02>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mem-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x03>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
modemtx-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x6d 0x04>;
|
|
|
|
trips {
|
|
|
|
trip-point0 {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x7d0>;
|
|
type = "hot";
|
|
phandle = <0xc7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
|
|
};
|
|
|
|
aliases {
|
|
serial0 = "/soc/serial@75b0000";
|
|
};
|
|
|
|
__symbols__ {
|
|
xo_board = "/clocks/xo-board";
|
|
sleep_clk = "/clocks/sleep-clk";
|
|
CPU0 = "/cpus/cpu@0";
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
|
CPU1 = "/cpus/cpu@1";
|
|
CPU2 = "/cpus/cpu@100";
|
|
L2_1 = "/cpus/cpu@100/l2-cache";
|
|
CPU3 = "/cpus/cpu@101";
|
|
CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0";
|
|
tcsr_mutex = "/hwlock";
|
|
mba_region = "/reserved-memory/mba@91500000";
|
|
slpi_region = "/reserved-memory/slpi@90b00000";
|
|
venus_region = "/reserved-memory/venus@90400000";
|
|
adsp_region = "/reserved-memory/adsp@8ea00000";
|
|
mpss_region = "/reserved-memory/mpss@88800000";
|
|
smem_mem = "/reserved-memory/smem-mem@86000000";
|
|
zap_shader_region = "/reserved-memory/gpu@8f200000";
|
|
rpm_requests = "/rpm-glink/rpm-requests";
|
|
rpmcc = "/rpm-glink/rpm-requests/qcom,rpmcc";
|
|
rpmpd = "/rpm-glink/rpm-requests/power-controller";
|
|
rpmpd_opp_table = "/rpm-glink/rpm-requests/power-controller/opp-table";
|
|
rpmpd_opp1 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp1";
|
|
rpmpd_opp2 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp2";
|
|
rpmpd_opp3 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp3";
|
|
rpmpd_opp4 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp4";
|
|
rpmpd_opp5 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp5";
|
|
rpmpd_opp6 = "/rpm-glink/rpm-requests/power-controller/opp-table/opp6";
|
|
smp2p_adsp_out = "/smp2p-adsp/master-kernel";
|
|
smp2p_adsp_in = "/smp2p-adsp/slave-kernel";
|
|
modem_smp2p_out = "/smp2p-modem/master-kernel";
|
|
modem_smp2p_in = "/smp2p-modem/slave-kernel";
|
|
smp2p_slpi_in = "/smp2p-slpi/slave-kernel";
|
|
smp2p_slpi_out = "/smp2p-slpi/master-kernel";
|
|
soc = "/soc";
|
|
pcie_phy = "/soc/phy@34000";
|
|
pciephy_0 = "/soc/phy@34000/lane@35000";
|
|
pciephy_1 = "/soc/phy@34000/lane@36000";
|
|
pciephy_2 = "/soc/phy@34000/lane@37000";
|
|
rpm_msg_ram = "/soc/memory@68000";
|
|
qusb2p_hstx_trim = "/soc/qfprom@74000/hstx_trim@24e";
|
|
qusb2s_hstx_trim = "/soc/qfprom@74000/hstx_trim@24f";
|
|
gpu_speed_bin = "/soc/qfprom@74000/gpu_speed_bin@133";
|
|
rng = "/soc/rng@83000";
|
|
gcc = "/soc/clock-controller@300000";
|
|
tsens0 = "/soc/thermal-sensor@4a9000";
|
|
tsens1 = "/soc/thermal-sensor@4ad000";
|
|
tcsr_mutex_regs = "/soc/syscon@740000";
|
|
tcsr = "/soc/syscon@7a0000";
|
|
mmcc = "/soc/clock-controller@8c0000";
|
|
mdss = "/soc/mdss@900000";
|
|
mdp = "/soc/mdss@900000/mdp@901000";
|
|
mdp5_intf3_out = "/soc/mdss@900000/mdp@901000/ports/port@0/endpoint";
|
|
hdmi = "/soc/mdss@900000/hdmi-tx@9a0000";
|
|
hdmi_in = "/soc/mdss@900000/hdmi-tx@9a0000/ports/port@0/endpoint";
|
|
hdmi_phy = "/soc/mdss@900000/hdmi-phy@9a0600";
|
|
gpu_opp_table = "/soc/gpu@b00000/opp-table";
|
|
msmgpio = "/soc/pinctrl@1010000";
|
|
wcd_intr_default = "/soc/pinctrl@1010000/wcd9xxx_intr/wcd_intr_default";
|
|
cdc_reset_sleep = "/soc/pinctrl@1010000/cdc_reset_ctrl/cdc_reset_sleep";
|
|
cdc_reset_active = "/soc/pinctrl@1010000/cdc_reset_ctrl/cdc_reset_active";
|
|
blsp1_spi0_default = "/soc/pinctrl@1010000/blsp1_spi0_default";
|
|
blsp1_spi0_sleep = "/soc/pinctrl@1010000/blsp1_spi0_sleep";
|
|
blsp1_i2c2_default = "/soc/pinctrl@1010000/blsp1_i2c2_default";
|
|
blsp1_i2c2_sleep = "/soc/pinctrl@1010000/blsp1_i2c2_sleep";
|
|
blsp2_i2c0_default = "/soc/pinctrl@1010000/blsp2_i2c0";
|
|
blsp2_i2c0_sleep = "/soc/pinctrl@1010000/blsp2_i2c0_sleep";
|
|
blsp2_uart1_2pins_default = "/soc/pinctrl@1010000/blsp2_uart1_2pins";
|
|
blsp2_uart1_2pins_sleep = "/soc/pinctrl@1010000/blsp2_uart1_2pins_sleep";
|
|
blsp2_uart1_4pins_default = "/soc/pinctrl@1010000/blsp2_uart1_4pins";
|
|
blsp2_uart1_4pins_sleep = "/soc/pinctrl@1010000/blsp2_uart1_4pins_sleep";
|
|
blsp2_i2c1_default = "/soc/pinctrl@1010000/blsp2_i2c1";
|
|
blsp2_i2c1_sleep = "/soc/pinctrl@1010000/blsp2_i2c1_sleep";
|
|
blsp2_uart2_2pins_default = "/soc/pinctrl@1010000/blsp2_uart2_2pins";
|
|
blsp2_uart2_2pins_sleep = "/soc/pinctrl@1010000/blsp2_uart2_2pins_sleep";
|
|
blsp2_uart2_4pins_default = "/soc/pinctrl@1010000/blsp2_uart2_4pins";
|
|
blsp2_uart2_4pins_sleep = "/soc/pinctrl@1010000/blsp2_uart2_4pins_sleep";
|
|
blsp2_spi5_default = "/soc/pinctrl@1010000/blsp2_spi5_default";
|
|
blsp2_spi5_sleep = "/soc/pinctrl@1010000/blsp2_spi5_sleep";
|
|
sdc2_clk_on = "/soc/pinctrl@1010000/sdc2_clk_on";
|
|
sdc2_clk_off = "/soc/pinctrl@1010000/sdc2_clk_off";
|
|
sdc2_cmd_on = "/soc/pinctrl@1010000/sdc2_cmd_on";
|
|
sdc2_cmd_off = "/soc/pinctrl@1010000/sdc2_cmd_off";
|
|
sdc2_data_on = "/soc/pinctrl@1010000/sdc2_data_on";
|
|
sdc2_data_off = "/soc/pinctrl@1010000/sdc2_data_off";
|
|
pcie0_clkreq_default = "/soc/pinctrl@1010000/pcie0_clkreq_default";
|
|
pcie0_perst_default = "/soc/pinctrl@1010000/pcie0_perst_default";
|
|
pcie0_wake_default = "/soc/pinctrl@1010000/pcie0_wake_default";
|
|
pcie0_clkreq_sleep = "/soc/pinctrl@1010000/pcie0_clkreq_sleep";
|
|
pcie0_wake_sleep = "/soc/pinctrl@1010000/pcie0_wake_sleep";
|
|
pcie1_clkreq_default = "/soc/pinctrl@1010000/pcie1_clkreq_default";
|
|
pcie1_perst_default = "/soc/pinctrl@1010000/pcie1_perst_default";
|
|
pcie1_wake_default = "/soc/pinctrl@1010000/pcie1_wake_default";
|
|
pcie1_clkreq_sleep = "/soc/pinctrl@1010000/pcie1_clkreq_sleep";
|
|
pcie1_wake_sleep = "/soc/pinctrl@1010000/pcie1_wake_sleep";
|
|
pcie2_clkreq_default = "/soc/pinctrl@1010000/pcie2_clkreq_default";
|
|
pcie2_perst_default = "/soc/pinctrl@1010000/pcie2_perst_default";
|
|
pcie2_wake_default = "/soc/pinctrl@1010000/pcie2_wake_default";
|
|
pcie2_clkreq_sleep = "/soc/pinctrl@1010000/pcie2_clkreq_sleep";
|
|
pcie2_wake_sleep = "/soc/pinctrl@1010000/pcie2_wake_sleep";
|
|
cci0_default = "/soc/pinctrl@1010000/cci0_default";
|
|
cci1_default = "/soc/pinctrl@1010000/cci1_default";
|
|
camera_board_default = "/soc/pinctrl@1010000/camera_board_default";
|
|
camera_front_default = "/soc/pinctrl@1010000/camera_front_default";
|
|
camera_rear_default = "/soc/pinctrl@1010000/camera_rear_default";
|
|
spmi_bus = "/soc/qcom,spmi@400f000";
|
|
pcie0 = "/soc/agnoc@0/pcie@600000";
|
|
pcie1 = "/soc/agnoc@0/pcie@608000";
|
|
pcie2 = "/soc/agnoc@0/pcie@610000";
|
|
ufshc = "/soc/ufshc@624000";
|
|
ufsphy = "/soc/phy@627000";
|
|
ufsphy_lane = "/soc/phy@627000/lanes@627400";
|
|
camss = "/soc/camss@a34000";
|
|
cci = "/soc/cci@a0c000";
|
|
cci_i2c0 = "/soc/cci@a0c000/i2c-bus@0";
|
|
cci_i2c1 = "/soc/cci@a0c000/i2c-bus@1";
|
|
adreno_smmu = "/soc/iommu@b40000";
|
|
mdp_smmu = "/soc/iommu@d00000";
|
|
venus_smmu = "/soc/iommu@d40000";
|
|
vfe_smmu = "/soc/iommu@da0000";
|
|
lpass_q6_smmu = "/soc/iommu@1600000";
|
|
stm_out = "/soc/stm@3002000/out-ports/port/endpoint";
|
|
tpiu_in = "/soc/tpiu@3020000/in-ports/port/endpoint";
|
|
funnel0_in = "/soc/funnel@3021000/in-ports/port@7/endpoint";
|
|
funnel0_out = "/soc/funnel@3021000/out-ports/port/endpoint";
|
|
funnel1_in = "/soc/funnel@3022000/in-ports/port@6/endpoint";
|
|
funnel1_out = "/soc/funnel@3022000/out-ports/port/endpoint";
|
|
funnel2_out = "/soc/funnel@3023000/out-ports/port/endpoint";
|
|
merge_funnel_in0 = "/soc/funnel@3025000/in-ports/port@0/endpoint";
|
|
merge_funnel_in1 = "/soc/funnel@3025000/in-ports/port@1/endpoint";
|
|
merge_funnel_in2 = "/soc/funnel@3025000/in-ports/port@2/endpoint";
|
|
merge_funnel_out = "/soc/funnel@3025000/out-ports/port/endpoint";
|
|
replicator_in = "/soc/replicator@3026000/in-ports/port/endpoint";
|
|
replicator_out0 = "/soc/replicator@3026000/out-ports/port@0/endpoint";
|
|
replicator_out1 = "/soc/replicator@3026000/out-ports/port@1/endpoint";
|
|
etf_in = "/soc/etf@3027000/in-ports/port/endpoint";
|
|
etf_out = "/soc/etf@3027000/out-ports/port/endpoint";
|
|
etr_in = "/soc/etr@3028000/in-ports/port/endpoint";
|
|
etm0_out = "/soc/etm@3840000/out-ports/port/endpoint";
|
|
etm1_out = "/soc/etm@3940000/out-ports/port/endpoint";
|
|
apss_funnel0_in0 = "/soc/funnel@39b0000/in-ports/port@0/endpoint";
|
|
apss_funnel0_in1 = "/soc/funnel@39b0000/in-ports/port@1/endpoint";
|
|
apss_funnel0_out = "/soc/funnel@39b0000/out-ports/port/endpoint";
|
|
etm2_out = "/soc/etm@3a40000/out-ports/port/endpoint";
|
|
etm3_out = "/soc/etm@3b40000/out-ports/port/endpoint";
|
|
apss_funnel1_in0 = "/soc/funnel@3bb0000/in-ports/port@0/endpoint";
|
|
apss_funnel1_in1 = "/soc/funnel@3bb0000/in-ports/port@1/endpoint";
|
|
apss_funnel1_out = "/soc/funnel@3bb0000/out-ports/port/endpoint";
|
|
apss_merge_funnel_in0 = "/soc/funnel@3bc0000/in-ports/port@0/endpoint";
|
|
apss_merge_funnel_in1 = "/soc/funnel@3bc0000/in-ports/port@1/endpoint";
|
|
apss_merge_funnel_out = "/soc/funnel@3bc0000/out-ports/port/endpoint";
|
|
kryocc = "/soc/clock-controller@6400000";
|
|
usb3 = "/soc/usb@6af8800";
|
|
usb3phy = "/soc/phy@7410000";
|
|
ssusb_phy_0 = "/soc/phy@7410000/lane@7410200";
|
|
hsusb_phy1 = "/soc/phy@7411000";
|
|
hsusb_phy2 = "/soc/phy@7412000";
|
|
sdhc2 = "/soc/sdhci@74a4900";
|
|
blsp1_uart1 = "/soc/serial@7570000";
|
|
blsp1_spi0 = "/soc/spi@7575000";
|
|
blsp1_i2c2 = "/soc/i2c@7577000";
|
|
blsp2_uart1 = "/soc/serial@75b0000";
|
|
blsp2_uart2 = "/soc/serial@75b1000";
|
|
blsp2_i2c0 = "/soc/i2c@75b5000";
|
|
blsp2_i2c1 = "/soc/i2c@75b6000";
|
|
blsp2_spi5 = "/soc/spi@75ba000";
|
|
usb2 = "/soc/usb@76f8800";
|
|
slimbam = "/soc/dma@9184000";
|
|
slim_msm = "/soc/slim@91c0000";
|
|
tasha_ifd = "/soc/slim@91c0000/ngd@1/tas-ifd";
|
|
wcd9335 = "/soc/slim@91c0000/ngd@1/codec@1";
|
|
adsp_pil = "/soc/remoteproc@9300000";
|
|
q6afe = "/soc/remoteproc@9300000/smd-edge/apr/q6afe";
|
|
q6afedai = "/soc/remoteproc@9300000/smd-edge/apr/q6afe/dais";
|
|
q6asm = "/soc/remoteproc@9300000/smd-edge/apr/q6asm";
|
|
q6asmdai = "/soc/remoteproc@9300000/smd-edge/apr/q6asm/dais";
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|
q6adm = "/soc/remoteproc@9300000/smd-edge/apr/q6adm";
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|
q6routing = "/soc/remoteproc@9300000/smd-edge/apr/q6adm/routing";
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apcs_glb = "/soc/mailbox@9820000";
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|
saw3 = "/soc/syscon@9a10000";
|
|
intc = "/soc/interrupt-controller@9bc0000";
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sound = "/sound";
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|
cpu0_alert0 = "/thermal-zones/cpu0-thermal/trips/trip-point0";
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|
cpu0_crit = "/thermal-zones/cpu0-thermal/trips/cpu_crit";
|
|
cpu1_alert0 = "/thermal-zones/cpu1-thermal/trips/trip-point0";
|
|
cpu1_crit = "/thermal-zones/cpu1-thermal/trips/cpu_crit";
|
|
cpu2_alert0 = "/thermal-zones/cpu2-thermal/trips/trip-point0";
|
|
cpu2_crit = "/thermal-zones/cpu2-thermal/trips/cpu_crit";
|
|
cpu3_alert0 = "/thermal-zones/cpu3-thermal/trips/trip-point0";
|
|
cpu3_crit = "/thermal-zones/cpu3-thermal/trips/cpu_crit";
|
|
gpu1_alert0 = "/thermal-zones/gpu-thermal-top/trips/trip-point0";
|
|
gpu2_alert0 = "/thermal-zones/gpu-thermal-bottom/trips/trip-point0";
|
|
m4m_alert0 = "/thermal-zones/m4m-thermal/trips/trip-point0";
|
|
l3_or_venus_alert0 = "/thermal-zones/l3-or-venus-thermal/trips/trip-point0";
|
|
cluster0_l2_alert0 = "/thermal-zones/cluster0-l2-thermal/trips/trip-point0";
|
|
cluster1_l2_alert0 = "/thermal-zones/cluster1-l2-thermal/trips/trip-point0";
|
|
camera_alert0 = "/thermal-zones/camera-thermal/trips/trip-point0";
|
|
q6_dsp_alert0 = "/thermal-zones/q6-dsp-thermal/trips/trip-point0";
|
|
mem_alert0 = "/thermal-zones/mem-thermal/trips/trip-point0";
|
|
modemtx_alert0 = "/thermal-zones/modemtx-thermal/trips/trip-point0";
|
|
};
|
|
};
|