676 lines
17 KiB
Text
Executable file
676 lines
17 KiB
Text
Executable file
/dts-v1/;
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/ {
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model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
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compatible = "qcom,ipq8074-hk01\0qcom,ipq8074";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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interrupt-parent = <0x01>;
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clocks {
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sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <0x8000>;
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#clock-cells = <0x00>;
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phandle = <0x11>;
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};
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xo {
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compatible = "fixed-clock";
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clock-frequency = <0x124f800>;
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#clock-cells = <0x00>;
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phandle = <0x04>;
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};
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00>;
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next-level-cache = <0x02>;
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enable-method = "psci";
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phandle = <0x14>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x01>;
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next-level-cache = <0x02>;
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phandle = <0x15>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x02>;
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next-level-cache = <0x02>;
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phandle = <0x16>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x03>;
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next-level-cache = <0x02>;
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phandle = <0x17>;
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};
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x02>;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <0x01 0x07 0xf04>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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phandle = <0x18>;
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phy@58000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x58000 0x1c4>;
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#clock-cells = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x82 0x03 0x86 0x04>;
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clock-names = "aux\0cfg_ahb\0ref";
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resets = <0x03 0x2c 0x03 0x2d>;
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reset-names = "phy\0common";
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status = "okay";
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phandle = <0x19>;
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lane@58200 {
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reg = <0x58200 0x130 0x58400 0x200 0x58800 0x1f8 0x58600 0x44>;
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#phy-cells = <0x00>;
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clocks = <0x03 0x87>;
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clock-names = "pipe0";
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clock-output-names = "usb3phy_1_cc_pipe_clk";
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phandle = <0x10>;
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};
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};
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phy@59000 {
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compatible = "qcom,ipq8074-qusb2-phy";
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reg = <0x59000 0x180>;
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#phy-cells = <0x00>;
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clocks = <0x03 0x86 0x04>;
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clock-names = "cfg_ahb\0ref";
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resets = <0x03 0x30>;
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status = "okay";
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phandle = <0x0f>;
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};
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phy@78000 {
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compatible = "qcom,ipq8074-qmp-usb3-phy";
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reg = <0x78000 0x1c4>;
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#clock-cells = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x7b 0x03 0x7f 0x04>;
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clock-names = "aux\0cfg_ahb\0ref";
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resets = <0x03 0x29 0x03 0x2a>;
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reset-names = "phy\0common";
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status = "okay";
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phandle = <0x1a>;
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lane@78200 {
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reg = <0x78200 0x130 0x78400 0x200 0x78800 0x1f8 0x78600 0x44>;
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#phy-cells = <0x00>;
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clocks = <0x03 0x80>;
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clock-names = "pipe0";
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clock-output-names = "usb3phy_0_cc_pipe_clk";
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phandle = <0x0e>;
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};
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};
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phy@79000 {
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compatible = "qcom,ipq8074-qusb2-phy";
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reg = <0x79000 0x180>;
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#phy-cells = <0x00>;
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clocks = <0x03 0x7f 0x04>;
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clock-names = "cfg_ahb\0ref";
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resets = <0x03 0x2f>;
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status = "okay";
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phandle = <0x0d>;
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};
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phy@84000 {
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compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
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reg = <0x84000 0x1bc>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x70 0x03 0x6f>;
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clock-names = "aux\0cfg_ahb";
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resets = <0x03 0x4e 0x03 0x4f>;
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reset-names = "phy\0common";
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status = "okay";
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phandle = <0x1b>;
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phy@84200 {
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reg = <0x84200 0x16c 0x84400 0x200 0x84800 0x1f0 0x84c00 0xf4>;
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#phy-cells = <0x00>;
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#clock-cells = <0x00>;
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clocks = <0x03 0x73>;
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clock-names = "pipe0";
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clock-output-names = "pcie20_phy0_pipe_clk";
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phandle = <0x13>;
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};
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};
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phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x8e000 0x1c4>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x76 0x03 0x75>;
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clock-names = "aux\0cfg_ahb";
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resets = <0x03 0x52 0x03 0x53>;
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reset-names = "phy\0common";
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status = "okay";
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phandle = <0x1c>;
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phy@8e200 {
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reg = <0x8e200 0x130 0x8e400 0x200 0x8e800 0x1f8>;
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#phy-cells = <0x00>;
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#clock-cells = <0x00>;
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clocks = <0x03 0x79>;
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clock-names = "pipe0";
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clock-output-names = "pcie20_phy1_pipe_clk";
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phandle = <0x12>;
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};
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};
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pinctrl@1000000 {
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compatible = "qcom,ipq8074-pinctrl";
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reg = <0x1000000 0x300000>;
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interrupts = <0x00 0xd0 0x04>;
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gpio-controller;
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gpio-ranges = <0x05 0x00 0x00 0x46>;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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phandle = <0x05>;
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serial4-pinmux {
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pins = "gpio23\0gpio24";
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function = "blsp4_uart1";
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drive-strength = <0x08>;
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bias-disable;
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phandle = <0x08>;
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};
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i2c-0-pinmux {
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pins = "gpio42\0gpio43";
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function = "blsp1_i2c";
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drive-strength = <0x08>;
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bias-disable;
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phandle = <0x0a>;
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};
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spi-0-pins {
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pins = "gpio38\0gpio39\0gpio40\0gpio41";
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function = "blsp0_spi";
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drive-strength = <0x08>;
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bias-disable;
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phandle = <0x09>;
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};
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hsuart-pins {
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pins = "gpio46\0gpio47\0gpio48\0gpio49";
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function = "blsp2_uart";
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drive-strength = <0x08>;
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bias-disable;
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phandle = <0x07>;
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};
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qpic-pins {
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pins = "gpio1\0gpio3\0gpio4\0gpio5\0gpio6\0gpio7\0gpio8\0gpio10\0gpio11\0gpio12\0gpio13\0gpio14\0gpio15\0gpio16\0gpio17";
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function = "qpic";
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drive-strength = <0x08>;
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bias-disable;
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phandle = <0x0c>;
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};
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};
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gcc@1800000 {
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compatible = "qcom,gcc-ipq8074";
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reg = <0x1800000 0x80000>;
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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phandle = <0x03>;
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};
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sdhci@7824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x7824900 0x500 0x7824000 0x800>;
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reg-names = "hc_mem\0core_mem";
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interrupts = <0x00 0x7b 0x04 0x00 0x8a 0x04>;
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interrupt-names = "hc_irq\0pwr_irq";
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clocks = <0x04 0x03 0x89 0x03 0x8a>;
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clock-names = "xo\0iface\0core";
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max-frequency = <0x16e36000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <0x08>;
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status = "okay";
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phandle = <0x1d>;
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};
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dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7884000 0x2b000>;
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interrupts = <0x00 0xee 0x04>;
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clocks = <0x03 0x15>;
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clock-names = "bam_clk";
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#dma-cells = <0x01>;
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qcom,ee = <0x00>;
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phandle = <0x06>;
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};
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serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <0x00 0x6b 0x04>;
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clocks = <0x03 0x22 0x03 0x15>;
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clock-names = "core\0iface";
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status = "disabled";
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phandle = <0x1e>;
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};
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serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0x78b1000 0x200>;
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interrupts = <0x00 0x132 0x04>;
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clocks = <0x03 0x24 0x03 0x15>;
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clock-names = "core\0iface";
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dmas = <0x06 0x04 0x06 0x05>;
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dma-names = "tx\0rx";
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pinctrl-0 = <0x07>;
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pinctrl-names = "default";
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status = "okay";
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phandle = <0x1f>;
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};
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serial@78b3000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0x78b3000 0x200>;
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interrupts = <0x00 0x134 0x04>;
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clocks = <0x03 0x26 0x03 0x15>;
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clock-names = "core\0iface";
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pinctrl-0 = <0x08>;
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pinctrl-names = "default";
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status = "okay";
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phandle = <0x20>;
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};
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spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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reg = <0x78b5000 0x600>;
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interrupts = <0x00 0x5f 0x04>;
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spi-max-frequency = <0x2faf080>;
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clocks = <0x03 0x17 0x03 0x15>;
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clock-names = "core\0iface";
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dmas = <0x06 0x0c 0x06 0x0d>;
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dma-names = "tx\0rx";
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pinctrl-0 = <0x09>;
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pinctrl-names = "default";
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status = "okay";
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phandle = <0x21>;
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m25p80@0 {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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compatible = "jedec,spi-nor";
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reg = <0x00>;
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spi-max-frequency = <0x2faf080>;
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};
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};
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i2c@78b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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reg = <0x78b6000 0x600>;
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interrupts = <0x00 0x60 0x04>;
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clocks = <0x03 0x15 0x03 0x18>;
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clock-names = "iface\0core";
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clock-frequency = <0x61a80>;
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dmas = <0x06 0x0f 0x06 0x0e>;
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dma-names = "rx\0tx";
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pinctrl-0 = <0x0a>;
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pinctrl-names = "default";
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status = "okay";
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phandle = <0x22>;
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};
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i2c@78b7000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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reg = <0x78b7000 0x600>;
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interrupts = <0x00 0x61 0x04>;
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clocks = <0x03 0x15 0x03 0x1a>;
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clock-names = "iface\0core";
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clock-frequency = <0x186a0>;
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dmas = <0x06 0x11 0x06 0x10>;
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dma-names = "rx\0tx";
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status = "disabled";
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phandle = <0x23>;
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};
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dma@7984000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7984000 0x1a000>;
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interrupts = <0x00 0x92 0x04>;
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clocks = <0x03 0x29>;
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clock-names = "bam_clk";
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#dma-cells = <0x01>;
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qcom,ee = <0x00>;
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status = "okay";
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phandle = <0x0b>;
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};
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nand-controller@79b0000 {
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compatible = "qcom,ipq8074-nand";
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reg = <0x79b0000 0x10000>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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clocks = <0x03 0x2a 0x03 0x29>;
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clock-names = "core\0aon";
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dmas = <0x0b 0x00 0x0b 0x01 0x0b 0x02>;
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dma-names = "tx\0rx\0cmd";
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pinctrl-0 = <0x0c>;
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pinctrl-names = "default";
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status = "okay";
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phandle = <0x24>;
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nand@0 {
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reg = <0x00>;
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nand-ecc-strength = <0x04>;
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nand-ecc-step-size = <0x200>;
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nand-bus-width = <0x08>;
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};
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};
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usb@8af8800 {
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compatible = "qcom,dwc3";
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reg = <0x8af8800 0x400>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x7c 0x03 0x7d 0x03 0x81 0x03 0x7e>;
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clock-names = "sys_noc_axi\0master\0sleep\0mock_utmi";
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assigned-clocks = <0x03 0x7c 0x03 0x7d 0x03 0x7e>;
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assigned-clock-rates = <0x7f27450 0x7f27450 0x124f800>;
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resets = <0x03 0x2b>;
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status = "okay";
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phandle = <0x25>;
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dwc3@8a00000 {
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compatible = "snps,dwc3";
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reg = <0x8a00000 0xcd00>;
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interrupts = <0x00 0x8c 0x04>;
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phys = <0x0d 0x0e>;
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phy-names = "usb2-phy\0usb3-phy";
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snps,is-utmi-l1-suspend;
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snps,hird-threshold = [00];
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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dr_mode = "host";
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phandle = <0x26>;
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};
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};
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usb@8cf8800 {
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compatible = "qcom,dwc3";
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reg = <0x8cf8800 0x400>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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clocks = <0x03 0x83 0x03 0x84 0x03 0x88 0x03 0x85>;
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clock-names = "sys_noc_axi\0master\0sleep\0mock_utmi";
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assigned-clocks = <0x03 0x83 0x03 0x84 0x03 0x85>;
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assigned-clock-rates = <0x7f27450 0x7f27450 0x124f800>;
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resets = <0x03 0x2e>;
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status = "okay";
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phandle = <0x27>;
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dwc3@8c00000 {
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compatible = "snps,dwc3";
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reg = <0x8c00000 0xcd00>;
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interrupts = <0x00 0x63 0x04>;
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phys = <0x0f 0x10>;
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phy-names = "usb2-phy\0usb3-phy";
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snps,is-utmi-l1-suspend;
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snps,hird-threshold = [00];
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
|
|
dr_mode = "host";
|
|
phandle = <0x28>;
|
|
};
|
|
};
|
|
|
|
interrupt-controller@b000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
reg = <0xb000000 0x1000 0xb002000 0x1000>;
|
|
phandle = <0x01>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
|
|
};
|
|
|
|
watchdog@b017000 {
|
|
compatible = "qcom,kpss-wdt";
|
|
reg = <0xb017000 0x1000>;
|
|
interrupts = <0x00 0x03 0x01>;
|
|
clocks = <0x11>;
|
|
timeout-sec = <0x1e>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
timer@b120000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0xb120000 0x1000>;
|
|
clock-frequency = <0x124f800>;
|
|
|
|
frame@b120000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>;
|
|
reg = <0xb121000 0x1000 0xb122000 0x1000>;
|
|
};
|
|
|
|
frame@b123000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
reg = <0xb123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b124000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0xb124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b125000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
reg = <0xb125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b126000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
reg = <0xb126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b127000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
reg = <0xb127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b128000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
reg = <0xb128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pci@10000000 {
|
|
compatible = "qcom,pcie-ipq8074";
|
|
reg = <0x10000000 0xf1d 0x10000f20 0xa8 0x88000 0x2000 0x10100000 0x1000>;
|
|
reg-names = "dbi\0elbi\0parf\0config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0x01>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <0x01>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
phys = <0x12>;
|
|
phy-names = "pciephy";
|
|
ranges = <0x81000000 0x00 0x00 0x10200000 0x00 0x10000 0x82000000 0x00 0x10220000 0x10220000 0x00 0xfde0000>;
|
|
interrupts = <0x00 0x55 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x8e 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x8f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x90 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x91 0x04>;
|
|
clocks = <0x03 0x7a 0x03 0x77 0x03 0x78 0x03 0x75 0x03 0x76>;
|
|
clock-names = "iface\0axi_m\0axi_s\0ahb\0aux";
|
|
resets = <0x03 0x7c 0x03 0x7d 0x03 0x7e 0x03 0x7f 0x03 0x80 0x03 0x81 0x03 0x82>;
|
|
reset-names = "pipe\0sleep\0sticky\0axi_m\0axi_s\0ahb\0axi_m_sticky";
|
|
status = "okay";
|
|
perst-gpio = <0x05 0x3a 0x01>;
|
|
phandle = <0x2a>;
|
|
};
|
|
|
|
pci@20000000 {
|
|
compatible = "qcom,pcie-ipq8074-gen3";
|
|
reg = <0x20000000 0xf1d 0x20000f20 0xa8 0x20001000 0x1000 0x80000 0x4000 0x20100000 0x1000>;
|
|
reg-names = "dbi\0elbi\0atu\0parf\0config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0x00>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <0x01>;
|
|
max-link-speed = <0x03>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
phys = <0x13>;
|
|
phy-names = "pciephy";
|
|
ranges = <0x81000000 0x00 0x00 0x20200000 0x00 0x10000 0x82000000 0x00 0x20220000 0x20220000 0x00 0xfde0000>;
|
|
interrupts = <0x00 0x34 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x4b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x4e 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x4f 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x53 0x04>;
|
|
clocks = <0x03 0x74 0x03 0x71 0x03 0x72 0x03 0xe0 0x03 0xe2>;
|
|
clock-names = "iface\0axi_m\0axi_s\0axi_bridge\0rchng";
|
|
resets = <0x03 0x75 0x03 0x76 0x03 0x77 0x03 0x78 0x03 0x79 0x03 0x7a 0x03 0x7b 0x03 0x83>;
|
|
reset-names = "pipe\0sleep\0sticky\0axi_m\0axi_s\0ahb\0axi_m_sticky\0axi_s_sticky";
|
|
status = "okay";
|
|
perst-gpio = <0x05 0x3d 0x01>;
|
|
phandle = <0x2b>;
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
serial0 = "/soc/serial@78b3000";
|
|
serial1 = "/soc/serial@78b1000";
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0";
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x00 0x40000000 0x00 0x20000000>;
|
|
};
|
|
|
|
__symbols__ {
|
|
sleep_clk = "/clocks/sleep_clk";
|
|
xo = "/clocks/xo";
|
|
CPU0 = "/cpus/cpu@0";
|
|
CPU1 = "/cpus/cpu@1";
|
|
CPU2 = "/cpus/cpu@2";
|
|
CPU3 = "/cpus/cpu@3";
|
|
L2_0 = "/cpus/l2-cache";
|
|
soc = "/soc";
|
|
ssphy_1 = "/soc/phy@58000";
|
|
usb1_ssphy = "/soc/phy@58000/lane@58200";
|
|
qusb_phy_1 = "/soc/phy@59000";
|
|
ssphy_0 = "/soc/phy@78000";
|
|
usb0_ssphy = "/soc/phy@78000/lane@78200";
|
|
qusb_phy_0 = "/soc/phy@79000";
|
|
pcie_qmp0 = "/soc/phy@84000";
|
|
pcie_phy0 = "/soc/phy@84000/phy@84200";
|
|
pcie_qmp1 = "/soc/phy@8e000";
|
|
pcie_phy1 = "/soc/phy@8e000/phy@8e200";
|
|
tlmm = "/soc/pinctrl@1000000";
|
|
serial_4_pins = "/soc/pinctrl@1000000/serial4-pinmux";
|
|
i2c_0_pins = "/soc/pinctrl@1000000/i2c-0-pinmux";
|
|
spi_0_pins = "/soc/pinctrl@1000000/spi-0-pins";
|
|
hsuart_pins = "/soc/pinctrl@1000000/hsuart-pins";
|
|
qpic_pins = "/soc/pinctrl@1000000/qpic-pins";
|
|
gcc = "/soc/gcc@1800000";
|
|
sdhc_1 = "/soc/sdhci@7824900";
|
|
blsp_dma = "/soc/dma@7884000";
|
|
blsp1_uart1 = "/soc/serial@78af000";
|
|
blsp1_uart3 = "/soc/serial@78b1000";
|
|
blsp1_uart5 = "/soc/serial@78b3000";
|
|
blsp1_spi1 = "/soc/spi@78b5000";
|
|
blsp1_i2c2 = "/soc/i2c@78b6000";
|
|
blsp1_i2c3 = "/soc/i2c@78b7000";
|
|
qpic_bam = "/soc/dma@7984000";
|
|
qpic_nand = "/soc/nand-controller@79b0000";
|
|
usb_0 = "/soc/usb@8af8800";
|
|
dwc_0 = "/soc/usb@8af8800/dwc3@8a00000";
|
|
usb_1 = "/soc/usb@8cf8800";
|
|
dwc_1 = "/soc/usb@8cf8800/dwc3@8c00000";
|
|
intc = "/soc/interrupt-controller@b000000";
|
|
watchdog = "/soc/watchdog@b017000";
|
|
pcie1 = "/soc/pci@10000000";
|
|
pcie0 = "/soc/pci@20000000";
|
|
};
|
|
};
|