18525 lines
No EOL
1.3 MiB
Executable file
18525 lines
No EOL
1.3 MiB
Executable file
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/*
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* phy-exynos-usbdp-gen2-v4-reg.h
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*
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* Created on: 2020. 1. 20.
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* Author: daeman.ko
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*/
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#pragma once
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#define USBDP_BIT_MASK_1 0x00000001
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#define USBDP_BIT_MASK_2 0x00000003
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#define USBDP_BIT_MASK_3 0x00000007
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#define USBDP_BIT_MASK_4 0x0000000F
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#define USBDP_BIT_MASK_5 0x0000001F
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#define USBDP_BIT_MASK_6 0x0000003F
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#define USBDP_BIT_MASK_7 0x0000007F
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#define USBDP_BIT_MASK_8 0x000000FF
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#define USBDP_BIT_MASK_9 0x000001FF
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#define USBDP_BIT_MASK_10 0x000003FF
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#define USBDP_BIT_MASK_11 0x000007FF
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#define USBDP_BIT_MASK_12 0x00000FFF
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#define USBDP_BIT_MASK_13 0x00001FFF
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#define USBDP_BIT_MASK_14 0x00003FFF
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#define USBDP_BIT_MASK_15 0x00007FFF
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#define USBDP_BIT_MASK_16 0x0000FFFF
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#define USBDP_BIT_MASK_17 0x0001FFFF
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#define USBDP_BIT_MASK_18 0x0003FFFF
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#define USBDP_BIT_MASK_19 0x0007FFFF
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#define USBDP_BIT_MASK_20 0x000FFFFF
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#define USBDP_BIT_MASK_21 0x001FFFFF
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#define USBDP_BIT_MASK_22 0x003FFFFF
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#define USBDP_BIT_MASK_23 0x007FFFFF
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#define USBDP_BIT_MASK_24 0x00FFFFFF
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#define USBDP_BIT_MASK_25 0x01FFFFFF
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#define USBDP_BIT_MASK_26 0x03FFFFFF
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#define USBDP_BIT_MASK_27 0x07FFFFFF
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#define USBDP_BIT_MASK_28 0x0FFFFFFF
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#define USBDP_BIT_MASK_29 0x1FFFFFFF
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#define USBDP_BIT_MASK_30 0x3FFFFFFF
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#define USBDP_BIT_MASK_31 0x7FFFFFFF
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#define USBDP_BIT_MASK(_bw) USBDP_BIT_MASK_##_bw
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#define USBDP_REG_MSK(_pos, _B) (USBDP_BIT_MASK(_B) << _pos)
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#define USBDP_REG_CLR(_pos, _B) ~(USBDP_REG_MSK(_pos, _B))
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#define USBDP_REG_SET(_val, _pos, _B) ((_val & USBDP_BIT_MASK(_B)) << _pos)
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#define USBDP_REG_GET(_reg, _pos, _B) ((_reg & (USBDP_REG_MSK(_pos, _B))) >> _pos)
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#define EXYNOS_USBDP_CMN_REG0000 (0x0000)
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#define USBDP_CMN_REG0000_OVRD_BGR_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0000_BGR_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0000_BGR_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0000_BGR_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0000_BGR_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_LPF_BYPASS_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_LPF_BYPASS_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0000_OVRD_BGR_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0000_BGR_LPF_BYPASS_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0000_BGR_LPF_BYPASS_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0000_BGR_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0000_BGR_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_820M_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0000_ANA_BGR_820M_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0000_ANA_BGR_820M_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0000_ANA_BGR_820M_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0000_ANA_BGR_CLK_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_CLK_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_CLK_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_CLK_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_LADDER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_LADDER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_LADDER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0000_ANA_BGR_LADDER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0001 (0x0004)
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#define USBDP_CMN_REG0001_ANA_BGR_LADDER_SEL_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0001_ANA_BGR_LADDER_SEL_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0001_ANA_BGR_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0001_ANA_BGR_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0001_ANA_BGR_ATB_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0001_ANA_BGR_ATB_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0001_ANA_BGR_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0001_ANA_BGR_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0001_BIAS_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0001_BIAS_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0001_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0001_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0001_OVRD_BIAS_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0001_BIAS_RCAL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0001_BIAS_RCAL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0001_BIAS_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0001_BIAS_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0002 (0x0008)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0002_OVRD_BGR_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0002_OVRD_BGR_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0002_OVRD_BGR_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0002_OVRD_BGR_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0002_BGR_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0002_BGR_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0002_BGR_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0002_BGR_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_DIV_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_DIV_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0002_ANA_BGR_CHOPPER_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0003 (0x000C)
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#define USBDP_CMN_REG0003_ANA_BGR_SL_CTRL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_SL_CTRL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_SL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_SL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_IE_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_IE_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_IE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0003_ANA_BGR_IE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0004 (0x0010)
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#define USBDP_CMN_REG0004_ANA_BIAS_IREXT_CTRL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IREXT_CTRL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IREXT_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IREXT_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IRMRES_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IRMRES_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IRMRES_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_IRMRES_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_RX_RCAL_IRMRES_CTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_RX_RCAL_IRMRES_CTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_RX_RCAL_IRMRES_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_RX_RCAL_IRMRES_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_TX_RCAL_IRMRES_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_TX_RCAL_IRMRES_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_TX_RCAL_IRMRES_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0004_ANA_BIAS_TX_RCAL_IRMRES_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0005 (0x0014)
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#define USBDP_CMN_REG0005_ANA_BIAS_RX_RCAL_IREXT_CTRL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_RX_RCAL_IREXT_CTRL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_RX_RCAL_IREXT_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_RX_RCAL_IREXT_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_TX_RCAL_IREXT_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_TX_RCAL_IREXT_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_TX_RCAL_IREXT_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_TX_RCAL_IREXT_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0005_OVRD_BIAS_ICAL_COMP_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0005_OVRD_BIAS_ICAL_COMP_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0005_OVRD_BIAS_ICAL_COMP_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0005_OVRD_BIAS_ICAL_COMP_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0005_BIAS_ICAL_COMP_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0005_BIAS_ICAL_COMP_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0005_BIAS_ICAL_COMP_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0005_BIAS_ICAL_COMP_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0005_ANA_BIAS_ICAL_TARGET_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_ICAL_TARGET_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_ICAL_TARGET_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0005_ANA_BIAS_ICAL_TARGET_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0006 (0x0018)
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#define USBDP_CMN_REG0006_ANA_BIAS_VREXT_MON_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_VREXT_MON_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_VREXT_MON_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_VREXT_MON_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0006_OVRD_BIAS_ICAL_CODE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0006_OVRD_BIAS_ICAL_CODE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0006_OVRD_BIAS_ICAL_CODE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0006_OVRD_BIAS_ICAL_CODE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0006_BIAS_ICAL_CODE_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0006_BIAS_ICAL_CODE_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0006_BIAS_ICAL_CODE_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0006_BIAS_ICAL_CODE_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0006_ANA_BIAS_REXT_USE_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_REXT_USE_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_REXT_USE_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0006_ANA_BIAS_REXT_USE_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0007 (0x001C)
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#define USBDP_CMN_REG0007_ANA_BIAS_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0007_ANA_BIAS_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0007_ANA_BIAS_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0007_ANA_BIAS_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0008 (0x0020)
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#define USBDP_CMN_REG0008_OVRD_AUX_RX_TX_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_RX_TX_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_RX_TX_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_RX_TX_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0008_AUX_RX_TX_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0008_AUX_RX_TX_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0008_AUX_RX_TX_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0008_AUX_RX_TX_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0008_OVRD_AUX_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0008_AUX_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0008_AUX_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0008_AUX_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0008_AUX_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_CAP_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_CAP_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_CAP_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_CAP_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_TERM_GND_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_TERM_GND_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_TERM_GND_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0008_ANA_AUX_RX_TERM_GND_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0009 (0x0024)
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#define USBDP_CMN_REG0009_ANA_AUX_TX_TERM_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG0009_ANA_AUX_TX_TERM_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG0009_ANA_AUX_TX_TERM_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG0009_ANA_AUX_TX_TERM_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG0009_ANA_AUX_RX_TERM_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0009_ANA_AUX_RX_TERM_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0009_ANA_AUX_RX_TERM_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0009_ANA_AUX_RX_TERM_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG000A (0x0028)
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#define USBDP_CMN_REG000A_ANA_AUX_TX_LVL_CTRL_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_CMN_REG000A_ANA_AUX_TX_LVL_CTRL_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_CMN_REG000A_ANA_AUX_TX_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_CMN_REG000A_ANA_AUX_TX_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_P_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_P_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_P_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG000A_ANA_AUX_RX_VCM_P_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG000B (0x002C)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_VCM_N_CTRL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_VCM_N_CTRL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_VCM_N_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_VCM_N_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_HYS_CTRL_RESERVED_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_HYS_CTRL_RESERVED_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_HYS_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_RX_HYS_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_REF_CLK_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_REF_CLK_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_REF_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_REF_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_P_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_P_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_P_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_P_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_N_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_N_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_N_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG000B_ANA_AUX_ATB_SEL_N_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG000C (0x0030)
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#define USBDP_CMN_REG000C_ANA_AUX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG000C_ANA_AUX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG000C_ANA_AUX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG000C_ANA_AUX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG000D (0x0034)
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#define USBDP_CMN_REG000D_ANA_AUX_PCIE_TXMODE_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_PCIE_TXMODE_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_PCIE_TXMODE_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_PCIE_TXMODE_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_MODE_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_MODE_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_MODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG000D_ANA_AUX_MODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG000E (0x0038)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG000E_LCPLL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG000E_LCPLL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG000E_LCPLL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG000E_LCPLL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_BEACON_CLK_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_BEACON_CLK_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_BEACON_CLK_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_BEACON_CLK_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_LCVCO_MODE_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_LCVCO_MODE_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_LCVCO_MODE_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG000E_ANA_LCPLL_LCVCO_MODE_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_INIT_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_INIT_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_INIT_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_INIT_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG000E_OVRD_LCPLL_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG000E_LCPLL_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG000F (0x003C)
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#define USBDP_CMN_REG000F_ANA_LCPLL_PI_AFC_CLK_DIV2_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_PI_AFC_CLK_DIV2_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_PI_AFC_CLK_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_PI_AFC_CLK_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_BSEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_BSEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_FROM_PRE_CODE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_FROM_PRE_CODE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_FROM_PRE_CODE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_FROM_PRE_CODE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_MAN_BSEL_L_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_MAN_BSEL_L_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_MAN_BSEL_L_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG000F_ANA_LCPLL_AFC_MAN_BSEL_L_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0010 (0x0040)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_MAN_BSEL_M_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_MAN_BSEL_M_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_MAN_BSEL_M_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_MAN_BSEL_M_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_STB_NUM_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_STB_NUM_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0010_ANA_LCPLL_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0011 (0x0044)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_TOL_NUM_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_TOL_NUM_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_TOL_NUM_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_TOL_NUM_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_VCI_FORCE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_VCI_FORCE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_VCI_FORCE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0011_ANA_LCPLL_AFC_VCI_FORCE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0012 (0x0048)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_RUN_NUM_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_RUN_NUM_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_RUN_NUM_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_RUN_NUM_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_WAIT_NUM_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_WAIT_NUM_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_WAIT_NUM_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0012_ANA_LCPLL_AFC_VCO_CNT_WAIT_NUM_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0013 (0x004C)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_COMP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_COMP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_COMP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_COMP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_FROM_MAX_GM_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_FROM_MAX_GM_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_FROM_MAX_GM_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_FROM_MAX_GM_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_GM_ADD_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_GM_ADD_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_GM_ADD_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_GM_ADD_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_MAN_GM_SEL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_MAN_GM_SEL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_MAN_GM_SEL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0013_ANA_LCPLL_AGMC_MAN_GM_SEL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0014 (0x0050)
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#define USBDP_CMN_REG0014_ANA_LCPLL_AGMC_MAN_GM_SEL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0014_ANA_LCPLL_AGMC_MAN_GM_SEL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0014_ANA_LCPLL_AGMC_MAN_GM_SEL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0014_ANA_LCPLL_AGMC_MAN_GM_SEL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0015 (0x0054)
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#define USBDP_CMN_REG0015_ANA_LCPLL_AGMC_TG_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0015_ANA_LCPLL_AGMC_TG_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0015_ANA_LCPLL_AGMC_TG_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0015_ANA_LCPLL_AGMC_TG_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0016 (0x0058)
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#define USBDP_CMN_REG0016_ANA_LCPLL_AVC_CNT_RUN_NUM_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0016_ANA_LCPLL_AVC_CNT_RUN_NUM_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0016_ANA_LCPLL_AVC_CNT_RUN_NUM_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0016_ANA_LCPLL_AVC_CNT_RUN_NUM_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0017 (0x005C)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_CNT_WAIT_NUM_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_CNT_WAIT_NUM_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_CNT_WAIT_NUM_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_CNT_WAIT_NUM_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_FORCE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_FORCE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_FORCE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0017_ANA_LCPLL_AVC_FORCE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0018 (0x0060)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_VCI_MAX_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_VCI_MAX_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_VCI_MAX_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0018_ANA_LCPLL_AVC_VCI_MAX_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0019 (0x0064)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MID_SEL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MID_SEL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MID_SEL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MID_SEL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MIN_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MIN_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MIN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0019_ANA_LCPLL_AVC_VCI_MIN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG001A (0x0068)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_COARSE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_COARSE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_COARSE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_COARSE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_FINE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_FINE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG001A_LCPLL_ANA_CPI_CTRL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG001B (0x006C)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_COARSE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_COARSE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_COARSE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_COARSE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_FINE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_FINE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG001B_LCPLL_ANA_CPP_CTRL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG001C (0x0070)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_VREF_SEL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_VREF_SEL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_GM_COMP_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_VREG_I_CTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_VREG_I_CTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_VREG_I_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG001C_ANA_LCPLL_ANA_LC_VREG_I_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG001C_OVRD_LCPLL_ANA_LC_VREF_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG001C_OVRD_LCPLL_ANA_LC_VREF_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG001C_OVRD_LCPLL_ANA_LC_VREF_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG001C_OVRD_LCPLL_ANA_LC_VREF_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG001C_LCPLL_LC_VREF_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG001C_LCPLL_LC_VREF_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG001C_LCPLL_LC_VREF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG001C_LCPLL_LC_VREF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG001D (0x0074)
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#define USBDP_CMN_REG001D_ANA_LCPLL_ANA_LC_VREG_R_SEL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG001D_ANA_LCPLL_ANA_LC_VREG_R_SEL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG001D_ANA_LCPLL_ANA_LC_VREG_R_SEL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG001D_ANA_LCPLL_ANA_LC_VREG_R_SEL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG001D_LCPLL_ANA_LPF_C_SEL_COARSE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG001D_LCPLL_ANA_LPF_C_SEL_COARSE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG001D_LCPLL_ANA_LPF_C_SEL_COARSE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG001D_LCPLL_ANA_LPF_C_SEL_COARSE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG001E (0x0078)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_C_SEL_FINE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_C_SEL_FINE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_C_SEL_FINE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_C_SEL_FINE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_R_SEL_COARSE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_R_SEL_COARSE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_R_SEL_COARSE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG001E_LCPLL_ANA_LPF_R_SEL_COARSE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG001F (0x007C)
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#define USBDP_CMN_REG001F_LCPLL_ANA_LPF_R_SEL_FINE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG001F_LCPLL_ANA_LPF_R_SEL_FINE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG001F_LCPLL_ANA_LPF_R_SEL_FINE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG001F_LCPLL_ANA_LPF_R_SEL_FINE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_TEST_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_TEST_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_TEST_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG001F_ANA_LCPLL_ANA_VCI_TEST_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0020 (0x0080)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_HIGH_SEL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_HIGH_SEL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_HIGH_SEL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_HIGH_SEL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_MID_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_MID_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_MID_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0020_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_MID_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0021 (0x0084)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_LOW_SEL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_LOW_SEL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_LOW_SEL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_LOW_SEL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_FILTER_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_FILTER_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_FILTER_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_BIAS_FILTER_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_VDD_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_VDD_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_VDD_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_VCO_CAP_VDD_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_CAP_BIAS_LDO_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_CAP_BIAS_LDO_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_CAP_BIAS_LDO_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0021_ANA_LCPLL_ANA_LC_CAP_BIAS_LDO_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0022 (0x0088)
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#define USBDP_CMN_REG0022_ANA_LCPLL_ATB_SEL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0022_ANA_LCPLL_ATB_SEL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0022_ANA_LCPLL_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0022_ANA_LCPLL_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0023 (0x008C)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FINE_STEP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FINE_STEP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FINE_STEP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FINE_STEP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FIX_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FIX_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FIX_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_FIX_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_SEL_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_SEL_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_SEL_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0023_ANA_LCPLL_EOM_PH_SEL_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0023_ANA_LCPLL_FLD_FAST_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_FLD_FAST_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_FLD_FAST_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0023_ANA_LCPLL_FLD_FAST_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0024 (0x0090)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_FAST_SETTLE_NUM_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_FAST_SETTLE_NUM_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_FAST_SETTLE_NUM_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_FAST_SETTLE_NUM_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_LOCK_TOL_NUM_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_LOCK_TOL_NUM_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_LOCK_TOL_NUM_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0024_ANA_LCPLL_FLD_LOCK_TOL_NUM_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0025 (0x0094)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_NON_CONTINUOUS_MODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_NON_CONTINUOUS_MODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_NON_CONTINUOUS_MODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_NON_CONTINUOUS_MODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_SLOW_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_SLOW_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_SLOW_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_FLD_SLOW_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_STR_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_STR_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_STR_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0025_ANA_LCPLL_PI_STR_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0025_ANA_LCPLL_100M_CLK_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_100M_CLK_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_100M_CLK_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0025_ANA_LCPLL_100M_CLK_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0026 (0x0098)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_DIV2_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_DIV2_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_MON_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_MON_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_FB_CLK_MON_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_FB_CLK_MON_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_FB_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0026_ANA_LCPLL_PI_FB_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_MDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_MDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_MDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_MDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_PDIV_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_PDIV_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_PDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0026_OVRD_LCPLL_PMS_PDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_PDIV_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_PDIV_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_PDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0026_LCPLL_PMS_PDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0027 (0x009C)
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#define USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0028 (0x00A0)
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#define USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0029 (0x00A4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_PDIV_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_PDIV_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_PDIV_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_PDIV_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_REFDIV_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_REFDIV_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_REFDIV_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0029_ANA_LCPLL_PMS_REFDIV_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG002A (0x00A8)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG002B (0x00AC)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG002B_LCPLL_PMS_SDIV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG002C (0x00B0)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG002C_LCPLL_PMS_SDIV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG002D (0x00B4)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_MOD_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_MOD_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_MOD_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_MOD_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_PMS_IQDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_PMS_IQDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_PMS_IQDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_PMS_IQDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG002D_LCPLL_PMS_IQDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG002D_LCPLL_PMS_IQDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG002D_LCPLL_PMS_IQDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG002D_LCPLL_PMS_IQDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG002D_OVRD_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG002D_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG002D_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG002D_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG002D_LCPLL_REF_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG002E (0x00B8)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_BYPASS_CLK_SEL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_BYPASS_CLK_SEL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_BYPASS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_BYPASS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_DIV_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_DIV_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG002E_ANA_LCPLL_REF_CHOPPER_CLK_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG002E_OVRD_LCPLL_REF_CLK_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG002E_OVRD_LCPLL_REF_CLK_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG002E_OVRD_LCPLL_REF_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG002E_OVRD_LCPLL_REF_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG002E_LCPLL_REF_CLK_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG002E_LCPLL_REF_CLK_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG002E_LCPLL_REF_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG002E_LCPLL_REF_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG002F (0x00BC)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_DIG_CLK_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_DIG_CLK_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_DIG_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_DIG_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_AFC_CLK_SEL_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_AFC_CLK_SEL_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_AFC_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_CMN_REG002F_ANA_LCPLL_REF_AFC_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG002F_ANA_LCPLL_PI_CDIV_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG002F_ANA_LCPLL_SDM_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_SDM_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_SDM_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG002F_ANA_LCPLL_SDM_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0030 (0x00C0)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDM_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDM_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDM_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDM_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDM_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDM_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDM_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDM_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0030_ANA_LCPLL_SDC_FRACTIONAL_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0030_ANA_LCPLL_SDC_FRACTIONAL_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0030_ANA_LCPLL_SDC_FRACTIONAL_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0030_ANA_LCPLL_SDC_FRACTIONAL_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0030_OVRD_LCPLL_SDC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0030_LCPLL_SDC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0031 (0x00C4)
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#define USBDP_CMN_REG0031_ANA_LCPLL_SDM_CLK_DIV_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0031_ANA_LCPLL_SDM_CLK_DIV_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0031_ANA_LCPLL_SDM_CLK_DIV_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0031_ANA_LCPLL_SDM_CLK_DIV_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0032 (0x00C8)
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#define USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0033 (0x00CC)
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#define USBDP_CMN_REG0033_ANA_LCPLL_SDM_NUMERATOR_SIGN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0033_ANA_LCPLL_SDM_NUMERATOR_SIGN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0033_ANA_LCPLL_SDM_NUMERATOR_SIGN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0033_ANA_LCPLL_SDM_NUMERATOR_SIGN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0034 (0x00D0)
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#define USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0035 (0x00D4)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PI_STEP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PI_STEP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PI_STEP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDM_PI_STEP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0036 (0x00D8)
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#define USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0037 (0x00DC)
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#define USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_CMN_REG0037_OVRD_LCPLL_SDC_NDIV_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0037_OVRD_LCPLL_SDC_NDIV_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0037_OVRD_LCPLL_SDC_NDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0037_OVRD_LCPLL_SDC_NDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0037_LCPLL_SDC_NDIV_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0037_LCPLL_SDC_NDIV_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0037_LCPLL_SDC_NDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0037_LCPLL_SDC_NDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0038 (0x00E0)
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#define USBDP_CMN_REG0038_ANA_LCPLL_SDC_MC_VALUE_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0038_ANA_LCPLL_SDC_MC_VALUE_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0038_ANA_LCPLL_SDC_MC_VALUE_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0038_ANA_LCPLL_SDC_MC_VALUE_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0038_OVRD_LCPLL_SSC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0038_OVRD_LCPLL_SSC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0038_OVRD_LCPLL_SSC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0038_OVRD_LCPLL_SSC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0038_LCPLL_SSC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0038_LCPLL_SSC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0038_LCPLL_SSC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0038_LCPLL_SSC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0039 (0x00E4)
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#define USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG003A (0x00E8)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_PROFILE_OPT_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_PROFILE_OPT_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_PROFILE_OPT_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG003A_ANA_LCPLL_SSC_PROFILE_OPT_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG003B (0x00EC)
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#define USBDP_CMN_REG003B_ANA_LCPLL_SSC_CLK_DIV_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG003B_ANA_LCPLL_SSC_CLK_DIV_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG003B_ANA_LCPLL_SSC_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG003B_ANA_LCPLL_SSC_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_CLK_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_CLK_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_CLK_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_CLK_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_CLK_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_CLK_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_CLK_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_CLK_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_TX_SER_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_TX_SER_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_TX_SER_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG003B_OVRD_LCPLL_CD_TX_SER_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_TX_SER_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_TX_SER_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_TX_SER_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG003B_LCPLL_CD_TX_SER_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG003C (0x00F0)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_TX_SER_RATE_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_TX_SER_RATE_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_TX_SER_RATE_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_TX_SER_RATE_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_INV_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_INV_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_INV_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_INV_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_INV_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_INV_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_INV_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_INV_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_CTRL_RESERVED_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_CTRL_RESERVED_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_WEST_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG003C_ANA_LCPLL_CD_HSCLK_EAST_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG003D (0x00F4)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_WEST_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_WEST_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_WEST_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_WEST_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_WEST_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_WEST_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_WEST_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_WEST_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_EAST_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_EAST_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_EAST_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_RSTN_EAST_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_EAST_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_EAST_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_EAST_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_RSTN_EAST_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_WEST_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_WEST_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_WEST_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_WEST_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_EAST_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_EAST_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_EAST_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG003D_ANA_LCPLL_CD_DIV2_EAST_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_HSCLK_WEST_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_HSCLK_WEST_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_HSCLK_WEST_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG003D_OVRD_LCPLL_CD_HSCLK_WEST_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_HSCLK_WEST_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_HSCLK_WEST_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_HSCLK_WEST_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG003D_LCPLL_CD_HSCLK_WEST_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG003E (0x00F8)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_HSCLK_EAST_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_HSCLK_EAST_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_HSCLK_EAST_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_HSCLK_EAST_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_HSCLK_EAST_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_HSCLK_EAST_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_HSCLK_EAST_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_HSCLK_EAST_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG003E_OVRD_LCPLL_CD_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG003E_LCPLL_CD_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG003F (0x00FC)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_ICTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_ICTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_ICTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_ICTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_OUT_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_OUT_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG003F_ANA_LCPLL_CD_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0040 (0x0100)
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#define USBDP_CMN_REG0040_ANA_LCPLL_CD_VREG_LADDER_SEL_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0040_ANA_LCPLL_CD_VREG_LADDER_SEL_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0040_ANA_LCPLL_CD_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0040_ANA_LCPLL_CD_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_LANE_TX_CLK_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_LANE_TX_CLK_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_LANE_TX_CLK_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_LANE_TX_CLK_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0040_LCPLL_USB_LANE_TX_CLK_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0040_LCPLL_USB_LANE_TX_CLK_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0040_LCPLL_USB_LANE_TX_CLK_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0040_LCPLL_USB_LANE_TX_CLK_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_TX_CLK_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_TX_CLK_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_TX_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0040_OVRD_LCPLL_USB_TX_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0040_LCPLL_USB_TX_CLK_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0040_LCPLL_USB_TX_CLK_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0040_LCPLL_USB_TX_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0040_LCPLL_USB_TX_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0041 (0x0104)
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#define USBDP_CMN_REG0041_OVRD_LCPLL_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0041_OVRD_LCPLL_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0041_OVRD_LCPLL_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0041_OVRD_LCPLL_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0041_LCPLL_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0041_LCPLL_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0041_LCPLL_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0041_LCPLL_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SYNC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SYNC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_CLK_DIV10_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_CLK_DIV10_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_CLK_DIV10_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_CLK_DIV10_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_CMN_REG0041_ANA_LCPLL_MISC_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_CMN_REG0041_ANA_LCPLL_REF_CLK_MON_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_REF_CLK_MON_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_REF_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0041_ANA_LCPLL_REF_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0042 (0x0108)
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#define USBDP_CMN_REG0042_ANA_LCPLL_REF_CLK_MON_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0042_ANA_LCPLL_REF_CLK_MON_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0042_ANA_LCPLL_REF_CLK_MON_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0042_ANA_LCPLL_REF_CLK_MON_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0042_OVRD_LCPLL_MISC_OSC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0042_OVRD_LCPLL_MISC_OSC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0042_OVRD_LCPLL_MISC_OSC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0042_OVRD_LCPLL_MISC_OSC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0042_LCPLL_MISC_OSC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0042_LCPLL_MISC_OSC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0042_LCPLL_MISC_OSC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0042_LCPLL_MISC_OSC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0043 (0x010C)
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#define USBDP_CMN_REG0043_LCPLL_MISC_CLK_DIV_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0043_LCPLL_MISC_CLK_DIV_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0043_LCPLL_MISC_CLK_DIV_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0043_LCPLL_MISC_CLK_DIV_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0044 (0x0110)
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#define USBDP_CMN_REG0044_LCPLL_MISC_CLK_DIV_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0044_LCPLL_MISC_CLK_DIV_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0044_LCPLL_MISC_CLK_DIV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0044_LCPLL_MISC_CLK_DIV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0045 (0x0114)
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#define USBDP_CMN_REG0045_LCPLL_MISC_CLK_DIV_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0045_LCPLL_MISC_CLK_DIV_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0045_LCPLL_MISC_CLK_DIV_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0045_LCPLL_MISC_CLK_DIV_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0046 (0x0118)
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#define USBDP_CMN_REG0046_LCPLL_MISC_CLK_DIV_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0046_LCPLL_MISC_CLK_DIV_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0046_LCPLL_MISC_CLK_DIV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0046_LCPLL_MISC_CLK_DIV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0047 (0x011C)
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#define USBDP_CMN_REG0047_LCPLL_MISC_CLK_DIV_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0047_LCPLL_MISC_CLK_DIV_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0047_LCPLL_MISC_CLK_DIV_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0047_LCPLL_MISC_CLK_DIV_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0048 (0x0120)
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#define USBDP_CMN_REG0048_LCPLL_MISC_CLK_DIV_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0048_LCPLL_MISC_CLK_DIV_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0048_LCPLL_MISC_CLK_DIV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0048_LCPLL_MISC_CLK_DIV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0049 (0x0124)
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#define USBDP_CMN_REG0049_OVRD_LCPLL_MISC_OSC_FREQ_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0049_OVRD_LCPLL_MISC_OSC_FREQ_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0049_OVRD_LCPLL_MISC_OSC_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0049_OVRD_LCPLL_MISC_OSC_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0049_LCPLL_MISC_OSC_FREQ_SEL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_CMN_REG0049_LCPLL_MISC_OSC_FREQ_SEL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_CMN_REG0049_LCPLL_MISC_OSC_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_CMN_REG0049_LCPLL_MISC_OSC_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_CMN_REG0049_ANA_LCPLL_100M_CLK_DIV_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0049_ANA_LCPLL_100M_CLK_DIV_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0049_ANA_LCPLL_100M_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0049_ANA_LCPLL_100M_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG004A (0x0128)
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#define USBDP_CMN_REG004A_ANA_LCPLL_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004A_ANA_LCPLL_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004A_ANA_LCPLL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004A_ANA_LCPLL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG004B (0x012C)
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#define USBDP_CMN_REG004B_LCPLL_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004B_LCPLL_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004B_LCPLL_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004B_LCPLL_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG004C (0x0130)
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#define USBDP_CMN_REG004C_LCPLL_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004C_LCPLL_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004C_LCPLL_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004C_LCPLL_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG004D (0x0134)
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#define USBDP_CMN_REG004D_LCPLL_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004D_LCPLL_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004D_LCPLL_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004D_LCPLL_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG004E (0x0138)
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#define USBDP_CMN_REG004E_LCPLL_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004E_LCPLL_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004E_LCPLL_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004E_LCPLL_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG004F (0x013C)
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#define USBDP_CMN_REG004F_LCPLL_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG004F_LCPLL_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG004F_LCPLL_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG004F_LCPLL_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0050 (0x0140)
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#define USBDP_CMN_REG0050_LCPLL_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0050_LCPLL_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0050_LCPLL_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0050_LCPLL_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0051 (0x0144)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0051_ROPLL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0051_ROPLL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0051_ROPLL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0051_ROPLL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_BEACON_CLK_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_BEACON_CLK_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_BEACON_CLK_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_BEACON_CLK_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_LCVCO_MODE_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_LCVCO_MODE_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_LCVCO_MODE_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0051_ANA_ROPLL_LCVCO_MODE_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_INIT_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_INIT_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_INIT_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_INIT_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0051_OVRD_ROPLL_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0051_ROPLL_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0052 (0x0148)
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#define USBDP_CMN_REG0052_ANA_ROPLL_PI_AFC_CLK_DIV2_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_PI_AFC_CLK_DIV2_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_PI_AFC_CLK_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_PI_AFC_CLK_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_BSEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_BSEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_FROM_PRE_CODE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_FROM_PRE_CODE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_FROM_PRE_CODE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_FROM_PRE_CODE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_MAN_BSEL_L_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_MAN_BSEL_L_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_MAN_BSEL_L_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0052_ANA_ROPLL_AFC_MAN_BSEL_L_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0053 (0x014C)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_MAN_BSEL_M_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_MAN_BSEL_M_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_MAN_BSEL_M_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_MAN_BSEL_M_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_STB_NUM_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_STB_NUM_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0053_ANA_ROPLL_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0054 (0x0150)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_TOL_NUM_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_TOL_NUM_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_TOL_NUM_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_TOL_NUM_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_VCI_FORCE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_VCI_FORCE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_VCI_FORCE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0054_ANA_ROPLL_AFC_VCI_FORCE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0055 (0x0154)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_RUN_NUM_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_RUN_NUM_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_RUN_NUM_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_RUN_NUM_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_WAIT_NUM_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_WAIT_NUM_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_WAIT_NUM_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0055_ANA_ROPLL_AFC_VCO_CNT_WAIT_NUM_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0056 (0x0158)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_COMP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_COMP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_COMP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_COMP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_FROM_MAX_GM_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_FROM_MAX_GM_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_FROM_MAX_GM_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_FROM_MAX_GM_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_GM_ADD_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_GM_ADD_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_GM_ADD_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_GM_ADD_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_MAN_GM_SEL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_MAN_GM_SEL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_MAN_GM_SEL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0056_ANA_ROPLL_AGMC_MAN_GM_SEL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0057 (0x015C)
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#define USBDP_CMN_REG0057_ANA_ROPLL_AGMC_MAN_GM_SEL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0057_ANA_ROPLL_AGMC_MAN_GM_SEL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0057_ANA_ROPLL_AGMC_MAN_GM_SEL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0057_ANA_ROPLL_AGMC_MAN_GM_SEL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0058 (0x0160)
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#define USBDP_CMN_REG0058_ANA_ROPLL_AGMC_TG_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0058_ANA_ROPLL_AGMC_TG_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0058_ANA_ROPLL_AGMC_TG_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0058_ANA_ROPLL_AGMC_TG_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0059 (0x0164)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_COARSE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_COARSE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_COARSE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_COARSE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_FINE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_FINE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0059_ROPLL_ANA_CPI_CTRL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG005A (0x0168)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_COARSE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_COARSE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_COARSE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_COARSE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_FINE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_FINE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG005A_ROPLL_ANA_CPP_CTRL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG005B (0x016C)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_COARSE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_COARSE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_COARSE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_COARSE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_FINE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_FINE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG005B_ROPLL_ANA_LPF_C_SEL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG005C (0x0170)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_COARSE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_COARSE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_COARSE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_COARSE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_FINE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_FINE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG005C_ROPLL_ANA_LPF_R_SEL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG005D (0x0174)
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#define USBDP_CMN_REG005D_ANA_ROPLL_ANA_RING_DCC_EN_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG005D_ANA_ROPLL_ANA_RING_DCC_EN_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG005D_ANA_ROPLL_ANA_RING_DCC_EN_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG005D_ANA_ROPLL_ANA_RING_DCC_EN_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_COARSE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_COARSE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_COARSE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_COARSE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_FINE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_FINE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_FINE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG005D_ROPLL_ANA_RING_PI_RATIO_CTRL_FINE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG005E (0x0178)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_TEST_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_TEST_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_TEST_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG005E_ANA_ROPLL_ANA_VCI_TEST_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG005F (0x017C)
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#define USBDP_CMN_REG005F_ANA_ROPLL_ATB_SEL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG005F_ANA_ROPLL_ATB_SEL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG005F_ANA_ROPLL_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG005F_ANA_ROPLL_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0060 (0x0180)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FINE_STEP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FINE_STEP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FINE_STEP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FINE_STEP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FIX_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FIX_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FIX_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_FIX_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_SEL_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_SEL_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_SEL_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0060_ANA_ROPLL_EOM_PH_SEL_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0060_ANA_ROPLL_FLD_FAST_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_FLD_FAST_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_FLD_FAST_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0060_ANA_ROPLL_FLD_FAST_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0061 (0x0184)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_FAST_SETTLE_NUM_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_FAST_SETTLE_NUM_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_FAST_SETTLE_NUM_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_FAST_SETTLE_NUM_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_LOCK_TOL_NUM_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_LOCK_TOL_NUM_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_LOCK_TOL_NUM_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG0061_ANA_ROPLL_FLD_LOCK_TOL_NUM_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG0062 (0x0188)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_NON_CONTINUOUS_MODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_NON_CONTINUOUS_MODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_NON_CONTINUOUS_MODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_NON_CONTINUOUS_MODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_SLOW_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_SLOW_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_SLOW_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_FLD_SLOW_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_STR_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_STR_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_STR_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_CMN_REG0062_ANA_ROPLL_PI_STR_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_CMN_REG0062_ANA_ROPLL_100M_CLK_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_100M_CLK_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_100M_CLK_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0062_ANA_ROPLL_100M_CLK_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0063 (0x018C)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_DIV2_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_DIV2_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_MON_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_MON_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_FB_CLK_MON_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_FB_CLK_MON_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_FB_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0063_ANA_ROPLL_PI_FB_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_MDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_MDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_MDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_MDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_PDIV_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_PDIV_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_PDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0063_OVRD_ROPLL_PMS_PDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_PDIV_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_PDIV_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_PDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0063_ROPLL_PMS_PDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0064 (0x0190)
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#define USBDP_CMN_REG0064_ROPLL_PMS_MDIV_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0064_ROPLL_PMS_MDIV_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0064_ROPLL_PMS_MDIV_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0064_ROPLL_PMS_MDIV_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0065 (0x0194)
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#define USBDP_CMN_REG0065_ROPLL_PMS_MDIV_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0065_ROPLL_PMS_MDIV_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0065_ROPLL_PMS_MDIV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0065_ROPLL_PMS_MDIV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0066 (0x0198)
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#define USBDP_CMN_REG0066_ROPLL_PMS_MDIV_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0066_ROPLL_PMS_MDIV_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0066_ROPLL_PMS_MDIV_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0066_ROPLL_PMS_MDIV_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0067 (0x019C)
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#define USBDP_CMN_REG0067_ROPLL_PMS_MDIV_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0067_ROPLL_PMS_MDIV_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0067_ROPLL_PMS_MDIV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0067_ROPLL_PMS_MDIV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0068 (0x01A0)
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#define USBDP_CMN_REG0068_ROPLL_PMS_MDIV_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0068_ROPLL_PMS_MDIV_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0068_ROPLL_PMS_MDIV_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0068_ROPLL_PMS_MDIV_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0069 (0x01A4)
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#define USBDP_CMN_REG0069_ROPLL_PMS_MDIV_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0069_ROPLL_PMS_MDIV_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0069_ROPLL_PMS_MDIV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0069_ROPLL_PMS_MDIV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006A (0x01A8)
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#define USBDP_CMN_REG006A_ROPLL_PMS_MDIV_AFC_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006A_ROPLL_PMS_MDIV_AFC_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006A_ROPLL_PMS_MDIV_AFC_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006A_ROPLL_PMS_MDIV_AFC_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006B (0x01AC)
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#define USBDP_CMN_REG006B_ROPLL_PMS_MDIV_AFC_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006B_ROPLL_PMS_MDIV_AFC_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006B_ROPLL_PMS_MDIV_AFC_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006B_ROPLL_PMS_MDIV_AFC_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006C (0x01B0)
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#define USBDP_CMN_REG006C_ROPLL_PMS_MDIV_AFC_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006C_ROPLL_PMS_MDIV_AFC_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006C_ROPLL_PMS_MDIV_AFC_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006C_ROPLL_PMS_MDIV_AFC_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006D (0x01B4)
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#define USBDP_CMN_REG006D_ROPLL_PMS_MDIV_AFC_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006D_ROPLL_PMS_MDIV_AFC_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006D_ROPLL_PMS_MDIV_AFC_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006D_ROPLL_PMS_MDIV_AFC_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006E (0x01B8)
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#define USBDP_CMN_REG006E_ROPLL_PMS_MDIV_AFC_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006E_ROPLL_PMS_MDIV_AFC_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006E_ROPLL_PMS_MDIV_AFC_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006E_ROPLL_PMS_MDIV_AFC_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG006F (0x01BC)
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#define USBDP_CMN_REG006F_ROPLL_PMS_MDIV_AFC_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG006F_ROPLL_PMS_MDIV_AFC_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG006F_ROPLL_PMS_MDIV_AFC_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG006F_ROPLL_PMS_MDIV_AFC_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0070 (0x01C0)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_PDIV_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_PDIV_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_PDIV_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_PDIV_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_REFDIV_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_REFDIV_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_REFDIV_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0070_ANA_ROPLL_PMS_REFDIV_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0071 (0x01C4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0071_ROPLL_PMS_SDIV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0072 (0x01C8)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0072_ROPLL_PMS_SDIV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0073 (0x01CC)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0073_ROPLL_PMS_SDIV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0074 (0x01D0)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_MOD_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_MOD_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_MOD_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_MOD_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0074_OVRD_ROPLL_PMS_IQDIV_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0074_OVRD_ROPLL_PMS_IQDIV_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0074_OVRD_ROPLL_PMS_IQDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0074_OVRD_ROPLL_PMS_IQDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0074_ROPLL_PMS_IQDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0074_ROPLL_PMS_IQDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0074_ROPLL_PMS_IQDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0074_ROPLL_PMS_IQDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_BYPASS_CLK_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_BYPASS_CLK_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_BYPASS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_BYPASS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_CHOPPER_CLK_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_CHOPPER_CLK_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_CHOPPER_CLK_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0074_ANA_ROPLL_REF_CHOPPER_CLK_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0075 (0x01D4)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0075_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0075_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0075_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0075_ROPLL_REF_CHOPPER_CLK_DIV_RSTN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_CHOPPER_CLK_DIV_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_CHOPPER_CLK_DIV_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_CHOPPER_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_CHOPPER_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CLK_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CLK_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0075_OVRD_ROPLL_REF_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0075_ROPLL_REF_CLK_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_CMN_REG0075_ROPLL_REF_CLK_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_CMN_REG0075_ROPLL_REF_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_CMN_REG0075_ROPLL_REF_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_DIG_CLK_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_DIG_CLK_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_DIG_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0075_ANA_ROPLL_REF_DIG_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0076 (0x01D8)
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#define USBDP_CMN_REG0076_ANA_ROPLL_REF_AFC_CLK_SEL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0076_ANA_ROPLL_REF_AFC_CLK_SEL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0076_ANA_ROPLL_REF_AFC_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0076_ANA_ROPLL_REF_AFC_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0076_ANA_ROPLL_SDM_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0076_ANA_ROPLL_SDM_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0076_ANA_ROPLL_SDM_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0076_ANA_ROPLL_SDM_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0076_OVRD_ROPLL_SDM_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0076_OVRD_ROPLL_SDM_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0076_OVRD_ROPLL_SDM_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0076_OVRD_ROPLL_SDM_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDM_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDM_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDM_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDM_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SP_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SP_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SP_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SP_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SSP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SSP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SSP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_SSP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_RBR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_RBR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_RBR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0076_ROPLL_SDC_FRACTIONAL_EN_RBR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0077 (0x01DC)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR2_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR2_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR2_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR2_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR3_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR3_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_FRACTIONAL_EN_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0077_OVRD_ROPLL_SDC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0077_OVRD_ROPLL_SDC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0077_OVRD_ROPLL_SDC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0077_OVRD_ROPLL_SDC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0077_ROPLL_SDC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0078 (0x01E0)
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#define USBDP_CMN_REG0078_ANA_ROPLL_SDM_CLK_DIV_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0078_ANA_ROPLL_SDM_CLK_DIV_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0078_ANA_ROPLL_SDM_CLK_DIV_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0078_ANA_ROPLL_SDM_CLK_DIV_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0079 (0x01E4)
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#define USBDP_CMN_REG0079_ROPLL_SDM_DENOMINATOR_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0079_ROPLL_SDM_DENOMINATOR_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0079_ROPLL_SDM_DENOMINATOR_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0079_ROPLL_SDM_DENOMINATOR_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007A (0x01E8)
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#define USBDP_CMN_REG007A_ROPLL_SDM_DENOMINATOR_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG007A_ROPLL_SDM_DENOMINATOR_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG007A_ROPLL_SDM_DENOMINATOR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG007A_ROPLL_SDM_DENOMINATOR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007B (0x01EC)
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#define USBDP_CMN_REG007B_ROPLL_SDM_DENOMINATOR_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG007B_ROPLL_SDM_DENOMINATOR_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG007B_ROPLL_SDM_DENOMINATOR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG007B_ROPLL_SDM_DENOMINATOR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007C (0x01F0)
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#define USBDP_CMN_REG007C_ROPLL_SDM_DENOMINATOR_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG007C_ROPLL_SDM_DENOMINATOR_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG007C_ROPLL_SDM_DENOMINATOR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG007C_ROPLL_SDM_DENOMINATOR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007D (0x01F4)
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#define USBDP_CMN_REG007D_ROPLL_SDM_DENOMINATOR_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG007D_ROPLL_SDM_DENOMINATOR_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG007D_ROPLL_SDM_DENOMINATOR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG007D_ROPLL_SDM_DENOMINATOR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007E (0x01F8)
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#define USBDP_CMN_REG007E_ROPLL_SDM_DENOMINATOR_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG007E_ROPLL_SDM_DENOMINATOR_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG007E_ROPLL_SDM_DENOMINATOR_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG007E_ROPLL_SDM_DENOMINATOR_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG007F (0x01FC)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG007F_ROPLL_SDM_NUMERATOR_SIGN_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0080 (0x0200)
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#define USBDP_CMN_REG0080_ROPLL_SDM_NUMERATOR_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0080_ROPLL_SDM_NUMERATOR_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0080_ROPLL_SDM_NUMERATOR_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0080_ROPLL_SDM_NUMERATOR_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0081 (0x0204)
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#define USBDP_CMN_REG0081_ROPLL_SDM_NUMERATOR_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0081_ROPLL_SDM_NUMERATOR_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0081_ROPLL_SDM_NUMERATOR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0081_ROPLL_SDM_NUMERATOR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0082 (0x0208)
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#define USBDP_CMN_REG0082_ROPLL_SDM_NUMERATOR_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0082_ROPLL_SDM_NUMERATOR_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0082_ROPLL_SDM_NUMERATOR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0082_ROPLL_SDM_NUMERATOR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0083 (0x020C)
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#define USBDP_CMN_REG0083_ROPLL_SDM_NUMERATOR_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0083_ROPLL_SDM_NUMERATOR_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0083_ROPLL_SDM_NUMERATOR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0083_ROPLL_SDM_NUMERATOR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0084 (0x0210)
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#define USBDP_CMN_REG0084_ROPLL_SDM_NUMERATOR_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0084_ROPLL_SDM_NUMERATOR_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0084_ROPLL_SDM_NUMERATOR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0084_ROPLL_SDM_NUMERATOR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0085 (0x0214)
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#define USBDP_CMN_REG0085_ROPLL_SDM_NUMERATOR_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0085_ROPLL_SDM_NUMERATOR_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0085_ROPLL_SDM_NUMERATOR_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0085_ROPLL_SDM_NUMERATOR_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0086 (0x0218)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PI_STEP_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PI_STEP_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PI_STEP_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_CMN_REG0086_ANA_ROPLL_SDM_PI_STEP_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_CMN_REG0086_ROPLL_SDC_N_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0086_ROPLL_SDC_N_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0086_ROPLL_SDC_N_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0086_ROPLL_SDC_N_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0087 (0x021C)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0087_ROPLL_SDC_N_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0088 (0x0220)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0088_ROPLL_SDC_N_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0089 (0x0224)
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#define USBDP_CMN_REG0089_ROPLL_SDC_N_HBR3_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG0089_ROPLL_SDC_N_HBR3_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG0089_ROPLL_SDC_N_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG0089_ROPLL_SDC_N_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG008A (0x0228)
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#define USBDP_CMN_REG008A_ROPLL_SDC_NUMERATOR_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008A_ROPLL_SDC_NUMERATOR_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008A_ROPLL_SDC_NUMERATOR_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008A_ROPLL_SDC_NUMERATOR_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG008B (0x022C)
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#define USBDP_CMN_REG008B_ROPLL_SDC_NUMERATOR_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008B_ROPLL_SDC_NUMERATOR_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008B_ROPLL_SDC_NUMERATOR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008B_ROPLL_SDC_NUMERATOR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG008C (0x0230)
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#define USBDP_CMN_REG008C_ROPLL_SDC_NUMERATOR_RBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008C_ROPLL_SDC_NUMERATOR_RBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008C_ROPLL_SDC_NUMERATOR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008C_ROPLL_SDC_NUMERATOR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG008D (0x0234)
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#define USBDP_CMN_REG008D_ROPLL_SDC_NUMERATOR_HBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008D_ROPLL_SDC_NUMERATOR_HBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008D_ROPLL_SDC_NUMERATOR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008D_ROPLL_SDC_NUMERATOR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG008E (0x0238)
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#define USBDP_CMN_REG008E_ROPLL_SDC_NUMERATOR_HBR2_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008E_ROPLL_SDC_NUMERATOR_HBR2_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008E_ROPLL_SDC_NUMERATOR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008E_ROPLL_SDC_NUMERATOR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG008F (0x023C)
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#define USBDP_CMN_REG008F_ROPLL_SDC_NUMERATOR_HBR3_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG008F_ROPLL_SDC_NUMERATOR_HBR3_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG008F_ROPLL_SDC_NUMERATOR_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG008F_ROPLL_SDC_NUMERATOR_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0090 (0x0240)
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#define USBDP_CMN_REG0090_ROPLL_SDC_DENOMINATOR_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0090_ROPLL_SDC_DENOMINATOR_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0090_ROPLL_SDC_DENOMINATOR_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0090_ROPLL_SDC_DENOMINATOR_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0091 (0x0244)
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#define USBDP_CMN_REG0091_ROPLL_SDC_DENOMINATOR_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0091_ROPLL_SDC_DENOMINATOR_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0091_ROPLL_SDC_DENOMINATOR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0091_ROPLL_SDC_DENOMINATOR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0092 (0x0248)
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#define USBDP_CMN_REG0092_ROPLL_SDC_DENOMINATOR_RBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0092_ROPLL_SDC_DENOMINATOR_RBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0092_ROPLL_SDC_DENOMINATOR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0092_ROPLL_SDC_DENOMINATOR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0093 (0x024C)
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#define USBDP_CMN_REG0093_ROPLL_SDC_DENOMINATOR_HBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0093_ROPLL_SDC_DENOMINATOR_HBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0093_ROPLL_SDC_DENOMINATOR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0093_ROPLL_SDC_DENOMINATOR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0094 (0x0250)
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#define USBDP_CMN_REG0094_ROPLL_SDC_DENOMINATOR_HBR2_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0094_ROPLL_SDC_DENOMINATOR_HBR2_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0094_ROPLL_SDC_DENOMINATOR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0094_ROPLL_SDC_DENOMINATOR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0095 (0x0254)
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#define USBDP_CMN_REG0095_ROPLL_SDC_DENOMINATOR_HBR3_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_CMN_REG0095_ROPLL_SDC_DENOMINATOR_HBR3_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_CMN_REG0095_ROPLL_SDC_DENOMINATOR_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_CMN_REG0095_ROPLL_SDC_DENOMINATOR_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_CMN_REG0095_ANA_ROPLL_SDC_MC_VALUE_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0095_ANA_ROPLL_SDC_MC_VALUE_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0095_ANA_ROPLL_SDC_MC_VALUE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0095_ANA_ROPLL_SDC_MC_VALUE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0096 (0x0258)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SDC_NDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SDC_NDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SDC_NDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SDC_NDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0096_ROPLL_SDC_NDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0096_ROPLL_SDC_NDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0096_ROPLL_SDC_NDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0096_ROPLL_SDC_NDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SSC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SSC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SSC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0096_OVRD_ROPLL_SSC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0096_ROPLL_SSC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0096_ROPLL_SSC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0096_ROPLL_SSC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0096_ROPLL_SSC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0097 (0x025C)
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#define USBDP_CMN_REG0097_ROPLL_SSC_FM_DEVIATION_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0097_ROPLL_SSC_FM_DEVIATION_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0097_ROPLL_SSC_FM_DEVIATION_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0097_ROPLL_SSC_FM_DEVIATION_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0098 (0x0260)
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#define USBDP_CMN_REG0098_ROPLL_SSC_FM_DEVIATION_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0098_ROPLL_SSC_FM_DEVIATION_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0098_ROPLL_SSC_FM_DEVIATION_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0098_ROPLL_SSC_FM_DEVIATION_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG0099 (0x0264)
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#define USBDP_CMN_REG0099_ROPLL_SSC_FM_DEVIATION_RBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG0099_ROPLL_SSC_FM_DEVIATION_RBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG0099_ROPLL_SSC_FM_DEVIATION_RBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG0099_ROPLL_SSC_FM_DEVIATION_RBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG009A (0x0268)
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#define USBDP_CMN_REG009A_ROPLL_SSC_FM_DEVIATION_HBR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG009A_ROPLL_SSC_FM_DEVIATION_HBR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG009A_ROPLL_SSC_FM_DEVIATION_HBR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG009A_ROPLL_SSC_FM_DEVIATION_HBR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG009B (0x026C)
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#define USBDP_CMN_REG009B_ROPLL_SSC_FM_DEVIATION_HBR2_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG009B_ROPLL_SSC_FM_DEVIATION_HBR2_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG009B_ROPLL_SSC_FM_DEVIATION_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG009B_ROPLL_SSC_FM_DEVIATION_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG009C (0x0270)
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#define USBDP_CMN_REG009C_ROPLL_SSC_FM_DEVIATION_HBR3_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG009C_ROPLL_SSC_FM_DEVIATION_HBR3_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG009C_ROPLL_SSC_FM_DEVIATION_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG009C_ROPLL_SSC_FM_DEVIATION_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG009D (0x0274)
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#define USBDP_CMN_REG009D_ROPLL_SSC_FM_FREQ_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG009D_ROPLL_SSC_FM_FREQ_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG009D_ROPLL_SSC_FM_FREQ_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG009D_ROPLL_SSC_FM_FREQ_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG009E (0x0278)
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#define USBDP_CMN_REG009E_ROPLL_SSC_FM_FREQ_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG009E_ROPLL_SSC_FM_FREQ_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG009E_ROPLL_SSC_FM_FREQ_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG009E_ROPLL_SSC_FM_FREQ_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG009F (0x027C)
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#define USBDP_CMN_REG009F_ROPLL_SSC_FM_FREQ_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG009F_ROPLL_SSC_FM_FREQ_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG009F_ROPLL_SSC_FM_FREQ_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG009F_ROPLL_SSC_FM_FREQ_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00A0 (0x0280)
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#define USBDP_CMN_REG00A0_ROPLL_SSC_FM_FREQ_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00A0_ROPLL_SSC_FM_FREQ_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00A0_ROPLL_SSC_FM_FREQ_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00A0_ROPLL_SSC_FM_FREQ_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00A1 (0x0284)
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#define USBDP_CMN_REG00A1_ROPLL_SSC_FM_FREQ_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00A1_ROPLL_SSC_FM_FREQ_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00A1_ROPLL_SSC_FM_FREQ_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00A1_ROPLL_SSC_FM_FREQ_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00A2 (0x0288)
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#define USBDP_CMN_REG00A2_ROPLL_SSC_FM_FREQ_HBR3_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_CMN_REG00A2_ROPLL_SSC_FM_FREQ_HBR3_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_CMN_REG00A2_ROPLL_SSC_FM_FREQ_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_CMN_REG00A2_ROPLL_SSC_FM_FREQ_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_CMN_REG00A2_ANA_ROPLL_SSC_PROFILE_OPT_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00A2_ANA_ROPLL_SSC_PROFILE_OPT_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00A2_ANA_ROPLL_SSC_PROFILE_OPT_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00A2_ANA_ROPLL_SSC_PROFILE_OPT_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00A3 (0x028C)
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#define USBDP_CMN_REG00A3_ANA_ROPLL_SSC_CLK_DIV_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG00A3_ANA_ROPLL_SSC_CLK_DIV_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG00A3_ANA_ROPLL_SSC_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG00A3_ANA_ROPLL_SSC_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_CLK_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_CLK_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_CLK_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_CLK_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_CLK_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_CLK_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_CLK_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_CLK_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_TX_SER_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_TX_SER_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_TX_SER_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00A3_OVRD_ROPLL_CD_TX_SER_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_TX_SER_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_TX_SER_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_TX_SER_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00A3_ROPLL_CD_TX_SER_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00A4 (0x0290)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_TX_SER_RATE_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_TX_SER_RATE_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_TX_SER_RATE_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_TX_SER_RATE_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_INV_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_INV_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_INV_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_INV_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_INV_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_INV_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_INV_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_INV_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_CTRL_RESERVED_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_CTRL_RESERVED_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_WEST_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00A4_ANA_ROPLL_CD_HSCLK_EAST_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00A5 (0x0294)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_WEST_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_WEST_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_WEST_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_WEST_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_WEST_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_WEST_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_WEST_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_WEST_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_EAST_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_EAST_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_EAST_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_RSTN_EAST_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_EAST_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_EAST_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_EAST_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_RSTN_EAST_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_WEST_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_WEST_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_WEST_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_WEST_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_EAST_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_EAST_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_EAST_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00A5_ANA_ROPLL_CD_DIV2_EAST_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_HSCLK_WEST_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_HSCLK_WEST_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_HSCLK_WEST_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00A5_OVRD_ROPLL_CD_HSCLK_WEST_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_HSCLK_WEST_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_HSCLK_WEST_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_HSCLK_WEST_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00A5_ROPLL_CD_HSCLK_WEST_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00A6 (0x0298)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_HSCLK_EAST_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_HSCLK_EAST_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_HSCLK_EAST_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_HSCLK_EAST_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_HSCLK_EAST_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_HSCLK_EAST_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_HSCLK_EAST_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_HSCLK_EAST_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00A6_OVRD_ROPLL_CD_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00A6_ROPLL_CD_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00A7 (0x029C)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_ICTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_ICTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_ICTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_ICTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_OUT_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_OUT_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00A7_ANA_ROPLL_CD_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00A8 (0x02A0)
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#define USBDP_CMN_REG00A8_ANA_ROPLL_CD_VREG_LADDER_SEL_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG00A8_ANA_ROPLL_CD_VREG_LADDER_SEL_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG00A8_ANA_ROPLL_CD_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG00A8_ANA_ROPLL_CD_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_LANE_TX_CLK_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_LANE_TX_CLK_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_LANE_TX_CLK_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_LANE_TX_CLK_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00A8_ROPLL_USB_LANE_TX_CLK_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00A8_ROPLL_USB_LANE_TX_CLK_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00A8_ROPLL_USB_LANE_TX_CLK_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00A8_ROPLL_USB_LANE_TX_CLK_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_TX_CLK_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_TX_CLK_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_TX_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00A8_OVRD_ROPLL_USB_TX_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00A8_ROPLL_USB_TX_CLK_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00A8_ROPLL_USB_TX_CLK_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00A8_ROPLL_USB_TX_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00A8_ROPLL_USB_TX_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00A9 (0x02A4)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00A9_ROPLL_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00A9_ROPLL_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00A9_ROPLL_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00A9_ROPLL_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SYNC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SYNC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SEL_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SEL_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_MISC_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_REF_CLK_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_REF_CLK_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_REF_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00A9_ANA_ROPLL_REF_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_MISC_OSC_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_MISC_OSC_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_MISC_OSC_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00A9_OVRD_ROPLL_MISC_OSC_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00A9_ROPLL_MISC_OSC_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00A9_ROPLL_MISC_OSC_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00A9_ROPLL_MISC_OSC_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00A9_ROPLL_MISC_OSC_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00AA (0x02A8)
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#define USBDP_CMN_REG00AA_ROPLL_MISC_CLK_DIV_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AA_ROPLL_MISC_CLK_DIV_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AA_ROPLL_MISC_CLK_DIV_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AA_ROPLL_MISC_CLK_DIV_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00AB (0x02AC)
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#define USBDP_CMN_REG00AB_ROPLL_MISC_CLK_DIV_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AB_ROPLL_MISC_CLK_DIV_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AB_ROPLL_MISC_CLK_DIV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AB_ROPLL_MISC_CLK_DIV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00AC (0x02B0)
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#define USBDP_CMN_REG00AC_ROPLL_MISC_CLK_DIV_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AC_ROPLL_MISC_CLK_DIV_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AC_ROPLL_MISC_CLK_DIV_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AC_ROPLL_MISC_CLK_DIV_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00AD (0x02B4)
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#define USBDP_CMN_REG00AD_ROPLL_MISC_CLK_DIV_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AD_ROPLL_MISC_CLK_DIV_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AD_ROPLL_MISC_CLK_DIV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AD_ROPLL_MISC_CLK_DIV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00AE (0x02B8)
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#define USBDP_CMN_REG00AE_ROPLL_MISC_CLK_DIV_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AE_ROPLL_MISC_CLK_DIV_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AE_ROPLL_MISC_CLK_DIV_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AE_ROPLL_MISC_CLK_DIV_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00AF (0x02BC)
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#define USBDP_CMN_REG00AF_ROPLL_MISC_CLK_DIV_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00AF_ROPLL_MISC_CLK_DIV_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00AF_ROPLL_MISC_CLK_DIV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00AF_ROPLL_MISC_CLK_DIV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00B0 (0x02C0)
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#define USBDP_CMN_REG00B0_OVRD_ROPLL_MISC_OSC_FREQ_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00B0_OVRD_ROPLL_MISC_OSC_FREQ_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00B0_OVRD_ROPLL_MISC_OSC_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00B0_OVRD_ROPLL_MISC_OSC_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00B0_ROPLL_MISC_OSC_FREQ_SEL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_CMN_REG00B0_ROPLL_MISC_OSC_FREQ_SEL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_CMN_REG00B0_ROPLL_MISC_OSC_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_CMN_REG00B0_ROPLL_MISC_OSC_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_CMN_REG00B0_ANA_ROPLL_100M_CLK_DIV_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00B0_ANA_ROPLL_100M_CLK_DIV_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00B0_ANA_ROPLL_100M_CLK_DIV_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00B0_ANA_ROPLL_100M_CLK_DIV_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00B1 (0x02C4)
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#define USBDP_CMN_REG00B1_ANA_ROPLL_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B1_ANA_ROPLL_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B1_ANA_ROPLL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B1_ANA_ROPLL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B2 (0x02C8)
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#define USBDP_CMN_REG00B2_ROPLL_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B2_ROPLL_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B2_ROPLL_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B2_ROPLL_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B3 (0x02CC)
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#define USBDP_CMN_REG00B3_ROPLL_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B3_ROPLL_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B3_ROPLL_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B3_ROPLL_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B4 (0x02D0)
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#define USBDP_CMN_REG00B4_ROPLL_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B4_ROPLL_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B4_ROPLL_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B4_ROPLL_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B5 (0x02D4)
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#define USBDP_CMN_REG00B5_ROPLL_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B5_ROPLL_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B5_ROPLL_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B5_ROPLL_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B6 (0x02D8)
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#define USBDP_CMN_REG00B6_ROPLL_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B6_ROPLL_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B6_ROPLL_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B6_ROPLL_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B7 (0x02DC)
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#define USBDP_CMN_REG00B7_ROPLL_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00B7_ROPLL_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00B7_ROPLL_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00B7_ROPLL_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00B8 (0x02E0)
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#define USBDP_CMN_REG00B8_CMN_RESERVED0_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG00B8_CMN_RESERVED0_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG00B8_CMN_RESERVED0_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG00B8_CMN_RESERVED0_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG00B8_SSC_EN_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG00B8_SSC_EN_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG00B8_SSC_EN_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG00B8_SSC_EN_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG00B8_LANE_MUX_SEL_DP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00B8_LANE_MUX_SEL_DP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00B8_LANE_MUX_SEL_DP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00B8_LANE_MUX_SEL_DP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00B9 (0x02E4)
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#define USBDP_CMN_REG00B9_CMN_RESERVED1_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG00B9_CMN_RESERVED1_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG00B9_CMN_RESERVED1_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG00B9_CMN_RESERVED1_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG00B9_DP_TX_LINK_BW_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG00B9_DP_TX_LINK_BW_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG00B9_DP_TX_LINK_BW_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG00B9_DP_TX_LINK_BW_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG00B9_DP_LANE_EN_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00B9_DP_LANE_EN_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00B9_DP_LANE_EN_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00B9_DP_LANE_EN_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00BA (0x02E8)
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#define USBDP_CMN_REG00BA_DTB_OUT_EN_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00BA_DTB_OUT_EN_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00BA_DTB_OUT_EN_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00BA_DTB_OUT_EN_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00BB (0x02EC)
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#define USBDP_CMN_REG00BB_AUX_DTB_OUT_EN_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00BB_AUX_DTB_OUT_EN_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00BB_AUX_DTB_OUT_EN_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00BB_AUX_DTB_OUT_EN_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00BC (0x02F0)
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#define USBDP_CMN_REG00BC_CMN_DTB_SEL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00BC_CMN_DTB_SEL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00BC_CMN_DTB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00BC_CMN_DTB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00BD (0x02F4)
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#define USBDP_CMN_REG00BD_DP_TX_LANE_SWAP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00BD_DP_TX_LANE_SWAP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00BD_DP_TX_LANE_SWAP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00BD_DP_TX_LANE_SWAP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_SWAP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_SWAP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_SWAP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_SWAP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_INV_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_INV_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_INV_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00BD_DP_TX_DATA_INV_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00BD_AUX_RX_DATA_INV_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00BD_AUX_RX_DATA_INV_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00BD_AUX_RX_DATA_INV_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00BD_AUX_RX_DATA_INV_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00BD_AUX_TX_DATA_INV_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00BD_AUX_TX_DATA_INV_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00BD_AUX_TX_DATA_INV_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00BD_AUX_TX_DATA_INV_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00BD_DP_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00BD_DP_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00BD_DP_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00BD_DP_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00BD_DP_CMN_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00BD_DP_CMN_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00BD_DP_CMN_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00BD_DP_CMN_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00BE (0x02F8)
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#define USBDP_CMN_REG00BE_DP_TX_LN0_DATA_DELAY_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN0_DATA_DELAY_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN0_DATA_DELAY_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN0_DATA_DELAY_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN1_DATA_DELAY_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN1_DATA_DELAY_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN1_DATA_DELAY_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN1_DATA_DELAY_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN2_DATA_DELAY_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN2_DATA_DELAY_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN2_DATA_DELAY_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN2_DATA_DELAY_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN3_DATA_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN3_DATA_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN3_DATA_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00BE_DP_TX_LN3_DATA_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00BF (0x02FC)
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#define USBDP_CMN_REG00BF_RX_LFPS_DET_FILT_MODE_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_CMN_REG00BF_RX_LFPS_DET_FILT_MODE_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_CMN_REG00BF_RX_LFPS_DET_FILT_MODE_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_CMN_REG00BF_RX_LFPS_DET_FILT_MODE_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_CMN_REG00BF_CMN_RESERVED2_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED2_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED2_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED2_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED3_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED3_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED3_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED3_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED4_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED4_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED4_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00BF_CMN_RESERVED4_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00C0 (0x0300)
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#define USBDP_CMN_REG00C0_CMN_RESERVED5_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG00C0_CMN_RESERVED5_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG00C0_CMN_RESERVED5_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG00C0_CMN_RESERVED5_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG00C1 (0x0304)
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#define USBDP_CMN_REG00C1_CMN_RESERVED6_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG00C1_CMN_RESERVED6_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG00C1_CMN_RESERVED6_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG00C1_CMN_RESERVED6_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG00C2 (0x0308)
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#define USBDP_CMN_REG00C2_CMN_RESERVED7_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG00C2_CMN_RESERVED7_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG00C2_CMN_RESERVED7_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG00C2_CMN_RESERVED7_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG00C3 (0x030C)
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#define USBDP_CMN_REG00C3_CMN_RESERVED8_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG00C3_CMN_RESERVED8_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG00C3_CMN_RESERVED8_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG00C3_CMN_RESERVED8_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG00C4 (0x0310)
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#define USBDP_CMN_REG00C4_CMN_RESERVED9_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00C4_CMN_RESERVED9_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00C4_CMN_RESERVED9_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00C4_CMN_RESERVED9_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00C5 (0x0314)
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#define USBDP_CMN_REG00C5_CMN_RESERVED10_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00C5_CMN_RESERVED10_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00C5_CMN_RESERVED10_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00C5_CMN_RESERVED10_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00C6 (0x0318)
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#define USBDP_CMN_REG00C6_CMN_RESERVED11_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00C6_CMN_RESERVED11_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00C6_CMN_RESERVED11_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00C6_CMN_RESERVED11_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00C7 (0x031C)
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#define USBDP_CMN_REG00C7_CMN_RESERVED12_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00C7_CMN_RESERVED12_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00C7_CMN_RESERVED12_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00C7_CMN_RESERVED12_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00C8 (0x0320)
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#define USBDP_CMN_REG00C8_RX_CLK_MASK_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00C8_RX_CLK_MASK_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00C8_RX_CLK_MASK_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00C8_RX_CLK_MASK_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00C8_HS_CLK_MASK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00C8_HS_CLK_MASK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00C8_HS_CLK_MASK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00C8_HS_CLK_MASK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00C8_DP_TX_CLK_MASK_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00C8_DP_TX_CLK_MASK_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00C8_DP_TX_CLK_MASK_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00C8_DP_TX_CLK_MASK_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00C8_VCOCLK_MON_SEL_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_CMN_REG00C8_VCOCLK_MON_SEL_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_CMN_REG00C8_VCOCLK_MON_SEL_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_CMN_REG00C8_VCOCLK_MON_SEL_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_CMN_REG00C8_LCPLL_LOCK_DONE_DELAY_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00C8_LCPLL_LOCK_DONE_DELAY_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00C8_LCPLL_LOCK_DONE_DELAY_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00C8_LCPLL_LOCK_DONE_DELAY_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00C9 (0x0324)
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#define USBDP_CMN_REG00C9_ROPLL_LOCK_DONE_DELAY_CODE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00C9_ROPLL_LOCK_DONE_DELAY_CODE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00C9_ROPLL_LOCK_DONE_DELAY_CODE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00C9_ROPLL_LOCK_DONE_DELAY_CODE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00C9_CDR_LOCK_DELAY_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00C9_CDR_LOCK_DELAY_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00C9_CDR_LOCK_DELAY_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00C9_CDR_LOCK_DELAY_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00CA (0x0328)
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#define USBDP_CMN_REG00CA_RX_OC_DONE_DELAY_CODE_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG00CA_RX_OC_DONE_DELAY_CODE_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG00CA_RX_OC_DONE_DELAY_CODE_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG00CA_RX_OC_DONE_DELAY_CODE_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG00CA_OVRD_LCPLL_FINE_TUNE_START_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00CA_OVRD_LCPLL_FINE_TUNE_START_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00CA_OVRD_LCPLL_FINE_TUNE_START_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00CA_OVRD_LCPLL_FINE_TUNE_START_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00CA_LCPLL_FINE_TUNE_START_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00CA_LCPLL_FINE_TUNE_START_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00CA_LCPLL_FINE_TUNE_START_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00CA_LCPLL_FINE_TUNE_START_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00CA_OVRD_ROPLL_FINE_TUNE_START_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00CA_OVRD_ROPLL_FINE_TUNE_START_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00CA_OVRD_ROPLL_FINE_TUNE_START_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00CA_OVRD_ROPLL_FINE_TUNE_START_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00CA_ROPLL_FINE_TUNE_START_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00CA_ROPLL_FINE_TUNE_START_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00CA_ROPLL_FINE_TUNE_START_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00CA_ROPLL_FINE_TUNE_START_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00CA_CMN_TIMER_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00CA_CMN_TIMER_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00CA_CMN_TIMER_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00CA_CMN_TIMER_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00CB (0x032C)
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#define USBDP_CMN_REG00CB_TG_BGR_FAST_PULSE_TIME_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG00CB_TG_BGR_FAST_PULSE_TIME_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG00CB_TG_BGR_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG00CB_TG_BGR_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG00CB_TG_LCPLL_VREG_FAST_PULSE_TIME_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00CB_TG_LCPLL_VREG_FAST_PULSE_TIME_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00CB_TG_LCPLL_VREG_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00CB_TG_LCPLL_VREG_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00CC (0x0330)
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#define USBDP_CMN_REG00CC_TG_BGR_SET_DELAY_TIME_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG00CC_TG_BGR_SET_DELAY_TIME_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG00CC_TG_BGR_SET_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG00CC_TG_BGR_SET_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG00CC_TG_LCPLL_CD_VREG_FAST_PULSE_TIME_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00CC_TG_LCPLL_CD_VREG_FAST_PULSE_TIME_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00CC_TG_LCPLL_CD_VREG_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00CC_TG_LCPLL_CD_VREG_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00CD (0x0334)
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#define USBDP_CMN_REG00CD_TG_ROPLL_CD_VREG_FAST_PULSE_TIME_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_CMN_REG00CD_TG_ROPLL_CD_VREG_FAST_PULSE_TIME_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_CMN_REG00CD_TG_ROPLL_CD_VREG_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_CMN_REG00CD_TG_ROPLL_CD_VREG_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_CMN_REG00CD_TG_LCPLL_SDM_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00CD_TG_LCPLL_SDM_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00CD_TG_LCPLL_SDM_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00CD_TG_LCPLL_SDM_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00CE (0x0338)
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#define USBDP_CMN_REG00CE_TG_ROPLL_SDM_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00CE_TG_ROPLL_SDM_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00CE_TG_ROPLL_SDM_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00CE_TG_ROPLL_SDM_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00CE_TG_LCPLL_AFC_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00CE_TG_LCPLL_AFC_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00CE_TG_LCPLL_AFC_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00CE_TG_LCPLL_AFC_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00CF (0x033C)
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#define USBDP_CMN_REG00CF_TG_ROPLL_AFC_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00CF_TG_ROPLL_AFC_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00CF_TG_ROPLL_AFC_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00CF_TG_ROPLL_AFC_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00CF_TG_LCPLL_FINE_LOCK_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00CF_TG_LCPLL_FINE_LOCK_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00CF_TG_LCPLL_FINE_LOCK_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00CF_TG_LCPLL_FINE_LOCK_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D0 (0x0340)
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#define USBDP_CMN_REG00D0_TG_ROPLL_FINE_LOCK_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00D0_TG_ROPLL_FINE_LOCK_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00D0_TG_ROPLL_FINE_LOCK_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00D0_TG_ROPLL_FINE_LOCK_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00D0_TG_LCPLL_SSC_EN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00D0_TG_LCPLL_SSC_EN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00D0_TG_LCPLL_SSC_EN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00D0_TG_LCPLL_SSC_EN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D1 (0x0344)
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#define USBDP_CMN_REG00D1_TG_ROPLL_SSC_EN_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00D1_TG_ROPLL_SSC_EN_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00D1_TG_ROPLL_SSC_EN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00D1_TG_ROPLL_SSC_EN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00D1_TG_LCPLL_SDC_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00D1_TG_LCPLL_SDC_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00D1_TG_LCPLL_SDC_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00D1_TG_LCPLL_SDC_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D2 (0x0348)
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#define USBDP_CMN_REG00D2_TG_ROPLL_SDC_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00D2_TG_ROPLL_SDC_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00D2_TG_ROPLL_SDC_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00D2_TG_ROPLL_SDC_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00D2_TG_LCPLL_CD_TX_SER_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00D2_TG_LCPLL_CD_TX_SER_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00D2_TG_LCPLL_CD_TX_SER_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00D2_TG_LCPLL_CD_TX_SER_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D3 (0x034C)
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#define USBDP_CMN_REG00D3_TG_ROPLL_CD_TX_SER_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00D3_TG_ROPLL_CD_TX_SER_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00D3_TG_ROPLL_CD_TX_SER_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00D3_TG_ROPLL_CD_TX_SER_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00D3_TG_LCPLL_SDC_NDIV_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00D3_TG_LCPLL_SDC_NDIV_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00D3_TG_LCPLL_SDC_NDIV_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00D3_TG_LCPLL_SDC_NDIV_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D4 (0x0350)
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#define USBDP_CMN_REG00D4_TG_ROPLL_SDC_NDIV_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00D4_TG_ROPLL_SDC_NDIV_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00D4_TG_ROPLL_SDC_NDIV_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00D4_TG_ROPLL_SDC_NDIV_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00D5 (0x0354)
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#define USBDP_CMN_REG00D5_DP_CTS_RESERVED0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00D5_DP_CTS_RESERVED0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00D5_DP_CTS_RESERVED0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00D5_DP_CTS_RESERVED0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00D6 (0x0358)
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#define USBDP_CMN_REG00D6_DP_CTS_ENHANCED_MODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_ENHANCED_MODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_ENHANCED_MODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_ENHANCED_MODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_MST_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_MST_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_MST_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_MST_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_INSERT_ERROR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_INSERT_ERROR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_INSERT_ERROR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_INSERT_ERROR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_DISABLE_AUTO_RESET_ENCODE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_DISABLE_AUTO_RESET_ENCODE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_DISABLE_AUTO_RESET_ENCODE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_DISABLE_AUTO_RESET_ENCODE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_PRBS_31_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_PRBS_31_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_PRBS_31_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_PRBS_31_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_NEW_PRBS7_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_NEW_PRBS7_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_NEW_PRBS7_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00D6_DP_CTS_R_NEW_PRBS7_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_USER_PATTERN_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_USER_PATTERN_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_USER_PATTERN_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_USER_PATTERN_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00D6_DP_BIST_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00D7 (0x035C)
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#define USBDP_CMN_REG00D7_DP_BIST_USER_PATTERN__19_16_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00D7_DP_BIST_USER_PATTERN__19_16_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00D7_DP_BIST_USER_PATTERN__19_16_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00D7_DP_BIST_USER_PATTERN__19_16_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00D8 (0x0360)
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#define USBDP_CMN_REG00D8_DP_BIST_USER_PATTERN__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00D8_DP_BIST_USER_PATTERN__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00D8_DP_BIST_USER_PATTERN__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00D8_DP_BIST_USER_PATTERN__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00D9 (0x0364)
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#define USBDP_CMN_REG00D9_DP_BIST_USER_PATTERN__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00D9_DP_BIST_USER_PATTERN__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00D9_DP_BIST_USER_PATTERN__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00D9_DP_BIST_USER_PATTERN__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00DA (0x0368)
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#define USBDP_CMN_REG00DA_DP_CTS_FEC_ENC_CTRL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00DA_DP_CTS_FEC_ENC_CTRL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00DA_DP_CTS_FEC_ENC_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00DA_DP_CTS_FEC_ENC_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00DB (0x036C)
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#define USBDP_CMN_REG00DB_DP_CTS_R_HBR2_EYE_SR_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00DB_DP_CTS_R_HBR2_EYE_SR_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00DB_DP_CTS_R_HBR2_EYE_SR_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00DB_DP_CTS_R_HBR2_EYE_SR_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00DC (0x0370)
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#define USBDP_CMN_REG00DC_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00DC_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00DC_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00DC_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00DD (0x0374)
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#define USBDP_CMN_REG00DD_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00DD_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00DD_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00DD_DP_CTS_R_HBR2_COMPLIANCE_SR_COUNT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00DE (0x0378)
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#define USBDP_CMN_REG00DE_DP_CTS_R_SCRAMBLE_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00DE_DP_CTS_R_SCRAMBLE_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00DE_DP_CTS_R_SCRAMBLE_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00DE_DP_CTS_R_SCRAMBLE_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_TRAINING_PATTERN_SET_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_TRAINING_PATTERN_SET_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_TRAINING_PATTERN_SET_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_TRAINING_PATTERN_SET_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_QUAL_PATTERN_SET_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_QUAL_PATTERN_SET_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_QUAL_PATTERN_SET_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00DE_DP_CTS_R_LINK_QUAL_PATTERN_SET_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00DF (0x037C)
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#define USBDP_CMN_REG00DF_DP_CTS_HBR3_TPS4_PATTERN_CNT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00DF_DP_CTS_HBR3_TPS4_PATTERN_CNT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00DF_DP_CTS_HBR3_TPS4_PATTERN_CNT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00DF_DP_CTS_HBR3_TPS4_PATTERN_CNT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00E0 (0x0380)
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#define USBDP_CMN_REG00E0_DP_CTS_HBR3_TPS4_PATTERN_CNT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00E0_DP_CTS_HBR3_TPS4_PATTERN_CNT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00E0_DP_CTS_HBR3_TPS4_PATTERN_CNT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00E0_DP_CTS_HBR3_TPS4_PATTERN_CNT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00E1 (0x0384)
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#define USBDP_CMN_REG00E1_OVRD_PCS_PM_STATE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_PM_STATE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_PM_STATE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_PM_STATE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E1_PCS_PM_STATE_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG00E1_PCS_PM_STATE_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG00E1_PCS_PM_STATE_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG00E1_PCS_PM_STATE_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG00E1_OVRD_PCS_RATE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_RATE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_RATE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00E1_OVRD_PCS_RATE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00E1_PCS_RATE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG00E1_PCS_RATE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG00E1_PCS_RATE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG00E1_PCS_RATE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG00E2 (0x0388)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BGR_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BGR_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BGR_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BGR_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00E2_PCS_BGR_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E2_PCS_BGR_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E2_PCS_BGR_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E2_PCS_BGR_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BIAS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BIAS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E2_PCS_BIAS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E2_PCS_BIAS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E2_PCS_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E2_PCS_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_POWERDOWN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_POWERDOWN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_POWERDOWN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_POWERDOWN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00E2_PCS_POWERDOWN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00E2_PCS_POWERDOWN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00E2_PCS_POWERDOWN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00E2_PCS_POWERDOWN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_CDR_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_CDR_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_CDR_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E2_OVRD_PCS_CDR_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E2_PCS_CDR_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E2_PCS_CDR_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E2_PCS_CDR_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E2_PCS_CDR_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00E3 (0x038C)
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#define USBDP_CMN_REG00E3_OVRD_PCS_CMN_RSTN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_CMN_RSTN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_CMN_RSTN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_CMN_RSTN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00E3_PCS_CMN_RSTN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E3_PCS_CMN_RSTN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E3_PCS_CMN_RSTN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E3_PCS_CMN_RSTN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_DES_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_DES_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_DES_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_DES_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E3_PCS_DES_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E3_PCS_DES_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E3_PCS_DES_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E3_PCS_DES_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_INIT_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_INIT_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00E3_PCS_INIT_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00E3_PCS_INIT_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00E3_PCS_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00E3_PCS_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_LANE_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_LANE_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_LANE_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E3_OVRD_PCS_LANE_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E3_PCS_LANE_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E3_PCS_LANE_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E3_PCS_LANE_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E3_PCS_LANE_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00E4 (0x0390)
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#define USBDP_CMN_REG00E4_OVRD_PCS_PLL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_PLL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_PLL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_PLL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E4_PCS_PLL_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E4_PCS_PLL_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E4_PCS_PLL_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E4_PCS_PLL_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_REF_FREQ_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_REF_FREQ_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_REF_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_REF_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E4_PCS_REF_FREQ_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG00E4_PCS_REF_FREQ_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG00E4_PCS_REF_FREQ_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG00E4_PCS_REF_FREQ_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG00E4_OVRD_PCS_RX_CTLE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_RX_CTLE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E4_OVRD_PCS_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E4_PCS_RX_CTLE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E4_PCS_RX_CTLE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E4_PCS_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E4_PCS_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00E5 (0x0394)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_HOLD_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_HOLD_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_DFE_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_HOLD_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_HOLD_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_DFE_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_FOM_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_FOM_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_FOM_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_FOM_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_FOM_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_FOM_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_FOM_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_FOM_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_SQHS_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_SQHS_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E5_OVRD_PCS_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_SQHS_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_SQHS_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E5_PCS_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00E6 (0x0398)
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#define USBDP_CMN_REG00E6_OVRD_PCS_RX_TERM_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_RX_TERM_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_RX_TERM_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_RX_TERM_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00E6_PCS_RX_TERM_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E6_PCS_RX_TERM_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E6_PCS_RX_TERM_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E6_PCS_RX_TERM_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_BEACON_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_BEACON_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_BEACON_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_BEACON_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_BEACON_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_BEACON_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_BEACON_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_BEACON_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E6_OVRD_PCS_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E6_PCS_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00E7 (0x039C)
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#define USBDP_CMN_REG00E7_OVRD_PCS_TX_DRVR_LVL_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00E7_OVRD_PCS_TX_DRVR_LVL_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00E7_OVRD_PCS_TX_DRVR_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00E7_OVRD_PCS_TX_DRVR_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00E7_PCS_TX_DRVR_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG00E7_PCS_TX_DRVR_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG00E7_PCS_TX_DRVR_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG00E7_PCS_TX_DRVR_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG00E8 (0x03A0)
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#define USBDP_CMN_REG00E8_OVRD_PCS_TX_DRVR_POST_LVL_CTRL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00E8_OVRD_PCS_TX_DRVR_POST_LVL_CTRL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00E8_OVRD_PCS_TX_DRVR_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00E8_OVRD_PCS_TX_DRVR_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00E8_PCS_TX_DRVR_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG00E8_PCS_TX_DRVR_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG00E8_PCS_TX_DRVR_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG00E8_PCS_TX_DRVR_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG00E9 (0x03A4)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_DRVR_PRE_LVL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_DRVR_PRE_LVL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_DRVR_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_DRVR_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00E9_PCS_TX_DRVR_PRE_LVL_CTRL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_CMN_REG00E9_PCS_TX_DRVR_PRE_LVL_CTRL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_CMN_REG00E9_PCS_TX_DRVR_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_CMN_REG00E9_PCS_TX_DRVR_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_ELECIDLE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_ELECIDLE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_ELECIDLE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00E9_OVRD_PCS_TX_ELECIDLE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00E9_PCS_TX_ELECIDLE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00E9_PCS_TX_ELECIDLE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00E9_PCS_TX_ELECIDLE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00E9_PCS_TX_ELECIDLE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00EA (0x03A8)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_LFPS_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_LFPS_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_LFPS_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_LFPS_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_RX_LFPS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_RX_LFPS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_RX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_RX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00EA_PCS_RX_LFPS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00EA_PCS_RX_LFPS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00EA_PCS_RX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00EA_PCS_RX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_RCV_DET_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_RCV_DET_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_RCV_DET_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_RCV_DET_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_RCV_DET_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_RCV_DET_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_RCV_DET_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_RCV_DET_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_SER_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_SER_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_SER_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00EA_OVRD_PCS_TX_SER_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_SER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_SER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_SER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00EA_PCS_TX_SER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00EB (0x03AC)
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#define USBDP_CMN_REG00EB_OVRD_PCS_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00EB_PCS_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00EB_PCS_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00EB_PCS_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00EB_PCS_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_BGR_SET_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_BGR_SET_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_BGR_SET_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_BGR_SET_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00EB_PCS_BGR_SET_DONE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00EB_PCS_BGR_SET_DONE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00EB_PCS_BGR_SET_DONE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00EB_PCS_BGR_SET_DONE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_CDR_LOCK_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_CDR_LOCK_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_CDR_LOCK_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_CDR_LOCK_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00EB_PCS_CDR_LOCK_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00EB_PCS_CDR_LOCK_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00EB_PCS_CDR_LOCK_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00EB_PCS_CDR_LOCK_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_DP_PLL_LOCK_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_DP_PLL_LOCK_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_DP_PLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00EB_OVRD_PCS_DP_PLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00EB_PCS_DP_PLL_LOCK_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00EB_PCS_DP_PLL_LOCK_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00EB_PCS_DP_PLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00EB_PCS_DP_PLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00EC (0x03B0)
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#define USBDP_CMN_REG00EC_OVRD_PCS_PLL_LOCK_DONE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_PLL_LOCK_DONE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_PLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_PLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00EC_PCS_PLL_LOCK_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00EC_PCS_PLL_LOCK_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00EC_PCS_PLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00EC_PCS_PLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RATE_CHANGE_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RATE_CHANGE_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RATE_CHANGE_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RATE_CHANGE_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00EC_PCS_RATE_CHANGE_DONE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00EC_PCS_RATE_CHANGE_DONE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00EC_PCS_RATE_CHANGE_DONE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00EC_PCS_RATE_CHANGE_DONE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_DFE_ADAP_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_DFE_ADAP_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_DFE_ADAP_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_DFE_ADAP_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_DFE_ADAP_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_DFE_ADAP_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_DFE_ADAP_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_DFE_ADAP_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_EFOM_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_EFOM_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00EC_OVRD_PCS_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_EFOM_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_EFOM_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00EC_PCS_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00ED (0x03B4)
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#define USBDP_CMN_REG00ED_OVRD_PCS_RX_EFOM_FEEDBACK_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00ED_OVRD_PCS_RX_EFOM_FEEDBACK_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00ED_OVRD_PCS_RX_EFOM_FEEDBACK_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00ED_OVRD_PCS_RX_EFOM_FEEDBACK_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00EE (0x03B8)
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#define USBDP_CMN_REG00EE_PCS_RX_EFOM_FEEDBACK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00EE_PCS_RX_EFOM_FEEDBACK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00EE_PCS_RX_EFOM_FEEDBACK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00EE_PCS_RX_EFOM_FEEDBACK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00EF (0x03BC)
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#define USBDP_CMN_REG00EF_PCS_RX_EFOM_FEEDBACK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00EF_PCS_RX_EFOM_FEEDBACK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00EF_PCS_RX_EFOM_FEEDBACK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00EF_PCS_RX_EFOM_FEEDBACK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00F0 (0x03C0)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_LFPS_DET_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_LFPS_DET_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_LFPS_DET_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_LFPS_DET_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_OFFSET_CAL_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_OFFSET_CAL_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_OFFSET_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_OFFSET_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_OFFSET_CAL_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_OFFSET_CAL_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_OFFSET_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_OFFSET_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_SIGVAL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_SIGVAL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_SIGVAL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00F0_OVRD_PCS_RX_SIGVAL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_SIGVAL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_SIGVAL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_SIGVAL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00F0_PCS_RX_SIGVAL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00F1 (0x03C4)
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#define USBDP_CMN_REG00F1_OVRD_PCS_TX_RCV_STATUS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_TX_RCV_STATUS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_TX_RCV_STATUS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_TX_RCV_STATUS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00F1_PCS_TX_RCV_STATUS_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG00F1_PCS_TX_RCV_STATUS_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG00F1_PCS_TX_RCV_STATUS_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG00F1_PCS_TX_RCV_STATUS_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG00F1_OVRD_PCS_VALID_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_VALID_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00F1_OVRD_PCS_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00F1_PCS_VALID_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00F1_PCS_VALID_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00F1_PCS_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00F1_PCS_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00F1_OVRD_AUX_IN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00F1_OVRD_AUX_IN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00F1_OVRD_AUX_IN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00F1_OVRD_AUX_IN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00F1_AUX_IN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00F1_AUX_IN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00F1_AUX_IN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00F1_AUX_IN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00F2 (0x03C8)
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#define USBDP_CMN_REG00F2_OVRD_AUX_OUT_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00F2_OVRD_AUX_OUT_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00F2_OVRD_AUX_OUT_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00F2_OVRD_AUX_OUT_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00F2_AUX_OUT_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00F2_AUX_OUT_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00F2_AUX_OUT_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00F2_AUX_OUT_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_AFC_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_AFC_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG00F2_LCPLL_AFC_DONE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG00F2_LCPLL_AFC_DONE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG00F2_LCPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG00F2_LCPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG00F2_OVRD_ROPLL_AFC_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00F2_OVRD_ROPLL_AFC_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00F2_OVRD_ROPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00F2_OVRD_ROPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00F2_ROPLL_AFC_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG00F2_ROPLL_AFC_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG00F2_ROPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG00F2_ROPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_LOCK_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_LOCK_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00F2_OVRD_LCPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00F2_LCPLL_LOCK_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00F2_LCPLL_LOCK_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00F2_LCPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00F2_LCPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00F3 (0x03CC)
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#define USBDP_CMN_REG00F3_OVRD_ROPLL_LOCK_DONE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG00F3_OVRD_ROPLL_LOCK_DONE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG00F3_OVRD_ROPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG00F3_OVRD_ROPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG00F3_ROPLL_LOCK_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG00F3_ROPLL_LOCK_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG00F3_ROPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG00F3_ROPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG00F3_RX_SSLMS_LFPS_DET_SRC_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG00F3_RX_SSLMS_LFPS_DET_SRC_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG00F3_RX_SSLMS_LFPS_DET_SRC_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG00F3_RX_SSLMS_LFPS_DET_SRC_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_ENABLE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_ENABLE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_ENABLE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_ENABLE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_DELAY_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_DELAY_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG00F3_TX_DRV_LFPS_MODE_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG00F4 (0x03D0)
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#define USBDP_CMN_REG00F4_TX_DRV_LFPS_MODE_EXTEND_SEL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG00F4_TX_DRV_LFPS_MODE_EXTEND_SEL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG00F4_TX_DRV_LFPS_MODE_EXTEND_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG00F4_TX_DRV_LFPS_MODE_EXTEND_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG00F5 (0x03D4)
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#define USBDP_CMN_REG00F5_TX_DRV_LFPS_MODE_EXTEND_SEL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_CMN_REG00F5_TX_DRV_LFPS_MODE_EXTEND_SEL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_CMN_REG00F5_TX_DRV_LFPS_MODE_EXTEND_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_CMN_REG00F5_TX_DRV_LFPS_MODE_EXTEND_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_CMN_REG00F6 (0x03D8)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_LVL_CTRL_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_LVL_CTRL_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_IDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_IDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00F6_TX_DRV_LFPS_MODE_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00F7 (0x03DC)
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#define USBDP_CMN_REG00F7_CMN_RESERVED13_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00F7_CMN_RESERVED13_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00F7_CMN_RESERVED13_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00F7_CMN_RESERVED13_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00F8 (0x03E0)
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#define USBDP_CMN_REG00F8_CMN_RESERVED14_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00F8_CMN_RESERVED14_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00F8_CMN_RESERVED14_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00F8_CMN_RESERVED14_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00F9 (0x03E4)
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#define USBDP_CMN_REG00F9_CMN_RESERVED15_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00F9_CMN_RESERVED15_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00F9_CMN_RESERVED15_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00F9_CMN_RESERVED15_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00FA (0x03E8)
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#define USBDP_CMN_REG00FA_CMN_RESERVED16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00FA_CMN_RESERVED16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00FA_CMN_RESERVED16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00FA_CMN_RESERVED16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00FB (0x03EC)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_MASK_CDR_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_MASK_CDR_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_MASK_CDR_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG00FB_CDR_WATCHDOG_MASK_CDR_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG00FC (0x03F0)
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#define USBDP_CMN_REG00FC_TIME_CDR_WATCHDOG_THRESHOLD__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00FC_TIME_CDR_WATCHDOG_THRESHOLD__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00FC_TIME_CDR_WATCHDOG_THRESHOLD__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00FC_TIME_CDR_WATCHDOG_THRESHOLD__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00FD (0x03F4)
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#define USBDP_CMN_REG00FD_TIME_CDR_WATCHDOG_THRESHOLD__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00FD_TIME_CDR_WATCHDOG_THRESHOLD__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00FD_TIME_CDR_WATCHDOG_THRESHOLD__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00FD_TIME_CDR_WATCHDOG_THRESHOLD__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00FE (0x03F8)
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#define USBDP_CMN_REG00FE_TIME_CDR_WATCHDOG_THRESHOLD__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00FE_TIME_CDR_WATCHDOG_THRESHOLD__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00FE_TIME_CDR_WATCHDOG_THRESHOLD__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00FE_TIME_CDR_WATCHDOG_THRESHOLD__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG00FF (0x03FC)
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#define USBDP_CMN_REG00FF_TIME_CDR_WATCHDOG_RESET_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG00FF_TIME_CDR_WATCHDOG_RESET_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG00FF_TIME_CDR_WATCHDOG_RESET_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG00FF_TIME_CDR_WATCHDOG_RESET_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0100 (0x0400)
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#define USBDP_CMN_REG0100_TIME_CDR_WATCHDOG_WAIT_RESTART__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0100_TIME_CDR_WATCHDOG_WAIT_RESTART__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0100_TIME_CDR_WATCHDOG_WAIT_RESTART__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0100_TIME_CDR_WATCHDOG_WAIT_RESTART__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0101 (0x0404)
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#define USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0102 (0x0408)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG0102_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG0102_CDR_WATCHDOG_MASK_CDR_AFC_RESTART_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0102_CDR_WATCHDOG_MASK_CDR_AFC_RESTART_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0102_CDR_WATCHDOG_MASK_CDR_AFC_RESTART_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0102_CDR_WATCHDOG_MASK_CDR_AFC_RESTART_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0103 (0x040C)
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#define USBDP_CMN_REG0103_BIST_USER_PAT_DUP_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_CMN_REG0103_BIST_USER_PAT_DUP_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_CMN_REG0103_BIST_USER_PAT_DUP_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_CMN_REG0103_BIST_USER_PAT_DUP_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_CMN_REG0103_LCPLL_LOCK_DONE_DELAY_BYPASS_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0103_LCPLL_LOCK_DONE_DELAY_BYPASS_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0103_LCPLL_LOCK_DONE_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0103_LCPLL_LOCK_DONE_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0103_ROPLL_LOCK_DONE_DELAY_BYPASS_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0103_ROPLL_LOCK_DONE_DELAY_BYPASS_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0103_ROPLL_LOCK_DONE_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0103_ROPLL_LOCK_DONE_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0103_ANA_LCPLL_EN_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0103_ANA_LCPLL_EN_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0103_ANA_LCPLL_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0103_ANA_LCPLL_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0104 (0x0410)
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#define USBDP_CMN_REG0104_ANA_ROPLL_EN_DELAY_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0104_ANA_ROPLL_EN_DELAY_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0104_ANA_ROPLL_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0104_ANA_ROPLL_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0104_PLL_LOCK_DONE_OUT_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0104_PLL_LOCK_DONE_OUT_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0104_PLL_LOCK_DONE_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0104_PLL_LOCK_DONE_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0104_DP_PLL_LOCK_DONE_OUT_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0104_DP_PLL_LOCK_DONE_OUT_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0104_DP_PLL_LOCK_DONE_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0104_DP_PLL_LOCK_DONE_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0104_RX_CDR_LOCK_OUT_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0104_RX_CDR_LOCK_OUT_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0104_RX_CDR_LOCK_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0104_RX_CDR_LOCK_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0104_LCPLL_CD_VREG_EN_MASK_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0104_LCPLL_CD_VREG_EN_MASK_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0104_LCPLL_CD_VREG_EN_MASK_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0104_LCPLL_CD_VREG_EN_MASK_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0104_ROPLL_CD_VREG_EN_MASK_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0104_ROPLL_CD_VREG_EN_MASK_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0104_ROPLL_CD_VREG_EN_MASK_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0104_ROPLL_CD_VREG_EN_MASK_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0104_RX_RTERM_VCM_EN_INV_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0104_RX_RTERM_VCM_EN_INV_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0104_RX_RTERM_VCM_EN_INV_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0104_RX_RTERM_VCM_EN_INV_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0105 (0x0414)
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#define USBDP_CMN_REG0105_RX_RTERM_CM_PULLDN_INV_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0105_RX_RTERM_CM_PULLDN_INV_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0105_RX_RTERM_CM_PULLDN_INV_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0105_RX_RTERM_CM_PULLDN_INV_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0105_BIST_USB_GEN2_CP9_EN_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0105_BIST_USB_GEN2_CP9_EN_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0105_BIST_USB_GEN2_CP9_EN_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0105_BIST_USB_GEN2_CP9_EN_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0105_DP_LINK_DIV10_CLK_OUT_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0105_DP_LINK_DIV10_CLK_OUT_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0105_DP_LINK_DIV10_CLK_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0105_DP_LINK_DIV10_CLK_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0106 (0x0418)
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#define USBDP_CMN_REG0106_BIAS_ICAL_CODE_OFFSET_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0106_BIAS_ICAL_CODE_OFFSET_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0106_BIAS_ICAL_CODE_OFFSET_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0106_BIAS_ICAL_CODE_OFFSET_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0106_TXCLK_GMUX_SEL_MODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0106_TXCLK_GMUX_SEL_MODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0106_TXCLK_GMUX_SEL_MODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0106_TXCLK_GMUX_SEL_MODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0106_RXCLK_GMUX_SEL_MODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0106_RXCLK_GMUX_SEL_MODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0106_RXCLK_GMUX_SEL_MODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0106_RXCLK_GMUX_SEL_MODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0107 (0x041C)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_SEL_MODE_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_SEL_MODE_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_SEL_MODE_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_SEL_MODE_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0107_TXCLK_GMUX_RST_MODE_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0107_TXCLK_GMUX_RST_MODE_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0107_TXCLK_GMUX_RST_MODE_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0107_TXCLK_GMUX_RST_MODE_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0107_RXCLK_GMUX_RST_MODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0107_RXCLK_GMUX_RST_MODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0107_RXCLK_GMUX_RST_MODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0107_RXCLK_GMUX_RST_MODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_RST_MODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_RST_MODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_RST_MODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0107_DP_TXCLK_GMUX_RST_MODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0108 (0x0420)
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#define USBDP_CMN_REG0108_LCPLL_AFC_TIMEOUT_OPT_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_CMN_REG0108_LCPLL_AFC_TIMEOUT_OPT_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_CMN_REG0108_LCPLL_AFC_TIMEOUT_OPT_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_CMN_REG0108_LCPLL_AFC_TIMEOUT_OPT_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_CMN_REG0108_ROPLL_AFC_TIMEOUT_OPT_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0108_ROPLL_AFC_TIMEOUT_OPT_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0108_ROPLL_AFC_TIMEOUT_OPT_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0108_ROPLL_AFC_TIMEOUT_OPT_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0109 (0x0424)
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#define USBDP_CMN_REG0109_LN0_ANA_TX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0109_LN0_ANA_TX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0109_LN0_ANA_TX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0109_LN0_ANA_TX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010A (0x0428)
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#define USBDP_CMN_REG010A_LN1_ANA_TX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010A_LN1_ANA_TX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010A_LN1_ANA_TX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010A_LN1_ANA_TX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010B (0x042C)
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#define USBDP_CMN_REG010B_LN2_ANA_TX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010B_LN2_ANA_TX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010B_LN2_ANA_TX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010B_LN2_ANA_TX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010C (0x0430)
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#define USBDP_CMN_REG010C_LN3_ANA_TX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010C_LN3_ANA_TX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010C_LN3_ANA_TX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010C_LN3_ANA_TX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010D (0x0434)
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#define USBDP_CMN_REG010D_LN0_ANA_RX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010D_LN0_ANA_RX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010D_LN0_ANA_RX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010D_LN0_ANA_RX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010E (0x0438)
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#define USBDP_CMN_REG010E_LN0_ANA_RX_RESERVED_23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010E_LN0_ANA_RX_RESERVED_23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010E_LN0_ANA_RX_RESERVED_23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010E_LN0_ANA_RX_RESERVED_23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG010F (0x043C)
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#define USBDP_CMN_REG010F_LN2_ANA_RX_RESERVED_15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG010F_LN2_ANA_RX_RESERVED_15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG010F_LN2_ANA_RX_RESERVED_15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG010F_LN2_ANA_RX_RESERVED_15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0110 (0x0440)
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#define USBDP_CMN_REG0110_LN2_ANA_RX_RESERVED_23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0110_LN2_ANA_RX_RESERVED_23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0110_LN2_ANA_RX_RESERVED_23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0110_LN2_ANA_RX_RESERVED_23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0111 (0x0444)
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#define USBDP_CMN_REG0111_SFR_VERSION_YEAR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0111_SFR_VERSION_YEAR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0111_SFR_VERSION_YEAR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0111_SFR_VERSION_YEAR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0112 (0x0448)
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#define USBDP_CMN_REG0112_SFR_VERSION_MONTH_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0112_SFR_VERSION_MONTH_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0112_SFR_VERSION_MONTH_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0112_SFR_VERSION_MONTH_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0113 (0x044C)
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#define USBDP_CMN_REG0113_SFR_VERSION_DAY_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0113_SFR_VERSION_DAY_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0113_SFR_VERSION_DAY_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0113_SFR_VERSION_DAY_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0114 (0x0450)
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#define USBDP_CMN_REG0114_POWER_OFF_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG0114_POWER_OFF_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG0114_POWER_OFF_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG0114_POWER_OFF_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SP_RESERVED_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SP_RESERVED_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SSP_RESERVED_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SSP_RESERVED_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0114_PCS_RX_CLK_INV_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0114_LANE_SSM_LEGACY_MODE_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0114_LANE_SSM_LEGACY_MODE_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0114_LANE_SSM_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0114_LANE_SSM_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0114_EFOM_LEGACY_MODE_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0114_EFOM_LEGACY_MODE_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0114_EFOM_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0114_EFOM_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0114_LCPLL_RATE_CHANGE_RESTART_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0114_LCPLL_RATE_CHANGE_RESTART_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0114_LCPLL_RATE_CHANGE_RESTART_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0114_LCPLL_RATE_CHANGE_RESTART_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0114_CDR_RATE_CHANGE_RESTART_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0114_CDR_RATE_CHANGE_RESTART_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0114_CDR_RATE_CHANGE_RESTART_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0114_CDR_RATE_CHANGE_RESTART_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0114_OFS_CAL_RATE_CHANGE_RESTART_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0114_OFS_CAL_RATE_CHANGE_RESTART_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0114_OFS_CAL_RATE_CHANGE_RESTART_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0114_OFS_CAL_RATE_CHANGE_RESTART_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0115 (0x0454)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0115_RX_LFPS_DET_DIGITAL_EN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0116 (0x0458)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0116_RX_LFPS_DET_DIGITAL_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0117 (0x045C)
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#define USBDP_CMN_REG0117_RX_LFPS_DET_DIGITAL_TH0_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0117_RX_LFPS_DET_DIGITAL_TH0_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0117_RX_LFPS_DET_DIGITAL_TH0_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0117_RX_LFPS_DET_DIGITAL_TH0_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0118 (0x0460)
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#define USBDP_CMN_REG0118_RX_LFPS_DET_DIGITAL_TH1_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0118_RX_LFPS_DET_DIGITAL_TH1_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0118_RX_LFPS_DET_DIGITAL_TH1_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0118_RX_LFPS_DET_DIGITAL_TH1_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0119 (0x0464)
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#define USBDP_CMN_REG0119_RX_LFPS_DET_DIGITAL_TH2_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0119_RX_LFPS_DET_DIGITAL_TH2_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0119_RX_LFPS_DET_DIGITAL_TH2_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0119_RX_LFPS_DET_DIGITAL_TH2_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011A (0x0468)
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#define USBDP_CMN_REG011A_RX_LFPS_DET_DIGITAL_TH3_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG011A_RX_LFPS_DET_DIGITAL_TH3_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG011A_RX_LFPS_DET_DIGITAL_TH3_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG011A_RX_LFPS_DET_DIGITAL_TH3_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011B (0x046C)
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#define USBDP_CMN_REG011B_RX_LFPS_DET_DIGITAL_TH0_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG011B_RX_LFPS_DET_DIGITAL_TH0_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG011B_RX_LFPS_DET_DIGITAL_TH0_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG011B_RX_LFPS_DET_DIGITAL_TH0_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011C (0x0470)
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#define USBDP_CMN_REG011C_RX_LFPS_DET_DIGITAL_TH1_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG011C_RX_LFPS_DET_DIGITAL_TH1_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG011C_RX_LFPS_DET_DIGITAL_TH1_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG011C_RX_LFPS_DET_DIGITAL_TH1_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011D (0x0474)
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#define USBDP_CMN_REG011D_RX_LFPS_DET_DIGITAL_TH2_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG011D_RX_LFPS_DET_DIGITAL_TH2_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG011D_RX_LFPS_DET_DIGITAL_TH2_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG011D_RX_LFPS_DET_DIGITAL_TH2_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011E (0x0478)
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#define USBDP_CMN_REG011E_RX_LFPS_DET_DIGITAL_TH3_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG011E_RX_LFPS_DET_DIGITAL_TH3_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG011E_RX_LFPS_DET_DIGITAL_TH3_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG011E_RX_LFPS_DET_DIGITAL_TH3_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG011F (0x047C)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG011F_RX_LFPS_DET_FILT_BYPASS_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0120 (0x0480)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0120_RX_LFPS_DET_FILT_EN_LONG_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0121 (0x0484)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0121_RX_LFPS_DET_FILT_EN_SHORT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0122 (0x0488)
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#define USBDP_CMN_REG0122_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0122_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0122_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0122_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0123 (0x048C)
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#define USBDP_CMN_REG0123_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0123_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0123_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0123_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0124 (0x0490)
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#define USBDP_CMN_REG0124_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0124_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0124_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0124_RX_LFPS_DET_FILT_TH0_SHORT_RISE_CDR_LO_BW_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0125 (0x0494)
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#define USBDP_CMN_REG0125_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0125_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0125_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0125_RX_LFPS_DET_FILT_TH0_SHORT_FALL_CDR_LO_BW_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0126 (0x0498)
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#define USBDP_CMN_REG0126_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0126_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0126_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0126_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0127 (0x049C)
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#define USBDP_CMN_REG0127_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0127_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0127_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0127_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0128 (0x04A0)
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#define USBDP_CMN_REG0128_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0128_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0128_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0128_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0129 (0x04A4)
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#define USBDP_CMN_REG0129_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0129_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0129_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0129_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012A (0x04A8)
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#define USBDP_CMN_REG012A_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012A_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012A_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012A_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012B (0x04AC)
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#define USBDP_CMN_REG012B_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012B_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012B_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012B_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012C (0x04B0)
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#define USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012D (0x04B4)
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#define USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012E (0x04B8)
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#define USBDP_CMN_REG012E_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012E_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012E_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012E_RX_LFPS_DET_FILT_TH0_SHORT_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG012F (0x04BC)
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#define USBDP_CMN_REG012F_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG012F_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG012F_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG012F_RX_LFPS_DET_FILT_TH0_SHORT_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0130 (0x04C0)
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#define USBDP_CMN_REG0130_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0130_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0130_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0130_RX_LFPS_DET_FILT_TH1_SHORT_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0131 (0x04C4)
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#define USBDP_CMN_REG0131_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0131_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0131_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0131_RX_LFPS_DET_FILT_TH1_SHORT_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0132 (0x04C8)
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#define USBDP_CMN_REG0132_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0132_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0132_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0132_RX_LFPS_DET_FILT_TH2_SHORT_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0133 (0x04CC)
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#define USBDP_CMN_REG0133_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0133_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0133_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0133_RX_LFPS_DET_FILT_TH2_SHORT_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0134 (0x04D0)
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#define USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0135 (0x04D4)
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#define USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG0136 (0x04D8)
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#define USBDP_CMN_REG0136_RX_LFPS_DET_FILT_TH0_LONG_RISE_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0136_RX_LFPS_DET_FILT_TH0_LONG_RISE_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0136_RX_LFPS_DET_FILT_TH0_LONG_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0136_RX_LFPS_DET_FILT_TH0_LONG_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0137 (0x04DC)
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#define USBDP_CMN_REG0137_RX_LFPS_DET_FILT_TH0_LONG_FALL_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0137_RX_LFPS_DET_FILT_TH0_LONG_FALL_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0137_RX_LFPS_DET_FILT_TH0_LONG_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0137_RX_LFPS_DET_FILT_TH0_LONG_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0138 (0x04E0)
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#define USBDP_CMN_REG0138_RX_LFPS_DET_FILT_TH1_LONG_RISE_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0138_RX_LFPS_DET_FILT_TH1_LONG_RISE_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0138_RX_LFPS_DET_FILT_TH1_LONG_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0138_RX_LFPS_DET_FILT_TH1_LONG_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0139 (0x04E4)
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#define USBDP_CMN_REG0139_RX_LFPS_DET_FILT_TH1_LONG_FALL_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0139_RX_LFPS_DET_FILT_TH1_LONG_FALL_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0139_RX_LFPS_DET_FILT_TH1_LONG_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0139_RX_LFPS_DET_FILT_TH1_LONG_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013A (0x04E8)
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#define USBDP_CMN_REG013A_RX_LFPS_DET_FILT_TH2_LONG_RISE_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013A_RX_LFPS_DET_FILT_TH2_LONG_RISE_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013A_RX_LFPS_DET_FILT_TH2_LONG_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013A_RX_LFPS_DET_FILT_TH2_LONG_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013B (0x04EC)
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#define USBDP_CMN_REG013B_RX_LFPS_DET_FILT_TH2_LONG_FALL_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013B_RX_LFPS_DET_FILT_TH2_LONG_FALL_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013B_RX_LFPS_DET_FILT_TH2_LONG_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013B_RX_LFPS_DET_FILT_TH2_LONG_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013C (0x04F0)
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#define USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013D (0x04F4)
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#define USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013E (0x04F8)
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#define USBDP_CMN_REG013E_RX_LFPS_DET_FILT_TH0_LONG_RISE_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013E_RX_LFPS_DET_FILT_TH0_LONG_RISE_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013E_RX_LFPS_DET_FILT_TH0_LONG_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013E_RX_LFPS_DET_FILT_TH0_LONG_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG013F (0x04FC)
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#define USBDP_CMN_REG013F_RX_LFPS_DET_FILT_TH0_LONG_FALL_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG013F_RX_LFPS_DET_FILT_TH0_LONG_FALL_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG013F_RX_LFPS_DET_FILT_TH0_LONG_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG013F_RX_LFPS_DET_FILT_TH0_LONG_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0140 (0x0500)
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#define USBDP_CMN_REG0140_RX_LFPS_DET_FILT_TH1_LONG_RISE_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0140_RX_LFPS_DET_FILT_TH1_LONG_RISE_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0140_RX_LFPS_DET_FILT_TH1_LONG_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0140_RX_LFPS_DET_FILT_TH1_LONG_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0141 (0x0504)
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#define USBDP_CMN_REG0141_RX_LFPS_DET_FILT_TH1_LONG_FALL_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0141_RX_LFPS_DET_FILT_TH1_LONG_FALL_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0141_RX_LFPS_DET_FILT_TH1_LONG_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0141_RX_LFPS_DET_FILT_TH1_LONG_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0142 (0x0508)
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#define USBDP_CMN_REG0142_RX_LFPS_DET_FILT_TH2_LONG_RISE_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0142_RX_LFPS_DET_FILT_TH2_LONG_RISE_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0142_RX_LFPS_DET_FILT_TH2_LONG_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0142_RX_LFPS_DET_FILT_TH2_LONG_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0143 (0x050C)
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#define USBDP_CMN_REG0143_RX_LFPS_DET_FILT_TH2_LONG_FALL_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0143_RX_LFPS_DET_FILT_TH2_LONG_FALL_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0143_RX_LFPS_DET_FILT_TH2_LONG_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0143_RX_LFPS_DET_FILT_TH2_LONG_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0144 (0x0510)
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#define USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0145 (0x0514)
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#define USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0146 (0x0518)
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#define USBDP_CMN_REG0146_OVRD_TX_CLK_GMUX_SEL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0146_OVRD_TX_CLK_GMUX_SEL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0146_OVRD_TX_CLK_GMUX_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0146_OVRD_TX_CLK_GMUX_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0146_TX_CLK_GMUX_SEL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0146_TX_CLK_GMUX_SEL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0146_TX_CLK_GMUX_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0146_TX_CLK_GMUX_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0147 (0x051C)
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#define USBDP_CMN_REG0147_OVRD_TX_CLK_GMUX_SEL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0147_OVRD_TX_CLK_GMUX_SEL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0147_OVRD_TX_CLK_GMUX_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0147_OVRD_TX_CLK_GMUX_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0147_TX_CLK_GMUX_SEL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0147_TX_CLK_GMUX_SEL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0147_TX_CLK_GMUX_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0147_TX_CLK_GMUX_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0148 (0x0520)
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#define USBDP_CMN_REG0148_OVRD_RX_CLK_GMUX_SEL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0148_OVRD_RX_CLK_GMUX_SEL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0148_OVRD_RX_CLK_GMUX_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0148_OVRD_RX_CLK_GMUX_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0148_RX_CLK_GMUX_SEL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0148_RX_CLK_GMUX_SEL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0148_RX_CLK_GMUX_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0148_RX_CLK_GMUX_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0149 (0x0524)
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#define USBDP_CMN_REG0149_OVRD_RX_CLK_GMUX_SEL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0149_OVRD_RX_CLK_GMUX_SEL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0149_OVRD_RX_CLK_GMUX_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0149_OVRD_RX_CLK_GMUX_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0149_RX_CLK_GMUX_SEL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0149_RX_CLK_GMUX_SEL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0149_RX_CLK_GMUX_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0149_RX_CLK_GMUX_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014A (0x0528)
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#define USBDP_CMN_REG014A_OVRD_TX_CLK_GMUX_RSTN_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG014A_OVRD_TX_CLK_GMUX_RSTN_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG014A_OVRD_TX_CLK_GMUX_RSTN_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG014A_OVRD_TX_CLK_GMUX_RSTN_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG014A_TX_CLK_GMUX_RSTN_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG014A_TX_CLK_GMUX_RSTN_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG014A_TX_CLK_GMUX_RSTN_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG014A_TX_CLK_GMUX_RSTN_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014B (0x052C)
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#define USBDP_CMN_REG014B_OVRD_TX_CLK_GMUX_RSTN_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG014B_OVRD_TX_CLK_GMUX_RSTN_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG014B_OVRD_TX_CLK_GMUX_RSTN_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG014B_OVRD_TX_CLK_GMUX_RSTN_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG014B_TX_CLK_GMUX_RSTN_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG014B_TX_CLK_GMUX_RSTN_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG014B_TX_CLK_GMUX_RSTN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG014B_TX_CLK_GMUX_RSTN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014C (0x0530)
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#define USBDP_CMN_REG014C_OVRD_RX_CLK_GMUX_RSTN_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG014C_OVRD_RX_CLK_GMUX_RSTN_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG014C_OVRD_RX_CLK_GMUX_RSTN_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG014C_OVRD_RX_CLK_GMUX_RSTN_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG014C_RX_CLK_GMUX_RSTN_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG014C_RX_CLK_GMUX_RSTN_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG014C_RX_CLK_GMUX_RSTN_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG014C_RX_CLK_GMUX_RSTN_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014D (0x0534)
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#define USBDP_CMN_REG014D_OVRD_RX_CLK_GMUX_RSTN_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG014D_OVRD_RX_CLK_GMUX_RSTN_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG014D_OVRD_RX_CLK_GMUX_RSTN_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG014D_OVRD_RX_CLK_GMUX_RSTN_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG014D_RX_CLK_GMUX_RSTN_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG014D_RX_CLK_GMUX_RSTN_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG014D_RX_CLK_GMUX_RSTN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG014D_RX_CLK_GMUX_RSTN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014E (0x0538)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG014E_DP_TX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG014E_OVRD_DP_TX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG014E_CMN_RESERVED17_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG014E_CMN_RESERVED17_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG014E_CMN_RESERVED17_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG014E_CMN_RESERVED17_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG014F (0x053C)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG014F_LCPLL_CD_HSCLK_WEST_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0150 (0x0540)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR2_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR2_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0150_LCPLL_CD_HSCLK_WEST_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0150_CMN_RESERVED18_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0150_CMN_RESERVED18_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0150_CMN_RESERVED18_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0150_CMN_RESERVED18_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0151 (0x0544)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0151_LCPLL_CD_HSCLK_EAST_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0152 (0x0548)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR2_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR2_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0152_LCPLL_CD_HSCLK_EAST_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0152_CMN_RESERVED19_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0152_CMN_RESERVED19_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0152_CMN_RESERVED19_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0152_CMN_RESERVED19_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0153 (0x054C)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0153_ROPLL_CD_HSCLK_WEST_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0154 (0x0550)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR2_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR2_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0154_ROPLL_CD_HSCLK_WEST_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0154_CMN_RESERVED20_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0154_CMN_RESERVED20_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0154_CMN_RESERVED20_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0154_CMN_RESERVED20_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0155 (0x0554)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0155_ROPLL_CD_HSCLK_EAST_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0156 (0x0558)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR2_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR2_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0156_ROPLL_CD_HSCLK_EAST_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0156_CMN_RESERVED21_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0156_CMN_RESERVED21_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0156_CMN_RESERVED21_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0156_CMN_RESERVED21_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0157 (0x055C)
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#define USBDP_CMN_REG0157_CMN_RESERVED22_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0157_CMN_RESERVED22_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0157_CMN_RESERVED22_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0157_CMN_RESERVED22_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0157_LN0_TX_SER_TXCLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0158 (0x0560)
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#define USBDP_CMN_REG0158_CMN_RESERVED23_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0158_CMN_RESERVED23_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0158_CMN_RESERVED23_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0158_CMN_RESERVED23_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0158_LN1_TX_SER_TXCLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0159 (0x0564)
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#define USBDP_CMN_REG0159_CMN_RESERVED24_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0159_CMN_RESERVED24_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0159_CMN_RESERVED24_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0159_CMN_RESERVED24_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0159_LN2_TX_SER_TXCLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG015A (0x0568)
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#define USBDP_CMN_REG015A_CMN_RESERVED25_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG015A_CMN_RESERVED25_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG015A_CMN_RESERVED25_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG015A_CMN_RESERVED25_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG015A_LN3_TX_SER_TXCLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG015B (0x056C)
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#define USBDP_CMN_REG015B_DATA_MON_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG015B_DATA_MON_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG015B_DATA_MON_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG015B_DATA_MON_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG015B_DATA_MON_HOLD_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG015B_DATA_MON_HOLD_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG015B_DATA_MON_HOLD_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG015B_DATA_MON_HOLD_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG015B_DATA_MON_RXDATA_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG015B_DATA_MON_RXDATA_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG015B_DATA_MON_RXDATA_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG015B_DATA_MON_RXDATA_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_MODE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_MODE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_MODE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_MODE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_TIMER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_TIMER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_TIMER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG015B_PCS_PORT_MON_TIMER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG015C (0x0570)
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#define USBDP_CMN_REG015C_PCS_PORT_MON_TIMER_CNT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG015C_PCS_PORT_MON_TIMER_CNT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG015C_PCS_PORT_MON_TIMER_CNT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG015C_PCS_PORT_MON_TIMER_CNT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG015D (0x0574)
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#define USBDP_CMN_REG015D_PCS_PORT_MON_TIMER_CNT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG015D_PCS_PORT_MON_TIMER_CNT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG015D_PCS_PORT_MON_TIMER_CNT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG015D_PCS_PORT_MON_TIMER_CNT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG015E (0x0578)
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#define USBDP_CMN_REG015E_PCS_PORT_MON_TRIGGER_SRC_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG015E_PCS_PORT_MON_TRIGGER_SRC_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG015E_PCS_PORT_MON_TRIGGER_SRC_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG015E_PCS_PORT_MON_TRIGGER_SRC_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG015F (0x057C)
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#define USBDP_CMN_REG015F_PCS_PORT_MON_TRIGGER_CNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG015F_PCS_PORT_MON_TRIGGER_CNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG015F_PCS_PORT_MON_TRIGGER_CNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG015F_PCS_PORT_MON_TRIGGER_CNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0160 (0x0580)
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#define USBDP_CMN_REG0160_PCS_PORT_MON_PORT_MASK__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0160_PCS_PORT_MON_PORT_MASK__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0160_PCS_PORT_MON_PORT_MASK__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0160_PCS_PORT_MON_PORT_MASK__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0161 (0x0584)
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#define USBDP_CMN_REG0161_PCS_PORT_MON_PORT_MASK__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0161_PCS_PORT_MON_PORT_MASK__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0161_PCS_PORT_MON_PORT_MASK__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0161_PCS_PORT_MON_PORT_MASK__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0162 (0x0588)
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#define USBDP_CMN_REG0162_PCS_PORT_MON_PORT_MASK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0162_PCS_PORT_MON_PORT_MASK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0162_PCS_PORT_MON_PORT_MASK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0162_PCS_PORT_MON_PORT_MASK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0163 (0x058C)
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#define USBDP_CMN_REG0163_PCS_PORT_MON_PORT_MASK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0163_PCS_PORT_MON_PORT_MASK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0163_PCS_PORT_MON_PORT_MASK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0163_PCS_PORT_MON_PORT_MASK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0164 (0x0590)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_READ_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_READ_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_READ_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0164_ANA_LCPLL_FLD_VCO_CNT_MON_READ_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_READ_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_READ_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_READ_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0164_ANA_ROPLL_FLD_VCO_CNT_MON_READ_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0164_RX_CDR_VCO_CNT_MON_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0164_RX_CDR_VCO_CNT_MON_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0164_RX_CDR_VCO_CNT_MON_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0164_RX_CDR_VCO_CNT_MON_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0164_RX_CDR_FBB_CODE_CTRL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0164_RX_CDR_FBB_CODE_CTRL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0164_RX_CDR_FBB_CODE_CTRL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0164_RX_CDR_FBB_CODE_CTRL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0165 (0x0594)
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#define USBDP_CMN_REG0165_RX_CDR_FBB_CODE_CTRL_DELAY_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0165_RX_CDR_FBB_CODE_CTRL_DELAY_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0165_RX_CDR_FBB_CODE_CTRL_DELAY_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0165_RX_CDR_FBB_CODE_CTRL_DELAY_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0165_RX_SSLMS_WAIT_OFS_CAL_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0165_RX_SSLMS_WAIT_OFS_CAL_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0165_RX_SSLMS_WAIT_OFS_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0165_RX_SSLMS_WAIT_OFS_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_TYPE0_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_TYPE0_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_TYPE0_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0165_TX_LFPS_TP_GEN_TYPE0_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0166 (0x0598)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE1_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE1_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE1_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE1_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE4_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE4_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE4_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0166_TX_LFPS_TP_GEN_TYPE4_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0167 (0x059C)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE5_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE5_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE5_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE5_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE6_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE6_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE6_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE6_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE7_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE7_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE7_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE7_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE8_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE8_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE8_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0167_TX_LFPS_TP_GEN_TYPE8_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0168 (0x05A0)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE9_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE9_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE9_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE9_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE10_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE10_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE10_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE10_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE11_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE11_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE11_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0168_TX_LFPS_TP_GEN_TYPE11_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0169 (0x05A4)
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#define USBDP_CMN_REG0169_TX_LFPS_TP_GEN_LAST_INDEX_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0169_TX_LFPS_TP_GEN_LAST_INDEX_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0169_TX_LFPS_TP_GEN_LAST_INDEX_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0169_TX_LFPS_TP_GEN_LAST_INDEX_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG016A (0x05A8)
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#define USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG016B (0x05AC)
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#define USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG016C (0x05B0)
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#define USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG016D (0x05B4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_MAX_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_MAX_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_MAX_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_MAX_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_INIT_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_INIT_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_INIT_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG016D_BIAS_ICAL_AUTO_CODE_INIT_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG016E (0x05B8)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_RESTART_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_RESTART_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_RESTART_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_RESTART_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_COMP_EN_SRC_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_COMP_EN_SRC_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_COMP_EN_SRC_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_COMP_EN_SRC_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_CAL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_CAL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_CAL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG016E_BIAS_ICAL_AUTO_CAL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG016F (0x05BC)
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#define USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0170 (0x05C0)
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#define USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0171 (0x05C4)
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#define USBDP_CMN_REG0171_RX_VALID_RSTN_LEGACY_MODE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0171_RX_VALID_RSTN_LEGACY_MODE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0171_RX_VALID_RSTN_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0171_RX_VALID_RSTN_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0171_RX_OC_LEGACY_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0171_RX_OC_LEGACY_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0171_RX_OC_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0171_RX_OC_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0172 (0x05C8)
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#define USBDP_CMN_REG0172_PCS_TSEQ_MASK_EXTEND__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0172_PCS_TSEQ_MASK_EXTEND__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0172_PCS_TSEQ_MASK_EXTEND__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0172_PCS_TSEQ_MASK_EXTEND__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0173 (0x05CC)
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#define USBDP_CMN_REG0173_PCS_TSEQ_MASK_EXTEND__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0173_PCS_TSEQ_MASK_EXTEND__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0173_PCS_TSEQ_MASK_EXTEND__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0173_PCS_TSEQ_MASK_EXTEND__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0174 (0x05D0)
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#define USBDP_CMN_REG0174_PCS_TSEQ_MASK_EXTEND__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0174_PCS_TSEQ_MASK_EXTEND__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0174_PCS_TSEQ_MASK_EXTEND__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0174_PCS_TSEQ_MASK_EXTEND__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0175 (0x05D4)
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#define USBDP_CMN_REG0175_PCS_TSEQ_MASK_EXTEND__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0175_PCS_TSEQ_MASK_EXTEND__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0175_PCS_TSEQ_MASK_EXTEND__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0175_PCS_TSEQ_MASK_EXTEND__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0176 (0x05D8)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_MODE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_MODE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_MODE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_MODE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_DATA_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_DATA_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_DATA_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_DATA_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_SIGVAL_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_SIGVAL_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_SIGVAL_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_SIGVAL_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_VALID_RSTN_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_VALID_RSTN_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_VALID_RSTN_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0176_PCS_TSEQ_MASK_VALID_RSTN_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0176_OVRD_PCS_HS_CLK_LANE_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0176_OVRD_PCS_HS_CLK_LANE_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0176_OVRD_PCS_HS_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0176_OVRD_PCS_HS_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0176_PCS_HS_CLK_LANE_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0176_PCS_HS_CLK_LANE_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0176_PCS_HS_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0176_PCS_HS_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0177 (0x05DC)
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#define USBDP_CMN_REG0177_OVRD_PCS_RX_CLK_LANE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0177_OVRD_PCS_RX_CLK_LANE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0177_OVRD_PCS_RX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0177_OVRD_PCS_RX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0177_PCS_RX_CLK_LANE_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0177_PCS_RX_CLK_LANE_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0177_PCS_RX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0177_PCS_RX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0177_OVRD_DP_TX_CLK_LANE_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0177_OVRD_DP_TX_CLK_LANE_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0177_OVRD_DP_TX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0177_OVRD_DP_TX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0177_DP_TX_CLK_LANE_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG0177_DP_TX_CLK_LANE_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG0177_DP_TX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG0177_DP_TX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0178 (0x05E0)
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#define USBDP_CMN_REG0178_RX_CDR_FBB_CODE_CTRL_STEP_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_CMN_REG0178_RX_CDR_FBB_CODE_CTRL_STEP_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_CMN_REG0178_RX_CDR_FBB_CODE_CTRL_STEP_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_CMN_REG0178_RX_CDR_FBB_CODE_CTRL_STEP_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_CMN_REG0178_CMN_SSM_BGR_LPF_TIMER_LEGACY_MODE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_BGR_LPF_TIMER_LEGACY_MODE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_BGR_LPF_TIMER_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_BGR_LPF_TIMER_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_VREG_BYPASS_OFF_LEGACY_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_VREG_BYPASS_OFF_LEGACY_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_VREG_BYPASS_OFF_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0178_CMN_SSM_VREG_BYPASS_OFF_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0179 (0x05E4)
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#define USBDP_CMN_REG0179_RX_VALID_RSTN_DELAY_PM_STATE_LEGACY_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0179_RX_VALID_RSTN_DELAY_PM_STATE_LEGACY_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0179_RX_VALID_RSTN_DELAY_PM_STATE_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0179_RX_VALID_RSTN_DELAY_PM_STATE_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG017A (0x05E8)
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#define USBDP_CMN_REG017A_USB_DBG_BLK_START_ERROR_DET_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG017A_USB_DBG_BLK_START_ERROR_DET_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG017A_USB_DBG_BLK_START_ERROR_DET_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG017A_USB_DBG_BLK_START_ERROR_DET_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG017B (0x05EC)
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#define USBDP_CMN_REG017B_USB_DBG_BLK_ERROR_COUNT_CTRL__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG017B_USB_DBG_BLK_ERROR_COUNT_CTRL__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG017B_USB_DBG_BLK_ERROR_COUNT_CTRL__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG017B_USB_DBG_BLK_ERROR_COUNT_CTRL__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG017C (0x05F0)
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#define USBDP_CMN_REG017C_USB_DBG_BLK_ERROR_COUNT_CTRL__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG017C_USB_DBG_BLK_ERROR_COUNT_CTRL__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG017C_USB_DBG_BLK_ERROR_COUNT_CTRL__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG017C_USB_DBG_BLK_ERROR_COUNT_CTRL__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG017D (0x05F4)
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#define USBDP_CMN_REG017D_USB_DBG_BLK_ERROR_COUNT_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG017D_USB_DBG_BLK_ERROR_COUNT_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG017D_USB_DBG_BLK_ERROR_COUNT_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG017D_USB_DBG_BLK_ERROR_COUNT_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG017E (0x05F8)
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#define USBDP_CMN_REG017E_CMN_RESERVED26_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG017E_CMN_RESERVED26_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG017E_CMN_RESERVED26_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG017E_CMN_RESERVED26_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERROR_COUNT_RSTN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERROR_COUNT_RSTN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERROR_COUNT_RSTN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERROR_COUNT_RSTN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_EMPTY_ERROR_BUFFER_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_EMPTY_ERROR_BUFFER_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_EMPTY_ERROR_BUFFER_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_EMPTY_ERROR_BUFFER_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG017E_OVRD_USB_DBG_BLK_ERR_BUFFER_RD_PTR_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG017E_OVRD_USB_DBG_BLK_ERR_BUFFER_RD_PTR_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG017E_OVRD_USB_DBG_BLK_ERR_BUFFER_RD_PTR_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG017E_OVRD_USB_DBG_BLK_ERR_BUFFER_RD_PTR_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERR_BUFFER_RD_PTR_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERR_BUFFER_RD_PTR_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERR_BUFFER_RD_PTR_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_ERR_BUFFER_RD_PTR_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_LFPS_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_LFPS_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_LFPS_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG017E_USB_DBG_BLK_LFPS_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG017F (0x05FC)
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#define USBDP_CMN_REG017F_CMN_RESERVED27_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG017F_CMN_RESERVED27_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG017F_CMN_RESERVED27_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG017F_CMN_RESERVED27_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG017F_CMN_SSM_LCPLL_CD_CLK_EN_LEGACY_MODE_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG017F_CMN_SSM_LCPLL_CD_CLK_EN_LEGACY_MODE_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG017F_CMN_SSM_LCPLL_CD_CLK_EN_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG017F_CMN_SSM_LCPLL_CD_CLK_EN_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG017F_RX_VALID_RSTN_AT_CDR_LOCK_DOWN_LEGACY_MODE_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG017F_RX_VALID_RSTN_AT_CDR_LOCK_DOWN_LEGACY_MODE_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG017F_RX_VALID_RSTN_AT_CDR_LOCK_DOWN_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG017F_RX_VALID_RSTN_AT_CDR_LOCK_DOWN_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG017F_CMN_RSTN_MASKING_LEGACY_MODE_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG017F_CMN_RSTN_MASKING_LEGACY_MODE_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG017F_CMN_RSTN_MASKING_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG017F_CMN_RSTN_MASKING_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG017F_BIAS_ICAL_CODE_OFFSET_DIRECTION_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG017F_BIAS_ICAL_CODE_OFFSET_DIRECTION_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG017F_BIAS_ICAL_CODE_OFFSET_DIRECTION_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG017F_BIAS_ICAL_CODE_OFFSET_DIRECTION_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG017F_USB_TX_DATAPATH_RSTN_LEGACY_MODE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG017F_USB_TX_DATAPATH_RSTN_LEGACY_MODE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG017F_USB_TX_DATAPATH_RSTN_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG017F_USB_TX_DATAPATH_RSTN_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG017F_RX_LFPS_DET_FILT_BYPASS_LEGACY_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG017F_RX_LFPS_DET_FILT_BYPASS_LEGACY_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG017F_RX_LFPS_DET_FILT_BYPASS_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG017F_RX_LFPS_DET_FILT_BYPASS_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0180 (0x0600)
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#define USBDP_CMN_REG0180_CMN_RESERVED28_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_CMN_REG0180_CMN_RESERVED28_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_CMN_REG0180_CMN_RESERVED28_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_CMN_REG0180_CMN_RESERVED28_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_BOOST_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_BOOST_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_BOOST_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_BOOST_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0180_CMN_RESERVED29_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0180_CMN_RESERVED29_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0180_CMN_RESERVED29_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0180_CMN_RESERVED29_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_HYS_CTRL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_HYS_CTRL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_HYS_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0180_ANA_AUX_RX_HYS_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0181 (0x0604)
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#define USBDP_CMN_REG0181_CMN_RESERVED30_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0181_CMN_RESERVED30_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0181_CMN_RESERVED30_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0181_CMN_RESERVED30_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VDDH_MODE_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VDDH_MODE_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VDDH_MODE_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VDDH_MODE_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_MODE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_MODE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_MODE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_MODE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0181_CMN_RESERVED31_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0181_CMN_RESERVED31_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0181_CMN_RESERVED31_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0181_CMN_RESERVED31_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_VCI_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_VCI_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_VCI_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG0181_ANA_LCPLL_ANA_LC_CAP_BIAS_VREF_VCI_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG0182 (0x0608)
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#define USBDP_CMN_REG0182_CMN_RESERVED32_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0182_CMN_RESERVED32_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0182_CMN_RESERVED32_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0182_CMN_RESERVED32_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0182_LN0_ANA_TX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0183 (0x060C)
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#define USBDP_CMN_REG0183_CMN_RESERVED33_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0183_CMN_RESERVED33_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0183_CMN_RESERVED33_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0183_CMN_RESERVED33_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0183_LN1_ANA_TX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0184 (0x0610)
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#define USBDP_CMN_REG0184_CMN_RESERVED34_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0184_CMN_RESERVED34_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0184_CMN_RESERVED34_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0184_CMN_RESERVED34_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0184_LN2_ANA_TX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0185 (0x0614)
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#define USBDP_CMN_REG0185_CMN_RESERVED35_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0185_CMN_RESERVED35_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0185_CMN_RESERVED35_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0185_CMN_RESERVED35_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0185_LN3_ANA_TX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0186 (0x0618)
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#define USBDP_CMN_REG0186_CMN_RESERVED36_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0186_CMN_RESERVED36_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0186_CMN_RESERVED36_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0186_CMN_RESERVED36_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0186_LN0_ANA_RX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0187 (0x061C)
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#define USBDP_CMN_REG0187_CMN_RESERVED37_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0187_CMN_RESERVED37_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0187_CMN_RESERVED37_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0187_CMN_RESERVED37_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0187_LN2_ANA_RX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0188 (0x0620)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0188_DP_TX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0189 (0x0624)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0189_DP_TX_CLK_INV_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG018A (0x0628)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG018A_DP_TX_CLK_INV_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG018B (0x062C)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG018B_PCS_HS_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SSP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SSP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SSP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG018B_PCS_RX_CLK_INV_SSP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG018C (0x0630)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG018C_DP_TX_CLK_INV_OUT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG018D (0x0634)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG018D_DP_TX_CLK_INV_OUT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG018E (0x0638)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG018E_DP_TX_CLK_INV_OUT_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG018F (0x063C)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG018F_PCS_HS_CLK_INV_OUT_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SSP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SSP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_CMN_REG018F_PCS_RX_CLK_INV_OUT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_CMN_REG0190 (0x0640)
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#define USBDP_CMN_REG0190_BIAS_EN_GFMUX_SEL_LEGACY_MODE_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_CMN_REG0190_BIAS_EN_GFMUX_SEL_LEGACY_MODE_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_CMN_REG0190_BIAS_EN_GFMUX_SEL_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_CMN_REG0190_BIAS_EN_GFMUX_SEL_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_CMN_REG0190_USB_RX_LANE_TX_MODE_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_CMN_REG0190_USB_RX_LANE_TX_MODE_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_CMN_REG0190_USB_RX_LANE_TX_MODE_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_CMN_REG0190_USB_RX_LANE_TX_MODE_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_CMN_REG0190_DTB_OUT_MODE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG0190_DTB_OUT_MODE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG0190_DTB_OUT_MODE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG0190_DTB_OUT_MODE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG0190_USER_PAT_LEGACY_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG0190_USER_PAT_LEGACY_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG0190_USER_PAT_LEGACY_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG0190_USER_PAT_LEGACY_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG0191 (0x0644)
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#define USBDP_CMN_REG0191_USER_PAT_COMMA_TIMER__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0191_USER_PAT_COMMA_TIMER__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0191_USER_PAT_COMMA_TIMER__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0191_USER_PAT_COMMA_TIMER__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0192 (0x0648)
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#define USBDP_CMN_REG0192_USER_PAT_COMMA_TIMER__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG0192_USER_PAT_COMMA_TIMER__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG0192_USER_PAT_COMMA_TIMER__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG0192_USER_PAT_COMMA_TIMER__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG0193 (0x064C)
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#define USBDP_CMN_REG0193_CMN_RESERVED38_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0193_CMN_RESERVED38_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0193_CMN_RESERVED38_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0193_CMN_RESERVED38_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_CLK_OUT_TO_EXT_IO_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0193_ANA_LCPLL_ATB_SEL__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0193_ANA_LCPLL_ATB_SEL__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0193_ANA_LCPLL_ATB_SEL__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0193_ANA_LCPLL_ATB_SEL__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG0194 (0x0650)
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#define USBDP_CMN_REG0194_CMN_RESERVED39_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_CMN_REG0194_CMN_RESERVED39_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_CMN_REG0194_CMN_RESERVED39_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_CMN_REG0194_CMN_RESERVED39_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_CLK_OUT_TO_EXT_IO_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_CMN_REG0194_ANA_ROPLL_ATB_SEL__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG0194_ANA_ROPLL_ATB_SEL__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG0194_ANA_ROPLL_ATB_SEL__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG0194_ANA_ROPLL_ATB_SEL__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01C0 (0x0700)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_LOCK_DONE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_LOCK_DONE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_AFC_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_AFC_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_L_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_L_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_L_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_L_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_M_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_M_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_M_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG01C0_ANA_LCPLL_MON_AFC_M_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01C1 (0x0704)
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#define USBDP_CMN_REG01C1_ANA_LCPLL_MON_GM_CODE_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_CMN_REG01C1_ANA_LCPLL_MON_GM_CODE_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_CMN_REG01C1_ANA_LCPLL_MON_GM_CODE_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_CMN_REG01C1_ANA_LCPLL_MON_GM_CODE_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_LOCK_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_LOCK_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_AFC_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_AFC_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG01C1_ANA_ROPLL_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG01C2 (0x0708)
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#define USBDP_CMN_REG01C2_ANA_ROPLL_MON_AFC_M_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG01C2_ANA_ROPLL_MON_AFC_M_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG01C2_ANA_ROPLL_MON_AFC_M_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG01C2_ANA_ROPLL_MON_AFC_M_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01C3 (0x070C)
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#define USBDP_CMN_REG01C3_MON_CMN_STATE_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG01C3_MON_CMN_STATE_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG01C3_MON_CMN_STATE_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG01C3_MON_CMN_STATE_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG01C4 (0x0710)
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#define USBDP_CMN_REG01C4_MON_CMN_TIME__14_8_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_CMN_REG01C4_MON_CMN_TIME__14_8_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_CMN_REG01C4_MON_CMN_TIME__14_8_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_CMN_REG01C4_MON_CMN_TIME__14_8_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_CMN_REG01C5 (0x0714)
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#define USBDP_CMN_REG01C5_MON_CMN_TIME__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01C5_MON_CMN_TIME__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01C5_MON_CMN_TIME__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01C5_MON_CMN_TIME__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01C6 (0x0718)
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#define USBDP_CMN_REG01C6_MON_BIAS_ICAL_COMP_OUT_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG01C6_MON_BIAS_ICAL_COMP_OUT_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG01C6_MON_BIAS_ICAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG01C6_MON_BIAS_ICAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG01C7 (0x071C)
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#define USBDP_CMN_REG01C7_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG01C7_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG01C7_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG01C7_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01C8 (0x0720)
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#define USBDP_CMN_REG01C8_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01C8_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01C8_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01C8_MON_LCPLL_FLD_VCO_CNT_MON_VALUE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01C9 (0x0724)
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#define USBDP_CMN_REG01C9_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG01C9_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG01C9_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG01C9_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01CA (0x0728)
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#define USBDP_CMN_REG01CA_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01CA_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01CA_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01CA_MON_ROPLL_FLD_VCO_CNT_MON_VALUE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01CB (0x072C)
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#define USBDP_CMN_REG01CB_LN0_MON_RX_OC_INIT_VGA_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01CB_LN0_MON_RX_OC_INIT_VGA_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01CB_LN0_MON_RX_OC_INIT_VGA_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01CB_LN0_MON_RX_OC_INIT_VGA_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01CC (0x0730)
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#define USBDP_CMN_REG01CC_LN0_MON_RX_OC_INIT_DAC_VGA_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG01CC_LN0_MON_RX_OC_INIT_DAC_VGA_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG01CC_LN0_MON_RX_OC_INIT_DAC_VGA_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG01CC_LN0_MON_RX_OC_INIT_DAC_VGA_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG01CD (0x0734)
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#define USBDP_CMN_REG01CD_LN0_MON_RX_OC_RAW_DATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01CD_LN0_MON_RX_OC_RAW_DATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01CD_LN0_MON_RX_OC_RAW_DATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01CD_LN0_MON_RX_OC_RAW_DATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01CE (0x0738)
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#define USBDP_CMN_REG01CE_LN0_MON_RX_OC_RAW_DATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01CE_LN0_MON_RX_OC_RAW_DATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01CE_LN0_MON_RX_OC_RAW_DATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01CE_LN0_MON_RX_OC_RAW_DATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01CF (0x073C)
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#define USBDP_CMN_REG01CF_LN0_MON_RX_OC_RAW_DATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01CF_LN0_MON_RX_OC_RAW_DATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01CF_LN0_MON_RX_OC_RAW_DATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01CF_LN0_MON_RX_OC_RAW_DATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D0 (0x0740)
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#define USBDP_CMN_REG01D0_LN0_MON_RX_OC_RAW_DATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D0_LN0_MON_RX_OC_RAW_DATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D0_LN0_MON_RX_OC_RAW_DATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D0_LN0_MON_RX_OC_RAW_DATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D1 (0x0744)
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#define USBDP_CMN_REG01D1_LN0_MON_RX_OC_RAW_DATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D1_LN0_MON_RX_OC_RAW_DATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D1_LN0_MON_RX_OC_RAW_DATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D1_LN0_MON_RX_OC_RAW_DATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D2 (0x0748)
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#define USBDP_CMN_REG01D2_LN2_MON_RX_OC_INIT_VGA_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D2_LN2_MON_RX_OC_INIT_VGA_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D2_LN2_MON_RX_OC_INIT_VGA_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D2_LN2_MON_RX_OC_INIT_VGA_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D3 (0x074C)
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#define USBDP_CMN_REG01D3_LN2_MON_RX_OC_INIT_DAC_VGA_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_CMN_REG01D3_LN2_MON_RX_OC_INIT_DAC_VGA_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_CMN_REG01D3_LN2_MON_RX_OC_INIT_DAC_VGA_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_CMN_REG01D3_LN2_MON_RX_OC_INIT_DAC_VGA_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_CMN_REG01D4 (0x0750)
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#define USBDP_CMN_REG01D4_LN2_MON_RX_OC_RAW_DATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D4_LN2_MON_RX_OC_RAW_DATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D4_LN2_MON_RX_OC_RAW_DATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D4_LN2_MON_RX_OC_RAW_DATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D5 (0x0754)
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#define USBDP_CMN_REG01D5_LN2_MON_RX_OC_RAW_DATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D5_LN2_MON_RX_OC_RAW_DATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D5_LN2_MON_RX_OC_RAW_DATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D5_LN2_MON_RX_OC_RAW_DATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D6 (0x0758)
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#define USBDP_CMN_REG01D6_LN2_MON_RX_OC_RAW_DATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D6_LN2_MON_RX_OC_RAW_DATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D6_LN2_MON_RX_OC_RAW_DATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D6_LN2_MON_RX_OC_RAW_DATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D7 (0x075C)
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#define USBDP_CMN_REG01D7_LN2_MON_RX_OC_RAW_DATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D7_LN2_MON_RX_OC_RAW_DATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D7_LN2_MON_RX_OC_RAW_DATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D7_LN2_MON_RX_OC_RAW_DATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D8 (0x0760)
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#define USBDP_CMN_REG01D8_LN2_MON_RX_OC_RAW_DATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01D8_LN2_MON_RX_OC_RAW_DATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01D8_LN2_MON_RX_OC_RAW_DATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01D8_LN2_MON_RX_OC_RAW_DATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01D9 (0x0764)
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#define USBDP_CMN_REG01D9_LN0_MON_RX_EFOM_ERR_CNT__52_48_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG01D9_LN0_MON_RX_EFOM_ERR_CNT__52_48_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG01D9_LN0_MON_RX_EFOM_ERR_CNT__52_48_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG01D9_LN0_MON_RX_EFOM_ERR_CNT__52_48_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG01DA (0x0768)
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#define USBDP_CMN_REG01DA_LN0_MON_RX_EFOM_ERR_CNT__47_40_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DA_LN0_MON_RX_EFOM_ERR_CNT__47_40_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DA_LN0_MON_RX_EFOM_ERR_CNT__47_40_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DA_LN0_MON_RX_EFOM_ERR_CNT__47_40_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01DB (0x076C)
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#define USBDP_CMN_REG01DB_LN0_MON_RX_EFOM_ERR_CNT__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DB_LN0_MON_RX_EFOM_ERR_CNT__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DB_LN0_MON_RX_EFOM_ERR_CNT__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DB_LN0_MON_RX_EFOM_ERR_CNT__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01DC (0x0770)
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#define USBDP_CMN_REG01DC_LN0_MON_RX_EFOM_ERR_CNT__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DC_LN0_MON_RX_EFOM_ERR_CNT__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DC_LN0_MON_RX_EFOM_ERR_CNT__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DC_LN0_MON_RX_EFOM_ERR_CNT__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01DD (0x0774)
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#define USBDP_CMN_REG01DD_LN0_MON_RX_EFOM_ERR_CNT__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DD_LN0_MON_RX_EFOM_ERR_CNT__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DD_LN0_MON_RX_EFOM_ERR_CNT__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DD_LN0_MON_RX_EFOM_ERR_CNT__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01DE (0x0778)
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#define USBDP_CMN_REG01DE_LN0_MON_RX_EFOM_ERR_CNT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DE_LN0_MON_RX_EFOM_ERR_CNT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DE_LN0_MON_RX_EFOM_ERR_CNT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DE_LN0_MON_RX_EFOM_ERR_CNT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01DF (0x077C)
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#define USBDP_CMN_REG01DF_LN0_MON_RX_EFOM_ERR_CNT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01DF_LN0_MON_RX_EFOM_ERR_CNT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01DF_LN0_MON_RX_EFOM_ERR_CNT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01DF_LN0_MON_RX_EFOM_ERR_CNT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E0 (0x0780)
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#define USBDP_CMN_REG01E0_LN2_MON_RX_EFOM_ERR_CNT__52_48_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_CMN_REG01E0_LN2_MON_RX_EFOM_ERR_CNT__52_48_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_CMN_REG01E0_LN2_MON_RX_EFOM_ERR_CNT__52_48_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_CMN_REG01E0_LN2_MON_RX_EFOM_ERR_CNT__52_48_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_CMN_REG01E1 (0x0784)
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#define USBDP_CMN_REG01E1_LN2_MON_RX_EFOM_ERR_CNT__47_40_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E1_LN2_MON_RX_EFOM_ERR_CNT__47_40_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E1_LN2_MON_RX_EFOM_ERR_CNT__47_40_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E1_LN2_MON_RX_EFOM_ERR_CNT__47_40_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E2 (0x0788)
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#define USBDP_CMN_REG01E2_LN2_MON_RX_EFOM_ERR_CNT__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E2_LN2_MON_RX_EFOM_ERR_CNT__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E2_LN2_MON_RX_EFOM_ERR_CNT__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E2_LN2_MON_RX_EFOM_ERR_CNT__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E3 (0x078C)
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#define USBDP_CMN_REG01E3_LN2_MON_RX_EFOM_ERR_CNT__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E3_LN2_MON_RX_EFOM_ERR_CNT__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E3_LN2_MON_RX_EFOM_ERR_CNT__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E3_LN2_MON_RX_EFOM_ERR_CNT__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E4 (0x0790)
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#define USBDP_CMN_REG01E4_LN2_MON_RX_EFOM_ERR_CNT__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E4_LN2_MON_RX_EFOM_ERR_CNT__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E4_LN2_MON_RX_EFOM_ERR_CNT__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E4_LN2_MON_RX_EFOM_ERR_CNT__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E5 (0x0794)
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#define USBDP_CMN_REG01E5_LN2_MON_RX_EFOM_ERR_CNT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E5_LN2_MON_RX_EFOM_ERR_CNT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E5_LN2_MON_RX_EFOM_ERR_CNT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E5_LN2_MON_RX_EFOM_ERR_CNT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E6 (0x0798)
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#define USBDP_CMN_REG01E6_LN2_MON_RX_EFOM_ERR_CNT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E6_LN2_MON_RX_EFOM_ERR_CNT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E6_LN2_MON_RX_EFOM_ERR_CNT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E6_LN2_MON_RX_EFOM_ERR_CNT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E7 (0x079C)
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#define USBDP_CMN_REG01E7_MON_USB_DBG_BLK_ERROR_COUNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E7_MON_USB_DBG_BLK_ERROR_COUNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E7_MON_USB_DBG_BLK_ERROR_COUNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E7_MON_USB_DBG_BLK_ERROR_COUNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E8 (0x07A0)
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#define USBDP_CMN_REG01E8_MON_USB_DBG_BLK_DEBUG_MISC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01E8_MON_USB_DBG_BLK_DEBUG_MISC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01E8_MON_USB_DBG_BLK_DEBUG_MISC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01E8_MON_USB_DBG_BLK_DEBUG_MISC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_CMN_REG01E9 (0x07A4)
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#define USBDP_CMN_REG01E9_MON_CMN_RESERVED0_MSK USBDP_REG_MSK(1, 7)
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#define USBDP_CMN_REG01E9_MON_CMN_RESERVED0_CLR USBDP_REG_CLR(1, 7)
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#define USBDP_CMN_REG01E9_MON_CMN_RESERVED0_SET(_x) USBDP_REG_SET(_x, 1, 7)
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#define USBDP_CMN_REG01E9_MON_CMN_RESERVED0_GET(_R) USBDP_REG_GET(_R, 1, 7)
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#define USBDP_CMN_REG01E9_MON_USB_DBG_BLK_ERR_IND_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_CMN_REG01E9_MON_USB_DBG_BLK_ERR_IND_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_CMN_REG01E9_MON_USB_DBG_BLK_ERR_IND_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_CMN_REG01E9_MON_USB_DBG_BLK_ERR_IND_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_CMN_REG01EA (0x07A8)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_START_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_START_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_START_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_START_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_TEST_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_TEST_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_TEST_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_CMN_REG01EA_DP_MON_BIST_COMP_TEST_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_CMN_REG01EB (0x07AC)
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#define USBDP_CMN_REG01EB_MON_BIST_STATUS_FLAG_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_CMN_REG01EB_MON_BIST_STATUS_FLAG_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_CMN_REG01EB_MON_BIST_STATUS_FLAG_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_CMN_REG01EB_MON_BIST_STATUS_FLAG_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0200 (0x0800)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0200_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0200_OVRD_LN0_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0200_LN0_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0201 (0x0804)
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#define USBDP_TRSV_REG0201_OVRD_LN0_TX_DRV_EI_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0201_OVRD_LN0_TX_DRV_EI_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0201_OVRD_LN0_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0201_OVRD_LN0_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0201_LN0_TX_DRV_EI_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0202 (0x0808)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0202_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0203 (0x080C)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0203_LN0_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_VREF_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_VREF_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_FB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_FB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_FB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_FB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0203_LN0_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0204 (0x0810)
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#define USBDP_TRSV_REG0204_OVRD_LN0_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0204_OVRD_LN0_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0204_OVRD_LN0_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0204_OVRD_LN0_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0204_LN0_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0204_LN0_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0204_LN0_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0204_LN0_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0205 (0x0814)
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#define USBDP_TRSV_REG0205_OVRD_LN0_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0205_OVRD_LN0_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0205_OVRD_LN0_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0205_OVRD_LN0_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0205_LN0_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0205_LN0_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0205_LN0_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0205_LN0_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0206 (0x0818)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0206_OVRD_LN0_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0206_LN0_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0207 (0x081C)
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#define USBDP_TRSV_REG0207_OVRD_LN0_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0207_OVRD_LN0_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0207_OVRD_LN0_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0207_OVRD_LN0_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0207_LN0_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0207_LN0_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0207_LN0_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0207_LN0_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_ACCDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_ACCDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_ACCDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0207_LN0_ANA_TX_DRV_ACCDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0208 (0x0820)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_CTRL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_CTRL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_ACCDRV_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_HSCLK_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_HSCLK_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_HSCLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_HSCLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0208_LN0_ANA_TX_DRV_PLL_REF_MON_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0209 (0x0824)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0209_LN0_TX_JEQ_CAP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020A (0x0828)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020A_LN0_TX_JEQ_CAP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020B (0x082C)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020B_LN0_TX_JEQ_CAP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020C (0x0830)
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#define USBDP_TRSV_REG020C_LN0_ANA_TX_JEQ_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG020C_LN0_ANA_TX_JEQ_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG020C_LN0_ANA_TX_JEQ_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG020C_LN0_ANA_TX_JEQ_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG020C_LN0_TX_JEQ_EVEN_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020C_LN0_TX_JEQ_EVEN_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020C_LN0_TX_JEQ_EVEN_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020C_LN0_TX_JEQ_EVEN_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020D (0x0834)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020D_LN0_TX_JEQ_EVEN_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020E (0x0838)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020E_LN0_TX_JEQ_EVEN_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG020F (0x083C)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_EVEN_CTRL_HBR3_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_EVEN_CTRL_HBR3_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_EVEN_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_EVEN_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_ODD_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_ODD_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_ODD_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG020F_LN0_TX_JEQ_ODD_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0210 (0x0840)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0210_LN0_TX_JEQ_ODD_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0211 (0x0844)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0211_LN0_TX_JEQ_ODD_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0212 (0x0848)
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#define USBDP_TRSV_REG0212_LN0_TX_JEQ_ODD_CTRL_HBR3_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG0212_LN0_TX_JEQ_ODD_CTRL_HBR3_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG0212_LN0_TX_JEQ_ODD_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG0212_LN0_TX_JEQ_ODD_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG0212_OVRD_LN0_TX_RCAL_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0212_OVRD_LN0_TX_RCAL_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0212_OVRD_LN0_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0212_OVRD_LN0_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0212_LN0_TX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0212_LN0_TX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0212_LN0_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0212_LN0_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0212_LN0_ANA_TX_RTERM_42P5_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0212_LN0_ANA_TX_RTERM_42P5_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0212_LN0_ANA_TX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0212_LN0_ANA_TX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0213 (0x084C)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0213_OVRD_LN0_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_COMP_I_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_COMP_I_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_COMP_I_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_COMP_I_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_VREF_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_VREF_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0213_LN0_ANA_TX_RXD_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0213_LN0_TX_SER_40BIT_EN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_SER_40BIT_EN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_SER_40BIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0213_LN0_TX_SER_40BIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0214 (0x0850)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_40BIT_EN_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0214_OVRD_LN0_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0214_OVRD_LN0_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0214_OVRD_LN0_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0214_OVRD_LN0_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_RATE_SEL_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_RATE_SEL_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_RATE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0214_LN0_TX_SER_RATE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0215 (0x0854)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_RATE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0215_OVRD_LN0_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0215_OVRD_LN0_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0215_OVRD_LN0_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0215_OVRD_LN0_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0215_LN0_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0215_LN0_ANA_TX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0215_LN0_ANA_TX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0215_LN0_ANA_TX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0215_LN0_ANA_TX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0216 (0x0858)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_SER_TXCLK_INV_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_SER_TXCLK_INV_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_SER_TXCLK_INV_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_SER_TXCLK_INV_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_TO_DIG_BYTE_CLK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_TO_DIG_BYTE_CLK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_TO_DIG_BYTE_CLK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0216_LN0_ANA_TX_TO_DIG_BYTE_CLK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0216_OVRD_LN0_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0216_OVRD_LN0_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0216_OVRD_LN0_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0216_OVRD_LN0_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SSP_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SSP_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_RBR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_RBR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_HBR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_HBR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0216_LN0_TX_LANE_LC_RO_CLK_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0217 (0x085C)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR2_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR2_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR3_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR3_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_LC_RO_CLK_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0217_LN0_ANA_TX_LANE_DIV2_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_SER_VREG_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_SER_VREG_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0217_OVRD_LN0_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_SER_VREG_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_SER_VREG_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0217_LN0_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0218 (0x0860)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0218_OVRD_LN0_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0218_OVRD_LN0_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0218_OVRD_LN0_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0218_OVRD_LN0_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0218_LN0_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0218_LN0_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0218_LN0_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0218_LN0_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_LADDER_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_LADDER_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0218_LN0_ANA_TX_SER_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0219 (0x0864)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_I_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_I_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_I_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_I_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0219_LN0_ANA_TX_SER_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG021A (0x0868)
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#define USBDP_TRSV_REG021A_LN0_TX_DCC_IN_BUF_STR_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG021A_LN0_TX_DCC_IN_BUF_STR_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG021A_LN0_TX_DCC_IN_BUF_STR_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG021A_LN0_TX_DCC_IN_BUF_STR_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG021B (0x086C)
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#define USBDP_TRSV_REG021B_LN0_TX_DCC_IN_BUF_STR_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG021B_LN0_TX_DCC_IN_BUF_STR_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG021B_LN0_TX_DCC_IN_BUF_STR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG021B_LN0_TX_DCC_IN_BUF_STR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG021C (0x0870)
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#define USBDP_TRSV_REG021C_LN0_TX_DCC_IN_BUF_STR_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG021C_LN0_TX_DCC_IN_BUF_STR_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG021C_LN0_TX_DCC_IN_BUF_STR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG021C_LN0_TX_DCC_IN_BUF_STR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG021D (0x0874)
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#define USBDP_TRSV_REG021D_LN0_TX_DCC_IN_BUF_STR_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG021D_LN0_TX_DCC_IN_BUF_STR_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG021D_LN0_TX_DCC_IN_BUF_STR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG021D_LN0_TX_DCC_IN_BUF_STR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG021E (0x0878)
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#define USBDP_TRSV_REG021E_LN0_TX_DCC_IN_BUF_STR_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG021E_LN0_TX_DCC_IN_BUF_STR_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG021E_LN0_TX_DCC_IN_BUF_STR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG021E_LN0_TX_DCC_IN_BUF_STR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG021F (0x087C)
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#define USBDP_TRSV_REG021F_LN0_TX_DCC_IN_BUF_STR_HBR3_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG021F_LN0_TX_DCC_IN_BUF_STR_HBR3_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG021F_LN0_TX_DCC_IN_BUF_STR_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG021F_LN0_TX_DCC_IN_BUF_STR_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG021F_LN0_ANA_TX_TO_RX_CLK_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG021F_LN0_ANA_TX_TO_RX_CLK_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG021F_LN0_ANA_TX_TO_RX_CLK_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG021F_LN0_ANA_TX_TO_RX_CLK_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0220 (0x0880)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_SEL_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_SEL_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_SLB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_SLB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_LLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_LLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_LLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0220_LN0_ANA_TX_LLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0221 (0x0884)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_SRLB_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_SRLB_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0221_OVRD_LN0_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0221_LN0_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_AFC_FORCE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_AFC_FORCE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_AFC_FORCE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_AFC_FORCE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_CLK_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_CLK_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0221_LN0_ANA_TX_LFPS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0222 (0x0888)
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#define USBDP_TRSV_REG0222_OVRD_LN0_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0222_OVRD_LN0_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0222_OVRD_LN0_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0222_OVRD_LN0_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0222_LN0_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0223 (0x088C)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0223_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0224 (0x0890)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0224_LN0_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0224_OVRD_LN0_TX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0224_OVRD_LN0_TX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0224_OVRD_LN0_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0224_OVRD_LN0_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0224_LN0_TX_INIT_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0224_LN0_TX_INIT_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0224_LN0_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0224_LN0_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0225 (0x0894)
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#define USBDP_TRSV_REG0225_LN0_ANA_TX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0225_LN0_ANA_TX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0225_LN0_ANA_TX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0225_LN0_ANA_TX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0226 (0x0898)
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#define USBDP_TRSV_REG0226_LN0_TX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0226_LN0_TX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0226_LN0_TX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0226_LN0_TX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0227 (0x089C)
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#define USBDP_TRSV_REG0227_LN0_TX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0227_LN0_TX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0227_LN0_TX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0227_LN0_TX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0228 (0x08A0)
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#define USBDP_TRSV_REG0228_LN0_TX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0228_LN0_TX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0228_LN0_TX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0228_LN0_TX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0229 (0x08A4)
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#define USBDP_TRSV_REG0229_LN0_TX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0229_LN0_TX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0229_LN0_TX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0229_LN0_TX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG022A (0x08A8)
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#define USBDP_TRSV_REG022A_LN0_TX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG022A_LN0_TX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG022A_LN0_TX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG022A_LN0_TX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG022B (0x08AC)
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#define USBDP_TRSV_REG022B_LN0_TX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG022B_LN0_TX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG022B_LN0_TX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG022B_LN0_TX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG022C (0x08B0)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG022C_OVRD_LN0_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG022C_LN0_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG022D (0x08B4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG022D_LN0_RX_CDR_REFDIV_SEL_PLL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG022E (0x08B8)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG022E_LN0_RX_CDR_REFDIV_SEL_PLL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG022F (0x08BC)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG022F_LN0_RX_CDR_REFDIV_SEL_PLL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0230 (0x08C0)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0230_LN0_RX_CDR_REFDIV_SEL_DATA_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0231 (0x08C4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0231_LN0_RX_CDR_REFDIV_SEL_DATA_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0232 (0x08C8)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0232_LN0_RX_CDR_REFDIV_SEL_DATA_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0233 (0x08CC)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0233_LN0_RX_CDR_MDIV_SEL_PLL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0234 (0x08D0)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0234_LN0_RX_CDR_MDIV_SEL_PLL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0235 (0x08D4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0235_LN0_RX_CDR_MDIV_SEL_PLL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0236 (0x08D8)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0236_LN0_RX_CDR_MDIV_SEL_DATA_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0237 (0x08DC)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0237_LN0_RX_CDR_MDIV_SEL_DATA_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0238 (0x08E0)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0238_LN0_RX_CDR_MDIV_SEL_DATA_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0239 (0x08E4)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_BW_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_BW_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_BW_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_BW_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_REFDIV_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_REFDIV_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_REFDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_REFDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_REFDIV_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_REFDIV_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_REFDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_REFDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_MDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_MDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0239_OVRD_LN0_RX_CDR_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_MDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_MDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0239_LN0_RX_CDR_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_DES_RXCLK_INV_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_DES_RXCLK_INV_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_DES_RXCLK_INV_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_DES_RXCLK_INV_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_AFC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_AFC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_AFC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0239_LN0_ANA_RX_CDR_AFC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG023A (0x08E8)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_TEST_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_TEST_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_TEST_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_TEST_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_FORCE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_FORCE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_FORCE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_FORCE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG023A_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG023B (0x08EC)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_CTRL_RESERVED_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_CTRL_RESERVED_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_E_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_E_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_E_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_E_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_O_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_O_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_O_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_O_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG023B_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG023B_OVRD_LN0_RX_CDR_CP_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG023B_OVRD_LN0_RX_CDR_CP_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG023B_OVRD_LN0_RX_CDR_CP_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG023B_OVRD_LN0_RX_CDR_CP_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG023B_LN0_RX_CDR_CP_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG023B_LN0_RX_CDR_CP_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG023B_LN0_RX_CDR_CP_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG023B_LN0_RX_CDR_CP_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG023C (0x08F0)
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#define USBDP_TRSV_REG023C_OVRD_LN0_RX_CDR_FBB_CAL_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG023C_OVRD_LN0_RX_CDR_FBB_CAL_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG023C_OVRD_LN0_RX_CDR_FBB_CAL_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG023C_OVRD_LN0_RX_CDR_FBB_CAL_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_FBB_CAL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_FBB_CAL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_FBB_CAL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_FBB_CAL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_O_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_O_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_O_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_O_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_E_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_E_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_E_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG023C_LN0_ANA_RX_CDR_FBB_E_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SSP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SSP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG023C_LN0_RX_CDR_INTEG_PULSE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG023D (0x08F4)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_RBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_RBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR2_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR2_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR3_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR3_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG023D_LN0_RX_CDR_INTEG_PULSE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG023E (0x08F8)
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#define USBDP_TRSV_REG023E_OVRD_LN0_RX_CDR_VCO_STARTUP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG023E_OVRD_LN0_RX_CDR_VCO_STARTUP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG023E_OVRD_LN0_RX_CDR_VCO_STARTUP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG023E_OVRD_LN0_RX_CDR_VCO_STARTUP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG023E_LN0_RX_CDR_VCO_STARTUP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG023E_LN0_RX_CDR_VCO_STARTUP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG023E_LN0_RX_CDR_VCO_STARTUP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG023E_LN0_RX_CDR_VCO_STARTUP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG023E_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG023E_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG023E_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG023E_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG023F (0x08FC)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG023F_LN0_RX_CDR_VCO_FREQ_BOOST_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0240 (0x0900)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0240_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0241 (0x0904)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0241_LN0_RX_CDR_VCO_FREQ_BOOST_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0242 (0x0908)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0242_LN0_RX_CDR_CCO_BAND_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0243 (0x090C)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0243_LN0_RX_CDR_CCO_BAND_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0243_LN0_ANA_RX_CDR_CCO_VREG_R_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0243_LN0_ANA_RX_CDR_CCO_VREG_R_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0243_LN0_ANA_RX_CDR_CCO_VREG_R_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0243_LN0_ANA_RX_CDR_CCO_VREG_R_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0244 (0x0910)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_DAC_OFS_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_DAC_OFS_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_DAC_OFS_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0244_OVRD_LN0_RX_CTLE_OC_DAC_OFS_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_DAC_OFS_CTRL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_DAC_OFS_CTRL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_DAC_OFS_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0244_LN0_RX_CTLE_OC_DAC_OFS_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0245 (0x0914)
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#define USBDP_TRSV_REG0245_OVRD_LN0_RX_CTLE_OC_DAC_CODE_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0245_OVRD_LN0_RX_CTLE_OC_DAC_CODE_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0245_OVRD_LN0_RX_CTLE_OC_DAC_CODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0245_OVRD_LN0_RX_CTLE_OC_DAC_CODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0246 (0x0918)
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#define USBDP_TRSV_REG0246_LN0_RX_CTLE_OC_DAC_CODE_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0246_LN0_RX_CTLE_OC_DAC_CODE_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0246_LN0_RX_CTLE_OC_DAC_CODE_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0246_LN0_RX_CTLE_OC_DAC_CODE_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0247 (0x091C)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0247_LN0_RX_CTLE_HF_RL_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0248 (0x0920)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0248_LN0_RX_CTLE_HF_RL_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0249 (0x0924)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR2_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR2_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR3_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR3_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0249_LN0_RX_CTLE_HF_RL_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0249_LN0_ANA_RX_CTLE_OC_DAC_PULLUP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0249_LN0_ANA_RX_CTLE_OC_DAC_PULLUP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0249_LN0_ANA_RX_CTLE_OC_DAC_PULLUP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0249_LN0_ANA_RX_CTLE_OC_DAC_PULLUP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG024A (0x0928)
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#define USBDP_TRSV_REG024A_LN0_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG024A_LN0_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG024A_LN0_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG024A_LN0_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG024A_LN0_RX_CTLE_HF_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG024B (0x092C)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG024B_LN0_RX_CTLE_HF_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG024C (0x0930)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR2_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR2_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR3_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR3_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_CS_CTRL_SP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_CS_CTRL_SP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_CS_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG024C_LN0_RX_CTLE_HF_CS_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG024D (0x0934)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_SSP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_SSP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_RBR_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_RBR_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR2_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR2_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG024D_LN0_RX_CTLE_HF_CS_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG024E (0x0938)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_HF_CS_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_HF_CS_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_HF_CS_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_HF_CS_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG024E_LN0_ANA_RX_CTLE_BIAS_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG024E_LN0_ANA_RX_CTLE_BIAS_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG024E_LN0_ANA_RX_CTLE_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG024E_LN0_ANA_RX_CTLE_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_VGA_I_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_VGA_I_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_VGA_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG024E_LN0_RX_CTLE_VGA_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG024F (0x093C)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG024F_LN0_RX_CTLE_VGA_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0250 (0x0940)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0250_LN0_RX_CTLE_VGA_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0251 (0x0944)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_I_CTRL_HBR3_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_I_CTRL_HBR3_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_RL_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_RL_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_RL_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0251_LN0_RX_CTLE_VGA_RL_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0252 (0x0948)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0252_LN0_RX_CTLE_VGA_RL_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0253 (0x094C)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0253_LN0_RX_CTLE_VGA_RL_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0254 (0x0950)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_VGA_RL_CTRL_HBR3_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_VGA_RL_CTRL_HBR3_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_VGA_RL_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_VGA_RL_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG0254_LN0_ANA_RX_CTLE_TIE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0254_LN0_ANA_RX_CTLE_TIE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0254_LN0_ANA_RX_CTLE_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0254_LN0_ANA_RX_CTLE_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_CTLE_DFE_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_CTLE_DFE_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_CTLE_DFE_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_CTLE_DFE_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_DFE_OC_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_DFE_OC_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_DFE_OC_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_CTLE_DFE_OC_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_PEQ_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_PEQ_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_PEQ_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0254_OVRD_LN0_RX_PEQ_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_PEQ_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_PEQ_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_PEQ_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0254_LN0_RX_PEQ_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0255 (0x0954)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0255_LN0_RX_PEQ_VCM_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0256 (0x0958)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0256_LN0_RX_PEQ_VCM_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0257 (0x095C)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR2_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR2_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0257_LN0_RX_PEQ_VCM_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0258 (0x0960)
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#define USBDP_TRSV_REG0258_OVRD_LN0_RX_PEQ_P_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0258_OVRD_LN0_RX_PEQ_P_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0258_OVRD_LN0_RX_PEQ_P_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0258_OVRD_LN0_RX_PEQ_P_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0259 (0x0964)
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#define USBDP_TRSV_REG0259_LN0_RX_PEQ_P_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0259_LN0_RX_PEQ_P_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0259_LN0_RX_PEQ_P_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0259_LN0_RX_PEQ_P_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG025A (0x0968)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_PULLDN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_PULLDN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_PULLDN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_PULLDN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG025A_LN0_ANA_RX_PEQ_VCM_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG025A_LN0_RX_PEQ_Z_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG025B (0x096C)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG025B_LN0_RX_PEQ_Z_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG025B_OVRD_LN0_RX_DES_DATA_CLEAR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG025B_OVRD_LN0_RX_DES_DATA_CLEAR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG025B_OVRD_LN0_RX_DES_DATA_CLEAR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG025B_OVRD_LN0_RX_DES_DATA_CLEAR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG025B_LN0_RX_DES_DATA_CLEAR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG025B_LN0_RX_DES_DATA_CLEAR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG025B_LN0_RX_DES_DATA_CLEAR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG025B_LN0_RX_DES_DATA_CLEAR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG025C (0x0970)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG025C_LN0_RX_DES_DATA_WIDTH_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG025D (0x0974)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_DATA_WIDTH_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG025D_OVRD_LN0_RX_DES_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG025D_OVRD_LN0_RX_DES_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG025D_OVRD_LN0_RX_DES_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG025D_OVRD_LN0_RX_DES_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG025D_LN0_RX_DES_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG025D_LN0_ANA_RX_DES_NON_DATA_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG025D_LN0_ANA_RX_DES_NON_DATA_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG025D_LN0_ANA_RX_DES_NON_DATA_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG025D_LN0_ANA_RX_DES_NON_DATA_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG025E (0x0978)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_NON_DATA_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_NON_DATA_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_NON_DATA_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_NON_DATA_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_NON_DATA_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_NON_DATA_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_NON_DATA_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_NON_DATA_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG025E_OVRD_LN0_RX_DES_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG025E_LN0_RX_DES_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG025E_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG025E_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG025E_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG025E_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG025F (0x097C)
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#define USBDP_TRSV_REG025F_OVRD_LN0_RX_DFE_OC_SA_ERR_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG025F_OVRD_LN0_RX_DFE_OC_SA_ERR_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG025F_OVRD_LN0_RX_DFE_OC_SA_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG025F_OVRD_LN0_RX_DFE_OC_SA_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0260 (0x0980)
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#define USBDP_TRSV_REG0260_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0260_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0260_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0260_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0261 (0x0984)
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#define USBDP_TRSV_REG0261_OVRD_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0261_OVRD_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0261_OVRD_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0261_OVRD_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0262 (0x0988)
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#define USBDP_TRSV_REG0262_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0262_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0262_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0262_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0263 (0x098C)
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#define USBDP_TRSV_REG0263_OVRD_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0263_OVRD_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0263_OVRD_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0263_OVRD_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0264 (0x0990)
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#define USBDP_TRSV_REG0264_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0264_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0264_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0264_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0265 (0x0994)
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#define USBDP_TRSV_REG0265_OVRD_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0265_OVRD_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0265_OVRD_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0265_OVRD_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0266 (0x0998)
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#define USBDP_TRSV_REG0266_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0266_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0266_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0266_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0267 (0x099C)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_MAIN_ADD_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_MAIN_ADD_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_MAIN_ADD_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_MAIN_ADD_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_SUB_ADD_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_SUB_ADD_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_SUB_ADD_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0267_LN0_ANA_RX_DFE_SUB_ADD_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_EOM_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_EOM_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_EOM_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0267_OVRD_LN0_RX_DFE_EOM_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_EOM_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_EOM_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_EOM_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0267_LN0_RX_DFE_EOM_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0268 (0x09A0)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0268_LN0_RX_DFE_EOM_PI_DIV_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0269 (0x09A4)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0269_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG026A (0x09A8)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR2_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR2_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG026A_LN0_RX_DFE_EOM_PI_DIV_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG026B (0x09AC)
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#define USBDP_TRSV_REG026B_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG026B_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG026B_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG026B_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG026C (0x09B0)
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#define USBDP_TRSV_REG026C_OVRD_LN0_RX_DFE_OC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG026C_OVRD_LN0_RX_DFE_OC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG026C_OVRD_LN0_RX_DFE_OC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG026C_OVRD_LN0_RX_DFE_OC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG026D (0x09B4)
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#define USBDP_TRSV_REG026D_LN0_RX_DFE_OC_ADDER_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG026D_LN0_RX_DFE_OC_ADDER_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG026D_LN0_RX_DFE_OC_ADDER_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG026D_LN0_RX_DFE_OC_ADDER_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG026E (0x09B8)
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#define USBDP_TRSV_REG026E_OVRD_LN0_RX_DFE_OC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG026E_OVRD_LN0_RX_DFE_OC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG026E_OVRD_LN0_RX_DFE_OC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG026E_OVRD_LN0_RX_DFE_OC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG026F (0x09BC)
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#define USBDP_TRSV_REG026F_LN0_RX_DFE_OC_ADDER_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG026F_LN0_RX_DFE_OC_ADDER_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG026F_LN0_RX_DFE_OC_ADDER_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG026F_LN0_RX_DFE_OC_ADDER_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0270 (0x09C0)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0270_OVRD_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0270_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0271 (0x09C4)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0271_OVRD_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0271_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0272 (0x09C8)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0272_OVRD_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0272_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0273 (0x09CC)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_ODD_OC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_DATA_ODD_OC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_ODD_OC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_DATA_ODD_OC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_EDGE_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_EDGE_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_EDGE_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_EDGE_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_EDGE_OC_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_EDGE_OC_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_EDGE_OC_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_EDGE_OC_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_ERR_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_ERR_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_ERR_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0273_OVRD_LN0_RX_DFE_SA_ERR_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_ERR_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_ERR_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_ERR_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0273_LN0_RX_DFE_SA_ERR_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0274 (0x09D0)
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#define USBDP_TRSV_REG0274_OVRD_LN0_RX_DFE_VREF_ODD_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0274_OVRD_LN0_RX_DFE_VREF_ODD_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0274_OVRD_LN0_RX_DFE_VREF_ODD_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0274_OVRD_LN0_RX_DFE_VREF_ODD_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0275 (0x09D4)
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#define USBDP_TRSV_REG0275_LN0_RX_DFE_VREF_ODD_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0275_LN0_RX_DFE_VREF_ODD_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0275_LN0_RX_DFE_VREF_ODD_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0275_LN0_RX_DFE_VREF_ODD_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0276 (0x09D8)
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#define USBDP_TRSV_REG0276_OVRD_LN0_RX_DFE_VREF_EVEN_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0276_OVRD_LN0_RX_DFE_VREF_EVEN_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0276_OVRD_LN0_RX_DFE_VREF_EVEN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0276_OVRD_LN0_RX_DFE_VREF_EVEN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0277 (0x09DC)
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#define USBDP_TRSV_REG0277_LN0_RX_DFE_VREF_EVEN_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0277_LN0_RX_DFE_VREF_EVEN_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0277_LN0_RX_DFE_VREF_EVEN_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0277_LN0_RX_DFE_VREF_EVEN_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0278 (0x09E0)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_VCM_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_VCM_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_VCM_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_DAC_VCM_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_VREF_DAC_LSB_CTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_VREF_DAC_LSB_CTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_VREF_DAC_LSB_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_VREF_DAC_LSB_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_OC_DAC_LSB_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_OC_DAC_LSB_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_OC_DAC_LSB_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0278_LN0_ANA_RX_DFE_OC_DAC_LSB_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0279 (0x09E4)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_EOM_CLK_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_EOM_CLK_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_EOM_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_EOM_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_MADD_V_TIE_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_MADD_V_TIE_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_MADD_V_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0279_LN0_ANA_RX_DFE_MADD_V_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0279_LN0_RX_DFE_MADD_RL_CONT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG027A (0x09E8)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG027A_LN0_RX_DFE_MADD_RL_CONT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG027B (0x09EC)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR2_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR2_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR3_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR3_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG027B_LN0_RX_DFE_MADD_RL_CONT_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG027B_LN0_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG027B_LN0_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG027B_LN0_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG027B_LN0_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG027C (0x09F0)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_V_TIE_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_V_TIE_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_V_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_V_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_RL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_RL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_RL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_RL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_BIAS_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_BIAS_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_VREG_OUT_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_VREG_OUT_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_VREG_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG027C_LN0_ANA_RX_DFE_VREG_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG027C_OVRD_LN0_RX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG027C_OVRD_LN0_RX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG027C_OVRD_LN0_RX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG027C_OVRD_LN0_RX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG027C_LN0_RX_RCAL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG027C_LN0_RX_RCAL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG027C_LN0_RX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG027C_LN0_RX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG027D (0x09F4)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_42P5_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_42P5_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSN_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSN_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSN_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSN_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSP_CTRL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSP_CTRL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSP_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG027D_LN0_ANA_RX_RTERM_OFSP_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_PATH_CTRL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_PATH_CTRL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_PATH_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG027D_OVRD_LN0_RX_RTERM_PATH_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_PATH_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_PATH_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_PATH_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG027D_LN0_RX_RTERM_PATH_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG027E (0x09F8)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_DIFN_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_DIFN_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_DIFN_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG027E_OVRD_LN0_RX_SQHS_DIFN_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_DIFN_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_DIFN_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_DIFN_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG027E_LN0_RX_SQHS_DIFN_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG027F (0x09FC)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFN_OC_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFN_OC_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFN_OC_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFN_OC_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFN_OC_CODE_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFN_OC_CODE_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFN_OC_CODE_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFN_OC_CODE_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG027F_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG027F_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG027F_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG027F_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFP_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFP_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFP_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG027F_OVRD_LN0_RX_SQHS_DIFP_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFP_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFP_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFP_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG027F_LN0_RX_SQHS_DIFP_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0280 (0x0A00)
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#define USBDP_TRSV_REG0280_OVRD_LN0_RX_SQHS_DIFP_OC_CODE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0280_OVRD_LN0_RX_SQHS_DIFP_OC_CODE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0280_OVRD_LN0_RX_SQHS_DIFP_OC_CODE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0280_OVRD_LN0_RX_SQHS_DIFP_OC_CODE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0280_LN0_RX_SQHS_DIFP_OC_CODE_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0280_LN0_RX_SQHS_DIFP_OC_CODE_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0280_LN0_RX_SQHS_DIFP_OC_CODE_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0280_LN0_RX_SQHS_DIFP_OC_CODE_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0280_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0281 (0x0A04)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_TH_CTRL_RESERVED_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_TH_CTRL_RESERVED_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_TH_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_TH_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_FILTER_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_FILTER_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_FILTER_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_FILTER_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_LPF_BW_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_LPF_BW_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_LPF_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_LPF_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0281_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0282 (0x0A08)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQLS_IN_LPF_CTRL_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQLS_IN_LPF_CTRL_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQLS_IN_LPF_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG0282_LN0_ANA_RX_SQLS_IN_LPF_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG0282_OVRD_LN0_RX_SQDIG_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0282_OVRD_LN0_RX_SQDIG_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0282_OVRD_LN0_RX_SQDIG_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0282_OVRD_LN0_RX_SQDIG_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0282_LN0_RX_SQDIG_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0282_LN0_RX_SQDIG_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0282_LN0_RX_SQDIG_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0282_LN0_RX_SQDIG_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0283 (0x0A0C)
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#define USBDP_TRSV_REG0283_OVRD_LN0_RX_LFPS_DET_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0283_OVRD_LN0_RX_LFPS_DET_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0283_OVRD_LN0_RX_LFPS_DET_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0283_OVRD_LN0_RX_LFPS_DET_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0283_LN0_RX_LFPS_DET_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0283_LN0_RX_LFPS_DET_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0283_LN0_RX_LFPS_DET_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0283_LN0_RX_LFPS_DET_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_BW_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_BW_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_TH_CTRL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_TH_CTRL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_TH_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_TH_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_I_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_I_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_I_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0283_LN0_ANA_RX_LFPS_I_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0284 (0x0A10)
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#define USBDP_TRSV_REG0284_OVRD_LN0_RX_BIAS_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0284_OVRD_LN0_RX_BIAS_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0284_OVRD_LN0_RX_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0284_OVRD_LN0_RX_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0284_LN0_RX_BIAS_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0284_LN0_RX_BIAS_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0284_LN0_RX_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0284_LN0_RX_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_D_LANE_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_D_LANE_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_D_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_D_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_CLK_LANE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_CLK_LANE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0284_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0285 (0x0A14)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0285_OVRD_LN0_RX_INIT_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0285_OVRD_LN0_RX_INIT_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0285_OVRD_LN0_RX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0285_OVRD_LN0_RX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0285_LN0_RX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0285_LN0_RX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0285_LN0_RX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0285_LN0_RX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_ATB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_ATB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0285_LN0_ANA_RX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0286 (0x0A18)
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#define USBDP_TRSV_REG0286_LN0_ANA_RX_ATB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0286_LN0_ANA_RX_ATB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0286_LN0_ANA_RX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0286_LN0_ANA_RX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0287 (0x0A1C)
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#define USBDP_TRSV_REG0287_LN0_ANA_RX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0287_LN0_ANA_RX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0287_LN0_ANA_RX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0287_LN0_ANA_RX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0288 (0x0A20)
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#define USBDP_TRSV_REG0288_LN0_RX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0288_LN0_RX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0288_LN0_RX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0288_LN0_RX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0289 (0x0A24)
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#define USBDP_TRSV_REG0289_LN0_RX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0289_LN0_RX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0289_LN0_RX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0289_LN0_RX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG028A (0x0A28)
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#define USBDP_TRSV_REG028A_LN0_RX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG028A_LN0_RX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG028A_LN0_RX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG028A_LN0_RX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG028B (0x0A2C)
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#define USBDP_TRSV_REG028B_LN0_RX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG028B_LN0_RX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG028B_LN0_RX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG028B_LN0_RX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG028C (0x0A30)
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#define USBDP_TRSV_REG028C_LN0_RX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG028C_LN0_RX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG028C_LN0_RX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG028C_LN0_RX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG028D (0x0A34)
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#define USBDP_TRSV_REG028D_LN0_RX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG028D_LN0_RX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG028D_LN0_RX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG028D_LN0_RX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG028E (0x0A38)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_SETTLE_TIME_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_SETTLE_TIME_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_SETTLE_TIME_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_SETTLE_TIME_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_NUM_OF_SAMPLE_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_NUM_OF_SAMPLE_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_NUM_OF_SAMPLE_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_NUM_OF_SAMPLE_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_20B_INPUT_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_20B_INPUT_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_20B_INPUT_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_20B_INPUT_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_VGA_CTLE_SA_START_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_VGA_CTLE_SA_START_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_VGA_CTLE_SA_START_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG028E_LN0_RX_OC_VGA_CTLE_SA_START_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG028F (0x0A3C)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_SQ_START_CODE_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_SQ_START_CODE_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_SQ_START_CODE_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_SQ_START_CODE_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG028F_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0290 (0x0A40)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_RX_SQ_DIFP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_CTLE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_CTLE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_CTLE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_BYPASS_CTLE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0290_LN0_OVRD_RX_OC_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0290_LN0_OVRD_RX_OC_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0290_LN0_OVRD_RX_OC_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0290_LN0_OVRD_RX_OC_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0290_LN0_RX_OC_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0291 (0x0A44)
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#define USBDP_TRSV_REG0291_LN0_LANE_RESERVED0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0291_LN0_LANE_RESERVED0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0291_LN0_LANE_RESERVED0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0291_LN0_LANE_RESERVED0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0292 (0x0A48)
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#define USBDP_TRSV_REG0292_LN0_LANE_RESERVED1_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0292_LN0_LANE_RESERVED1_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0292_LN0_LANE_RESERVED1_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0292_LN0_LANE_RESERVED1_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0293 (0x0A4C)
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#define USBDP_TRSV_REG0293_LN0_LANE_RESERVED2_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0293_LN0_LANE_RESERVED2_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0293_LN0_LANE_RESERVED2_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0293_LN0_LANE_RESERVED2_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0294 (0x0A50)
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#define USBDP_TRSV_REG0294_LN0_LANE_RESERVED3_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0294_LN0_LANE_RESERVED3_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0294_LN0_LANE_RESERVED3_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0294_LN0_LANE_RESERVED3_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0295 (0x0A54)
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#define USBDP_TRSV_REG0295_LN0_LANE_RESERVED4_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0295_LN0_LANE_RESERVED4_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0295_LN0_LANE_RESERVED4_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0295_LN0_LANE_RESERVED4_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0296 (0x0A58)
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#define USBDP_TRSV_REG0296_LN0_LANE_RESERVED5_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0296_LN0_LANE_RESERVED5_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0296_LN0_LANE_RESERVED5_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0296_LN0_LANE_RESERVED5_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0297 (0x0A5C)
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#define USBDP_TRSV_REG0297_LN0_RX_SSLMS_HF_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0297_LN0_RX_SSLMS_HF_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0297_LN0_RX_SSLMS_HF_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0297_LN0_RX_SSLMS_HF_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0298 (0x0A60)
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#define USBDP_TRSV_REG0298_LN0_RX_SSLMS_HF_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0298_LN0_RX_SSLMS_HF_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0298_LN0_RX_SSLMS_HF_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0298_LN0_RX_SSLMS_HF_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0299 (0x0A64)
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#define USBDP_TRSV_REG0299_LN0_RX_SSLMS_HF_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0299_LN0_RX_SSLMS_HF_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0299_LN0_RX_SSLMS_HF_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0299_LN0_RX_SSLMS_HF_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029A (0x0A68)
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#define USBDP_TRSV_REG029A_LN0_RX_SSLMS_HF_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029A_LN0_RX_SSLMS_HF_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029A_LN0_RX_SSLMS_HF_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029A_LN0_RX_SSLMS_HF_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029B (0x0A6C)
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#define USBDP_TRSV_REG029B_LN0_RX_SSLMS_HF_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029B_LN0_RX_SSLMS_HF_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029B_LN0_RX_SSLMS_HF_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029B_LN0_RX_SSLMS_HF_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029C (0x0A70)
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#define USBDP_TRSV_REG029C_LN0_RX_SSLMS_HF_INIT_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029C_LN0_RX_SSLMS_HF_INIT_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029C_LN0_RX_SSLMS_HF_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029C_LN0_RX_SSLMS_HF_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029D (0x0A74)
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#define USBDP_TRSV_REG029D_LN0_RX_SSLMS_MF_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029D_LN0_RX_SSLMS_MF_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029D_LN0_RX_SSLMS_MF_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029D_LN0_RX_SSLMS_MF_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029E (0x0A78)
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#define USBDP_TRSV_REG029E_LN0_RX_SSLMS_MF_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029E_LN0_RX_SSLMS_MF_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029E_LN0_RX_SSLMS_MF_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029E_LN0_RX_SSLMS_MF_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG029F (0x0A7C)
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#define USBDP_TRSV_REG029F_LN0_RX_SSLMS_MF_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG029F_LN0_RX_SSLMS_MF_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG029F_LN0_RX_SSLMS_MF_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG029F_LN0_RX_SSLMS_MF_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A0 (0x0A80)
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#define USBDP_TRSV_REG02A0_LN0_RX_SSLMS_MF_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A0_LN0_RX_SSLMS_MF_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A0_LN0_RX_SSLMS_MF_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A0_LN0_RX_SSLMS_MF_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A1 (0x0A84)
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#define USBDP_TRSV_REG02A1_LN0_RX_SSLMS_MF_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A1_LN0_RX_SSLMS_MF_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A1_LN0_RX_SSLMS_MF_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A1_LN0_RX_SSLMS_MF_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A2 (0x0A88)
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#define USBDP_TRSV_REG02A2_LN0_RX_SSLMS_MF_INIT_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A2_LN0_RX_SSLMS_MF_INIT_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A2_LN0_RX_SSLMS_MF_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A2_LN0_RX_SSLMS_MF_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A3 (0x0A8C)
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#define USBDP_TRSV_REG02A3_LN0_RX_SSLMS_VGA_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A3_LN0_RX_SSLMS_VGA_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A3_LN0_RX_SSLMS_VGA_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A3_LN0_RX_SSLMS_VGA_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A4 (0x0A90)
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#define USBDP_TRSV_REG02A4_LN0_RX_SSLMS_VGA_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A4_LN0_RX_SSLMS_VGA_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A4_LN0_RX_SSLMS_VGA_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A4_LN0_RX_SSLMS_VGA_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A5 (0x0A94)
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#define USBDP_TRSV_REG02A5_LN0_RX_SSLMS_VGA_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A5_LN0_RX_SSLMS_VGA_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A5_LN0_RX_SSLMS_VGA_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A5_LN0_RX_SSLMS_VGA_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A6 (0x0A98)
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#define USBDP_TRSV_REG02A6_LN0_RX_SSLMS_VGA_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A6_LN0_RX_SSLMS_VGA_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A6_LN0_RX_SSLMS_VGA_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A6_LN0_RX_SSLMS_VGA_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A7 (0x0A9C)
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#define USBDP_TRSV_REG02A7_LN0_RX_SSLMS_VGA_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02A7_LN0_RX_SSLMS_VGA_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02A7_LN0_RX_SSLMS_VGA_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02A7_LN0_RX_SSLMS_VGA_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02A8 (0x0AA0)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_VGA_INIT_HBR3_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_VGA_INIT_HBR3_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_VGA_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_VGA_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_C0_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_C0_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_C0_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02A8_LN0_RX_SSLMS_C0_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02A9 (0x0AA4)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C1_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C1_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C1_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C1_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C2_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C2_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C2_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02A9_LN0_RX_SSLMS_C2_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02AA (0x0AA8)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C3_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C3_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C3_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C3_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C4_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C4_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C4_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02AA_LN0_RX_SSLMS_C4_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02AB (0x0AAC)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_C5_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_C5_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_C5_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_C5_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_HF_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_HF_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_HF_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02AB_LN0_RX_SSLMS_HF_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02AC (0x0AB0)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_MF_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_MF_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_MF_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_MF_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_VGA_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_VGA_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_VGA_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02AC_LN0_RX_SSLMS_VGA_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02AD (0x0AB4)
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#define USBDP_TRSV_REG02AD_LN0_RX_SSLMS_VGA_REF_VALUE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02AD_LN0_RX_SSLMS_VGA_REF_VALUE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02AD_LN0_RX_SSLMS_VGA_REF_VALUE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02AD_LN0_RX_SSLMS_VGA_REF_VALUE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02AE (0x0AB8)
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#define USBDP_TRSV_REG02AE_LN0_RX_SSLMS_HF_START_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02AE_LN0_RX_SSLMS_HF_START_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02AE_LN0_RX_SSLMS_HF_START_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02AE_LN0_RX_SSLMS_HF_START_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02AF (0x0ABC)
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#define USBDP_TRSV_REG02AF_LN0_RX_SSLMS_HF_NUM_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02AF_LN0_RX_SSLMS_HF_NUM_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02AF_LN0_RX_SSLMS_HF_NUM_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02AF_LN0_RX_SSLMS_HF_NUM_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02B0 (0x0AC0)
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#define USBDP_TRSV_REG02B0_LN0_RX_SSLMS_MF_START_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02B0_LN0_RX_SSLMS_MF_START_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02B0_LN0_RX_SSLMS_MF_START_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02B0_LN0_RX_SSLMS_MF_START_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02B1 (0x0AC4)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_MF_NUM_CURSOR_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_MF_NUM_CURSOR_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_MF_NUM_CURSOR_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_MF_NUM_CURSOR_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_ADAP_EVENODD_SAME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_ADAP_EVENODD_SAME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_ADAP_EVENODD_SAME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02B1_LN0_RX_SSLMS_ADAP_EVENODD_SAME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02B2 (0x0AC8)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_SETTLE_CYCLE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_SETTLE_CYCLE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_SETTLE_CYCLE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_SETTLE_CYCLE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_HYSTERISIS_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_HYSTERISIS_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_HYSTERISIS_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_HYSTERISIS_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_ADAP_TOL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_ADAP_TOL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_ADAP_TOL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02B2_LN0_RX_SSLMS_ADAP_TOL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02B3 (0x0ACC)
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#define USBDP_TRSV_REG02B3_LN0_RX_SSLMS_ADAP_COEF_SEL__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02B3_LN0_RX_SSLMS_ADAP_COEF_SEL__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02B3_LN0_RX_SSLMS_ADAP_COEF_SEL__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02B3_LN0_RX_SSLMS_ADAP_COEF_SEL__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02B4 (0x0AD0)
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#define USBDP_TRSV_REG02B4_LN0_RX_SSLMS_ADAP_COEF_SEL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02B4_LN0_RX_SSLMS_ADAP_COEF_SEL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02B4_LN0_RX_SSLMS_ADAP_COEF_SEL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02B4_LN0_RX_SSLMS_ADAP_COEF_SEL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02B5 (0x0AD4)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_HOLD_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_HOLD_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02B5_LN0_OVRD_RX_SSLMS_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_HOLD_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_HOLD_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02B5_LN0_RX_SSLMS_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02B6 (0x0AD8)
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#define USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02B7 (0x0ADC)
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#define USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02B8 (0x0AE0)
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#define USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02B9 (0x0AE4)
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#define USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02BA (0x0AE8)
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#define USBDP_TRSV_REG02BA_LN0_RX_CDR_PMS_M_RBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02BA_LN0_RX_CDR_PMS_M_RBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02BA_LN0_RX_CDR_PMS_M_RBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02BA_LN0_RX_CDR_PMS_M_RBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02BB (0x0AEC)
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#define USBDP_TRSV_REG02BB_LN0_RX_CDR_PMS_M_RBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02BB_LN0_RX_CDR_PMS_M_RBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02BB_LN0_RX_CDR_PMS_M_RBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02BB_LN0_RX_CDR_PMS_M_RBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02BC (0x0AF0)
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#define USBDP_TRSV_REG02BC_LN0_RX_CDR_PMS_M_HBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02BC_LN0_RX_CDR_PMS_M_HBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02BC_LN0_RX_CDR_PMS_M_HBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02BC_LN0_RX_CDR_PMS_M_HBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02BD (0x0AF4)
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#define USBDP_TRSV_REG02BD_LN0_RX_CDR_PMS_M_HBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02BD_LN0_RX_CDR_PMS_M_HBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02BD_LN0_RX_CDR_PMS_M_HBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02BD_LN0_RX_CDR_PMS_M_HBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02BE (0x0AF8)
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#define USBDP_TRSV_REG02BE_LN0_RX_CDR_PMS_M_HBR2__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02BE_LN0_RX_CDR_PMS_M_HBR2__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02BE_LN0_RX_CDR_PMS_M_HBR2__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02BE_LN0_RX_CDR_PMS_M_HBR2__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02BF (0x0AFC)
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#define USBDP_TRSV_REG02BF_LN0_RX_CDR_PMS_M_HBR2__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02BF_LN0_RX_CDR_PMS_M_HBR2__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02BF_LN0_RX_CDR_PMS_M_HBR2__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02BF_LN0_RX_CDR_PMS_M_HBR2__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02C0 (0x0B00)
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#define USBDP_TRSV_REG02C0_LN0_RX_CDR_PMS_M_HBR3__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02C0_LN0_RX_CDR_PMS_M_HBR3__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02C0_LN0_RX_CDR_PMS_M_HBR3__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02C0_LN0_RX_CDR_PMS_M_HBR3__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02C1 (0x0B04)
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#define USBDP_TRSV_REG02C1_LN0_RX_CDR_PMS_M_HBR3__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02C1_LN0_RX_CDR_PMS_M_HBR3__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02C1_LN0_RX_CDR_PMS_M_HBR3__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02C1_LN0_RX_CDR_PMS_M_HBR3__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02C2 (0x0B08)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_RSTN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_RSTN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_RSTN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_RSTN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02C2_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_INIT_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_INIT_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_STB_NUM_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_STB_NUM_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG02C2_LN0_RX_CDR_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG02C3 (0x0B0C)
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#define USBDP_TRSV_REG02C3_LN0_RX_CDR_AFC_TOL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG02C3_LN0_RX_CDR_AFC_TOL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG02C3_LN0_RX_CDR_AFC_TOL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG02C3_LN0_RX_CDR_AFC_TOL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG02C4 (0x0B10)
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#define USBDP_TRSV_REG02C4_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02C4_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02C4_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02C4_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02C5 (0x0B14)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_VCO_CNT_WAIT_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_VCO_CNT_WAIT_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_VCO_CNT_WAIT_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_VCO_CNT_WAIT_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_FIX_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_FIX_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_FIX_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02C5_LN0_RX_CDR_AFC_FIX_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02C6 (0x0B18)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_MAN_BSEL_TIME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_MAN_BSEL_TIME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_MAN_BSEL_TIME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02C6_LN0_RX_CDR_AFC_MAN_BSEL_TIME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02C7 (0x0B1C)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_MAN_BSEL_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_MAN_BSEL_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_MAN_BSEL_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_MAN_BSEL_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_BSEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_BSEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02C7_LN0_RX_CDR_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02C8 (0x0B20)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02C8_LN0_RX_CDR_AFC_STEP_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02C9 (0x0B24)
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#define USBDP_TRSV_REG02C9_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02C9_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02C9_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02C9_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02CA (0x0B28)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_MAN_SEL_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_MAN_SEL_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_MAN_SEL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02CA_LN0_RX_CDR_FBB_MAN_SEL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02CB (0x0B2C)
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#define USBDP_TRSV_REG02CB_LN0_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02CB_LN0_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02CB_LN0_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02CB_LN0_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02CC (0x0B30)
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#define USBDP_TRSV_REG02CC_LN0_RX_CDR_FBB_DELTA_CNT_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02CC_LN0_RX_CDR_FBB_DELTA_CNT_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02CC_LN0_RX_CDR_FBB_DELTA_CNT_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02CC_LN0_RX_CDR_FBB_DELTA_CNT_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02CD (0x0B34)
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#define USBDP_TRSV_REG02CD_LN0_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02CD_LN0_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02CD_LN0_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02CD_LN0_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02CE (0x0B38)
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#define USBDP_TRSV_REG02CE_LN0_RX_CDR_FBB_COARSE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02CE_LN0_RX_CDR_FBB_COARSE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02CE_LN0_RX_CDR_FBB_COARSE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02CE_LN0_RX_CDR_FBB_COARSE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02CF (0x0B3C)
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#define USBDP_TRSV_REG02CF_LN0_RX_CDR_FBB_FINE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02CF_LN0_RX_CDR_FBB_FINE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02CF_LN0_RX_CDR_FBB_FINE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02CF_LN0_RX_CDR_FBB_FINE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02D0 (0x0B40)
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#define USBDP_TRSV_REG02D0_LN0_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02D0_LN0_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02D0_LN0_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02D0_LN0_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02D1 (0x0B44)
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#define USBDP_TRSV_REG02D1_LN0_RX_CDR_FBB_HI_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02D1_LN0_RX_CDR_FBB_HI_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02D1_LN0_RX_CDR_FBB_HI_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02D1_LN0_RX_CDR_FBB_HI_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02D2 (0x0B48)
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#define USBDP_TRSV_REG02D2_LN0_RX_CDR_FBB_LO_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02D2_LN0_RX_CDR_FBB_LO_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02D2_LN0_RX_CDR_FBB_LO_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02D2_LN0_RX_CDR_FBB_LO_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02D3 (0x0B4C)
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#define USBDP_TRSV_REG02D3_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02D3_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02D3_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02D3_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02D4 (0x0B50)
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#define USBDP_TRSV_REG02D4_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG02D4_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG02D4_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG02D4_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG02D5 (0x0B54)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_LOCK_PPM_SET_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_LOCK_PPM_SET_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_LOCK_PPM_SET_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_LOCK_PPM_SET_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_RESTART_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_RESTART_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_RESTART_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02D5_LN0_RX_CDR_PLL_MODE_RESTART_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02D6 (0x0B58)
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#define USBDP_TRSV_REG02D6_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02D6_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02D6_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02D6_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02D7 (0x0B5C)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_LOCK_SETTLE_NO_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_LOCK_SETTLE_NO_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_LOCK_SETTLE_NO_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02D7_LN0_RX_CDR_LOCK_SETTLE_NO_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02D8 (0x0B60)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CK_LOCK_PPM_SET_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CK_LOCK_PPM_SET_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CK_LOCK_PPM_SET_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CK_LOCK_PPM_SET_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG02D8_LN0_OVRD_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02D8_LN0_OVRD_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02D8_LN0_OVRD_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02D8_LN0_OVRD_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02D8_LN0_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02D9 (0x0B64)
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#define USBDP_TRSV_REG02D9_LN0_OVRD_RX_EFOM_FEEDBACK_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02D9_LN0_OVRD_RX_EFOM_FEEDBACK_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02D9_LN0_OVRD_RX_EFOM_FEEDBACK_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02D9_LN0_OVRD_RX_EFOM_FEEDBACK_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02DA (0x0B68)
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#define USBDP_TRSV_REG02DA_LN0_RX_EFOM_FEEDBACK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02DA_LN0_RX_EFOM_FEEDBACK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02DA_LN0_RX_EFOM_FEEDBACK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02DA_LN0_RX_EFOM_FEEDBACK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02DB (0x0B6C)
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#define USBDP_TRSV_REG02DB_LN0_RX_EFOM_FEEDBACK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02DB_LN0_RX_EFOM_FEEDBACK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02DB_LN0_RX_EFOM_FEEDBACK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02DB_LN0_RX_EFOM_FEEDBACK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02DC (0x0B70)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_MODE_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_MODE_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_MODE_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_MODE_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_START_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_START_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_START_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02DC_LN0_OVRD_RX_EFOM_START_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02DC_LN0_RX_EFOM_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02DD (0x0B74)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_VREF_RESOL_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_VREF_RESOL_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_VREF_RESOL_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_VREF_RESOL_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_START_SSM_DISABLE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_START_SSM_DISABLE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_START_SSM_DISABLE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_START_SSM_DISABLE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_H_WEIGHT_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_H_WEIGHT_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_H_WEIGHT_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_H_WEIGHT_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_V_WEIGHT_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_V_WEIGHT_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_V_WEIGHT_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02DD_LN0_RX_EFOM_V_WEIGHT_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02DE (0x0B78)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_SETTLE_TIME_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_SETTLE_TIME_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_SETTLE_TIME_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_SETTLE_TIME_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_BIT_WIDTH_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_BIT_WIDTH_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_BIT_WIDTH_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_BIT_WIDTH_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02DE_LN0_RX_EFOM_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02DF (0x0B7C)
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#define USBDP_TRSV_REG02DF_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG02DF_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG02DF_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG02DF_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG02E0 (0x0B80)
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#define USBDP_TRSV_REG02E0_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02E0_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02E0_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02E0_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02E1 (0x0B84)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_TRIAL_NUM_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_TRIAL_NUM_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_TRIAL_NUM_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_TRIAL_NUM_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_OUT_WIDTH_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_OUT_WIDTH_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_OUT_WIDTH_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02E1_LN0_RX_EFOM_OUT_WIDTH_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02E2 (0x0B88)
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#define USBDP_TRSV_REG02E2_LN0_RX_EFOM_DFE_VREF_CTRL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02E2_LN0_RX_EFOM_DFE_VREF_CTRL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02E2_LN0_RX_EFOM_DFE_VREF_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02E2_LN0_RX_EFOM_DFE_VREF_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02E3 (0x0B8C)
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#define USBDP_TRSV_REG02E3_LN0_RX_EFOM_ERROR_TH__9_8_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02E3_LN0_RX_EFOM_ERROR_TH__9_8_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02E3_LN0_RX_EFOM_ERROR_TH__9_8_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02E3_LN0_RX_EFOM_ERROR_TH__9_8_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02E4 (0x0B90)
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#define USBDP_TRSV_REG02E4_LN0_RX_EFOM_ERROR_TH__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02E4_LN0_RX_EFOM_ERROR_TH__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02E4_LN0_RX_EFOM_ERROR_TH__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02E4_LN0_RX_EFOM_ERROR_TH__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02E5 (0x0B94)
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#define USBDP_TRSV_REG02E5_LN0_RX_EFOM_EOM_PH_SEL_MSK USBDP_REG_MSK(1, 7)
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#define USBDP_TRSV_REG02E5_LN0_RX_EFOM_EOM_PH_SEL_CLR USBDP_REG_CLR(1, 7)
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#define USBDP_TRSV_REG02E5_LN0_RX_EFOM_EOM_PH_SEL_SET(_x) USBDP_REG_SET(_x, 1, 7)
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#define USBDP_TRSV_REG02E5_LN0_RX_EFOM_EOM_PH_SEL_GET(_R) USBDP_REG_GET(_R, 1, 7)
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#define USBDP_TRSV_REG02E5_LN0_RXD_ALIGN_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02E5_LN0_RXD_ALIGN_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02E5_LN0_RXD_ALIGN_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02E5_LN0_RXD_ALIGN_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02E6 (0x0B98)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_HOLD_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_HOLD_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_HOLD_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_HOLD_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_WORD_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_WORD_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_WORD_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_ALIGN_WORD_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_LOCK_NUM_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG02E6_LN0_RXD_LOCK_NUM_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG02E6_LN0_RXD_LOCK_NUM_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG02E6_LN0_RXD_LOCK_NUM_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BYTE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BYTE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BYTE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BYTE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BIT_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BIT_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BIT_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02E6_LN0_RXD_FLIP_BIT_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02E7 (0x0B9C)
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#define USBDP_TRSV_REG02E7_LN0_RXD_POLARITY_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02E7_LN0_RXD_POLARITY_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02E7_LN0_RXD_POLARITY_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02E7_LN0_RXD_POLARITY_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02E7_LN0_RX_SIGVAL_LPF_BYPASS_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02E7_LN0_RX_SIGVAL_LPF_BYPASS_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02E7_LN0_RX_SIGVAL_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02E7_LN0_RX_SIGVAL_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02E8 (0x0BA0)
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#define USBDP_TRSV_REG02E8_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02E8_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02E8_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02E8_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02E9 (0x0BA4)
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#define USBDP_TRSV_REG02E9_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02E9_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02E9_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02E9_LN0_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02EA (0x0BA8)
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#define USBDP_TRSV_REG02EA_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02EA_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02EA_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02EA_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02EB (0x0BAC)
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#define USBDP_TRSV_REG02EB_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02EB_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02EB_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02EB_LN0_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02EC (0x0BB0)
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#define USBDP_TRSV_REG02EC_LN0_RESERVED_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02EC_LN0_RESERVED_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02EC_LN0_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02EC_LN0_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02EC_LN0_OVRD_RX_RCAL_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02EC_LN0_OVRD_RX_RCAL_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02EC_LN0_OVRD_RX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02EC_LN0_OVRD_RX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02EC_LN0_RX_RCAL_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02ED (0x0BB4)
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#define USBDP_TRSV_REG02ED_LN0_RX_RTERM_CTRL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02ED_LN0_RX_RTERM_CTRL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02ED_LN0_RX_RTERM_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02ED_LN0_RX_RTERM_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02ED_LN0_OVRD_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02ED_LN0_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02EE (0x0BB8)
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#define USBDP_TRSV_REG02EE_LN0_OVRD_TX_RCAL_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02EE_LN0_OVRD_TX_RCAL_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02EE_LN0_OVRD_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02EE_LN0_OVRD_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_UP_OPT_CODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_UP_OPT_CODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_UP_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_UP_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_DN_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_DN_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_DN_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02EE_LN0_TX_RCAL_DN_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02EF (0x0BBC)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_UP_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_UP_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_UP_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_UP_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_DN_CODE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_DN_CODE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_DN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG02EF_LN0_TX_RCAL_DN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG02F0 (0x0BC0)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_DONE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_DONE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02F0_LN0_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02F0_LN0_LANE_MODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02F0_LN0_LANE_MODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02F0_LN0_LANE_MODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02F0_LN0_LANE_MODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_LANE_RATE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_LANE_RATE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_LANE_RATE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02F0_LN0_OVRD_LANE_RATE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02F0_LN0_LANE_RATE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02F0_LN0_LANE_RATE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02F0_LN0_LANE_RATE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02F0_LN0_LANE_RATE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02F1 (0x0BC4)
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#define USBDP_TRSV_REG02F1_LN0_LANE_TIMER_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02F1_LN0_LANE_TIMER_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02F1_LN0_LANE_TIMER_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02F1_LN0_LANE_TIMER_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_TX_CLK_SRC_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_TX_CLK_SRC_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_TX_CLK_SRC_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_TX_CLK_SRC_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_SRC_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_SRC_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_SRC_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_SRC_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_INV_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_INV_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_INV_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_CLK_INV_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02F1_LN0_OVRD_MISC_RX_SQHS_SIGVAL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02F1_LN0_OVRD_MISC_RX_SQHS_SIGVAL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02F1_LN0_OVRD_MISC_RX_SQHS_SIGVAL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02F1_LN0_OVRD_MISC_RX_SQHS_SIGVAL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_SQHS_SIGVAL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_SQHS_SIGVAL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_SQHS_SIGVAL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_SQHS_SIGVAL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_DATA_CLEAR_SRC_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_DATA_CLEAR_SRC_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_DATA_CLEAR_SRC_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02F1_LN0_MISC_RX_DATA_CLEAR_SRC_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02F2 (0x0BC8)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_LFPS_DET_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_LFPS_DET_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_LFPS_DET_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_LFPS_DET_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_TX_RXD_DETECTED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_TX_RXD_DETECTED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_TX_RXD_DETECTED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_TX_RXD_DETECTED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_TX_RXD_DETECTED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_TX_RXD_DETECTED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_TX_RXD_DETECTED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_TX_RXD_DETECTED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_VALID_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_VALID_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02F2_LN0_OVRD_MISC_RX_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_VALID_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_VALID_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02F2_LN0_MISC_RX_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02F3 (0x0BCC)
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#define USBDP_TRSV_REG02F3_LN0_LANE_RESERVED7_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG02F3_LN0_LANE_RESERVED7_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG02F3_LN0_LANE_RESERVED7_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG02F3_LN0_LANE_RESERVED7_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG02F3_LN0_TG_RCAL_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG02F3_LN0_TG_RCAL_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG02F3_LN0_TG_RCAL_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG02F3_LN0_TG_RCAL_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG02F3_LN0_RX_VALID_RSTN_DELAY_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02F3_LN0_RX_VALID_RSTN_DELAY_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02F3_LN0_RX_VALID_RSTN_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02F3_LN0_RX_VALID_RSTN_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02F4 (0x0BD0)
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#define USBDP_TRSV_REG02F4_LN0_RX_VALID_RSTN_DELAY_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG02F4_LN0_RX_VALID_RSTN_DELAY_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG02F4_LN0_RX_VALID_RSTN_DELAY_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG02F4_LN0_RX_VALID_RSTN_DELAY_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG02F4_LN0_TG_TX_DCC_EN_DELAY_TIME_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02F4_LN0_TG_TX_DCC_EN_DELAY_TIME_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02F4_LN0_TG_TX_DCC_EN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02F4_LN0_TG_TX_DCC_EN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG02F5 (0x0BD4)
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#define USBDP_TRSV_REG02F5_LN0_TG_SER_VREG_FAST_PULSE_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG02F5_LN0_TG_SER_VREG_FAST_PULSE_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG02F5_LN0_TG_SER_VREG_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG02F5_LN0_TG_SER_VREG_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG02F6 (0x0BD8)
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#define USBDP_TRSV_REG02F6_LN0_TX_LFPS_AFC_PMS_M__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02F6_LN0_TX_LFPS_AFC_PMS_M__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02F6_LN0_TX_LFPS_AFC_PMS_M__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02F6_LN0_TX_LFPS_AFC_PMS_M__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02F7 (0x0BDC)
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#define USBDP_TRSV_REG02F7_LN0_TX_LFPS_AFC_PMS_M__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG02F7_LN0_TX_LFPS_AFC_PMS_M__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG02F7_LN0_TX_LFPS_AFC_PMS_M__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG02F7_LN0_TX_LFPS_AFC_PMS_M__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG02F8 (0x0BE0)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_STB_NUM_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_STB_NUM_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_TOL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_TOL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_TOL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG02F8_LN0_TX_LFPS_AFC_TOL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG02F9 (0x0BE4)
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#define USBDP_TRSV_REG02F9_LN0_TX_LFPS_AFC_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG02F9_LN0_TX_LFPS_AFC_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG02F9_LN0_TX_LFPS_AFC_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG02F9_LN0_TX_LFPS_AFC_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG02FA (0x0BE8)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_VCO_CNT_WAIT_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_VCO_CNT_WAIT_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_VCO_CNT_WAIT_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_VCO_CNT_WAIT_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_FIX_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_FIX_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_FIX_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02FA_LN0_TX_LFPS_AFC_FIX_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02FB (0x0BEC)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_MAN_BSEL_TIME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_MAN_BSEL_TIME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_MAN_BSEL_TIME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02FB_LN0_TX_LFPS_AFC_MAN_BSEL_TIME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02FC (0x0BF0)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_MAN_BSEL_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_MAN_BSEL_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_MAN_BSEL_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_MAN_BSEL_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_BSEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_BSEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02FC_LN0_TX_LFPS_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02FD (0x0BF4)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG02FD_LN0_TX_LFPS_AFC_STEP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG02FD_LN0_OVRD_TXD_DESKEW_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG02FD_LN0_OVRD_TXD_DESKEW_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG02FD_LN0_OVRD_TXD_DESKEW_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG02FD_LN0_OVRD_TXD_DESKEW_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_BYPASS_ERR_CHK_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_BYPASS_ERR_CHK_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_BYPASS_ERR_CHK_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_BYPASS_ERR_CHK_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_FIX_DA_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_FIX_DA_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_FIX_DA_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02FD_LN0_TXD_DESKEW_FIX_DA_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02FE (0x0BF8)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_FIX_DB_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_FIX_DB_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_FIX_DB_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_FIX_DB_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DESKEW_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_CLK_TYPE_MAN_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_CLK_TYPE_MAN_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_CLK_TYPE_MAN_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_CLK_TYPE_MAN_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG02FE_LN0_TXD_CLK_TYPE_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_CLK_TYPE_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_CLK_TYPE_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_CLK_TYPE_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_TYPE_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_TYPE_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_TYPE_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG02FE_LN0_TXD_DATA_TYPE_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG02FE_LN0_RETIMEDLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG02FE_LN0_RETIMEDLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG02FE_LN0_RETIMEDLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG02FE_LN0_RETIMEDLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG02FF (0x0BFC)
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#define USBDP_TRSV_REG02FF_LN0_BIST_AUTO_RUN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG02FF_LN0_BIST_AUTO_RUN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG02FF_LN0_BIST_AUTO_RUN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG02FF_LN0_BIST_AUTO_RUN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG02FF_LN0_BIST_COMDET_NUM_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_COMDET_NUM_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_COMDET_NUM_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_COMDET_NUM_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_SEED_SEL_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG02FF_LN0_BIST_SEED_SEL_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG02FF_LN0_BIST_SEED_SEL_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG02FF_LN0_BIST_SEED_SEL_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG02FF_LN0_BIST_PRBS_MODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_PRBS_MODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_PRBS_MODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG02FF_LN0_BIST_PRBS_MODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0300 (0x0C00)
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#define USBDP_TRSV_REG0300_LN0_BIST_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_DATA_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_DATA_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_DATA_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_DATA_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_HOLD_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_HOLD_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_HOLD_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_HOLD_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_START_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_START_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_START_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_RX_START_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_ERRINJ_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_ERRINJ_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_ERRINJ_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_ERRINJ_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0300_LN0_BIST_TX_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0301 (0x0C04)
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#define USBDP_TRSV_REG0301_LN0_BIST_USER_PAT_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0301_LN0_BIST_USER_PAT_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0301_LN0_BIST_USER_PAT_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0301_LN0_BIST_USER_PAT_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0302 (0x0C08)
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#define USBDP_TRSV_REG0302_LN0_BIST_USER_PAT__79_72_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0302_LN0_BIST_USER_PAT__79_72_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0302_LN0_BIST_USER_PAT__79_72_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0302_LN0_BIST_USER_PAT__79_72_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0303 (0x0C0C)
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#define USBDP_TRSV_REG0303_LN0_BIST_USER_PAT__71_64_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0303_LN0_BIST_USER_PAT__71_64_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0303_LN0_BIST_USER_PAT__71_64_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0303_LN0_BIST_USER_PAT__71_64_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0304 (0x0C10)
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#define USBDP_TRSV_REG0304_LN0_BIST_USER_PAT__63_56_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0304_LN0_BIST_USER_PAT__63_56_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0304_LN0_BIST_USER_PAT__63_56_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0304_LN0_BIST_USER_PAT__63_56_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0305 (0x0C14)
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#define USBDP_TRSV_REG0305_LN0_BIST_USER_PAT__55_48_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0305_LN0_BIST_USER_PAT__55_48_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0305_LN0_BIST_USER_PAT__55_48_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0305_LN0_BIST_USER_PAT__55_48_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0306 (0x0C18)
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#define USBDP_TRSV_REG0306_LN0_BIST_USER_PAT__47_40_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0306_LN0_BIST_USER_PAT__47_40_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0306_LN0_BIST_USER_PAT__47_40_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0306_LN0_BIST_USER_PAT__47_40_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0307 (0x0C1C)
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#define USBDP_TRSV_REG0307_LN0_BIST_USER_PAT__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0307_LN0_BIST_USER_PAT__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0307_LN0_BIST_USER_PAT__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0307_LN0_BIST_USER_PAT__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0308 (0x0C20)
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#define USBDP_TRSV_REG0308_LN0_BIST_USER_PAT__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0308_LN0_BIST_USER_PAT__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0308_LN0_BIST_USER_PAT__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0308_LN0_BIST_USER_PAT__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0309 (0x0C24)
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#define USBDP_TRSV_REG0309_LN0_BIST_USER_PAT__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0309_LN0_BIST_USER_PAT__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0309_LN0_BIST_USER_PAT__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0309_LN0_BIST_USER_PAT__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG030A (0x0C28)
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#define USBDP_TRSV_REG030A_LN0_BIST_USER_PAT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG030A_LN0_BIST_USER_PAT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG030A_LN0_BIST_USER_PAT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG030A_LN0_BIST_USER_PAT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG030B (0x0C2C)
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#define USBDP_TRSV_REG030B_LN0_BIST_USER_PAT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG030B_LN0_BIST_USER_PAT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG030B_LN0_BIST_USER_PAT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG030B_LN0_BIST_USER_PAT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG030C (0x0C30)
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#define USBDP_TRSV_REG030C_LN0_RATE_CHANGE_DELAY_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG030C_LN0_RATE_CHANGE_DELAY_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG030C_LN0_RATE_CHANGE_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG030C_LN0_RATE_CHANGE_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG030D (0x0C34)
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#define USBDP_TRSV_REG030D_LN0_LANE_DTB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG030D_LN0_LANE_DTB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG030D_LN0_LANE_DTB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG030D_LN0_LANE_DTB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG030E (0x0C38)
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#define USBDP_TRSV_REG030E_LN0_RX_SSLMS_DFE_ADAP_DONE_WIDTH_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG030E_LN0_RX_SSLMS_DFE_ADAP_DONE_WIDTH_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG030E_LN0_RX_SSLMS_DFE_ADAP_DONE_WIDTH_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG030E_LN0_RX_SSLMS_DFE_ADAP_DONE_WIDTH_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG030F (0x0C3C)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_BLOCK_ADAP_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_BLOCK_ADAP_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_BLOCK_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG030F_LN0_RX_SSLMS_BLOCK_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0310 (0x0C40)
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#define USBDP_TRSV_REG0310_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0310_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0310_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0310_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0311 (0x0C44)
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#define USBDP_TRSV_REG0311_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0311_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0311_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0311_LN0_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0312 (0x0C48)
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#define USBDP_TRSV_REG0312_LN0_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0312_LN0_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0312_LN0_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0312_LN0_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0313 (0x0C4C)
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#define USBDP_TRSV_REG0313_LN0_RX_SSLMS_DFE_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0313_LN0_RX_SSLMS_DFE_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0313_LN0_RX_SSLMS_DFE_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0313_LN0_RX_SSLMS_DFE_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0314 (0x0C50)
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#define USBDP_TRSV_REG0314_LN0_RX_SSLMS_HF_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0314_LN0_RX_SSLMS_HF_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0314_LN0_RX_SSLMS_HF_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0314_LN0_RX_SSLMS_HF_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0315 (0x0C54)
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#define USBDP_TRSV_REG0315_LN0_RX_SSLMS_MF_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0315_LN0_RX_SSLMS_MF_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0315_LN0_RX_SSLMS_MF_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0315_LN0_RX_SSLMS_MF_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0316 (0x0C58)
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#define USBDP_TRSV_REG0316_LN0_RX_SSLMS_VGA_LOCK_TH_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG0316_LN0_RX_SSLMS_VGA_LOCK_TH_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG0316_LN0_RX_SSLMS_VGA_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG0316_LN0_RX_SSLMS_VGA_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_EIEN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_EIEN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_EIEN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_EIEN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_LFPS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_LFPS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_LFPS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0316_LN0_TXD_DESKEW_BYPASS_LFPS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0317 (0x0C5C)
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#define USBDP_TRSV_REG0317_LN0_TXD_DESKEW_BYPASS_DRV_LVL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0317_LN0_TXD_DESKEW_BYPASS_DRV_LVL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0317_LN0_TXD_DESKEW_BYPASS_DRV_LVL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0317_LN0_TXD_DESKEW_BYPASS_DRV_LVL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0317_LN0_ANA_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0317_LN0_ANA_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0317_LN0_ANA_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0317_LN0_ANA_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0318 (0x0C60)
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#define USBDP_TRSV_REG0318_LN0_ANA_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0318_LN0_ANA_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0318_LN0_ANA_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0318_LN0_ANA_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0319 (0x0C64)
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#define USBDP_TRSV_REG0319_LN0_ANA_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0319_LN0_ANA_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0319_LN0_ANA_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0319_LN0_ANA_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG031A (0x0C68)
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#define USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG031B (0x0C6C)
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#define USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG031C (0x0C70)
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#define USBDP_TRSV_REG031C_LN0_TG_RXD_STATUS_DELAY_TIME_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG031C_LN0_TG_RXD_STATUS_DELAY_TIME_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG031C_LN0_TG_RXD_STATUS_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG031C_LN0_TG_RXD_STATUS_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG031C_LN0_RX_SSLMS_ADAP_HOLD_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_SSLMS_ADAP_HOLD_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_SSLMS_ADAP_HOLD_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_SSLMS_ADAP_HOLD_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG031C_LN0_OVRD_RX_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG031C_LN0_OVRD_RX_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG031C_LN0_OVRD_RX_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG031C_LN0_OVRD_RX_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_OC_CAL_DATA_INV_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_OC_CAL_DATA_INV_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_OC_CAL_DATA_INV_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG031C_LN0_RX_OC_CAL_DATA_INV_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG031D (0x0C74)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_NON_DATA_INV_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_NON_DATA_INV_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_NON_DATA_INV_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_NON_DATA_INV_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_DATA_MASK_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_DATA_MASK_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_DATA_MASK_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_CAL_DATA_MASK_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG031D_LN0_CDR_LOCK_DELAY_BYPASS_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG031D_LN0_CDR_LOCK_DELAY_BYPASS_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG031D_LN0_CDR_LOCK_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG031D_LN0_CDR_LOCK_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_DONE_DELAY_BYPASS_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_DONE_DELAY_BYPASS_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_DONE_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG031D_LN0_RX_OC_DONE_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG031D_LN0_ANA_RX_CDR_EN_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG031D_LN0_ANA_RX_CDR_EN_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG031D_LN0_ANA_RX_CDR_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG031D_LN0_ANA_RX_CDR_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG031E (0x0C78)
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#define USBDP_TRSV_REG031E_LN0_ANA_RX_DES_EN_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG031E_LN0_ANA_RX_DES_EN_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG031E_LN0_ANA_RX_DES_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG031E_LN0_ANA_RX_DES_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG031F (0x0C7C)
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#define USBDP_TRSV_REG031F_LN0_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG031F_LN0_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG031F_LN0_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG031F_LN0_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0320 (0x0C80)
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#define USBDP_TRSV_REG0320_LN0_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0320_LN0_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0320_LN0_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0320_LN0_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0321 (0x0C84)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_MODE_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_MODE_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_MODE_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_MODE_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0321_LN0_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0322 (0x0C88)
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#define USBDP_TRSV_REG0322_LN0_RX_SIGVAL_DIGITAL_VALID_COUNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0322_LN0_RX_SIGVAL_DIGITAL_VALID_COUNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0322_LN0_RX_SIGVAL_DIGITAL_VALID_COUNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0322_LN0_RX_SIGVAL_DIGITAL_VALID_COUNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0323 (0x0C8C)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_EN_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_EN_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0323_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0324 (0x0C90)
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#define USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0325 (0x0C94)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_EN_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_EN_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0325_LN0_RX_CDR_DATA_MODE_EXIT_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0326 (0x0C98)
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#define USBDP_TRSV_REG0326_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0326_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0326_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0326_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0327 (0x0C9C)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0327_LN0_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0327_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0327_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0327_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0327_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0328 (0x0CA0)
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#define USBDP_TRSV_REG0328_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0328_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0328_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0328_LN0_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_FBB_CAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_FBB_CAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_FBB_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0328_LN0_OVRD_RX_CDR_FBB_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_FBB_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_FBB_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_FBB_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0328_LN0_RX_CDR_FBB_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0329 (0x0CA4)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_CK_MODE_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_CK_MODE_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_CK_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0329_LN0_OVRD_RX_CDR_FLD_CK_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_CK_MODE_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_CK_MODE_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_CK_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0329_LN0_RX_CDR_FLD_CK_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG032A (0x0CA8)
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#define USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG032B (0x0CAC)
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#define USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG032C (0x0CB0)
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#define USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG032D (0x0CB4)
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#define USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG032E (0x0CB8)
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#define USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG032F (0x0CBC)
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#define USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0330 (0x0CC0)
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#define USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0331 (0x0CC4)
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#define USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0332 (0x0CC8)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_ERR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_ERR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_ERR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_ERR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_EDGE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_EDGE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_EDGE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0332_LN0_RX_OC_DFE_ADAP_EN_EDGE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0333 (0x0CCC)
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#define USBDP_TRSV_REG0333_LN0_RX_SSLMS_C0_E_INIT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0333_LN0_RX_SSLMS_C0_E_INIT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0333_LN0_RX_SSLMS_C0_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0333_LN0_RX_SSLMS_C0_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0334 (0x0CD0)
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#define USBDP_TRSV_REG0334_LN0_RX_SSLMS_C1_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0334_LN0_RX_SSLMS_C1_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0334_LN0_RX_SSLMS_C1_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0334_LN0_RX_SSLMS_C1_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0335 (0x0CD4)
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#define USBDP_TRSV_REG0335_LN0_RX_SSLMS_C2_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0335_LN0_RX_SSLMS_C2_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0335_LN0_RX_SSLMS_C2_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0335_LN0_RX_SSLMS_C2_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0336 (0x0CD8)
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#define USBDP_TRSV_REG0336_LN0_RX_SSLMS_C3_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0336_LN0_RX_SSLMS_C3_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0336_LN0_RX_SSLMS_C3_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0336_LN0_RX_SSLMS_C3_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0337 (0x0CDC)
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#define USBDP_TRSV_REG0337_LN0_RX_SSLMS_C4_E_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0337_LN0_RX_SSLMS_C4_E_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0337_LN0_RX_SSLMS_C4_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0337_LN0_RX_SSLMS_C4_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0338 (0x0CE0)
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#define USBDP_TRSV_REG0338_LN0_RX_SSLMS_C5_E_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0338_LN0_RX_SSLMS_C5_E_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0338_LN0_RX_SSLMS_C5_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0338_LN0_RX_SSLMS_C5_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0339 (0x0CE4)
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#define USBDP_TRSV_REG0339_LN0_RX_SSLMS_C0_E_INIT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0339_LN0_RX_SSLMS_C0_E_INIT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0339_LN0_RX_SSLMS_C0_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0339_LN0_RX_SSLMS_C0_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG033A (0x0CE8)
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#define USBDP_TRSV_REG033A_LN0_RX_SSLMS_C1_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG033A_LN0_RX_SSLMS_C1_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG033A_LN0_RX_SSLMS_C1_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG033A_LN0_RX_SSLMS_C1_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG033B (0x0CEC)
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#define USBDP_TRSV_REG033B_LN0_RX_SSLMS_C2_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG033B_LN0_RX_SSLMS_C2_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG033B_LN0_RX_SSLMS_C2_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG033B_LN0_RX_SSLMS_C2_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG033C (0x0CF0)
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#define USBDP_TRSV_REG033C_LN0_RX_SSLMS_C3_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG033C_LN0_RX_SSLMS_C3_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG033C_LN0_RX_SSLMS_C3_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG033C_LN0_RX_SSLMS_C3_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG033D (0x0CF4)
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#define USBDP_TRSV_REG033D_LN0_RX_SSLMS_C4_E_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG033D_LN0_RX_SSLMS_C4_E_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG033D_LN0_RX_SSLMS_C4_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG033D_LN0_RX_SSLMS_C4_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG033E (0x0CF8)
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#define USBDP_TRSV_REG033E_LN0_RX_SSLMS_C5_E_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG033E_LN0_RX_SSLMS_C5_E_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG033E_LN0_RX_SSLMS_C5_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG033E_LN0_RX_SSLMS_C5_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG033F (0x0CFC)
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#define USBDP_TRSV_REG033F_LN0_RX_SSLMS_C0_O_INIT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG033F_LN0_RX_SSLMS_C0_O_INIT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG033F_LN0_RX_SSLMS_C0_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG033F_LN0_RX_SSLMS_C0_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0340 (0x0D00)
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#define USBDP_TRSV_REG0340_LN0_RX_SSLMS_C1_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0340_LN0_RX_SSLMS_C1_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0340_LN0_RX_SSLMS_C1_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0340_LN0_RX_SSLMS_C1_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0341 (0x0D04)
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#define USBDP_TRSV_REG0341_LN0_RX_SSLMS_C2_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0341_LN0_RX_SSLMS_C2_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0341_LN0_RX_SSLMS_C2_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0341_LN0_RX_SSLMS_C2_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0342 (0x0D08)
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#define USBDP_TRSV_REG0342_LN0_RX_SSLMS_C3_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0342_LN0_RX_SSLMS_C3_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0342_LN0_RX_SSLMS_C3_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0342_LN0_RX_SSLMS_C3_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0343 (0x0D0C)
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#define USBDP_TRSV_REG0343_LN0_RX_SSLMS_C4_O_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0343_LN0_RX_SSLMS_C4_O_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0343_LN0_RX_SSLMS_C4_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0343_LN0_RX_SSLMS_C4_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0344 (0x0D10)
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#define USBDP_TRSV_REG0344_LN0_RX_SSLMS_C5_O_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0344_LN0_RX_SSLMS_C5_O_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0344_LN0_RX_SSLMS_C5_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0344_LN0_RX_SSLMS_C5_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0345 (0x0D14)
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#define USBDP_TRSV_REG0345_LN0_RX_SSLMS_C0_O_INIT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0345_LN0_RX_SSLMS_C0_O_INIT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0345_LN0_RX_SSLMS_C0_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0345_LN0_RX_SSLMS_C0_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0346 (0x0D18)
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#define USBDP_TRSV_REG0346_LN0_RX_SSLMS_C1_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0346_LN0_RX_SSLMS_C1_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0346_LN0_RX_SSLMS_C1_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0346_LN0_RX_SSLMS_C1_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0347 (0x0D1C)
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#define USBDP_TRSV_REG0347_LN0_RX_SSLMS_C2_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0347_LN0_RX_SSLMS_C2_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0347_LN0_RX_SSLMS_C2_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0347_LN0_RX_SSLMS_C2_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0348 (0x0D20)
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#define USBDP_TRSV_REG0348_LN0_RX_SSLMS_C3_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0348_LN0_RX_SSLMS_C3_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0348_LN0_RX_SSLMS_C3_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0348_LN0_RX_SSLMS_C3_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0349 (0x0D24)
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#define USBDP_TRSV_REG0349_LN0_RX_SSLMS_C4_O_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0349_LN0_RX_SSLMS_C4_O_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0349_LN0_RX_SSLMS_C4_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0349_LN0_RX_SSLMS_C4_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG034A (0x0D28)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_C5_O_INIT_SSP_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_C5_O_INIT_SSP_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_C5_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_C5_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG034A_LN0_OVRD_RX_SSLMS_ADAP_DONE_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG034A_LN0_OVRD_RX_SSLMS_ADAP_DONE_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG034A_LN0_OVRD_RX_SSLMS_ADAP_DONE_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG034A_LN0_OVRD_RX_SSLMS_ADAP_DONE_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_ADAP_DONE_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_ADAP_DONE_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_ADAP_DONE_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG034A_LN0_RX_SSLMS_ADAP_DONE_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG034B (0x0D2C)
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#define USBDP_TRSV_REG034B_LN0_OVRD_RX_SSLMS_TRIG_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG034B_LN0_OVRD_RX_SSLMS_TRIG_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG034B_LN0_OVRD_RX_SSLMS_TRIG_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG034B_LN0_OVRD_RX_SSLMS_TRIG_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG034B_LN0_RX_SSLMS_TRIG_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG034B_LN0_RX_SSLMS_TRIG_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG034B_LN0_RX_SSLMS_TRIG_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG034B_LN0_RX_SSLMS_TRIG_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG034C (0x0D30)
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#define USBDP_TRSV_REG034C_LN0_OVRD_RX_SSLMS_C0_E_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG034C_LN0_OVRD_RX_SSLMS_C0_E_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG034C_LN0_OVRD_RX_SSLMS_C0_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG034C_LN0_OVRD_RX_SSLMS_C0_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG034D (0x0D34)
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#define USBDP_TRSV_REG034D_LN0_RX_SSLMS_C0_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG034D_LN0_RX_SSLMS_C0_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG034D_LN0_RX_SSLMS_C0_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG034D_LN0_RX_SSLMS_C0_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG034E (0x0D38)
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#define USBDP_TRSV_REG034E_LN0_OVRD_RX_SSLMS_C1_E_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG034E_LN0_OVRD_RX_SSLMS_C1_E_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG034E_LN0_OVRD_RX_SSLMS_C1_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG034E_LN0_OVRD_RX_SSLMS_C1_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG034F (0x0D3C)
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#define USBDP_TRSV_REG034F_LN0_RX_SSLMS_C1_E_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG034F_LN0_RX_SSLMS_C1_E_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG034F_LN0_RX_SSLMS_C1_E_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG034F_LN0_RX_SSLMS_C1_E_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0350 (0x0D40)
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#define USBDP_TRSV_REG0350_LN0_RX_SSLMS_C1_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0350_LN0_RX_SSLMS_C1_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0350_LN0_RX_SSLMS_C1_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0350_LN0_RX_SSLMS_C1_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0351 (0x0D44)
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#define USBDP_TRSV_REG0351_LN0_OVRD_RX_SSLMS_C2_E_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0351_LN0_OVRD_RX_SSLMS_C2_E_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0351_LN0_OVRD_RX_SSLMS_C2_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0351_LN0_OVRD_RX_SSLMS_C2_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0351_LN0_RX_SSLMS_C2_E_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0351_LN0_RX_SSLMS_C2_E_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0351_LN0_RX_SSLMS_C2_E_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0351_LN0_RX_SSLMS_C2_E_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0352 (0x0D48)
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#define USBDP_TRSV_REG0352_LN0_RX_SSLMS_C2_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0352_LN0_RX_SSLMS_C2_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0352_LN0_RX_SSLMS_C2_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0352_LN0_RX_SSLMS_C2_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0353 (0x0D4C)
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#define USBDP_TRSV_REG0353_LN0_OVRD_RX_SSLMS_C3_E_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0353_LN0_OVRD_RX_SSLMS_C3_E_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0353_LN0_OVRD_RX_SSLMS_C3_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0353_LN0_OVRD_RX_SSLMS_C3_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0353_LN0_RX_SSLMS_C3_E_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0353_LN0_RX_SSLMS_C3_E_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0353_LN0_RX_SSLMS_C3_E_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0353_LN0_RX_SSLMS_C3_E_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0354 (0x0D50)
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#define USBDP_TRSV_REG0354_LN0_RX_SSLMS_C3_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0354_LN0_RX_SSLMS_C3_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0354_LN0_RX_SSLMS_C3_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0354_LN0_RX_SSLMS_C3_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0355 (0x0D54)
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#define USBDP_TRSV_REG0355_LN0_OVRD_RX_SSLMS_C4_E_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0355_LN0_OVRD_RX_SSLMS_C4_E_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0355_LN0_OVRD_RX_SSLMS_C4_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0355_LN0_OVRD_RX_SSLMS_C4_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0355_LN0_RX_SSLMS_C4_E_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0355_LN0_RX_SSLMS_C4_E_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0355_LN0_RX_SSLMS_C4_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0355_LN0_RX_SSLMS_C4_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0356 (0x0D58)
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#define USBDP_TRSV_REG0356_LN0_OVRD_RX_SSLMS_C5_E_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0356_LN0_OVRD_RX_SSLMS_C5_E_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0356_LN0_OVRD_RX_SSLMS_C5_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0356_LN0_OVRD_RX_SSLMS_C5_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0356_LN0_RX_SSLMS_C5_E_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0356_LN0_RX_SSLMS_C5_E_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0356_LN0_RX_SSLMS_C5_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0356_LN0_RX_SSLMS_C5_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0357 (0x0D5C)
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#define USBDP_TRSV_REG0357_LN0_OVRD_RX_SSLMS_C0_O_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0357_LN0_OVRD_RX_SSLMS_C0_O_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0357_LN0_OVRD_RX_SSLMS_C0_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0357_LN0_OVRD_RX_SSLMS_C0_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0358 (0x0D60)
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#define USBDP_TRSV_REG0358_LN0_RX_SSLMS_C0_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0358_LN0_RX_SSLMS_C0_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0358_LN0_RX_SSLMS_C0_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0358_LN0_RX_SSLMS_C0_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0359 (0x0D64)
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#define USBDP_TRSV_REG0359_LN0_OVRD_RX_SSLMS_C1_O_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0359_LN0_OVRD_RX_SSLMS_C1_O_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0359_LN0_OVRD_RX_SSLMS_C1_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0359_LN0_OVRD_RX_SSLMS_C1_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG035A (0x0D68)
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#define USBDP_TRSV_REG035A_LN0_RX_SSLMS_C1_O_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG035A_LN0_RX_SSLMS_C1_O_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG035A_LN0_RX_SSLMS_C1_O_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG035A_LN0_RX_SSLMS_C1_O_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG035B (0x0D6C)
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#define USBDP_TRSV_REG035B_LN0_RX_SSLMS_C1_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG035B_LN0_RX_SSLMS_C1_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG035B_LN0_RX_SSLMS_C1_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG035B_LN0_RX_SSLMS_C1_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG035C (0x0D70)
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#define USBDP_TRSV_REG035C_LN0_OVRD_RX_SSLMS_C2_O_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG035C_LN0_OVRD_RX_SSLMS_C2_O_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG035C_LN0_OVRD_RX_SSLMS_C2_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG035C_LN0_OVRD_RX_SSLMS_C2_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG035C_LN0_RX_SSLMS_C2_O_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG035C_LN0_RX_SSLMS_C2_O_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG035C_LN0_RX_SSLMS_C2_O_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG035C_LN0_RX_SSLMS_C2_O_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG035D (0x0D74)
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#define USBDP_TRSV_REG035D_LN0_RX_SSLMS_C2_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG035D_LN0_RX_SSLMS_C2_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG035D_LN0_RX_SSLMS_C2_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG035D_LN0_RX_SSLMS_C2_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG035E (0x0D78)
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#define USBDP_TRSV_REG035E_LN0_OVRD_RX_SSLMS_C3_O_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG035E_LN0_OVRD_RX_SSLMS_C3_O_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG035E_LN0_OVRD_RX_SSLMS_C3_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG035E_LN0_OVRD_RX_SSLMS_C3_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG035E_LN0_RX_SSLMS_C3_O_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG035E_LN0_RX_SSLMS_C3_O_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG035E_LN0_RX_SSLMS_C3_O_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG035E_LN0_RX_SSLMS_C3_O_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG035F (0x0D7C)
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#define USBDP_TRSV_REG035F_LN0_RX_SSLMS_C3_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG035F_LN0_RX_SSLMS_C3_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG035F_LN0_RX_SSLMS_C3_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG035F_LN0_RX_SSLMS_C3_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0360 (0x0D80)
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#define USBDP_TRSV_REG0360_LN0_OVRD_RX_SSLMS_C4_O_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0360_LN0_OVRD_RX_SSLMS_C4_O_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0360_LN0_OVRD_RX_SSLMS_C4_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0360_LN0_OVRD_RX_SSLMS_C4_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0360_LN0_RX_SSLMS_C4_O_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0360_LN0_RX_SSLMS_C4_O_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0360_LN0_RX_SSLMS_C4_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0360_LN0_RX_SSLMS_C4_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0361 (0x0D84)
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#define USBDP_TRSV_REG0361_LN0_OVRD_RX_SSLMS_C5_O_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0361_LN0_OVRD_RX_SSLMS_C5_O_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0361_LN0_OVRD_RX_SSLMS_C5_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0361_LN0_OVRD_RX_SSLMS_C5_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0361_LN0_RX_SSLMS_C5_O_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0361_LN0_RX_SSLMS_C5_O_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0361_LN0_RX_SSLMS_C5_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0361_LN0_RX_SSLMS_C5_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0362 (0x0D88)
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#define USBDP_TRSV_REG0362_LN0_OVRD_RX_SSLMS_HF_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0362_LN0_OVRD_RX_SSLMS_HF_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0362_LN0_OVRD_RX_SSLMS_HF_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0362_LN0_OVRD_RX_SSLMS_HF_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0363 (0x0D8C)
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#define USBDP_TRSV_REG0363_LN0_RX_SSLMS_HF_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0363_LN0_RX_SSLMS_HF_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0363_LN0_RX_SSLMS_HF_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0363_LN0_RX_SSLMS_HF_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0364 (0x0D90)
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#define USBDP_TRSV_REG0364_LN0_RX_SSLMS_HF_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0364_LN0_RX_SSLMS_HF_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0364_LN0_RX_SSLMS_HF_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0364_LN0_RX_SSLMS_HF_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0365 (0x0D94)
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#define USBDP_TRSV_REG0365_LN0_OVRD_RX_SSLMS_MF_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0365_LN0_OVRD_RX_SSLMS_MF_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0365_LN0_OVRD_RX_SSLMS_MF_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0365_LN0_OVRD_RX_SSLMS_MF_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0366 (0x0D98)
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#define USBDP_TRSV_REG0366_LN0_RX_SSLMS_MF_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0366_LN0_RX_SSLMS_MF_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0366_LN0_RX_SSLMS_MF_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0366_LN0_RX_SSLMS_MF_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0367 (0x0D9C)
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#define USBDP_TRSV_REG0367_LN0_RX_SSLMS_MF_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0367_LN0_RX_SSLMS_MF_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0367_LN0_RX_SSLMS_MF_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0367_LN0_RX_SSLMS_MF_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0368 (0x0DA0)
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#define USBDP_TRSV_REG0368_LN0_OVRD_RX_SSLMS_VGA_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0368_LN0_OVRD_RX_SSLMS_VGA_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0368_LN0_OVRD_RX_SSLMS_VGA_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0368_LN0_OVRD_RX_SSLMS_VGA_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0369 (0x0DA4)
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#define USBDP_TRSV_REG0369_LN0_RX_SSLMS_VGA_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0369_LN0_RX_SSLMS_VGA_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0369_LN0_RX_SSLMS_VGA_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0369_LN0_RX_SSLMS_VGA_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG036A (0x0DA8)
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#define USBDP_TRSV_REG036A_LN0_RX_SSLMS_VGA_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG036A_LN0_RX_SSLMS_VGA_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG036A_LN0_RX_SSLMS_VGA_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG036A_LN0_RX_SSLMS_VGA_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG036B (0x0DAC)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_DONE_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_DONE_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_DONE_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_DONE_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_DONE_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_DONE_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_DONE_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_DONE_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_TRIG_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_TRIG_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_TRIG_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_TRIG_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_TRIG_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_TRIG_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_TRIG_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_TRIG_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SP_RESERVED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SP_RESERVED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG036B_LN0_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SSP_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SSP_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG036B_LN0_RX_SSLMS_ADAP_EN_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG036C (0x0DB0)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SP_RESERVED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SP_RESERVED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG036C_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG036C_LN0_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG036D (0x0DB4)
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#define USBDP_TRSV_REG036D_LN0_OVRD_RX_SSLMS_C0_E_BIN_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG036D_LN0_OVRD_RX_SSLMS_C0_E_BIN_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG036D_LN0_OVRD_RX_SSLMS_C0_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG036D_LN0_OVRD_RX_SSLMS_C0_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG036E (0x0DB8)
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#define USBDP_TRSV_REG036E_LN0_RX_SSLMS_C0_E_BIN_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG036E_LN0_RX_SSLMS_C0_E_BIN_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG036E_LN0_RX_SSLMS_C0_E_BIN_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG036E_LN0_RX_SSLMS_C0_E_BIN_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG036F (0x0DBC)
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#define USBDP_TRSV_REG036F_LN0_OVRD_RX_SSLMS_C1_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG036F_LN0_OVRD_RX_SSLMS_C1_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG036F_LN0_OVRD_RX_SSLMS_C1_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG036F_LN0_OVRD_RX_SSLMS_C1_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG036F_LN0_RX_SSLMS_C1_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG036F_LN0_RX_SSLMS_C1_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG036F_LN0_RX_SSLMS_C1_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG036F_LN0_RX_SSLMS_C1_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0370 (0x0DC0)
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#define USBDP_TRSV_REG0370_LN0_OVRD_RX_SSLMS_C2_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0370_LN0_OVRD_RX_SSLMS_C2_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0370_LN0_OVRD_RX_SSLMS_C2_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0370_LN0_OVRD_RX_SSLMS_C2_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0370_LN0_RX_SSLMS_C2_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0370_LN0_RX_SSLMS_C2_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0370_LN0_RX_SSLMS_C2_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0370_LN0_RX_SSLMS_C2_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0371 (0x0DC4)
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#define USBDP_TRSV_REG0371_LN0_OVRD_RX_SSLMS_C3_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0371_LN0_OVRD_RX_SSLMS_C3_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0371_LN0_OVRD_RX_SSLMS_C3_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0371_LN0_OVRD_RX_SSLMS_C3_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0371_LN0_RX_SSLMS_C3_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0371_LN0_RX_SSLMS_C3_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0371_LN0_RX_SSLMS_C3_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0371_LN0_RX_SSLMS_C3_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0372 (0x0DC8)
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#define USBDP_TRSV_REG0372_LN0_OVRD_RX_SSLMS_C4_E_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0372_LN0_OVRD_RX_SSLMS_C4_E_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0372_LN0_OVRD_RX_SSLMS_C4_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0372_LN0_OVRD_RX_SSLMS_C4_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0372_LN0_RX_SSLMS_C4_E_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0372_LN0_RX_SSLMS_C4_E_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0372_LN0_RX_SSLMS_C4_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0372_LN0_RX_SSLMS_C4_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0373 (0x0DCC)
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#define USBDP_TRSV_REG0373_LN0_OVRD_RX_SSLMS_C5_E_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0373_LN0_OVRD_RX_SSLMS_C5_E_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0373_LN0_OVRD_RX_SSLMS_C5_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0373_LN0_OVRD_RX_SSLMS_C5_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0373_LN0_RX_SSLMS_C5_E_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0373_LN0_RX_SSLMS_C5_E_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0373_LN0_RX_SSLMS_C5_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0373_LN0_RX_SSLMS_C5_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0374 (0x0DD0)
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#define USBDP_TRSV_REG0374_LN0_OVRD_RX_SSLMS_C0_O_BIN_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0374_LN0_OVRD_RX_SSLMS_C0_O_BIN_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0374_LN0_OVRD_RX_SSLMS_C0_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0374_LN0_OVRD_RX_SSLMS_C0_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0375 (0x0DD4)
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#define USBDP_TRSV_REG0375_LN0_RX_SSLMS_C0_O_BIN_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0375_LN0_RX_SSLMS_C0_O_BIN_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0375_LN0_RX_SSLMS_C0_O_BIN_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0375_LN0_RX_SSLMS_C0_O_BIN_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0376 (0x0DD8)
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#define USBDP_TRSV_REG0376_LN0_OVRD_RX_SSLMS_C1_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0376_LN0_OVRD_RX_SSLMS_C1_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0376_LN0_OVRD_RX_SSLMS_C1_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0376_LN0_OVRD_RX_SSLMS_C1_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0376_LN0_RX_SSLMS_C1_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0376_LN0_RX_SSLMS_C1_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0376_LN0_RX_SSLMS_C1_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0376_LN0_RX_SSLMS_C1_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0377 (0x0DDC)
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#define USBDP_TRSV_REG0377_LN0_OVRD_RX_SSLMS_C2_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0377_LN0_OVRD_RX_SSLMS_C2_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0377_LN0_OVRD_RX_SSLMS_C2_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0377_LN0_OVRD_RX_SSLMS_C2_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0377_LN0_RX_SSLMS_C2_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0377_LN0_RX_SSLMS_C2_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0377_LN0_RX_SSLMS_C2_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0377_LN0_RX_SSLMS_C2_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0378 (0x0DE0)
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#define USBDP_TRSV_REG0378_LN0_OVRD_RX_SSLMS_C3_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0378_LN0_OVRD_RX_SSLMS_C3_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0378_LN0_OVRD_RX_SSLMS_C3_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0378_LN0_OVRD_RX_SSLMS_C3_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0378_LN0_RX_SSLMS_C3_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0378_LN0_RX_SSLMS_C3_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0378_LN0_RX_SSLMS_C3_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0378_LN0_RX_SSLMS_C3_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0379 (0x0DE4)
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#define USBDP_TRSV_REG0379_LN0_OVRD_RX_SSLMS_C4_O_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0379_LN0_OVRD_RX_SSLMS_C4_O_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0379_LN0_OVRD_RX_SSLMS_C4_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0379_LN0_OVRD_RX_SSLMS_C4_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0379_LN0_RX_SSLMS_C4_O_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0379_LN0_RX_SSLMS_C4_O_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0379_LN0_RX_SSLMS_C4_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0379_LN0_RX_SSLMS_C4_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG037A (0x0DE8)
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#define USBDP_TRSV_REG037A_LN0_OVRD_RX_SSLMS_C5_O_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG037A_LN0_OVRD_RX_SSLMS_C5_O_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG037A_LN0_OVRD_RX_SSLMS_C5_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG037A_LN0_OVRD_RX_SSLMS_C5_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG037A_LN0_RX_SSLMS_C5_O_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG037A_LN0_RX_SSLMS_C5_O_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG037A_LN0_RX_SSLMS_C5_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG037A_LN0_RX_SSLMS_C5_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG037B (0x0DEC)
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#define USBDP_TRSV_REG037B_LN0_OVRD_RX_SSLMS_HF_BIN_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG037B_LN0_OVRD_RX_SSLMS_HF_BIN_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG037B_LN0_OVRD_RX_SSLMS_HF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG037B_LN0_OVRD_RX_SSLMS_HF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG037B_LN0_RX_SSLMS_HF_BIN_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG037B_LN0_RX_SSLMS_HF_BIN_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG037B_LN0_RX_SSLMS_HF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG037B_LN0_RX_SSLMS_HF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG037C (0x0DF0)
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#define USBDP_TRSV_REG037C_LN0_OVRD_RX_SSLMS_MF_BIN_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG037C_LN0_OVRD_RX_SSLMS_MF_BIN_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG037C_LN0_OVRD_RX_SSLMS_MF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG037C_LN0_OVRD_RX_SSLMS_MF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG037C_LN0_RX_SSLMS_MF_BIN_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG037C_LN0_RX_SSLMS_MF_BIN_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG037C_LN0_RX_SSLMS_MF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG037C_LN0_RX_SSLMS_MF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG037D (0x0DF4)
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#define USBDP_TRSV_REG037D_LN0_OVRD_RX_SSLMS_VGA_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG037D_LN0_OVRD_RX_SSLMS_VGA_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG037D_LN0_OVRD_RX_SSLMS_VGA_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG037D_LN0_OVRD_RX_SSLMS_VGA_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG037D_LN0_RX_SSLMS_VGA_BIN_SSP_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG037D_LN0_RX_SSLMS_VGA_BIN_SSP_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG037D_LN0_RX_SSLMS_VGA_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG037D_LN0_RX_SSLMS_VGA_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG037D_LN0_TX_RXD_STATUS_ASYNC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG037D_LN0_TX_RXD_STATUS_ASYNC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG037D_LN0_TX_RXD_STATUS_ASYNC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG037D_LN0_TX_RXD_STATUS_ASYNC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG037E (0x0DF8)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG037E_LN0_RX_SQHS_TH_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG037F (0x0DFC)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG037F_LN0_RX_SQHS_TH_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0380 (0x0E00)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0380_LN0_RX_SQHS_TH_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0381 (0x0E04)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0381_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0382 (0x0E08)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_DFE_MADD_PBIAS_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0382_LN0_RX_CDR_CP_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0382_LN0_RX_CDR_CP_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0382_LN0_RX_CDR_CP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0382_LN0_RX_CDR_CP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0383 (0x0E0C)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0383_LN0_RX_CDR_CP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0384 (0x0E10)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0384_LN0_RX_CDR_CP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0385 (0x0E14)
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#define USBDP_TRSV_REG0385_LN0_RX_CDR_CP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0385_LN0_RX_CDR_CP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0385_LN0_RX_CDR_CP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0385_LN0_RX_CDR_CP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0386 (0x0E18)
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#define USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0387 (0x0E1C)
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#define USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0388 (0x0E20)
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#define USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0389 (0x0E24)
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#define USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG038A (0x0E28)
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#define USBDP_TRSV_REG038A_LN0_RX_CDR_AFC_PMS_M_RBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG038A_LN0_RX_CDR_AFC_PMS_M_RBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG038A_LN0_RX_CDR_AFC_PMS_M_RBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG038A_LN0_RX_CDR_AFC_PMS_M_RBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG038B (0x0E2C)
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#define USBDP_TRSV_REG038B_LN0_RX_CDR_AFC_PMS_M_RBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG038B_LN0_RX_CDR_AFC_PMS_M_RBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG038B_LN0_RX_CDR_AFC_PMS_M_RBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG038B_LN0_RX_CDR_AFC_PMS_M_RBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG038C (0x0E30)
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#define USBDP_TRSV_REG038C_LN0_RX_CDR_AFC_PMS_M_HBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG038C_LN0_RX_CDR_AFC_PMS_M_HBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG038C_LN0_RX_CDR_AFC_PMS_M_HBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG038C_LN0_RX_CDR_AFC_PMS_M_HBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG038D (0x0E34)
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#define USBDP_TRSV_REG038D_LN0_RX_CDR_AFC_PMS_M_HBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG038D_LN0_RX_CDR_AFC_PMS_M_HBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG038D_LN0_RX_CDR_AFC_PMS_M_HBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG038D_LN0_RX_CDR_AFC_PMS_M_HBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG038E (0x0E38)
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#define USBDP_TRSV_REG038E_LN0_RX_CDR_AFC_PMS_M_HBR2__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG038E_LN0_RX_CDR_AFC_PMS_M_HBR2__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG038E_LN0_RX_CDR_AFC_PMS_M_HBR2__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG038E_LN0_RX_CDR_AFC_PMS_M_HBR2__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG038F (0x0E3C)
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#define USBDP_TRSV_REG038F_LN0_RX_CDR_AFC_PMS_M_HBR2__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG038F_LN0_RX_CDR_AFC_PMS_M_HBR2__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG038F_LN0_RX_CDR_AFC_PMS_M_HBR2__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG038F_LN0_RX_CDR_AFC_PMS_M_HBR2__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0390 (0x0E40)
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#define USBDP_TRSV_REG0390_LN0_RX_CDR_AFC_PMS_M_HBR3__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0390_LN0_RX_CDR_AFC_PMS_M_HBR3__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0390_LN0_RX_CDR_AFC_PMS_M_HBR3__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0390_LN0_RX_CDR_AFC_PMS_M_HBR3__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0391 (0x0E44)
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#define USBDP_TRSV_REG0391_LN0_RX_CDR_AFC_PMS_M_HBR3__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0391_LN0_RX_CDR_AFC_PMS_M_HBR3__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0391_LN0_RX_CDR_AFC_PMS_M_HBR3__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0391_LN0_RX_CDR_AFC_PMS_M_HBR3__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0392 (0x0E48)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0392_LN0_OVRD_RX_CDR_AFC_PMS_M_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0393 (0x0E4C)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_TARGET_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_TARGET_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_TARGET_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_TARGET_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MAN_MODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MAN_MODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MAN_MODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MAN_MODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_DAC_CODE_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_DAC_CODE_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_DAC_CODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0393_LN0_RX_OC_MON_DAC_CODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0394 (0x0E50)
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#define USBDP_TRSV_REG0394_LN0_RX_OC_MON_CODE_SEL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0394_LN0_RX_OC_MON_CODE_SEL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0394_LN0_RX_OC_MON_CODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0394_LN0_RX_OC_MON_CODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0395 (0x0E54)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_MAN_TARGET_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_MAN_TARGET_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_MAN_TARGET_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_MAN_TARGET_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_RAW_DATA_READ_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_RAW_DATA_READ_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_RAW_DATA_READ_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0395_LN0_RX_OC_RAW_DATA_READ_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0395_LN0_RX_OV_I_OC_DAC_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0395_LN0_RX_OV_I_OC_DAC_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0395_LN0_RX_OV_I_OC_DAC_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0395_LN0_RX_OV_I_OC_DAC_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0396 (0x0E58)
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#define USBDP_TRSV_REG0396_LN0_RX_OV_I_OC_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0396_LN0_RX_OV_I_OC_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0396_LN0_RX_OV_I_OC_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0396_LN0_RX_OV_I_OC_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0397 (0x0E5C)
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#define USBDP_TRSV_REG0397_LN0_RX_OC_MODE_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0397_LN0_RX_OC_MODE_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0397_LN0_RX_OC_MODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0397_LN0_RX_OC_MODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0398 (0x0E60)
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#define USBDP_TRSV_REG0398_LN0_RX_CDR_VCO_STARTUP_DELAY_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0398_LN0_RX_CDR_VCO_STARTUP_DELAY_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0398_LN0_RX_CDR_VCO_STARTUP_DELAY_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0398_LN0_RX_CDR_VCO_STARTUP_DELAY_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0399 (0x0E64)
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#define USBDP_TRSV_REG0399_LN0_RX_CDR_VCO_STARTUP_DELAY_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0399_LN0_RX_CDR_VCO_STARTUP_DELAY_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0399_LN0_RX_CDR_VCO_STARTUP_DELAY_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0399_LN0_RX_CDR_VCO_STARTUP_DELAY_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039A (0x0E68)
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#define USBDP_TRSV_REG039A_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG039A_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG039A_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG039A_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039B (0x0E6C)
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#define USBDP_TRSV_REG039B_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG039B_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG039B_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG039B_LN0_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039C (0x0E70)
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#define USBDP_TRSV_REG039C_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG039C_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG039C_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG039C_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039D (0x0E74)
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#define USBDP_TRSV_REG039D_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG039D_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG039D_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG039D_LN0_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039E (0x0E78)
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#define USBDP_TRSV_REG039E_LN0_BIST_AUTO_RX_HOLD_COUNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG039E_LN0_BIST_AUTO_RX_HOLD_COUNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG039E_LN0_BIST_AUTO_RX_HOLD_COUNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG039E_LN0_BIST_AUTO_RX_HOLD_COUNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG039F (0x0E7C)
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#define USBDP_TRSV_REG039F_LN0_LANE_RESERVED8_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG039F_LN0_LANE_RESERVED8_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG039F_LN0_LANE_RESERVED8_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG039F_LN0_LANE_RESERVED8_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_VDD_BYPASS_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_VDD_BYPASS_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_VDD_BYPASS_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG039F_LN0_ANA_RX_CDR_FBB_VDD_BYPASS_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03A0 (0x0E80)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED9_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED9_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED9_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED9_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED10_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED10_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED10_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG03A0_LN0_LANE_RESERVED10_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG03A0_LN0_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG03A1 (0x0E84)
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#define USBDP_TRSV_REG03A1_LN0_LANE_RESERVED11_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG03A1_LN0_LANE_RESERVED11_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG03A1_LN0_LANE_RESERVED11_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG03A1_LN0_LANE_RESERVED11_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG03A1_LN0_ANA_RX_CDR_FBB_POWER_SAVE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG03A1_LN0_ANA_RX_CDR_FBB_POWER_SAVE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG03A1_LN0_ANA_RX_CDR_FBB_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG03A1_LN0_ANA_RX_CDR_FBB_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG03A1_LN0_LANE_AUX_DTB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A1_LN0_LANE_AUX_DTB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A1_LN0_LANE_AUX_DTB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A1_LN0_LANE_AUX_DTB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A2 (0x0E88)
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#define USBDP_TRSV_REG03A2_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A2_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A2_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A2_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A3 (0x0E8C)
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#define USBDP_TRSV_REG03A3_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A3_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A3_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A3_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A4 (0x0E90)
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#define USBDP_TRSV_REG03A4_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A4_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A4_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A4_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A5 (0x0E94)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03A5_LN0_RX_CDR_FBB_MAN_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03A6 (0x0E98)
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#define USBDP_TRSV_REG03A6_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A6_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A6_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A6_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A7 (0x0E9C)
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#define USBDP_TRSV_REG03A7_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A7_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A7_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A7_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A8 (0x0EA0)
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#define USBDP_TRSV_REG03A8_LN0_RX_CDR_FBB_DELTA_CNT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A8_LN0_RX_CDR_FBB_DELTA_CNT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A8_LN0_RX_CDR_FBB_DELTA_CNT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A8_LN0_RX_CDR_FBB_DELTA_CNT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03A9 (0x0EA4)
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#define USBDP_TRSV_REG03A9_LN0_RX_CDR_FBB_DELTA_CNT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03A9_LN0_RX_CDR_FBB_DELTA_CNT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03A9_LN0_RX_CDR_FBB_DELTA_CNT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03A9_LN0_RX_CDR_FBB_DELTA_CNT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AA (0x0EA8)
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#define USBDP_TRSV_REG03AA_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AA_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AA_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AA_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AB (0x0EAC)
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#define USBDP_TRSV_REG03AB_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AB_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AB_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AB_LN0_RX_CDR_FBB_PLL_MODE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AC (0x0EB0)
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#define USBDP_TRSV_REG03AC_LN0_RX_CDR_FBB_COARSE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AC_LN0_RX_CDR_FBB_COARSE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AC_LN0_RX_CDR_FBB_COARSE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AC_LN0_RX_CDR_FBB_COARSE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AD (0x0EB4)
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#define USBDP_TRSV_REG03AD_LN0_RX_CDR_FBB_COARSE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AD_LN0_RX_CDR_FBB_COARSE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AD_LN0_RX_CDR_FBB_COARSE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AD_LN0_RX_CDR_FBB_COARSE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AE (0x0EB8)
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#define USBDP_TRSV_REG03AE_LN0_RX_CDR_FBB_FINE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AE_LN0_RX_CDR_FBB_FINE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AE_LN0_RX_CDR_FBB_FINE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AE_LN0_RX_CDR_FBB_FINE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03AF (0x0EBC)
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#define USBDP_TRSV_REG03AF_LN0_RX_CDR_FBB_FINE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03AF_LN0_RX_CDR_FBB_FINE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03AF_LN0_RX_CDR_FBB_FINE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03AF_LN0_RX_CDR_FBB_FINE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B0 (0x0EC0)
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#define USBDP_TRSV_REG03B0_LN0_RX_CDR_FBB_PLL_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B0_LN0_RX_CDR_FBB_PLL_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B0_LN0_RX_CDR_FBB_PLL_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B0_LN0_RX_CDR_FBB_PLL_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B1 (0x0EC4)
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#define USBDP_TRSV_REG03B1_LN0_RX_CDR_FBB_PLL_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B1_LN0_RX_CDR_FBB_PLL_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B1_LN0_RX_CDR_FBB_PLL_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B1_LN0_RX_CDR_FBB_PLL_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B2 (0x0EC8)
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#define USBDP_TRSV_REG03B2_LN0_RX_CDR_FBB_HI_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B2_LN0_RX_CDR_FBB_HI_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B2_LN0_RX_CDR_FBB_HI_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B2_LN0_RX_CDR_FBB_HI_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B3 (0x0ECC)
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#define USBDP_TRSV_REG03B3_LN0_RX_CDR_FBB_HI_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B3_LN0_RX_CDR_FBB_HI_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B3_LN0_RX_CDR_FBB_HI_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B3_LN0_RX_CDR_FBB_HI_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B4 (0x0ED0)
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#define USBDP_TRSV_REG03B4_LN0_RX_CDR_FBB_LO_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B4_LN0_RX_CDR_FBB_LO_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B4_LN0_RX_CDR_FBB_LO_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B4_LN0_RX_CDR_FBB_LO_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03B5 (0x0ED4)
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#define USBDP_TRSV_REG03B5_LN0_RX_CDR_FBB_LO_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03B5_LN0_RX_CDR_FBB_LO_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03B5_LN0_RX_CDR_FBB_LO_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03B5_LN0_RX_CDR_FBB_LO_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03C0 (0x0F00)
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#define USBDP_TRSV_REG03C0_LN0_MON_LANE_STATE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_LANE_STATE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_LANE_STATE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_LANE_STATE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_CDR_STATE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_CDR_STATE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_CDR_STATE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03C0_LN0_MON_CDR_STATE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03C1 (0x0F04)
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#define USBDP_TRSV_REG03C1_LN0_MON_LANE_TIME__14_8_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03C1_LN0_MON_LANE_TIME__14_8_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03C1_LN0_MON_LANE_TIME__14_8_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03C1_LN0_MON_LANE_TIME__14_8_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03C2 (0x0F08)
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#define USBDP_TRSV_REG03C2_LN0_MON_LANE_TIME__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03C2_LN0_MON_LANE_TIME__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03C2_LN0_MON_LANE_TIME__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03C2_LN0_MON_LANE_TIME__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03C3 (0x0F0C)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03C4 (0x0F10)
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#define USBDP_TRSV_REG03C4_LN0_MON_RX_CDR_AFC_SEL_LOGIC_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03C4_LN0_MON_RX_CDR_AFC_SEL_LOGIC_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03C4_LN0_MON_RX_CDR_AFC_SEL_LOGIC_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03C4_LN0_MON_RX_CDR_AFC_SEL_LOGIC_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03C5 (0x0F14)
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#define USBDP_TRSV_REG03C5_LN0_MON_RX_CDR_FBB_FINE_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03C5_LN0_MON_RX_CDR_FBB_FINE_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03C5_LN0_MON_RX_CDR_FBB_FINE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03C5_LN0_MON_RX_CDR_FBB_FINE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03C6 (0x0F18)
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#define USBDP_TRSV_REG03C6_LN0_MON_RX_CDR_FBB_COARSE_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03C6_LN0_MON_RX_CDR_FBB_COARSE_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03C6_LN0_MON_RX_CDR_FBB_COARSE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03C6_LN0_MON_RX_CDR_FBB_COARSE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03C7 (0x0F1C)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG03C7_LN0_MON_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG03C8 (0x0F20)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_TEST_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_TEST_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_TEST_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_TEST_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_ERRINJ_TEST_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_ERRINJ_TEST_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_ERRINJ_TEST_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_ERRINJ_TEST_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03C8_LN0_MON_BIST_COMP_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03C9 (0x0F24)
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#define USBDP_TRSV_REG03C9_LN0_MON_BIST_EOUT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03C9_LN0_MON_BIST_EOUT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03C9_LN0_MON_BIST_EOUT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03C9_LN0_MON_BIST_EOUT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03CA (0x0F28)
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#define USBDP_TRSV_REG03CA_LN0_MON_RX_OC_DFE_ADDER_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03CA_LN0_MON_RX_OC_DFE_ADDER_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03CA_LN0_MON_RX_OC_DFE_ADDER_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03CA_LN0_MON_RX_OC_DFE_ADDER_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03CB (0x0F2C)
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#define USBDP_TRSV_REG03CB_LN0_MON_RX_OC_DFE_ADDER_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03CB_LN0_MON_RX_OC_DFE_ADDER_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03CB_LN0_MON_RX_OC_DFE_ADDER_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03CB_LN0_MON_RX_OC_DFE_ADDER_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03CC (0x0F30)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG03CC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG03CD (0x0F34)
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#define USBDP_TRSV_REG03CD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03CD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03CD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03CD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03CE (0x0F38)
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#define USBDP_TRSV_REG03CE_LN0_MON_RX_OC_DFE_SA_EDGE_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03CE_LN0_MON_RX_OC_DFE_SA_EDGE_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03CE_LN0_MON_RX_OC_DFE_SA_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03CE_LN0_MON_RX_OC_DFE_SA_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03CF (0x0F3C)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG03CF_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG03D0 (0x0F40)
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#define USBDP_TRSV_REG03D0_LN0_MON_RX_OC_DFE_SA_ERR_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D0_LN0_MON_RX_OC_DFE_SA_ERR_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D0_LN0_MON_RX_OC_DFE_SA_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D0_LN0_MON_RX_OC_DFE_SA_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03D1 (0x0F44)
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#define USBDP_TRSV_REG03D1_LN0_MON_RX_OC_DFE_SA_ERR_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D1_LN0_MON_RX_OC_DFE_SA_ERR_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D1_LN0_MON_RX_OC_DFE_SA_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D1_LN0_MON_RX_OC_DFE_SA_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03D2 (0x0F48)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG03D2_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG03D3 (0x0F4C)
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#define USBDP_TRSV_REG03D3_LN0_MON_RX_OC_CTLE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D3_LN0_MON_RX_OC_CTLE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D3_LN0_MON_RX_OC_CTLE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D3_LN0_MON_RX_OC_CTLE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03D4 (0x0F50)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFN_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFN_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFN_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFN_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03D4_LN0_MON_RX_OC_SQ_DIFP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03D5 (0x0F54)
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#define USBDP_TRSV_REG03D5_LN0_MON_RX_OC_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03D5_LN0_MON_RX_OC_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03D5_LN0_MON_RX_OC_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03D5_LN0_MON_RX_OC_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03D6 (0x0F58)
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#define USBDP_TRSV_REG03D6_LN0_MON_RX_OC_FAIL__10_8_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG03D6_LN0_MON_RX_OC_FAIL__10_8_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG03D6_LN0_MON_RX_OC_FAIL__10_8_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG03D6_LN0_MON_RX_OC_FAIL__10_8_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG03D7 (0x0F5C)
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#define USBDP_TRSV_REG03D7_LN0_MON_RX_OC_FAIL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D7_LN0_MON_RX_OC_FAIL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D7_LN0_MON_RX_OC_FAIL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D7_LN0_MON_RX_OC_FAIL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03D8 (0x0F60)
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#define USBDP_TRSV_REG03D8_LN0_MON_RX_SSLMS_C0_E_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D8_LN0_MON_RX_SSLMS_C0_E_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D8_LN0_MON_RX_SSLMS_C0_E_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D8_LN0_MON_RX_SSLMS_C0_E_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03D9 (0x0F64)
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#define USBDP_TRSV_REG03D9_LN0_MON_RX_SSLMS_C0_O_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03D9_LN0_MON_RX_SSLMS_C0_O_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03D9_LN0_MON_RX_SSLMS_C0_O_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03D9_LN0_MON_RX_SSLMS_C0_O_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03DA (0x0F68)
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#define USBDP_TRSV_REG03DA_LN0_MON_RX_SSLMS_C1_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DA_LN0_MON_RX_SSLMS_C1_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DA_LN0_MON_RX_SSLMS_C1_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DA_LN0_MON_RX_SSLMS_C1_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03DB (0x0F6C)
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#define USBDP_TRSV_REG03DB_LN0_MON_RX_SSLMS_C1_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DB_LN0_MON_RX_SSLMS_C1_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DB_LN0_MON_RX_SSLMS_C1_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DB_LN0_MON_RX_SSLMS_C1_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03DC (0x0F70)
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#define USBDP_TRSV_REG03DC_LN0_MON_RX_SSLMS_C2_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DC_LN0_MON_RX_SSLMS_C2_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DC_LN0_MON_RX_SSLMS_C2_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DC_LN0_MON_RX_SSLMS_C2_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03DD (0x0F74)
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#define USBDP_TRSV_REG03DD_LN0_MON_RX_SSLMS_C2_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DD_LN0_MON_RX_SSLMS_C2_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DD_LN0_MON_RX_SSLMS_C2_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DD_LN0_MON_RX_SSLMS_C2_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03DE (0x0F78)
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#define USBDP_TRSV_REG03DE_LN0_MON_RX_SSLMS_C3_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DE_LN0_MON_RX_SSLMS_C3_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DE_LN0_MON_RX_SSLMS_C3_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DE_LN0_MON_RX_SSLMS_C3_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03DF (0x0F7C)
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#define USBDP_TRSV_REG03DF_LN0_MON_RX_SSLMS_C3_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG03DF_LN0_MON_RX_SSLMS_C3_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG03DF_LN0_MON_RX_SSLMS_C3_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG03DF_LN0_MON_RX_SSLMS_C3_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG03E0 (0x0F80)
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#define USBDP_TRSV_REG03E0_LN0_MON_RX_SSLMS_C4_E_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03E0_LN0_MON_RX_SSLMS_C4_E_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03E0_LN0_MON_RX_SSLMS_C4_E_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03E0_LN0_MON_RX_SSLMS_C4_E_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03E1 (0x0F84)
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#define USBDP_TRSV_REG03E1_LN0_MON_RX_SSLMS_C4_O_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03E1_LN0_MON_RX_SSLMS_C4_O_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03E1_LN0_MON_RX_SSLMS_C4_O_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03E1_LN0_MON_RX_SSLMS_C4_O_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03E2 (0x0F88)
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#define USBDP_TRSV_REG03E2_LN0_MON_RX_SSLMS_C5_E_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03E2_LN0_MON_RX_SSLMS_C5_E_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03E2_LN0_MON_RX_SSLMS_C5_E_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03E2_LN0_MON_RX_SSLMS_C5_E_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03E3 (0x0F8C)
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#define USBDP_TRSV_REG03E3_LN0_MON_RX_SSLMS_C5_O_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03E3_LN0_MON_RX_SSLMS_C5_O_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03E3_LN0_MON_RX_SSLMS_C5_O_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03E3_LN0_MON_RX_SSLMS_C5_O_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03E4 (0x0F90)
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#define USBDP_TRSV_REG03E4_LN0_MON_RX_SSLMS_HF_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG03E4_LN0_MON_RX_SSLMS_HF_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG03E4_LN0_MON_RX_SSLMS_HF_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG03E4_LN0_MON_RX_SSLMS_HF_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG03E5 (0x0F94)
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#define USBDP_TRSV_REG03E5_LN0_MON_RX_SSLMS_MF_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG03E5_LN0_MON_RX_SSLMS_MF_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG03E5_LN0_MON_RX_SSLMS_MF_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG03E5_LN0_MON_RX_SSLMS_MF_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG03E6 (0x0F98)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_VGA_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_VGA_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_VGA_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_VGA_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_ADAP_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_ADAP_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_ADAP_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_SSLMS_ADAP_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_EFOM_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_EFOM_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03E6_LN0_MON_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03E7 (0x0F9C)
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#define USBDP_TRSV_REG03E7_LN0_MON_RX_EFOM_ERR_CNT_OLD__13_8_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG03E7_LN0_MON_RX_EFOM_ERR_CNT_OLD__13_8_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG03E7_LN0_MON_RX_EFOM_ERR_CNT_OLD__13_8_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG03E7_LN0_MON_RX_EFOM_ERR_CNT_OLD__13_8_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG03E8 (0x0FA0)
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#define USBDP_TRSV_REG03E8_LN0_MON_RX_EFOM_ERR_CNT_OLD__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03E8_LN0_MON_RX_EFOM_ERR_CNT_OLD__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03E8_LN0_MON_RX_EFOM_ERR_CNT_OLD__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03E8_LN0_MON_RX_EFOM_ERR_CNT_OLD__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03E9 (0x0FA4)
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#define USBDP_TRSV_REG03E9_LN0_MON_RX_EFOM_FEEDBACK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03E9_LN0_MON_RX_EFOM_FEEDBACK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03E9_LN0_MON_RX_EFOM_FEEDBACK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03E9_LN0_MON_RX_EFOM_FEEDBACK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03EA (0x0FA8)
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#define USBDP_TRSV_REG03EA_LN0_MON_RX_EFOM_FEEDBACK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03EA_LN0_MON_RX_EFOM_FEEDBACK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03EA_LN0_MON_RX_EFOM_FEEDBACK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03EA_LN0_MON_RX_EFOM_FEEDBACK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03EB (0x0FAC)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03EB_LN0_MON_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03EC (0x0FB0)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_LANE_DTB_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_LANE_DTB_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_LANE_DTB_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_LANE_DTB_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03EC_LN0_MON_TX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03ED (0x0FB4)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG03ED_LN0_MON_RX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG03EE (0x0FB8)
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#define USBDP_TRSV_REG03EE_LN0_MON_TX_CLK_GMUX_COUNTER__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03EE_LN0_MON_TX_CLK_GMUX_COUNTER__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03EE_LN0_MON_TX_CLK_GMUX_COUNTER__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03EE_LN0_MON_TX_CLK_GMUX_COUNTER__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03EF (0x0FBC)
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#define USBDP_TRSV_REG03EF_LN0_MON_TX_CLK_GMUX_COUNTER__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03EF_LN0_MON_TX_CLK_GMUX_COUNTER__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03EF_LN0_MON_TX_CLK_GMUX_COUNTER__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03EF_LN0_MON_TX_CLK_GMUX_COUNTER__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F0 (0x0FC0)
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#define USBDP_TRSV_REG03F0_LN0_MON_RX_CLK_GMUX_COUNTER__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F0_LN0_MON_RX_CLK_GMUX_COUNTER__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F0_LN0_MON_RX_CLK_GMUX_COUNTER__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F0_LN0_MON_RX_CLK_GMUX_COUNTER__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F1 (0x0FC4)
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#define USBDP_TRSV_REG03F1_LN0_MON_RX_CLK_GMUX_COUNTER__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F1_LN0_MON_RX_CLK_GMUX_COUNTER__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F1_LN0_MON_RX_CLK_GMUX_COUNTER__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F1_LN0_MON_RX_CLK_GMUX_COUNTER__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F2 (0x0FC8)
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#define USBDP_TRSV_REG03F2_LN0_MON_RX_CDR_VCO_CNT_AFC__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03F2_LN0_MON_RX_CDR_VCO_CNT_AFC__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03F2_LN0_MON_RX_CDR_VCO_CNT_AFC__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03F2_LN0_MON_RX_CDR_VCO_CNT_AFC__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03F3 (0x0FCC)
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#define USBDP_TRSV_REG03F3_LN0_MON_RX_CDR_VCO_CNT_AFC__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F3_LN0_MON_RX_CDR_VCO_CNT_AFC__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F3_LN0_MON_RX_CDR_VCO_CNT_AFC__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F3_LN0_MON_RX_CDR_VCO_CNT_AFC__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F4 (0x0FD0)
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#define USBDP_TRSV_REG03F4_LN0_MON_RX_CDR_VCO_CNT_FBB__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03F4_LN0_MON_RX_CDR_VCO_CNT_FBB__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03F4_LN0_MON_RX_CDR_VCO_CNT_FBB__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03F4_LN0_MON_RX_CDR_VCO_CNT_FBB__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03F5 (0x0FD4)
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#define USBDP_TRSV_REG03F5_LN0_MON_RX_CDR_VCO_CNT_FBB__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F5_LN0_MON_RX_CDR_VCO_CNT_FBB__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F5_LN0_MON_RX_CDR_VCO_CNT_FBB__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F5_LN0_MON_RX_CDR_VCO_CNT_FBB__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F6 (0x0FD8)
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#define USBDP_TRSV_REG03F6_LN0_MON_RX_CDR_VCO_CNT_FBB_P__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03F6_LN0_MON_RX_CDR_VCO_CNT_FBB_P__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03F6_LN0_MON_RX_CDR_VCO_CNT_FBB_P__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03F6_LN0_MON_RX_CDR_VCO_CNT_FBB_P__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03F7 (0x0FDC)
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#define USBDP_TRSV_REG03F7_LN0_MON_RX_CDR_VCO_CNT_FBB_P__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F7_LN0_MON_RX_CDR_VCO_CNT_FBB_P__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F7_LN0_MON_RX_CDR_VCO_CNT_FBB_P__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F7_LN0_MON_RX_CDR_VCO_CNT_FBB_P__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03F8 (0x0FE0)
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#define USBDP_TRSV_REG03F8_LN0_MON_RX_CDR_VCO_CNT_PLL__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03F8_LN0_MON_RX_CDR_VCO_CNT_PLL__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03F8_LN0_MON_RX_CDR_VCO_CNT_PLL__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03F8_LN0_MON_RX_CDR_VCO_CNT_PLL__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03F9 (0x0FE4)
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#define USBDP_TRSV_REG03F9_LN0_MON_RX_CDR_VCO_CNT_PLL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03F9_LN0_MON_RX_CDR_VCO_CNT_PLL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03F9_LN0_MON_RX_CDR_VCO_CNT_PLL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03F9_LN0_MON_RX_CDR_VCO_CNT_PLL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03FA (0x0FE8)
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#define USBDP_TRSV_REG03FA_LN0_MON_RX_CDR_VCO_CNT_CK__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03FA_LN0_MON_RX_CDR_VCO_CNT_CK__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03FA_LN0_MON_RX_CDR_VCO_CNT_CK__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03FA_LN0_MON_RX_CDR_VCO_CNT_CK__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03FB (0x0FEC)
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#define USBDP_TRSV_REG03FB_LN0_MON_RX_CDR_VCO_CNT_CK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03FB_LN0_MON_RX_CDR_VCO_CNT_CK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03FB_LN0_MON_RX_CDR_VCO_CNT_CK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03FB_LN0_MON_RX_CDR_VCO_CNT_CK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03FC (0x0FF0)
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#define USBDP_TRSV_REG03FC_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03FC_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03FC_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03FC_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03FD (0x0FF4)
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#define USBDP_TRSV_REG03FD_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03FD_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03FD_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03FD_LN0_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG03FE (0x0FF8)
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#define USBDP_TRSV_REG03FE_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG03FE_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG03FE_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG03FE_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG03FF (0x0FFC)
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#define USBDP_TRSV_REG03FF_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG03FF_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG03FF_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG03FF_LN0_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0400 (0x1000)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0400_OVRD_LN1_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0400_LN1_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0401 (0x1004)
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#define USBDP_TRSV_REG0401_OVRD_LN1_TX_DRV_EI_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0401_OVRD_LN1_TX_DRV_EI_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0401_OVRD_LN1_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0401_OVRD_LN1_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0401_LN1_TX_DRV_EI_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0402 (0x1008)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0402_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0403 (0x100C)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0403_LN1_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_VREF_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_VREF_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_FB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_FB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_FB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_FB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0403_LN1_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0404 (0x1010)
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#define USBDP_TRSV_REG0404_OVRD_LN1_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0404_OVRD_LN1_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0404_OVRD_LN1_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0404_OVRD_LN1_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0404_LN1_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0404_LN1_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0404_LN1_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0404_LN1_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0405 (0x1014)
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#define USBDP_TRSV_REG0405_OVRD_LN1_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0405_OVRD_LN1_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0405_OVRD_LN1_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0405_OVRD_LN1_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0405_LN1_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0405_LN1_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0405_LN1_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0405_LN1_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0406 (0x1018)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0406_OVRD_LN1_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0406_LN1_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0407 (0x101C)
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#define USBDP_TRSV_REG0407_OVRD_LN1_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0407_OVRD_LN1_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0407_OVRD_LN1_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0407_OVRD_LN1_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0407_LN1_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0407_LN1_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0407_LN1_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0407_LN1_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_ACCDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_ACCDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_ACCDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0407_LN1_ANA_TX_DRV_ACCDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0408 (0x1020)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_POL_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_POL_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_POL_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_POL_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_CTRL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_CTRL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_ACCDRV_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_HSCLK_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_HSCLK_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_HSCLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_HSCLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0408_LN1_ANA_TX_DRV_PLL_REF_MON_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0409 (0x1024)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0409_LN1_TX_JEQ_CAP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040A (0x1028)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040A_LN1_TX_JEQ_CAP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040B (0x102C)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040B_LN1_TX_JEQ_CAP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040C (0x1030)
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#define USBDP_TRSV_REG040C_LN1_ANA_TX_JEQ_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG040C_LN1_ANA_TX_JEQ_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG040C_LN1_ANA_TX_JEQ_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG040C_LN1_ANA_TX_JEQ_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG040C_LN1_TX_JEQ_EVEN_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040C_LN1_TX_JEQ_EVEN_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040C_LN1_TX_JEQ_EVEN_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040C_LN1_TX_JEQ_EVEN_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040D (0x1034)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040D_LN1_TX_JEQ_EVEN_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040E (0x1038)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040E_LN1_TX_JEQ_EVEN_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG040F (0x103C)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_EVEN_CTRL_HBR3_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_EVEN_CTRL_HBR3_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_EVEN_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_EVEN_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_ODD_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_ODD_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_ODD_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG040F_LN1_TX_JEQ_ODD_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0410 (0x1040)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0410_LN1_TX_JEQ_ODD_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0411 (0x1044)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0411_LN1_TX_JEQ_ODD_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0412 (0x1048)
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#define USBDP_TRSV_REG0412_LN1_TX_JEQ_ODD_CTRL_HBR3_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG0412_LN1_TX_JEQ_ODD_CTRL_HBR3_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG0412_LN1_TX_JEQ_ODD_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG0412_LN1_TX_JEQ_ODD_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG0412_OVRD_LN1_TX_RCAL_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0412_OVRD_LN1_TX_RCAL_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0412_OVRD_LN1_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0412_OVRD_LN1_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0412_LN1_TX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0412_LN1_TX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0412_LN1_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0412_LN1_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0412_LN1_ANA_TX_RTERM_42P5_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0412_LN1_ANA_TX_RTERM_42P5_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0412_LN1_ANA_TX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0412_LN1_ANA_TX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0413 (0x104C)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0413_OVRD_LN1_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_COMP_I_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_COMP_I_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_COMP_I_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_COMP_I_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_VREF_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_VREF_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0413_LN1_ANA_TX_RXD_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0413_LN1_TX_SER_40BIT_EN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_SER_40BIT_EN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_SER_40BIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0413_LN1_TX_SER_40BIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0414 (0x1050)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_40BIT_EN_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0414_OVRD_LN1_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0414_OVRD_LN1_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0414_OVRD_LN1_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0414_OVRD_LN1_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_RATE_SEL_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_RATE_SEL_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_RATE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0414_LN1_TX_SER_RATE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0415 (0x1054)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_RATE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0415_OVRD_LN1_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0415_OVRD_LN1_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0415_OVRD_LN1_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0415_OVRD_LN1_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0415_LN1_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0415_LN1_ANA_TX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0415_LN1_ANA_TX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0415_LN1_ANA_TX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0415_LN1_ANA_TX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0416 (0x1058)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_SER_TXCLK_INV_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_SER_TXCLK_INV_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_SER_TXCLK_INV_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_SER_TXCLK_INV_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_TO_DIG_BYTE_CLK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_TO_DIG_BYTE_CLK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_TO_DIG_BYTE_CLK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0416_LN1_ANA_TX_TO_DIG_BYTE_CLK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0416_OVRD_LN1_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0416_OVRD_LN1_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0416_OVRD_LN1_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0416_OVRD_LN1_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SSP_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SSP_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_RBR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_RBR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_HBR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_HBR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0416_LN1_TX_LANE_LC_RO_CLK_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0417 (0x105C)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR2_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR2_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR3_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR3_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_LC_RO_CLK_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0417_LN1_ANA_TX_LANE_DIV2_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_SER_VREG_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_SER_VREG_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0417_OVRD_LN1_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_SER_VREG_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_SER_VREG_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0417_LN1_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0418 (0x1060)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0418_OVRD_LN1_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0418_OVRD_LN1_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0418_OVRD_LN1_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0418_OVRD_LN1_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0418_LN1_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0418_LN1_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0418_LN1_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0418_LN1_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_LADDER_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_LADDER_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0418_LN1_ANA_TX_SER_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0419 (0x1064)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_I_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_I_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_I_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_I_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0419_LN1_ANA_TX_SER_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG041A (0x1068)
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#define USBDP_TRSV_REG041A_LN1_TX_DCC_IN_BUF_STR_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG041A_LN1_TX_DCC_IN_BUF_STR_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG041A_LN1_TX_DCC_IN_BUF_STR_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG041A_LN1_TX_DCC_IN_BUF_STR_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG041B (0x106C)
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#define USBDP_TRSV_REG041B_LN1_TX_DCC_IN_BUF_STR_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG041B_LN1_TX_DCC_IN_BUF_STR_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG041B_LN1_TX_DCC_IN_BUF_STR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG041B_LN1_TX_DCC_IN_BUF_STR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG041C (0x1070)
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#define USBDP_TRSV_REG041C_LN1_TX_DCC_IN_BUF_STR_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG041C_LN1_TX_DCC_IN_BUF_STR_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG041C_LN1_TX_DCC_IN_BUF_STR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG041C_LN1_TX_DCC_IN_BUF_STR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG041D (0x1074)
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#define USBDP_TRSV_REG041D_LN1_TX_DCC_IN_BUF_STR_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG041D_LN1_TX_DCC_IN_BUF_STR_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG041D_LN1_TX_DCC_IN_BUF_STR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG041D_LN1_TX_DCC_IN_BUF_STR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG041E (0x1078)
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#define USBDP_TRSV_REG041E_LN1_TX_DCC_IN_BUF_STR_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG041E_LN1_TX_DCC_IN_BUF_STR_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG041E_LN1_TX_DCC_IN_BUF_STR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG041E_LN1_TX_DCC_IN_BUF_STR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG041F (0x107C)
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#define USBDP_TRSV_REG041F_LN1_TX_DCC_IN_BUF_STR_HBR3_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG041F_LN1_TX_DCC_IN_BUF_STR_HBR3_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG041F_LN1_TX_DCC_IN_BUF_STR_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG041F_LN1_TX_DCC_IN_BUF_STR_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG041F_LN1_ANA_TX_TO_RX_CLK_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG041F_LN1_ANA_TX_TO_RX_CLK_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG041F_LN1_ANA_TX_TO_RX_CLK_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG041F_LN1_ANA_TX_TO_RX_CLK_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0420 (0x1080)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_SEL_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_SEL_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_SLB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_SLB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_LLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_LLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_LLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0420_LN1_ANA_TX_LLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0421 (0x1084)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_SRLB_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_SRLB_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0421_OVRD_LN1_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0421_LN1_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_AFC_FORCE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_AFC_FORCE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_AFC_FORCE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_AFC_FORCE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_CLK_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_CLK_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0421_LN1_ANA_TX_LFPS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0422 (0x1088)
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#define USBDP_TRSV_REG0422_OVRD_LN1_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0422_OVRD_LN1_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0422_OVRD_LN1_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0422_OVRD_LN1_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0422_LN1_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0423 (0x108C)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0423_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0424 (0x1090)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0424_LN1_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0424_OVRD_LN1_TX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0424_OVRD_LN1_TX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0424_OVRD_LN1_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0424_OVRD_LN1_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0424_LN1_TX_INIT_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0424_LN1_TX_INIT_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0424_LN1_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0424_LN1_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0425 (0x1094)
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#define USBDP_TRSV_REG0425_LN1_ANA_TX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0425_LN1_ANA_TX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0425_LN1_ANA_TX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0425_LN1_ANA_TX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0426 (0x1098)
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#define USBDP_TRSV_REG0426_LN1_TX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0426_LN1_TX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0426_LN1_TX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0426_LN1_TX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0427 (0x109C)
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#define USBDP_TRSV_REG0427_LN1_TX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0427_LN1_TX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0427_LN1_TX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0427_LN1_TX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0428 (0x10A0)
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#define USBDP_TRSV_REG0428_LN1_TX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0428_LN1_TX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0428_LN1_TX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0428_LN1_TX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0429 (0x10A4)
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#define USBDP_TRSV_REG0429_LN1_TX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0429_LN1_TX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0429_LN1_TX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0429_LN1_TX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG042A (0x10A8)
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#define USBDP_TRSV_REG042A_LN1_TX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG042A_LN1_TX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG042A_LN1_TX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG042A_LN1_TX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG042B (0x10AC)
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#define USBDP_TRSV_REG042B_LN1_TX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG042B_LN1_TX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG042B_LN1_TX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG042B_LN1_TX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG042C (0x10B0)
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#define USBDP_TRSV_REG042C_LN1_OVRD_TX_RCAL_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG042C_LN1_OVRD_TX_RCAL_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG042C_LN1_OVRD_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG042C_LN1_OVRD_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_UP_OPT_CODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_UP_OPT_CODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_UP_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_UP_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_DN_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_DN_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_DN_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG042C_LN1_TX_RCAL_DN_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG042D (0x10B4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_UP_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_UP_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_UP_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_UP_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_DN_CODE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_DN_CODE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_DN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG042D_LN1_TX_RCAL_DN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG042E (0x10B8)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG042E_LN1_OVRD_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG042E_LN1_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0500 (0x1400)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0500_LN1_MON_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0501 (0x1404)
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#define USBDP_TRSV_REG0501_LN1_MON_RXNONDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0501_LN1_MON_RXNONDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0501_LN1_MON_RXNONDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0501_LN1_MON_RXNONDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0502 (0x1408)
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#define USBDP_TRSV_REG0502_LN1_MON_RXNONDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0502_LN1_MON_RXNONDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0502_LN1_MON_RXNONDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0502_LN1_MON_RXNONDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0503 (0x140C)
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#define USBDP_TRSV_REG0503_LN1_MON_RXNONDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0503_LN1_MON_RXNONDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0503_LN1_MON_RXNONDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0503_LN1_MON_RXNONDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0504 (0x1410)
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#define USBDP_TRSV_REG0504_LN1_MON_RXNONDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0504_LN1_MON_RXNONDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0504_LN1_MON_RXNONDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0504_LN1_MON_RXNONDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0505 (0x1414)
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#define USBDP_TRSV_REG0505_LN1_MON_RXNONDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0505_LN1_MON_RXNONDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0505_LN1_MON_RXNONDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0505_LN1_MON_RXNONDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0506 (0x1418)
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#define USBDP_TRSV_REG0506_LN1_MON_TRXDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0506_LN1_MON_TRXDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0506_LN1_MON_TRXDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0506_LN1_MON_TRXDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0507 (0x141C)
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#define USBDP_TRSV_REG0507_LN1_MON_TRXDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0507_LN1_MON_TRXDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0507_LN1_MON_TRXDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0507_LN1_MON_TRXDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0508 (0x1420)
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#define USBDP_TRSV_REG0508_LN1_MON_TRXDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0508_LN1_MON_TRXDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0508_LN1_MON_TRXDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0508_LN1_MON_TRXDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0509 (0x1424)
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#define USBDP_TRSV_REG0509_LN1_MON_TRXDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0509_LN1_MON_TRXDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0509_LN1_MON_TRXDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0509_LN1_MON_TRXDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050A (0x1428)
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#define USBDP_TRSV_REG050A_LN1_MON_TRXDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050A_LN1_MON_TRXDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050A_LN1_MON_TRXDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050A_LN1_MON_TRXDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050B (0x142C)
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#define USBDP_TRSV_REG050B_LN1_MON_TXDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050B_LN1_MON_TXDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050B_LN1_MON_TXDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050B_LN1_MON_TXDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050C (0x1430)
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#define USBDP_TRSV_REG050C_LN1_MON_TXDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050C_LN1_MON_TXDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050C_LN1_MON_TXDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050C_LN1_MON_TXDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050D (0x1434)
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#define USBDP_TRSV_REG050D_LN1_MON_TXDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050D_LN1_MON_TXDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050D_LN1_MON_TXDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050D_LN1_MON_TXDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050E (0x1438)
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#define USBDP_TRSV_REG050E_LN1_MON_TXDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050E_LN1_MON_TXDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050E_LN1_MON_TXDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050E_LN1_MON_TXDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG050F (0x143C)
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#define USBDP_TRSV_REG050F_LN1_MON_TXDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG050F_LN1_MON_TXDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG050F_LN1_MON_TXDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG050F_LN1_MON_TXDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0510 (0x1440)
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#define USBDP_TRSV_REG0510_LN1_MON_PCS_PORT_LOG_T00__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0510_LN1_MON_PCS_PORT_LOG_T00__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0510_LN1_MON_PCS_PORT_LOG_T00__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0510_LN1_MON_PCS_PORT_LOG_T00__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0511 (0x1444)
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#define USBDP_TRSV_REG0511_LN1_MON_PCS_PORT_LOG_T00__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0511_LN1_MON_PCS_PORT_LOG_T00__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0511_LN1_MON_PCS_PORT_LOG_T00__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0511_LN1_MON_PCS_PORT_LOG_T00__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0512 (0x1448)
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#define USBDP_TRSV_REG0512_LN1_MON_PCS_PORT_LOG_T00__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0512_LN1_MON_PCS_PORT_LOG_T00__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0512_LN1_MON_PCS_PORT_LOG_T00__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0512_LN1_MON_PCS_PORT_LOG_T00__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0513 (0x144C)
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#define USBDP_TRSV_REG0513_LN1_MON_PCS_PORT_LOG_T00__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0513_LN1_MON_PCS_PORT_LOG_T00__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0513_LN1_MON_PCS_PORT_LOG_T00__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0513_LN1_MON_PCS_PORT_LOG_T00__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0514 (0x1450)
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#define USBDP_TRSV_REG0514_LN1_MON_PCS_PORT_LOG_T01__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0514_LN1_MON_PCS_PORT_LOG_T01__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0514_LN1_MON_PCS_PORT_LOG_T01__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0514_LN1_MON_PCS_PORT_LOG_T01__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0515 (0x1454)
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#define USBDP_TRSV_REG0515_LN1_MON_PCS_PORT_LOG_T01__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0515_LN1_MON_PCS_PORT_LOG_T01__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0515_LN1_MON_PCS_PORT_LOG_T01__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0515_LN1_MON_PCS_PORT_LOG_T01__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0516 (0x1458)
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#define USBDP_TRSV_REG0516_LN1_MON_PCS_PORT_LOG_T01__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0516_LN1_MON_PCS_PORT_LOG_T01__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0516_LN1_MON_PCS_PORT_LOG_T01__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0516_LN1_MON_PCS_PORT_LOG_T01__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0517 (0x145C)
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#define USBDP_TRSV_REG0517_LN1_MON_PCS_PORT_LOG_T01__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0517_LN1_MON_PCS_PORT_LOG_T01__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0517_LN1_MON_PCS_PORT_LOG_T01__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0517_LN1_MON_PCS_PORT_LOG_T01__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0518 (0x1460)
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#define USBDP_TRSV_REG0518_LN1_MON_PCS_PORT_LOG_T02__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0518_LN1_MON_PCS_PORT_LOG_T02__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0518_LN1_MON_PCS_PORT_LOG_T02__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0518_LN1_MON_PCS_PORT_LOG_T02__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0519 (0x1464)
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#define USBDP_TRSV_REG0519_LN1_MON_PCS_PORT_LOG_T02__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0519_LN1_MON_PCS_PORT_LOG_T02__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0519_LN1_MON_PCS_PORT_LOG_T02__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0519_LN1_MON_PCS_PORT_LOG_T02__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051A (0x1468)
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#define USBDP_TRSV_REG051A_LN1_MON_PCS_PORT_LOG_T02__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051A_LN1_MON_PCS_PORT_LOG_T02__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051A_LN1_MON_PCS_PORT_LOG_T02__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051A_LN1_MON_PCS_PORT_LOG_T02__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051B (0x146C)
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#define USBDP_TRSV_REG051B_LN1_MON_PCS_PORT_LOG_T02__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051B_LN1_MON_PCS_PORT_LOG_T02__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051B_LN1_MON_PCS_PORT_LOG_T02__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051B_LN1_MON_PCS_PORT_LOG_T02__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051C (0x1470)
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#define USBDP_TRSV_REG051C_LN1_MON_PCS_PORT_LOG_T03__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051C_LN1_MON_PCS_PORT_LOG_T03__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051C_LN1_MON_PCS_PORT_LOG_T03__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051C_LN1_MON_PCS_PORT_LOG_T03__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051D (0x1474)
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#define USBDP_TRSV_REG051D_LN1_MON_PCS_PORT_LOG_T03__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051D_LN1_MON_PCS_PORT_LOG_T03__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051D_LN1_MON_PCS_PORT_LOG_T03__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051D_LN1_MON_PCS_PORT_LOG_T03__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051E (0x1478)
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#define USBDP_TRSV_REG051E_LN1_MON_PCS_PORT_LOG_T03__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051E_LN1_MON_PCS_PORT_LOG_T03__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051E_LN1_MON_PCS_PORT_LOG_T03__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051E_LN1_MON_PCS_PORT_LOG_T03__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG051F (0x147C)
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#define USBDP_TRSV_REG051F_LN1_MON_PCS_PORT_LOG_T03__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG051F_LN1_MON_PCS_PORT_LOG_T03__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG051F_LN1_MON_PCS_PORT_LOG_T03__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG051F_LN1_MON_PCS_PORT_LOG_T03__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0520 (0x1480)
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#define USBDP_TRSV_REG0520_LN1_MON_PCS_PORT_LOG_T04__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0520_LN1_MON_PCS_PORT_LOG_T04__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0520_LN1_MON_PCS_PORT_LOG_T04__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0520_LN1_MON_PCS_PORT_LOG_T04__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0521 (0x1484)
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#define USBDP_TRSV_REG0521_LN1_MON_PCS_PORT_LOG_T04__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0521_LN1_MON_PCS_PORT_LOG_T04__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0521_LN1_MON_PCS_PORT_LOG_T04__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0521_LN1_MON_PCS_PORT_LOG_T04__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0522 (0x1488)
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#define USBDP_TRSV_REG0522_LN1_MON_PCS_PORT_LOG_T04__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0522_LN1_MON_PCS_PORT_LOG_T04__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0522_LN1_MON_PCS_PORT_LOG_T04__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0522_LN1_MON_PCS_PORT_LOG_T04__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0523 (0x148C)
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#define USBDP_TRSV_REG0523_LN1_MON_PCS_PORT_LOG_T04__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0523_LN1_MON_PCS_PORT_LOG_T04__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0523_LN1_MON_PCS_PORT_LOG_T04__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0523_LN1_MON_PCS_PORT_LOG_T04__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0524 (0x1490)
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#define USBDP_TRSV_REG0524_LN1_MON_PCS_PORT_LOG_T05__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0524_LN1_MON_PCS_PORT_LOG_T05__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0524_LN1_MON_PCS_PORT_LOG_T05__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0524_LN1_MON_PCS_PORT_LOG_T05__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0525 (0x1494)
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#define USBDP_TRSV_REG0525_LN1_MON_PCS_PORT_LOG_T05__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0525_LN1_MON_PCS_PORT_LOG_T05__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0525_LN1_MON_PCS_PORT_LOG_T05__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0525_LN1_MON_PCS_PORT_LOG_T05__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0526 (0x1498)
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#define USBDP_TRSV_REG0526_LN1_MON_PCS_PORT_LOG_T05__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0526_LN1_MON_PCS_PORT_LOG_T05__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0526_LN1_MON_PCS_PORT_LOG_T05__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0526_LN1_MON_PCS_PORT_LOG_T05__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0527 (0x149C)
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#define USBDP_TRSV_REG0527_LN1_MON_PCS_PORT_LOG_T05__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0527_LN1_MON_PCS_PORT_LOG_T05__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0527_LN1_MON_PCS_PORT_LOG_T05__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0527_LN1_MON_PCS_PORT_LOG_T05__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0528 (0x14A0)
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#define USBDP_TRSV_REG0528_LN1_MON_PCS_PORT_LOG_T06__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0528_LN1_MON_PCS_PORT_LOG_T06__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0528_LN1_MON_PCS_PORT_LOG_T06__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0528_LN1_MON_PCS_PORT_LOG_T06__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0529 (0x14A4)
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#define USBDP_TRSV_REG0529_LN1_MON_PCS_PORT_LOG_T06__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0529_LN1_MON_PCS_PORT_LOG_T06__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0529_LN1_MON_PCS_PORT_LOG_T06__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0529_LN1_MON_PCS_PORT_LOG_T06__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052A (0x14A8)
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#define USBDP_TRSV_REG052A_LN1_MON_PCS_PORT_LOG_T06__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052A_LN1_MON_PCS_PORT_LOG_T06__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052A_LN1_MON_PCS_PORT_LOG_T06__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052A_LN1_MON_PCS_PORT_LOG_T06__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052B (0x14AC)
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#define USBDP_TRSV_REG052B_LN1_MON_PCS_PORT_LOG_T06__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052B_LN1_MON_PCS_PORT_LOG_T06__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052B_LN1_MON_PCS_PORT_LOG_T06__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052B_LN1_MON_PCS_PORT_LOG_T06__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052C (0x14B0)
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#define USBDP_TRSV_REG052C_LN1_MON_PCS_PORT_LOG_T07__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052C_LN1_MON_PCS_PORT_LOG_T07__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052C_LN1_MON_PCS_PORT_LOG_T07__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052C_LN1_MON_PCS_PORT_LOG_T07__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052D (0x14B4)
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#define USBDP_TRSV_REG052D_LN1_MON_PCS_PORT_LOG_T07__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052D_LN1_MON_PCS_PORT_LOG_T07__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052D_LN1_MON_PCS_PORT_LOG_T07__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052D_LN1_MON_PCS_PORT_LOG_T07__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052E (0x14B8)
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#define USBDP_TRSV_REG052E_LN1_MON_PCS_PORT_LOG_T07__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052E_LN1_MON_PCS_PORT_LOG_T07__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052E_LN1_MON_PCS_PORT_LOG_T07__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052E_LN1_MON_PCS_PORT_LOG_T07__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG052F (0x14BC)
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#define USBDP_TRSV_REG052F_LN1_MON_PCS_PORT_LOG_T07__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG052F_LN1_MON_PCS_PORT_LOG_T07__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG052F_LN1_MON_PCS_PORT_LOG_T07__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG052F_LN1_MON_PCS_PORT_LOG_T07__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0530 (0x14C0)
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#define USBDP_TRSV_REG0530_LN1_MON_PCS_PORT_LOG_T08__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0530_LN1_MON_PCS_PORT_LOG_T08__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0530_LN1_MON_PCS_PORT_LOG_T08__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0530_LN1_MON_PCS_PORT_LOG_T08__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0531 (0x14C4)
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#define USBDP_TRSV_REG0531_LN1_MON_PCS_PORT_LOG_T08__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0531_LN1_MON_PCS_PORT_LOG_T08__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0531_LN1_MON_PCS_PORT_LOG_T08__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0531_LN1_MON_PCS_PORT_LOG_T08__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0532 (0x14C8)
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#define USBDP_TRSV_REG0532_LN1_MON_PCS_PORT_LOG_T08__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0532_LN1_MON_PCS_PORT_LOG_T08__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0532_LN1_MON_PCS_PORT_LOG_T08__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0532_LN1_MON_PCS_PORT_LOG_T08__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0533 (0x14CC)
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#define USBDP_TRSV_REG0533_LN1_MON_PCS_PORT_LOG_T08__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0533_LN1_MON_PCS_PORT_LOG_T08__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0533_LN1_MON_PCS_PORT_LOG_T08__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0533_LN1_MON_PCS_PORT_LOG_T08__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0534 (0x14D0)
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#define USBDP_TRSV_REG0534_LN1_MON_PCS_PORT_LOG_T09__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0534_LN1_MON_PCS_PORT_LOG_T09__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0534_LN1_MON_PCS_PORT_LOG_T09__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0534_LN1_MON_PCS_PORT_LOG_T09__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0535 (0x14D4)
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#define USBDP_TRSV_REG0535_LN1_MON_PCS_PORT_LOG_T09__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0535_LN1_MON_PCS_PORT_LOG_T09__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0535_LN1_MON_PCS_PORT_LOG_T09__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0535_LN1_MON_PCS_PORT_LOG_T09__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0536 (0x14D8)
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#define USBDP_TRSV_REG0536_LN1_MON_PCS_PORT_LOG_T09__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0536_LN1_MON_PCS_PORT_LOG_T09__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0536_LN1_MON_PCS_PORT_LOG_T09__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0536_LN1_MON_PCS_PORT_LOG_T09__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0537 (0x14DC)
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#define USBDP_TRSV_REG0537_LN1_MON_PCS_PORT_LOG_T09__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0537_LN1_MON_PCS_PORT_LOG_T09__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0537_LN1_MON_PCS_PORT_LOG_T09__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0537_LN1_MON_PCS_PORT_LOG_T09__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0538 (0x14E0)
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#define USBDP_TRSV_REG0538_LN1_MON_PCS_PORT_LOG_T10__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0538_LN1_MON_PCS_PORT_LOG_T10__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0538_LN1_MON_PCS_PORT_LOG_T10__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0538_LN1_MON_PCS_PORT_LOG_T10__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0539 (0x14E4)
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#define USBDP_TRSV_REG0539_LN1_MON_PCS_PORT_LOG_T10__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0539_LN1_MON_PCS_PORT_LOG_T10__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0539_LN1_MON_PCS_PORT_LOG_T10__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0539_LN1_MON_PCS_PORT_LOG_T10__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053A (0x14E8)
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#define USBDP_TRSV_REG053A_LN1_MON_PCS_PORT_LOG_T10__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053A_LN1_MON_PCS_PORT_LOG_T10__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053A_LN1_MON_PCS_PORT_LOG_T10__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053A_LN1_MON_PCS_PORT_LOG_T10__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053B (0x14EC)
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#define USBDP_TRSV_REG053B_LN1_MON_PCS_PORT_LOG_T10__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053B_LN1_MON_PCS_PORT_LOG_T10__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053B_LN1_MON_PCS_PORT_LOG_T10__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053B_LN1_MON_PCS_PORT_LOG_T10__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053C (0x14F0)
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#define USBDP_TRSV_REG053C_LN1_MON_PCS_PORT_LOG_T11__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053C_LN1_MON_PCS_PORT_LOG_T11__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053C_LN1_MON_PCS_PORT_LOG_T11__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053C_LN1_MON_PCS_PORT_LOG_T11__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053D (0x14F4)
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#define USBDP_TRSV_REG053D_LN1_MON_PCS_PORT_LOG_T11__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053D_LN1_MON_PCS_PORT_LOG_T11__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053D_LN1_MON_PCS_PORT_LOG_T11__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053D_LN1_MON_PCS_PORT_LOG_T11__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053E (0x14F8)
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#define USBDP_TRSV_REG053E_LN1_MON_PCS_PORT_LOG_T11__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053E_LN1_MON_PCS_PORT_LOG_T11__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053E_LN1_MON_PCS_PORT_LOG_T11__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053E_LN1_MON_PCS_PORT_LOG_T11__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG053F (0x14FC)
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#define USBDP_TRSV_REG053F_LN1_MON_PCS_PORT_LOG_T11__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG053F_LN1_MON_PCS_PORT_LOG_T11__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG053F_LN1_MON_PCS_PORT_LOG_T11__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG053F_LN1_MON_PCS_PORT_LOG_T11__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0540 (0x1500)
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#define USBDP_TRSV_REG0540_LN1_MON_PCS_PORT_LOG_T12__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0540_LN1_MON_PCS_PORT_LOG_T12__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0540_LN1_MON_PCS_PORT_LOG_T12__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0540_LN1_MON_PCS_PORT_LOG_T12__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0541 (0x1504)
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#define USBDP_TRSV_REG0541_LN1_MON_PCS_PORT_LOG_T12__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0541_LN1_MON_PCS_PORT_LOG_T12__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0541_LN1_MON_PCS_PORT_LOG_T12__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0541_LN1_MON_PCS_PORT_LOG_T12__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0542 (0x1508)
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#define USBDP_TRSV_REG0542_LN1_MON_PCS_PORT_LOG_T12__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0542_LN1_MON_PCS_PORT_LOG_T12__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0542_LN1_MON_PCS_PORT_LOG_T12__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0542_LN1_MON_PCS_PORT_LOG_T12__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0543 (0x150C)
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#define USBDP_TRSV_REG0543_LN1_MON_PCS_PORT_LOG_T12__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0543_LN1_MON_PCS_PORT_LOG_T12__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0543_LN1_MON_PCS_PORT_LOG_T12__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0543_LN1_MON_PCS_PORT_LOG_T12__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0544 (0x1510)
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#define USBDP_TRSV_REG0544_LN1_MON_PCS_PORT_LOG_T13__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0544_LN1_MON_PCS_PORT_LOG_T13__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0544_LN1_MON_PCS_PORT_LOG_T13__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0544_LN1_MON_PCS_PORT_LOG_T13__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0545 (0x1514)
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#define USBDP_TRSV_REG0545_LN1_MON_PCS_PORT_LOG_T13__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0545_LN1_MON_PCS_PORT_LOG_T13__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0545_LN1_MON_PCS_PORT_LOG_T13__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0545_LN1_MON_PCS_PORT_LOG_T13__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0546 (0x1518)
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#define USBDP_TRSV_REG0546_LN1_MON_PCS_PORT_LOG_T13__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0546_LN1_MON_PCS_PORT_LOG_T13__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0546_LN1_MON_PCS_PORT_LOG_T13__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0546_LN1_MON_PCS_PORT_LOG_T13__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0547 (0x151C)
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#define USBDP_TRSV_REG0547_LN1_MON_PCS_PORT_LOG_T13__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0547_LN1_MON_PCS_PORT_LOG_T13__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0547_LN1_MON_PCS_PORT_LOG_T13__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0547_LN1_MON_PCS_PORT_LOG_T13__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0548 (0x1520)
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#define USBDP_TRSV_REG0548_LN1_MON_PCS_PORT_LOG_T14__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0548_LN1_MON_PCS_PORT_LOG_T14__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0548_LN1_MON_PCS_PORT_LOG_T14__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0548_LN1_MON_PCS_PORT_LOG_T14__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0549 (0x1524)
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#define USBDP_TRSV_REG0549_LN1_MON_PCS_PORT_LOG_T14__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0549_LN1_MON_PCS_PORT_LOG_T14__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0549_LN1_MON_PCS_PORT_LOG_T14__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0549_LN1_MON_PCS_PORT_LOG_T14__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054A (0x1528)
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#define USBDP_TRSV_REG054A_LN1_MON_PCS_PORT_LOG_T14__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054A_LN1_MON_PCS_PORT_LOG_T14__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054A_LN1_MON_PCS_PORT_LOG_T14__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054A_LN1_MON_PCS_PORT_LOG_T14__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054B (0x152C)
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#define USBDP_TRSV_REG054B_LN1_MON_PCS_PORT_LOG_T14__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054B_LN1_MON_PCS_PORT_LOG_T14__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054B_LN1_MON_PCS_PORT_LOG_T14__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054B_LN1_MON_PCS_PORT_LOG_T14__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054C (0x1530)
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#define USBDP_TRSV_REG054C_LN1_MON_PCS_PORT_LOG_T15__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054C_LN1_MON_PCS_PORT_LOG_T15__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054C_LN1_MON_PCS_PORT_LOG_T15__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054C_LN1_MON_PCS_PORT_LOG_T15__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054D (0x1534)
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#define USBDP_TRSV_REG054D_LN1_MON_PCS_PORT_LOG_T15__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054D_LN1_MON_PCS_PORT_LOG_T15__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054D_LN1_MON_PCS_PORT_LOG_T15__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054D_LN1_MON_PCS_PORT_LOG_T15__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054E (0x1538)
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#define USBDP_TRSV_REG054E_LN1_MON_PCS_PORT_LOG_T15__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054E_LN1_MON_PCS_PORT_LOG_T15__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054E_LN1_MON_PCS_PORT_LOG_T15__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054E_LN1_MON_PCS_PORT_LOG_T15__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG054F (0x153C)
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#define USBDP_TRSV_REG054F_LN1_MON_PCS_PORT_LOG_T15__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG054F_LN1_MON_PCS_PORT_LOG_T15__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG054F_LN1_MON_PCS_PORT_LOG_T15__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG054F_LN1_MON_PCS_PORT_LOG_T15__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0550 (0x1540)
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#define USBDP_TRSV_REG0550_LN1_MON_PCS_PORT_LOG_T16__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0550_LN1_MON_PCS_PORT_LOG_T16__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0550_LN1_MON_PCS_PORT_LOG_T16__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0550_LN1_MON_PCS_PORT_LOG_T16__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0551 (0x1544)
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#define USBDP_TRSV_REG0551_LN1_MON_PCS_PORT_LOG_T16__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0551_LN1_MON_PCS_PORT_LOG_T16__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0551_LN1_MON_PCS_PORT_LOG_T16__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0551_LN1_MON_PCS_PORT_LOG_T16__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0552 (0x1548)
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#define USBDP_TRSV_REG0552_LN1_MON_PCS_PORT_LOG_T16__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0552_LN1_MON_PCS_PORT_LOG_T16__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0552_LN1_MON_PCS_PORT_LOG_T16__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0552_LN1_MON_PCS_PORT_LOG_T16__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0553 (0x154C)
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#define USBDP_TRSV_REG0553_LN1_MON_PCS_PORT_LOG_T16__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0553_LN1_MON_PCS_PORT_LOG_T16__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0553_LN1_MON_PCS_PORT_LOG_T16__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0553_LN1_MON_PCS_PORT_LOG_T16__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0554 (0x1550)
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#define USBDP_TRSV_REG0554_LN1_MON_PCS_PORT_LOG_T17__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0554_LN1_MON_PCS_PORT_LOG_T17__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0554_LN1_MON_PCS_PORT_LOG_T17__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0554_LN1_MON_PCS_PORT_LOG_T17__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0555 (0x1554)
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#define USBDP_TRSV_REG0555_LN1_MON_PCS_PORT_LOG_T17__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0555_LN1_MON_PCS_PORT_LOG_T17__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0555_LN1_MON_PCS_PORT_LOG_T17__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0555_LN1_MON_PCS_PORT_LOG_T17__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0556 (0x1558)
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#define USBDP_TRSV_REG0556_LN1_MON_PCS_PORT_LOG_T17__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0556_LN1_MON_PCS_PORT_LOG_T17__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0556_LN1_MON_PCS_PORT_LOG_T17__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0556_LN1_MON_PCS_PORT_LOG_T17__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0557 (0x155C)
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#define USBDP_TRSV_REG0557_LN1_MON_PCS_PORT_LOG_T17__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0557_LN1_MON_PCS_PORT_LOG_T17__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0557_LN1_MON_PCS_PORT_LOG_T17__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0557_LN1_MON_PCS_PORT_LOG_T17__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0558 (0x1560)
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#define USBDP_TRSV_REG0558_LN1_MON_PCS_PORT_LOG_T18__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0558_LN1_MON_PCS_PORT_LOG_T18__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0558_LN1_MON_PCS_PORT_LOG_T18__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0558_LN1_MON_PCS_PORT_LOG_T18__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0559 (0x1564)
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#define USBDP_TRSV_REG0559_LN1_MON_PCS_PORT_LOG_T18__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0559_LN1_MON_PCS_PORT_LOG_T18__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0559_LN1_MON_PCS_PORT_LOG_T18__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0559_LN1_MON_PCS_PORT_LOG_T18__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055A (0x1568)
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#define USBDP_TRSV_REG055A_LN1_MON_PCS_PORT_LOG_T18__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055A_LN1_MON_PCS_PORT_LOG_T18__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055A_LN1_MON_PCS_PORT_LOG_T18__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055A_LN1_MON_PCS_PORT_LOG_T18__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055B (0x156C)
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#define USBDP_TRSV_REG055B_LN1_MON_PCS_PORT_LOG_T18__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055B_LN1_MON_PCS_PORT_LOG_T18__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055B_LN1_MON_PCS_PORT_LOG_T18__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055B_LN1_MON_PCS_PORT_LOG_T18__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055C (0x1570)
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#define USBDP_TRSV_REG055C_LN1_MON_PCS_PORT_LOG_T19__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055C_LN1_MON_PCS_PORT_LOG_T19__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055C_LN1_MON_PCS_PORT_LOG_T19__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055C_LN1_MON_PCS_PORT_LOG_T19__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055D (0x1574)
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#define USBDP_TRSV_REG055D_LN1_MON_PCS_PORT_LOG_T19__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055D_LN1_MON_PCS_PORT_LOG_T19__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055D_LN1_MON_PCS_PORT_LOG_T19__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055D_LN1_MON_PCS_PORT_LOG_T19__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055E (0x1578)
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#define USBDP_TRSV_REG055E_LN1_MON_PCS_PORT_LOG_T19__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055E_LN1_MON_PCS_PORT_LOG_T19__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055E_LN1_MON_PCS_PORT_LOG_T19__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055E_LN1_MON_PCS_PORT_LOG_T19__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG055F (0x157C)
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#define USBDP_TRSV_REG055F_LN1_MON_PCS_PORT_LOG_T19__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG055F_LN1_MON_PCS_PORT_LOG_T19__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG055F_LN1_MON_PCS_PORT_LOG_T19__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG055F_LN1_MON_PCS_PORT_LOG_T19__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0560 (0x1580)
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#define USBDP_TRSV_REG0560_LN1_MON_PCS_PORT_LOG_T20__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0560_LN1_MON_PCS_PORT_LOG_T20__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0560_LN1_MON_PCS_PORT_LOG_T20__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0560_LN1_MON_PCS_PORT_LOG_T20__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0561 (0x1584)
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#define USBDP_TRSV_REG0561_LN1_MON_PCS_PORT_LOG_T20__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0561_LN1_MON_PCS_PORT_LOG_T20__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0561_LN1_MON_PCS_PORT_LOG_T20__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0561_LN1_MON_PCS_PORT_LOG_T20__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0562 (0x1588)
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#define USBDP_TRSV_REG0562_LN1_MON_PCS_PORT_LOG_T20__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0562_LN1_MON_PCS_PORT_LOG_T20__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0562_LN1_MON_PCS_PORT_LOG_T20__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0562_LN1_MON_PCS_PORT_LOG_T20__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0563 (0x158C)
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#define USBDP_TRSV_REG0563_LN1_MON_PCS_PORT_LOG_T20__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0563_LN1_MON_PCS_PORT_LOG_T20__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0563_LN1_MON_PCS_PORT_LOG_T20__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0563_LN1_MON_PCS_PORT_LOG_T20__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0564 (0x1590)
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#define USBDP_TRSV_REG0564_LN1_MON_PCS_PORT_LOG_T21__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0564_LN1_MON_PCS_PORT_LOG_T21__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0564_LN1_MON_PCS_PORT_LOG_T21__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0564_LN1_MON_PCS_PORT_LOG_T21__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0565 (0x1594)
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#define USBDP_TRSV_REG0565_LN1_MON_PCS_PORT_LOG_T21__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0565_LN1_MON_PCS_PORT_LOG_T21__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0565_LN1_MON_PCS_PORT_LOG_T21__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0565_LN1_MON_PCS_PORT_LOG_T21__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0566 (0x1598)
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#define USBDP_TRSV_REG0566_LN1_MON_PCS_PORT_LOG_T21__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0566_LN1_MON_PCS_PORT_LOG_T21__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0566_LN1_MON_PCS_PORT_LOG_T21__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0566_LN1_MON_PCS_PORT_LOG_T21__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0567 (0x159C)
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#define USBDP_TRSV_REG0567_LN1_MON_PCS_PORT_LOG_T21__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0567_LN1_MON_PCS_PORT_LOG_T21__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0567_LN1_MON_PCS_PORT_LOG_T21__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0567_LN1_MON_PCS_PORT_LOG_T21__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0568 (0x15A0)
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#define USBDP_TRSV_REG0568_LN1_MON_PCS_PORT_LOG_T22__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0568_LN1_MON_PCS_PORT_LOG_T22__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0568_LN1_MON_PCS_PORT_LOG_T22__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0568_LN1_MON_PCS_PORT_LOG_T22__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0569 (0x15A4)
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#define USBDP_TRSV_REG0569_LN1_MON_PCS_PORT_LOG_T22__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0569_LN1_MON_PCS_PORT_LOG_T22__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0569_LN1_MON_PCS_PORT_LOG_T22__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0569_LN1_MON_PCS_PORT_LOG_T22__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056A (0x15A8)
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#define USBDP_TRSV_REG056A_LN1_MON_PCS_PORT_LOG_T22__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056A_LN1_MON_PCS_PORT_LOG_T22__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056A_LN1_MON_PCS_PORT_LOG_T22__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056A_LN1_MON_PCS_PORT_LOG_T22__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056B (0x15AC)
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#define USBDP_TRSV_REG056B_LN1_MON_PCS_PORT_LOG_T22__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056B_LN1_MON_PCS_PORT_LOG_T22__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056B_LN1_MON_PCS_PORT_LOG_T22__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056B_LN1_MON_PCS_PORT_LOG_T22__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056C (0x15B0)
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#define USBDP_TRSV_REG056C_LN1_MON_PCS_PORT_LOG_T23__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056C_LN1_MON_PCS_PORT_LOG_T23__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056C_LN1_MON_PCS_PORT_LOG_T23__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056C_LN1_MON_PCS_PORT_LOG_T23__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056D (0x15B4)
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#define USBDP_TRSV_REG056D_LN1_MON_PCS_PORT_LOG_T23__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056D_LN1_MON_PCS_PORT_LOG_T23__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056D_LN1_MON_PCS_PORT_LOG_T23__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056D_LN1_MON_PCS_PORT_LOG_T23__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056E (0x15B8)
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#define USBDP_TRSV_REG056E_LN1_MON_PCS_PORT_LOG_T23__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056E_LN1_MON_PCS_PORT_LOG_T23__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056E_LN1_MON_PCS_PORT_LOG_T23__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056E_LN1_MON_PCS_PORT_LOG_T23__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG056F (0x15BC)
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#define USBDP_TRSV_REG056F_LN1_MON_PCS_PORT_LOG_T23__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG056F_LN1_MON_PCS_PORT_LOG_T23__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG056F_LN1_MON_PCS_PORT_LOG_T23__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG056F_LN1_MON_PCS_PORT_LOG_T23__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0570 (0x15C0)
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#define USBDP_TRSV_REG0570_LN1_MON_PCS_PORT_LOG_T24__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0570_LN1_MON_PCS_PORT_LOG_T24__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0570_LN1_MON_PCS_PORT_LOG_T24__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0570_LN1_MON_PCS_PORT_LOG_T24__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0571 (0x15C4)
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#define USBDP_TRSV_REG0571_LN1_MON_PCS_PORT_LOG_T24__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0571_LN1_MON_PCS_PORT_LOG_T24__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0571_LN1_MON_PCS_PORT_LOG_T24__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0571_LN1_MON_PCS_PORT_LOG_T24__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0572 (0x15C8)
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#define USBDP_TRSV_REG0572_LN1_MON_PCS_PORT_LOG_T24__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0572_LN1_MON_PCS_PORT_LOG_T24__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0572_LN1_MON_PCS_PORT_LOG_T24__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0572_LN1_MON_PCS_PORT_LOG_T24__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0573 (0x15CC)
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#define USBDP_TRSV_REG0573_LN1_MON_PCS_PORT_LOG_T24__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0573_LN1_MON_PCS_PORT_LOG_T24__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0573_LN1_MON_PCS_PORT_LOG_T24__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0573_LN1_MON_PCS_PORT_LOG_T24__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0574 (0x15D0)
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#define USBDP_TRSV_REG0574_LN1_MON_PCS_PORT_LOG_T25__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0574_LN1_MON_PCS_PORT_LOG_T25__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0574_LN1_MON_PCS_PORT_LOG_T25__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0574_LN1_MON_PCS_PORT_LOG_T25__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0575 (0x15D4)
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#define USBDP_TRSV_REG0575_LN1_MON_PCS_PORT_LOG_T25__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0575_LN1_MON_PCS_PORT_LOG_T25__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0575_LN1_MON_PCS_PORT_LOG_T25__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0575_LN1_MON_PCS_PORT_LOG_T25__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0576 (0x15D8)
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#define USBDP_TRSV_REG0576_LN1_MON_PCS_PORT_LOG_T25__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0576_LN1_MON_PCS_PORT_LOG_T25__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0576_LN1_MON_PCS_PORT_LOG_T25__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0576_LN1_MON_PCS_PORT_LOG_T25__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0577 (0x15DC)
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#define USBDP_TRSV_REG0577_LN1_MON_PCS_PORT_LOG_T25__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0577_LN1_MON_PCS_PORT_LOG_T25__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0577_LN1_MON_PCS_PORT_LOG_T25__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0577_LN1_MON_PCS_PORT_LOG_T25__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0578 (0x15E0)
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#define USBDP_TRSV_REG0578_LN1_MON_PCS_PORT_LOG_T26__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0578_LN1_MON_PCS_PORT_LOG_T26__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0578_LN1_MON_PCS_PORT_LOG_T26__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0578_LN1_MON_PCS_PORT_LOG_T26__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0579 (0x15E4)
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#define USBDP_TRSV_REG0579_LN1_MON_PCS_PORT_LOG_T26__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0579_LN1_MON_PCS_PORT_LOG_T26__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0579_LN1_MON_PCS_PORT_LOG_T26__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0579_LN1_MON_PCS_PORT_LOG_T26__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057A (0x15E8)
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#define USBDP_TRSV_REG057A_LN1_MON_PCS_PORT_LOG_T26__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057A_LN1_MON_PCS_PORT_LOG_T26__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057A_LN1_MON_PCS_PORT_LOG_T26__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057A_LN1_MON_PCS_PORT_LOG_T26__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057B (0x15EC)
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#define USBDP_TRSV_REG057B_LN1_MON_PCS_PORT_LOG_T26__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057B_LN1_MON_PCS_PORT_LOG_T26__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057B_LN1_MON_PCS_PORT_LOG_T26__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057B_LN1_MON_PCS_PORT_LOG_T26__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057C (0x15F0)
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#define USBDP_TRSV_REG057C_LN1_MON_PCS_PORT_LOG_T27__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057C_LN1_MON_PCS_PORT_LOG_T27__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057C_LN1_MON_PCS_PORT_LOG_T27__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057C_LN1_MON_PCS_PORT_LOG_T27__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057D (0x15F4)
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#define USBDP_TRSV_REG057D_LN1_MON_PCS_PORT_LOG_T27__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057D_LN1_MON_PCS_PORT_LOG_T27__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057D_LN1_MON_PCS_PORT_LOG_T27__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057D_LN1_MON_PCS_PORT_LOG_T27__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057E (0x15F8)
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#define USBDP_TRSV_REG057E_LN1_MON_PCS_PORT_LOG_T27__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057E_LN1_MON_PCS_PORT_LOG_T27__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057E_LN1_MON_PCS_PORT_LOG_T27__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057E_LN1_MON_PCS_PORT_LOG_T27__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG057F (0x15FC)
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#define USBDP_TRSV_REG057F_LN1_MON_PCS_PORT_LOG_T27__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG057F_LN1_MON_PCS_PORT_LOG_T27__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG057F_LN1_MON_PCS_PORT_LOG_T27__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG057F_LN1_MON_PCS_PORT_LOG_T27__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0580 (0x1600)
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#define USBDP_TRSV_REG0580_LN1_MON_PCS_PORT_LOG_T28__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0580_LN1_MON_PCS_PORT_LOG_T28__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0580_LN1_MON_PCS_PORT_LOG_T28__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0580_LN1_MON_PCS_PORT_LOG_T28__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0581 (0x1604)
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#define USBDP_TRSV_REG0581_LN1_MON_PCS_PORT_LOG_T28__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0581_LN1_MON_PCS_PORT_LOG_T28__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0581_LN1_MON_PCS_PORT_LOG_T28__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0581_LN1_MON_PCS_PORT_LOG_T28__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0582 (0x1608)
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#define USBDP_TRSV_REG0582_LN1_MON_PCS_PORT_LOG_T28__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0582_LN1_MON_PCS_PORT_LOG_T28__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0582_LN1_MON_PCS_PORT_LOG_T28__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0582_LN1_MON_PCS_PORT_LOG_T28__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0583 (0x160C)
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#define USBDP_TRSV_REG0583_LN1_MON_PCS_PORT_LOG_T28__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0583_LN1_MON_PCS_PORT_LOG_T28__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0583_LN1_MON_PCS_PORT_LOG_T28__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0583_LN1_MON_PCS_PORT_LOG_T28__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0584 (0x1610)
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#define USBDP_TRSV_REG0584_LN1_MON_PCS_PORT_LOG_T29__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0584_LN1_MON_PCS_PORT_LOG_T29__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0584_LN1_MON_PCS_PORT_LOG_T29__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0584_LN1_MON_PCS_PORT_LOG_T29__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0585 (0x1614)
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#define USBDP_TRSV_REG0585_LN1_MON_PCS_PORT_LOG_T29__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0585_LN1_MON_PCS_PORT_LOG_T29__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0585_LN1_MON_PCS_PORT_LOG_T29__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0585_LN1_MON_PCS_PORT_LOG_T29__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0586 (0x1618)
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#define USBDP_TRSV_REG0586_LN1_MON_PCS_PORT_LOG_T29__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0586_LN1_MON_PCS_PORT_LOG_T29__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0586_LN1_MON_PCS_PORT_LOG_T29__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0586_LN1_MON_PCS_PORT_LOG_T29__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0587 (0x161C)
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#define USBDP_TRSV_REG0587_LN1_MON_PCS_PORT_LOG_T29__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0587_LN1_MON_PCS_PORT_LOG_T29__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0587_LN1_MON_PCS_PORT_LOG_T29__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0587_LN1_MON_PCS_PORT_LOG_T29__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0588 (0x1620)
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#define USBDP_TRSV_REG0588_LN1_MON_PCS_PORT_LOG_T30__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0588_LN1_MON_PCS_PORT_LOG_T30__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0588_LN1_MON_PCS_PORT_LOG_T30__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0588_LN1_MON_PCS_PORT_LOG_T30__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0589 (0x1624)
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#define USBDP_TRSV_REG0589_LN1_MON_PCS_PORT_LOG_T30__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0589_LN1_MON_PCS_PORT_LOG_T30__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0589_LN1_MON_PCS_PORT_LOG_T30__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0589_LN1_MON_PCS_PORT_LOG_T30__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058A (0x1628)
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#define USBDP_TRSV_REG058A_LN1_MON_PCS_PORT_LOG_T30__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058A_LN1_MON_PCS_PORT_LOG_T30__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058A_LN1_MON_PCS_PORT_LOG_T30__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058A_LN1_MON_PCS_PORT_LOG_T30__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058B (0x162C)
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#define USBDP_TRSV_REG058B_LN1_MON_PCS_PORT_LOG_T30__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058B_LN1_MON_PCS_PORT_LOG_T30__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058B_LN1_MON_PCS_PORT_LOG_T30__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058B_LN1_MON_PCS_PORT_LOG_T30__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058C (0x1630)
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#define USBDP_TRSV_REG058C_LN1_MON_PCS_PORT_LOG_T31__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058C_LN1_MON_PCS_PORT_LOG_T31__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058C_LN1_MON_PCS_PORT_LOG_T31__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058C_LN1_MON_PCS_PORT_LOG_T31__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058D (0x1634)
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#define USBDP_TRSV_REG058D_LN1_MON_PCS_PORT_LOG_T31__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058D_LN1_MON_PCS_PORT_LOG_T31__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058D_LN1_MON_PCS_PORT_LOG_T31__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058D_LN1_MON_PCS_PORT_LOG_T31__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058E (0x1638)
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#define USBDP_TRSV_REG058E_LN1_MON_PCS_PORT_LOG_T31__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058E_LN1_MON_PCS_PORT_LOG_T31__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058E_LN1_MON_PCS_PORT_LOG_T31__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058E_LN1_MON_PCS_PORT_LOG_T31__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG058F (0x163C)
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#define USBDP_TRSV_REG058F_LN1_MON_PCS_PORT_LOG_T31__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG058F_LN1_MON_PCS_PORT_LOG_T31__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG058F_LN1_MON_PCS_PORT_LOG_T31__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG058F_LN1_MON_PCS_PORT_LOG_T31__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0600 (0x1800)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0600_LN2_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0600_OVRD_LN2_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0600_LN2_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0601 (0x1804)
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#define USBDP_TRSV_REG0601_OVRD_LN2_TX_DRV_EI_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0601_OVRD_LN2_TX_DRV_EI_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0601_OVRD_LN2_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0601_OVRD_LN2_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0601_LN2_TX_DRV_EI_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0602 (0x1808)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0602_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0603 (0x180C)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0603_LN2_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_VREF_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_VREF_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_FB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_FB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_FB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_FB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0603_LN2_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0604 (0x1810)
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#define USBDP_TRSV_REG0604_OVRD_LN2_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0604_OVRD_LN2_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0604_OVRD_LN2_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0604_OVRD_LN2_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0604_LN2_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0604_LN2_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0604_LN2_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0604_LN2_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0605 (0x1814)
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#define USBDP_TRSV_REG0605_OVRD_LN2_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0605_OVRD_LN2_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0605_OVRD_LN2_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0605_OVRD_LN2_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0605_LN2_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0605_LN2_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0605_LN2_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0605_LN2_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0606 (0x1818)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0606_OVRD_LN2_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0606_LN2_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0607 (0x181C)
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#define USBDP_TRSV_REG0607_OVRD_LN2_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0607_OVRD_LN2_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0607_OVRD_LN2_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0607_OVRD_LN2_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0607_LN2_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0607_LN2_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0607_LN2_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0607_LN2_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_ACCDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_ACCDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_ACCDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0607_LN2_ANA_TX_DRV_ACCDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0608 (0x1820)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_POL_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_POL_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_POL_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_POL_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_CTRL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_CTRL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_ACCDRV_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_HSCLK_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_HSCLK_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_HSCLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_HSCLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0608_LN2_ANA_TX_DRV_PLL_REF_MON_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0609 (0x1824)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0609_LN2_TX_JEQ_CAP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060A (0x1828)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060A_LN2_TX_JEQ_CAP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060B (0x182C)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060B_LN2_TX_JEQ_CAP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060C (0x1830)
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#define USBDP_TRSV_REG060C_LN2_ANA_TX_JEQ_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG060C_LN2_ANA_TX_JEQ_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG060C_LN2_ANA_TX_JEQ_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG060C_LN2_ANA_TX_JEQ_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG060C_LN2_TX_JEQ_EVEN_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060C_LN2_TX_JEQ_EVEN_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060C_LN2_TX_JEQ_EVEN_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060C_LN2_TX_JEQ_EVEN_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060D (0x1834)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060D_LN2_TX_JEQ_EVEN_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060E (0x1838)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060E_LN2_TX_JEQ_EVEN_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG060F (0x183C)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_EVEN_CTRL_HBR3_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_EVEN_CTRL_HBR3_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_EVEN_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_EVEN_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_ODD_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_ODD_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_ODD_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG060F_LN2_TX_JEQ_ODD_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0610 (0x1840)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0610_LN2_TX_JEQ_ODD_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0611 (0x1844)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0611_LN2_TX_JEQ_ODD_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0612 (0x1848)
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#define USBDP_TRSV_REG0612_LN2_TX_JEQ_ODD_CTRL_HBR3_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG0612_LN2_TX_JEQ_ODD_CTRL_HBR3_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG0612_LN2_TX_JEQ_ODD_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG0612_LN2_TX_JEQ_ODD_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG0612_OVRD_LN2_TX_RCAL_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0612_OVRD_LN2_TX_RCAL_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0612_OVRD_LN2_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0612_OVRD_LN2_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0612_LN2_TX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0612_LN2_TX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0612_LN2_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0612_LN2_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0612_LN2_ANA_TX_RTERM_42P5_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0612_LN2_ANA_TX_RTERM_42P5_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0612_LN2_ANA_TX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0612_LN2_ANA_TX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0613 (0x184C)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0613_OVRD_LN2_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_COMP_I_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_COMP_I_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_COMP_I_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_COMP_I_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_VREF_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_VREF_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0613_LN2_ANA_TX_RXD_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0613_LN2_TX_SER_40BIT_EN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_SER_40BIT_EN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_SER_40BIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0613_LN2_TX_SER_40BIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0614 (0x1850)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_40BIT_EN_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0614_OVRD_LN2_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0614_OVRD_LN2_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0614_OVRD_LN2_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0614_OVRD_LN2_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_RATE_SEL_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_RATE_SEL_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_RATE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0614_LN2_TX_SER_RATE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0615 (0x1854)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_RATE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0615_OVRD_LN2_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0615_OVRD_LN2_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0615_OVRD_LN2_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0615_OVRD_LN2_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0615_LN2_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0615_LN2_ANA_TX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0615_LN2_ANA_TX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0615_LN2_ANA_TX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0615_LN2_ANA_TX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0616 (0x1858)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_SER_TXCLK_INV_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_SER_TXCLK_INV_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_SER_TXCLK_INV_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_SER_TXCLK_INV_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_TO_DIG_BYTE_CLK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_TO_DIG_BYTE_CLK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_TO_DIG_BYTE_CLK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0616_LN2_ANA_TX_TO_DIG_BYTE_CLK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0616_OVRD_LN2_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0616_OVRD_LN2_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0616_OVRD_LN2_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0616_OVRD_LN2_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SSP_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SSP_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_RBR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_RBR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_HBR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_HBR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0616_LN2_TX_LANE_LC_RO_CLK_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0617 (0x185C)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR2_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR2_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR3_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR3_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_LC_RO_CLK_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0617_LN2_ANA_TX_LANE_DIV2_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_SER_VREG_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_SER_VREG_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0617_OVRD_LN2_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_SER_VREG_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_SER_VREG_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0617_LN2_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0618 (0x1860)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0618_OVRD_LN2_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0618_OVRD_LN2_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0618_OVRD_LN2_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0618_OVRD_LN2_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0618_LN2_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0618_LN2_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0618_LN2_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0618_LN2_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_LADDER_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_LADDER_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0618_LN2_ANA_TX_SER_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0619 (0x1864)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_I_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_I_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_I_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_I_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0619_LN2_ANA_TX_SER_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG061A (0x1868)
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#define USBDP_TRSV_REG061A_LN2_TX_DCC_IN_BUF_STR_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG061A_LN2_TX_DCC_IN_BUF_STR_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG061A_LN2_TX_DCC_IN_BUF_STR_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG061A_LN2_TX_DCC_IN_BUF_STR_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG061B (0x186C)
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#define USBDP_TRSV_REG061B_LN2_TX_DCC_IN_BUF_STR_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG061B_LN2_TX_DCC_IN_BUF_STR_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG061B_LN2_TX_DCC_IN_BUF_STR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG061B_LN2_TX_DCC_IN_BUF_STR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG061C (0x1870)
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#define USBDP_TRSV_REG061C_LN2_TX_DCC_IN_BUF_STR_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG061C_LN2_TX_DCC_IN_BUF_STR_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG061C_LN2_TX_DCC_IN_BUF_STR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG061C_LN2_TX_DCC_IN_BUF_STR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG061D (0x1874)
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#define USBDP_TRSV_REG061D_LN2_TX_DCC_IN_BUF_STR_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG061D_LN2_TX_DCC_IN_BUF_STR_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG061D_LN2_TX_DCC_IN_BUF_STR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG061D_LN2_TX_DCC_IN_BUF_STR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG061E (0x1878)
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#define USBDP_TRSV_REG061E_LN2_TX_DCC_IN_BUF_STR_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG061E_LN2_TX_DCC_IN_BUF_STR_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG061E_LN2_TX_DCC_IN_BUF_STR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG061E_LN2_TX_DCC_IN_BUF_STR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG061F (0x187C)
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#define USBDP_TRSV_REG061F_LN2_TX_DCC_IN_BUF_STR_HBR3_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG061F_LN2_TX_DCC_IN_BUF_STR_HBR3_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG061F_LN2_TX_DCC_IN_BUF_STR_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG061F_LN2_TX_DCC_IN_BUF_STR_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG061F_LN2_ANA_TX_TO_RX_CLK_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG061F_LN2_ANA_TX_TO_RX_CLK_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG061F_LN2_ANA_TX_TO_RX_CLK_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG061F_LN2_ANA_TX_TO_RX_CLK_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0620 (0x1880)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_SEL_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_SEL_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_SLB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_SLB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_LLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_LLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_LLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0620_LN2_ANA_TX_LLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0621 (0x1884)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_SRLB_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_SRLB_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0621_OVRD_LN2_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0621_LN2_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_AFC_FORCE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_AFC_FORCE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_AFC_FORCE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_AFC_FORCE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_CLK_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_CLK_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0621_LN2_ANA_TX_LFPS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0622 (0x1888)
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#define USBDP_TRSV_REG0622_OVRD_LN2_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0622_OVRD_LN2_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0622_OVRD_LN2_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0622_OVRD_LN2_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0622_LN2_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0623 (0x188C)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0623_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0624 (0x1890)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0624_LN2_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0624_OVRD_LN2_TX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0624_OVRD_LN2_TX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0624_OVRD_LN2_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0624_OVRD_LN2_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0624_LN2_TX_INIT_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0624_LN2_TX_INIT_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0624_LN2_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0624_LN2_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0625 (0x1894)
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#define USBDP_TRSV_REG0625_LN2_ANA_TX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0625_LN2_ANA_TX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0625_LN2_ANA_TX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0625_LN2_ANA_TX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0626 (0x1898)
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#define USBDP_TRSV_REG0626_LN2_TX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0626_LN2_TX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0626_LN2_TX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0626_LN2_TX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0627 (0x189C)
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#define USBDP_TRSV_REG0627_LN2_TX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0627_LN2_TX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0627_LN2_TX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0627_LN2_TX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0628 (0x18A0)
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#define USBDP_TRSV_REG0628_LN2_TX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0628_LN2_TX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0628_LN2_TX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0628_LN2_TX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0629 (0x18A4)
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#define USBDP_TRSV_REG0629_LN2_TX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0629_LN2_TX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0629_LN2_TX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0629_LN2_TX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG062A (0x18A8)
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#define USBDP_TRSV_REG062A_LN2_TX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG062A_LN2_TX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG062A_LN2_TX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG062A_LN2_TX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG062B (0x18AC)
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#define USBDP_TRSV_REG062B_LN2_TX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG062B_LN2_TX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG062B_LN2_TX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG062B_LN2_TX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG062C (0x18B0)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG062C_OVRD_LN2_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG062C_LN2_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG062D (0x18B4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG062D_LN2_RX_CDR_REFDIV_SEL_PLL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG062E (0x18B8)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG062E_LN2_RX_CDR_REFDIV_SEL_PLL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG062F (0x18BC)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG062F_LN2_RX_CDR_REFDIV_SEL_PLL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0630 (0x18C0)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0630_LN2_RX_CDR_REFDIV_SEL_DATA_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0631 (0x18C4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0631_LN2_RX_CDR_REFDIV_SEL_DATA_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0632 (0x18C8)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0632_LN2_RX_CDR_REFDIV_SEL_DATA_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0633 (0x18CC)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0633_LN2_RX_CDR_MDIV_SEL_PLL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0634 (0x18D0)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0634_LN2_RX_CDR_MDIV_SEL_PLL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0635 (0x18D4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0635_LN2_RX_CDR_MDIV_SEL_PLL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0636 (0x18D8)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0636_LN2_RX_CDR_MDIV_SEL_DATA_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0637 (0x18DC)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0637_LN2_RX_CDR_MDIV_SEL_DATA_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0638 (0x18E0)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0638_LN2_RX_CDR_MDIV_SEL_DATA_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0639 (0x18E4)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_BW_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_BW_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_BW_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_BW_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_REFDIV_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_REFDIV_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_REFDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_REFDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_REFDIV_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_REFDIV_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_REFDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_REFDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_MDIV_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_MDIV_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0639_OVRD_LN2_RX_CDR_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_MDIV_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_MDIV_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_MDIV_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0639_LN2_RX_CDR_MDIV_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_DES_RXCLK_INV_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_DES_RXCLK_INV_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_DES_RXCLK_INV_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_DES_RXCLK_INV_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_AFC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_AFC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_AFC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0639_LN2_ANA_RX_CDR_AFC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG063A (0x18E8)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_TEST_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_TEST_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_TEST_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_TEST_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_FORCE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_FORCE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_FORCE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_FORCE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG063A_LN2_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG063B (0x18EC)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_CTRL_RESERVED_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_CTRL_RESERVED_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_E_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_E_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_E_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_E_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_O_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_O_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_O_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_O_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_VREG_IN_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_VREG_IN_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_VREG_IN_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG063B_LN2_ANA_RX_CDR_CP_VREG_IN_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG063B_OVRD_LN2_RX_CDR_CP_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG063B_OVRD_LN2_RX_CDR_CP_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG063B_OVRD_LN2_RX_CDR_CP_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG063B_OVRD_LN2_RX_CDR_CP_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG063B_LN2_RX_CDR_CP_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG063B_LN2_RX_CDR_CP_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG063B_LN2_RX_CDR_CP_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG063B_LN2_RX_CDR_CP_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG063C (0x18F0)
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#define USBDP_TRSV_REG063C_OVRD_LN2_RX_CDR_FBB_CAL_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG063C_OVRD_LN2_RX_CDR_FBB_CAL_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG063C_OVRD_LN2_RX_CDR_FBB_CAL_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG063C_OVRD_LN2_RX_CDR_FBB_CAL_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_FBB_CAL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_FBB_CAL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_FBB_CAL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_FBB_CAL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_O_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_O_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_O_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_O_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_E_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_E_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_E_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG063C_LN2_ANA_RX_CDR_FBB_E_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SSP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SSP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG063C_LN2_RX_CDR_INTEG_PULSE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG063D (0x18F4)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_RBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_RBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR2_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR2_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR3_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR3_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG063D_LN2_RX_CDR_INTEG_PULSE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG063E (0x18F8)
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#define USBDP_TRSV_REG063E_OVRD_LN2_RX_CDR_VCO_STARTUP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG063E_OVRD_LN2_RX_CDR_VCO_STARTUP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG063E_OVRD_LN2_RX_CDR_VCO_STARTUP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG063E_OVRD_LN2_RX_CDR_VCO_STARTUP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG063E_LN2_RX_CDR_VCO_STARTUP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG063E_LN2_RX_CDR_VCO_STARTUP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG063E_LN2_RX_CDR_VCO_STARTUP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG063E_LN2_RX_CDR_VCO_STARTUP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG063E_LN2_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG063E_LN2_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG063E_LN2_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG063E_LN2_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG063F (0x18FC)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG063F_LN2_RX_CDR_VCO_FREQ_BOOST_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0640 (0x1900)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0640_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0641 (0x1904)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0641_LN2_RX_CDR_VCO_FREQ_BOOST_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0642 (0x1908)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0642_LN2_RX_CDR_CCO_BAND_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0643 (0x190C)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0643_LN2_RX_CDR_CCO_BAND_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0643_LN2_ANA_RX_CDR_CCO_VREG_R_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0643_LN2_ANA_RX_CDR_CCO_VREG_R_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0643_LN2_ANA_RX_CDR_CCO_VREG_R_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0643_LN2_ANA_RX_CDR_CCO_VREG_R_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0644 (0x1910)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_DAC_OFS_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_DAC_OFS_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_DAC_OFS_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0644_OVRD_LN2_RX_CTLE_OC_DAC_OFS_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_DAC_OFS_CTRL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_DAC_OFS_CTRL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_DAC_OFS_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0644_LN2_RX_CTLE_OC_DAC_OFS_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0645 (0x1914)
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#define USBDP_TRSV_REG0645_OVRD_LN2_RX_CTLE_OC_DAC_CODE_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0645_OVRD_LN2_RX_CTLE_OC_DAC_CODE_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0645_OVRD_LN2_RX_CTLE_OC_DAC_CODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0645_OVRD_LN2_RX_CTLE_OC_DAC_CODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0646 (0x1918)
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#define USBDP_TRSV_REG0646_LN2_RX_CTLE_OC_DAC_CODE_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0646_LN2_RX_CTLE_OC_DAC_CODE_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0646_LN2_RX_CTLE_OC_DAC_CODE_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0646_LN2_RX_CTLE_OC_DAC_CODE_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0647 (0x191C)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0647_LN2_RX_CTLE_HF_RL_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0648 (0x1920)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0648_LN2_RX_CTLE_HF_RL_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0649 (0x1924)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR2_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR2_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR3_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR3_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0649_LN2_RX_CTLE_HF_RL_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0649_LN2_ANA_RX_CTLE_OC_DAC_PULLUP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0649_LN2_ANA_RX_CTLE_OC_DAC_PULLUP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0649_LN2_ANA_RX_CTLE_OC_DAC_PULLUP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0649_LN2_ANA_RX_CTLE_OC_DAC_PULLUP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG064A (0x1928)
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#define USBDP_TRSV_REG064A_LN2_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG064A_LN2_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG064A_LN2_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG064A_LN2_ANA_RX_CTLE_OC_DAC_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG064A_LN2_RX_CTLE_HF_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG064B (0x192C)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG064B_LN2_RX_CTLE_HF_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG064C (0x1930)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR2_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR2_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR3_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR3_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_CS_CTRL_SP_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_CS_CTRL_SP_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_CS_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG064C_LN2_RX_CTLE_HF_CS_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG064D (0x1934)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_SSP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_SSP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_RBR_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_RBR_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR2_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR2_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG064D_LN2_RX_CTLE_HF_CS_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG064E (0x1938)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_HF_CS_CTRL_HBR3_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_HF_CS_CTRL_HBR3_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_HF_CS_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_HF_CS_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG064E_LN2_ANA_RX_CTLE_BIAS_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG064E_LN2_ANA_RX_CTLE_BIAS_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG064E_LN2_ANA_RX_CTLE_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG064E_LN2_ANA_RX_CTLE_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_VGA_I_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_VGA_I_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_VGA_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG064E_LN2_RX_CTLE_VGA_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG064F (0x193C)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG064F_LN2_RX_CTLE_VGA_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0650 (0x1940)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0650_LN2_RX_CTLE_VGA_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0651 (0x1944)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_I_CTRL_HBR3_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_I_CTRL_HBR3_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_RL_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_RL_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_RL_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0651_LN2_RX_CTLE_VGA_RL_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0652 (0x1948)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0652_LN2_RX_CTLE_VGA_RL_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0653 (0x194C)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0653_LN2_RX_CTLE_VGA_RL_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0654 (0x1950)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_VGA_RL_CTRL_HBR3_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_VGA_RL_CTRL_HBR3_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_VGA_RL_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_VGA_RL_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG0654_LN2_ANA_RX_CTLE_TIE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0654_LN2_ANA_RX_CTLE_TIE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0654_LN2_ANA_RX_CTLE_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0654_LN2_ANA_RX_CTLE_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_CTLE_DFE_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_CTLE_DFE_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_CTLE_DFE_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_CTLE_DFE_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_DFE_OC_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_DFE_OC_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_DFE_OC_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_CTLE_DFE_OC_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_PEQ_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_PEQ_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_PEQ_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0654_OVRD_LN2_RX_PEQ_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_PEQ_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_PEQ_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_PEQ_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0654_LN2_RX_PEQ_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0655 (0x1954)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0655_LN2_RX_PEQ_VCM_I_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0656 (0x1958)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0656_LN2_RX_PEQ_VCM_I_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0657 (0x195C)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR2_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR2_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0657_LN2_RX_PEQ_VCM_I_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0658 (0x1960)
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#define USBDP_TRSV_REG0658_OVRD_LN2_RX_PEQ_P_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0658_OVRD_LN2_RX_PEQ_P_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0658_OVRD_LN2_RX_PEQ_P_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0658_OVRD_LN2_RX_PEQ_P_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0659 (0x1964)
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#define USBDP_TRSV_REG0659_LN2_RX_PEQ_P_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0659_LN2_RX_PEQ_P_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0659_LN2_RX_PEQ_P_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0659_LN2_RX_PEQ_P_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG065A (0x1968)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_PULLDN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_PULLDN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_PULLDN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_PULLDN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG065A_LN2_ANA_RX_PEQ_VCM_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG065A_LN2_RX_PEQ_Z_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG065B (0x196C)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG065B_LN2_RX_PEQ_Z_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG065B_OVRD_LN2_RX_DES_DATA_CLEAR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG065B_OVRD_LN2_RX_DES_DATA_CLEAR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG065B_OVRD_LN2_RX_DES_DATA_CLEAR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG065B_OVRD_LN2_RX_DES_DATA_CLEAR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG065B_LN2_RX_DES_DATA_CLEAR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG065B_LN2_RX_DES_DATA_CLEAR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG065B_LN2_RX_DES_DATA_CLEAR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG065B_LN2_RX_DES_DATA_CLEAR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG065C (0x1970)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG065C_LN2_RX_DES_DATA_WIDTH_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG065D (0x1974)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_DATA_WIDTH_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG065D_OVRD_LN2_RX_DES_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG065D_OVRD_LN2_RX_DES_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG065D_OVRD_LN2_RX_DES_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG065D_OVRD_LN2_RX_DES_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG065D_LN2_RX_DES_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG065D_LN2_ANA_RX_DES_NON_DATA_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG065D_LN2_ANA_RX_DES_NON_DATA_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG065D_LN2_ANA_RX_DES_NON_DATA_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG065D_LN2_ANA_RX_DES_NON_DATA_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG065E (0x1978)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_NON_DATA_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_NON_DATA_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_NON_DATA_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_NON_DATA_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_NON_DATA_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_NON_DATA_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_NON_DATA_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_NON_DATA_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG065E_OVRD_LN2_RX_DES_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG065E_LN2_RX_DES_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG065E_LN2_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG065E_LN2_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG065E_LN2_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG065E_LN2_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG065F (0x197C)
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#define USBDP_TRSV_REG065F_OVRD_LN2_RX_DFE_OC_SA_ERR_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG065F_OVRD_LN2_RX_DFE_OC_SA_ERR_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG065F_OVRD_LN2_RX_DFE_OC_SA_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG065F_OVRD_LN2_RX_DFE_OC_SA_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0660 (0x1980)
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#define USBDP_TRSV_REG0660_LN2_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0660_LN2_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0660_LN2_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0660_LN2_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0661 (0x1984)
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#define USBDP_TRSV_REG0661_OVRD_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0661_OVRD_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0661_OVRD_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0661_OVRD_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0662 (0x1988)
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#define USBDP_TRSV_REG0662_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0662_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0662_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0662_LN2_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0663 (0x198C)
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#define USBDP_TRSV_REG0663_OVRD_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0663_OVRD_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0663_OVRD_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0663_OVRD_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0664 (0x1990)
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#define USBDP_TRSV_REG0664_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0664_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0664_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0664_LN2_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0665 (0x1994)
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#define USBDP_TRSV_REG0665_OVRD_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0665_OVRD_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0665_OVRD_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0665_OVRD_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0666 (0x1998)
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#define USBDP_TRSV_REG0666_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0666_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0666_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0666_LN2_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0667 (0x199C)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_ADAP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_ADAP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_MAIN_ADD_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_MAIN_ADD_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_MAIN_ADD_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_MAIN_ADD_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_SUB_ADD_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_SUB_ADD_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_SUB_ADD_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0667_LN2_ANA_RX_DFE_SUB_ADD_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_EOM_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_EOM_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_EOM_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0667_OVRD_LN2_RX_DFE_EOM_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_EOM_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_EOM_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_EOM_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0667_LN2_RX_DFE_EOM_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0668 (0x19A0)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0668_LN2_RX_DFE_EOM_PI_DIV_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0669 (0x19A4)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0669_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG066A (0x19A8)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR2_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR2_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG066A_LN2_RX_DFE_EOM_PI_DIV_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG066B (0x19AC)
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#define USBDP_TRSV_REG066B_LN2_ANA_RX_DFE_EOM_PI_STR_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG066B_LN2_ANA_RX_DFE_EOM_PI_STR_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG066B_LN2_ANA_RX_DFE_EOM_PI_STR_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG066B_LN2_ANA_RX_DFE_EOM_PI_STR_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG066C (0x19B0)
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#define USBDP_TRSV_REG066C_OVRD_LN2_RX_DFE_OC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG066C_OVRD_LN2_RX_DFE_OC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG066C_OVRD_LN2_RX_DFE_OC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG066C_OVRD_LN2_RX_DFE_OC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG066D (0x19B4)
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#define USBDP_TRSV_REG066D_LN2_RX_DFE_OC_ADDER_EVEN_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG066D_LN2_RX_DFE_OC_ADDER_EVEN_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG066D_LN2_RX_DFE_OC_ADDER_EVEN_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG066D_LN2_RX_DFE_OC_ADDER_EVEN_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG066E (0x19B8)
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#define USBDP_TRSV_REG066E_OVRD_LN2_RX_DFE_OC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG066E_OVRD_LN2_RX_DFE_OC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG066E_OVRD_LN2_RX_DFE_OC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG066E_OVRD_LN2_RX_DFE_OC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG066F (0x19BC)
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#define USBDP_TRSV_REG066F_LN2_RX_DFE_OC_ADDER_ODD_CODE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG066F_LN2_RX_DFE_OC_ADDER_ODD_CODE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG066F_LN2_RX_DFE_OC_ADDER_ODD_CODE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG066F_LN2_RX_DFE_OC_ADDER_ODD_CODE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0670 (0x19C0)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0670_OVRD_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0670_LN2_RX_DFE_OC_DAC_ADDER_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0671 (0x19C4)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0671_OVRD_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0671_LN2_RX_DFE_OC_DAC_EDGE_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0672 (0x19C8)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_EVEN_CODE_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0672_OVRD_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0672_LN2_RX_DFE_OC_DAC_ERR_ODD_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0673 (0x19CC)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_EVEN_OC_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_ODD_OC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_ODD_OC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_ODD_OC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_DATA_ODD_OC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_ODD_OC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_ODD_OC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_ODD_OC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_DATA_ODD_OC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_EDGE_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_EDGE_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_EDGE_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_EDGE_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_EDGE_OC_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_EDGE_OC_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_EDGE_OC_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_EDGE_OC_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_ERR_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_ERR_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_ERR_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0673_OVRD_LN2_RX_DFE_SA_ERR_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_ERR_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_ERR_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_ERR_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0673_LN2_RX_DFE_SA_ERR_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0674 (0x19D0)
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#define USBDP_TRSV_REG0674_OVRD_LN2_RX_DFE_VREF_ODD_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0674_OVRD_LN2_RX_DFE_VREF_ODD_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0674_OVRD_LN2_RX_DFE_VREF_ODD_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0674_OVRD_LN2_RX_DFE_VREF_ODD_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0675 (0x19D4)
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#define USBDP_TRSV_REG0675_LN2_RX_DFE_VREF_ODD_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0675_LN2_RX_DFE_VREF_ODD_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0675_LN2_RX_DFE_VREF_ODD_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0675_LN2_RX_DFE_VREF_ODD_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0676 (0x19D8)
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#define USBDP_TRSV_REG0676_OVRD_LN2_RX_DFE_VREF_EVEN_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0676_OVRD_LN2_RX_DFE_VREF_EVEN_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0676_OVRD_LN2_RX_DFE_VREF_EVEN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0676_OVRD_LN2_RX_DFE_VREF_EVEN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0677 (0x19DC)
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#define USBDP_TRSV_REG0677_LN2_RX_DFE_VREF_EVEN_CTRL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0677_LN2_RX_DFE_VREF_EVEN_CTRL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0677_LN2_RX_DFE_VREF_EVEN_CTRL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0677_LN2_RX_DFE_VREF_EVEN_CTRL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0678 (0x19E0)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_OUT_PULLUP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_OUT_PULLUP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_OUT_PULLUP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_OUT_PULLUP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_VCM_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_VCM_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_VCM_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_DAC_VCM_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_VREF_DAC_LSB_CTRL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_VREF_DAC_LSB_CTRL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_VREF_DAC_LSB_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_VREF_DAC_LSB_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_OC_DAC_LSB_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_OC_DAC_LSB_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_OC_DAC_LSB_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0678_LN2_ANA_RX_DFE_OC_DAC_LSB_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0679 (0x19E4)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_EOM_CLK_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_EOM_CLK_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_EOM_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_EOM_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_MADD_V_TIE_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_MADD_V_TIE_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_MADD_V_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0679_LN2_ANA_RX_DFE_MADD_V_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SSP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SSP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0679_LN2_RX_DFE_MADD_RL_CONT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG067A (0x19E8)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_RBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_RBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_RBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_RBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_HBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_HBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG067A_LN2_RX_DFE_MADD_RL_CONT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG067B (0x19EC)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR2_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR2_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR3_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR3_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG067B_LN2_RX_DFE_MADD_RL_CONT_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG067B_LN2_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG067B_LN2_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG067B_LN2_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG067B_LN2_ANA_RX_DFE_MADD_PBIAS_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG067C (0x19F0)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_V_TIE_SEL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_V_TIE_SEL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_V_TIE_SEL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_V_TIE_SEL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_RL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_RL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_RL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_RL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_BIAS_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_BIAS_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_SADD_ALWAYS_OFF_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_VREG_OUT_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_VREG_OUT_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_VREG_OUT_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG067C_LN2_ANA_RX_DFE_VREG_OUT_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG067C_OVRD_LN2_RX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG067C_OVRD_LN2_RX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG067C_OVRD_LN2_RX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG067C_OVRD_LN2_RX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG067C_LN2_RX_RCAL_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG067C_LN2_RX_RCAL_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG067C_LN2_RX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG067C_LN2_RX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG067D (0x19F4)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_42P5_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_42P5_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSN_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSN_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSN_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSN_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSP_CTRL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSP_CTRL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSP_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG067D_LN2_ANA_RX_RTERM_OFSP_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_PATH_CTRL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_PATH_CTRL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_PATH_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG067D_OVRD_LN2_RX_RTERM_PATH_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_PATH_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_PATH_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_PATH_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG067D_LN2_RX_RTERM_PATH_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG067E (0x19F8)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_DIFN_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_DIFN_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_DIFN_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG067E_OVRD_LN2_RX_SQHS_DIFN_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_DIFN_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_DIFN_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_DIFN_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG067E_LN2_RX_SQHS_DIFN_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG067F (0x19FC)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFN_OC_CODE_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFN_OC_CODE_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFN_OC_CODE_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFN_OC_CODE_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFN_OC_CODE_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFN_OC_CODE_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFN_OC_CODE_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFN_OC_CODE_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG067F_LN2_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG067F_LN2_ANA_RX_SQHS_DIFN_SKEWBUF_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG067F_LN2_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG067F_LN2_ANA_RX_SQHS_DIFN_SKEWBUF_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFP_OC_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFP_OC_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFP_OC_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG067F_OVRD_LN2_RX_SQHS_DIFP_OC_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFP_OC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFP_OC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFP_OC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG067F_LN2_RX_SQHS_DIFP_OC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0680 (0x1A00)
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#define USBDP_TRSV_REG0680_OVRD_LN2_RX_SQHS_DIFP_OC_CODE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0680_OVRD_LN2_RX_SQHS_DIFP_OC_CODE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0680_OVRD_LN2_RX_SQHS_DIFP_OC_CODE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0680_OVRD_LN2_RX_SQHS_DIFP_OC_CODE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0680_LN2_RX_SQHS_DIFP_OC_CODE_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0680_LN2_RX_SQHS_DIFP_OC_CODE_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0680_LN2_RX_SQHS_DIFP_OC_CODE_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0680_LN2_RX_SQHS_DIFP_OC_CODE_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_DIFP_SKEWBUF_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_DIFP_SKEWBUF_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_SKEW_DEFAULT_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_SKEW_DEFAULT_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_SKEW_DEFAULT_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0680_LN2_ANA_RX_SQHS_SKEW_DEFAULT_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0681 (0x1A04)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_TH_CTRL_RESERVED_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_TH_CTRL_RESERVED_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_TH_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_TH_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_FILTER_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_FILTER_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_FILTER_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_FILTER_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_LPF_BW_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_LPF_BW_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_LPF_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_LPF_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_VREF_SUPPLY_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_VREF_SUPPLY_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_VREF_SUPPLY_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0681_LN2_ANA_RX_SQHS_VREF_SUPPLY_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0682 (0x1A08)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SKEW_BUF_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQHS_SCL2MOS_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQLS_IN_LPF_CTRL_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQLS_IN_LPF_CTRL_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQLS_IN_LPF_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG0682_LN2_ANA_RX_SQLS_IN_LPF_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG0682_OVRD_LN2_RX_SQDIG_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0682_OVRD_LN2_RX_SQDIG_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0682_OVRD_LN2_RX_SQDIG_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0682_OVRD_LN2_RX_SQDIG_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0682_LN2_RX_SQDIG_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0682_LN2_RX_SQDIG_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0682_LN2_RX_SQDIG_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0682_LN2_RX_SQDIG_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0683 (0x1A0C)
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#define USBDP_TRSV_REG0683_OVRD_LN2_RX_LFPS_DET_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0683_OVRD_LN2_RX_LFPS_DET_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0683_OVRD_LN2_RX_LFPS_DET_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0683_OVRD_LN2_RX_LFPS_DET_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0683_LN2_RX_LFPS_DET_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0683_LN2_RX_LFPS_DET_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0683_LN2_RX_LFPS_DET_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0683_LN2_RX_LFPS_DET_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_BW_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_BW_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_BW_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_BW_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_TH_CTRL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_TH_CTRL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_TH_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_TH_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_I_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_I_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_I_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0683_LN2_ANA_RX_LFPS_I_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0684 (0x1A10)
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#define USBDP_TRSV_REG0684_OVRD_LN2_RX_BIAS_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0684_OVRD_LN2_RX_BIAS_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0684_OVRD_LN2_RX_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0684_OVRD_LN2_RX_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0684_LN2_RX_BIAS_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0684_LN2_RX_BIAS_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0684_LN2_RX_BIAS_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0684_LN2_RX_BIAS_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_D_LANE_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_D_LANE_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_D_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_D_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_CLK_LANE_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_CLK_LANE_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_CLK_LANE_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_CLK_LANE_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EVEN_ODD_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EVEN_ODD_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EVEN_ODD_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_EVEN_ODD_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_DATA_EDGE_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_DATA_EDGE_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_DATA_EDGE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0684_LN2_ANA_RX_SRLB_DATA_EDGE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0685 (0x1A14)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0685_OVRD_LN2_RX_INIT_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0685_OVRD_LN2_RX_INIT_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0685_OVRD_LN2_RX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0685_OVRD_LN2_RX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0685_LN2_RX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0685_LN2_RX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0685_LN2_RX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0685_LN2_RX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_ATB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_ATB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0685_LN2_ANA_RX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0686 (0x1A18)
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#define USBDP_TRSV_REG0686_LN2_ANA_RX_ATB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0686_LN2_ANA_RX_ATB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0686_LN2_ANA_RX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0686_LN2_ANA_RX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0687 (0x1A1C)
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#define USBDP_TRSV_REG0687_LN2_ANA_RX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0687_LN2_ANA_RX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0687_LN2_ANA_RX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0687_LN2_ANA_RX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0688 (0x1A20)
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#define USBDP_TRSV_REG0688_LN2_RX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0688_LN2_RX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0688_LN2_RX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0688_LN2_RX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0689 (0x1A24)
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#define USBDP_TRSV_REG0689_LN2_RX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0689_LN2_RX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0689_LN2_RX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0689_LN2_RX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG068A (0x1A28)
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#define USBDP_TRSV_REG068A_LN2_RX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG068A_LN2_RX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG068A_LN2_RX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG068A_LN2_RX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG068B (0x1A2C)
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#define USBDP_TRSV_REG068B_LN2_RX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG068B_LN2_RX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG068B_LN2_RX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG068B_LN2_RX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG068C (0x1A30)
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#define USBDP_TRSV_REG068C_LN2_RX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG068C_LN2_RX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG068C_LN2_RX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG068C_LN2_RX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG068D (0x1A34)
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#define USBDP_TRSV_REG068D_LN2_RX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG068D_LN2_RX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG068D_LN2_RX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG068D_LN2_RX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG068E (0x1A38)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_SETTLE_TIME_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_SETTLE_TIME_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_SETTLE_TIME_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_SETTLE_TIME_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_NUM_OF_SAMPLE_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_NUM_OF_SAMPLE_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_NUM_OF_SAMPLE_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_NUM_OF_SAMPLE_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_20B_INPUT_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_20B_INPUT_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_20B_INPUT_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_20B_INPUT_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_VGA_CTLE_SA_START_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_VGA_CTLE_SA_START_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_VGA_CTLE_SA_START_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG068E_LN2_RX_OC_VGA_CTLE_SA_START_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG068F (0x1A3C)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_SQ_START_CODE_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_SQ_START_CODE_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_SQ_START_CODE_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_SQ_START_CODE_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_ODD_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_ODD_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_EVEN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_ODD_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_ODD_FINAL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG068F_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_FINAL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0690 (0x1A40)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_DFE_VGA_EVEN_INIT_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_RX_SQ_DIFP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_CTLE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_CTLE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_CTLE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_BYPASS_CTLE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0690_LN2_OVRD_RX_OC_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0690_LN2_OVRD_RX_OC_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0690_LN2_OVRD_RX_OC_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0690_LN2_OVRD_RX_OC_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0690_LN2_RX_OC_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0691 (0x1A44)
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#define USBDP_TRSV_REG0691_LN2_LANE_RESERVED0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0691_LN2_LANE_RESERVED0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0691_LN2_LANE_RESERVED0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0691_LN2_LANE_RESERVED0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0692 (0x1A48)
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#define USBDP_TRSV_REG0692_LN2_LANE_RESERVED1_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0692_LN2_LANE_RESERVED1_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0692_LN2_LANE_RESERVED1_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0692_LN2_LANE_RESERVED1_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0693 (0x1A4C)
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#define USBDP_TRSV_REG0693_LN2_LANE_RESERVED2_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0693_LN2_LANE_RESERVED2_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0693_LN2_LANE_RESERVED2_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0693_LN2_LANE_RESERVED2_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0694 (0x1A50)
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#define USBDP_TRSV_REG0694_LN2_LANE_RESERVED3_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0694_LN2_LANE_RESERVED3_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0694_LN2_LANE_RESERVED3_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0694_LN2_LANE_RESERVED3_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0695 (0x1A54)
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#define USBDP_TRSV_REG0695_LN2_LANE_RESERVED4_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0695_LN2_LANE_RESERVED4_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0695_LN2_LANE_RESERVED4_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0695_LN2_LANE_RESERVED4_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0696 (0x1A58)
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#define USBDP_TRSV_REG0696_LN2_LANE_RESERVED5_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0696_LN2_LANE_RESERVED5_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0696_LN2_LANE_RESERVED5_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0696_LN2_LANE_RESERVED5_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0697 (0x1A5C)
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#define USBDP_TRSV_REG0697_LN2_RX_SSLMS_HF_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0697_LN2_RX_SSLMS_HF_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0697_LN2_RX_SSLMS_HF_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0697_LN2_RX_SSLMS_HF_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0698 (0x1A60)
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#define USBDP_TRSV_REG0698_LN2_RX_SSLMS_HF_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0698_LN2_RX_SSLMS_HF_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0698_LN2_RX_SSLMS_HF_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0698_LN2_RX_SSLMS_HF_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0699 (0x1A64)
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#define USBDP_TRSV_REG0699_LN2_RX_SSLMS_HF_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0699_LN2_RX_SSLMS_HF_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0699_LN2_RX_SSLMS_HF_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0699_LN2_RX_SSLMS_HF_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069A (0x1A68)
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#define USBDP_TRSV_REG069A_LN2_RX_SSLMS_HF_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069A_LN2_RX_SSLMS_HF_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069A_LN2_RX_SSLMS_HF_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069A_LN2_RX_SSLMS_HF_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069B (0x1A6C)
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#define USBDP_TRSV_REG069B_LN2_RX_SSLMS_HF_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069B_LN2_RX_SSLMS_HF_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069B_LN2_RX_SSLMS_HF_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069B_LN2_RX_SSLMS_HF_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069C (0x1A70)
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#define USBDP_TRSV_REG069C_LN2_RX_SSLMS_HF_INIT_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069C_LN2_RX_SSLMS_HF_INIT_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069C_LN2_RX_SSLMS_HF_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069C_LN2_RX_SSLMS_HF_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069D (0x1A74)
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#define USBDP_TRSV_REG069D_LN2_RX_SSLMS_MF_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069D_LN2_RX_SSLMS_MF_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069D_LN2_RX_SSLMS_MF_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069D_LN2_RX_SSLMS_MF_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069E (0x1A78)
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#define USBDP_TRSV_REG069E_LN2_RX_SSLMS_MF_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069E_LN2_RX_SSLMS_MF_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069E_LN2_RX_SSLMS_MF_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069E_LN2_RX_SSLMS_MF_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG069F (0x1A7C)
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#define USBDP_TRSV_REG069F_LN2_RX_SSLMS_MF_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG069F_LN2_RX_SSLMS_MF_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG069F_LN2_RX_SSLMS_MF_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG069F_LN2_RX_SSLMS_MF_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A0 (0x1A80)
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#define USBDP_TRSV_REG06A0_LN2_RX_SSLMS_MF_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A0_LN2_RX_SSLMS_MF_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A0_LN2_RX_SSLMS_MF_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A0_LN2_RX_SSLMS_MF_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A1 (0x1A84)
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#define USBDP_TRSV_REG06A1_LN2_RX_SSLMS_MF_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A1_LN2_RX_SSLMS_MF_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A1_LN2_RX_SSLMS_MF_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A1_LN2_RX_SSLMS_MF_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A2 (0x1A88)
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#define USBDP_TRSV_REG06A2_LN2_RX_SSLMS_MF_INIT_HBR3_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A2_LN2_RX_SSLMS_MF_INIT_HBR3_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A2_LN2_RX_SSLMS_MF_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A2_LN2_RX_SSLMS_MF_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A3 (0x1A8C)
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#define USBDP_TRSV_REG06A3_LN2_RX_SSLMS_VGA_INIT_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A3_LN2_RX_SSLMS_VGA_INIT_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A3_LN2_RX_SSLMS_VGA_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A3_LN2_RX_SSLMS_VGA_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A4 (0x1A90)
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#define USBDP_TRSV_REG06A4_LN2_RX_SSLMS_VGA_INIT_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A4_LN2_RX_SSLMS_VGA_INIT_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A4_LN2_RX_SSLMS_VGA_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A4_LN2_RX_SSLMS_VGA_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A5 (0x1A94)
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#define USBDP_TRSV_REG06A5_LN2_RX_SSLMS_VGA_INIT_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A5_LN2_RX_SSLMS_VGA_INIT_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A5_LN2_RX_SSLMS_VGA_INIT_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A5_LN2_RX_SSLMS_VGA_INIT_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A6 (0x1A98)
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#define USBDP_TRSV_REG06A6_LN2_RX_SSLMS_VGA_INIT_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A6_LN2_RX_SSLMS_VGA_INIT_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A6_LN2_RX_SSLMS_VGA_INIT_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A6_LN2_RX_SSLMS_VGA_INIT_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A7 (0x1A9C)
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#define USBDP_TRSV_REG06A7_LN2_RX_SSLMS_VGA_INIT_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06A7_LN2_RX_SSLMS_VGA_INIT_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06A7_LN2_RX_SSLMS_VGA_INIT_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06A7_LN2_RX_SSLMS_VGA_INIT_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06A8 (0x1AA0)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_VGA_INIT_HBR3_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_VGA_INIT_HBR3_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_VGA_INIT_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_VGA_INIT_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_C0_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_C0_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_C0_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06A8_LN2_RX_SSLMS_C0_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06A9 (0x1AA4)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C1_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C1_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C1_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C1_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C2_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C2_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C2_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06A9_LN2_RX_SSLMS_C2_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06AA (0x1AA8)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C3_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C3_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C3_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C3_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C4_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C4_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C4_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06AA_LN2_RX_SSLMS_C4_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06AB (0x1AAC)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_C5_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_C5_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_C5_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_C5_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_HF_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_HF_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_HF_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06AB_LN2_RX_SSLMS_HF_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06AC (0x1AB0)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_MF_ADAP_SPEED_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_MF_ADAP_SPEED_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_MF_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_MF_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_VGA_ADAP_SPEED_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_VGA_ADAP_SPEED_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_VGA_ADAP_SPEED_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06AC_LN2_RX_SSLMS_VGA_ADAP_SPEED_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06AD (0x1AB4)
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#define USBDP_TRSV_REG06AD_LN2_RX_SSLMS_VGA_REF_VALUE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06AD_LN2_RX_SSLMS_VGA_REF_VALUE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06AD_LN2_RX_SSLMS_VGA_REF_VALUE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06AD_LN2_RX_SSLMS_VGA_REF_VALUE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06AE (0x1AB8)
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#define USBDP_TRSV_REG06AE_LN2_RX_SSLMS_HF_START_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06AE_LN2_RX_SSLMS_HF_START_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06AE_LN2_RX_SSLMS_HF_START_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06AE_LN2_RX_SSLMS_HF_START_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06AF (0x1ABC)
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#define USBDP_TRSV_REG06AF_LN2_RX_SSLMS_HF_NUM_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06AF_LN2_RX_SSLMS_HF_NUM_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06AF_LN2_RX_SSLMS_HF_NUM_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06AF_LN2_RX_SSLMS_HF_NUM_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06B0 (0x1AC0)
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#define USBDP_TRSV_REG06B0_LN2_RX_SSLMS_MF_START_CURSOR_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06B0_LN2_RX_SSLMS_MF_START_CURSOR_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06B0_LN2_RX_SSLMS_MF_START_CURSOR_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06B0_LN2_RX_SSLMS_MF_START_CURSOR_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06B1 (0x1AC4)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_MF_NUM_CURSOR_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_MF_NUM_CURSOR_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_MF_NUM_CURSOR_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_MF_NUM_CURSOR_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_ADAP_EVENODD_SAME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_ADAP_EVENODD_SAME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_ADAP_EVENODD_SAME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06B1_LN2_RX_SSLMS_ADAP_EVENODD_SAME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06B2 (0x1AC8)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_SETTLE_CYCLE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_SETTLE_CYCLE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_SETTLE_CYCLE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_SETTLE_CYCLE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_HYSTERISIS_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_HYSTERISIS_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_HYSTERISIS_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_HYSTERISIS_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_ADAP_TOL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_ADAP_TOL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_ADAP_TOL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06B2_LN2_RX_SSLMS_ADAP_TOL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06B3 (0x1ACC)
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#define USBDP_TRSV_REG06B3_LN2_RX_SSLMS_ADAP_COEF_SEL__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06B3_LN2_RX_SSLMS_ADAP_COEF_SEL__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06B3_LN2_RX_SSLMS_ADAP_COEF_SEL__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06B3_LN2_RX_SSLMS_ADAP_COEF_SEL__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06B4 (0x1AD0)
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#define USBDP_TRSV_REG06B4_LN2_RX_SSLMS_ADAP_COEF_SEL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06B4_LN2_RX_SSLMS_ADAP_COEF_SEL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06B4_LN2_RX_SSLMS_ADAP_COEF_SEL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06B4_LN2_RX_SSLMS_ADAP_COEF_SEL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06B5 (0x1AD4)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_HOLD_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_HOLD_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06B5_LN2_OVRD_RX_SSLMS_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_HOLD_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_HOLD_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_HOLD_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06B5_LN2_RX_SSLMS_ADAP_HOLD_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06B6 (0x1AD8)
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#define USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06B7 (0x1ADC)
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#define USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06B8 (0x1AE0)
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#define USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06B9 (0x1AE4)
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#define USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06BA (0x1AE8)
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#define USBDP_TRSV_REG06BA_LN2_RX_CDR_PMS_M_RBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06BA_LN2_RX_CDR_PMS_M_RBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06BA_LN2_RX_CDR_PMS_M_RBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06BA_LN2_RX_CDR_PMS_M_RBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06BB (0x1AEC)
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#define USBDP_TRSV_REG06BB_LN2_RX_CDR_PMS_M_RBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06BB_LN2_RX_CDR_PMS_M_RBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06BB_LN2_RX_CDR_PMS_M_RBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06BB_LN2_RX_CDR_PMS_M_RBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06BC (0x1AF0)
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#define USBDP_TRSV_REG06BC_LN2_RX_CDR_PMS_M_HBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06BC_LN2_RX_CDR_PMS_M_HBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06BC_LN2_RX_CDR_PMS_M_HBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06BC_LN2_RX_CDR_PMS_M_HBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06BD (0x1AF4)
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#define USBDP_TRSV_REG06BD_LN2_RX_CDR_PMS_M_HBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06BD_LN2_RX_CDR_PMS_M_HBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06BD_LN2_RX_CDR_PMS_M_HBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06BD_LN2_RX_CDR_PMS_M_HBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06BE (0x1AF8)
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#define USBDP_TRSV_REG06BE_LN2_RX_CDR_PMS_M_HBR2__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06BE_LN2_RX_CDR_PMS_M_HBR2__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06BE_LN2_RX_CDR_PMS_M_HBR2__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06BE_LN2_RX_CDR_PMS_M_HBR2__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06BF (0x1AFC)
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#define USBDP_TRSV_REG06BF_LN2_RX_CDR_PMS_M_HBR2__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06BF_LN2_RX_CDR_PMS_M_HBR2__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06BF_LN2_RX_CDR_PMS_M_HBR2__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06BF_LN2_RX_CDR_PMS_M_HBR2__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06C0 (0x1B00)
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#define USBDP_TRSV_REG06C0_LN2_RX_CDR_PMS_M_HBR3__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06C0_LN2_RX_CDR_PMS_M_HBR3__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06C0_LN2_RX_CDR_PMS_M_HBR3__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06C0_LN2_RX_CDR_PMS_M_HBR3__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06C1 (0x1B04)
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#define USBDP_TRSV_REG06C1_LN2_RX_CDR_PMS_M_HBR3__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06C1_LN2_RX_CDR_PMS_M_HBR3__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06C1_LN2_RX_CDR_PMS_M_HBR3__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06C1_LN2_RX_CDR_PMS_M_HBR3__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06C2 (0x1B08)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_RSTN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_RSTN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_RSTN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_RSTN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_RSTN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_RSTN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_INIT_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_INIT_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06C2_LN2_OVRD_RX_CDR_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_INIT_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_INIT_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_STB_NUM_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_STB_NUM_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG06C2_LN2_RX_CDR_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG06C3 (0x1B0C)
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#define USBDP_TRSV_REG06C3_LN2_RX_CDR_AFC_TOL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG06C3_LN2_RX_CDR_AFC_TOL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG06C3_LN2_RX_CDR_AFC_TOL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG06C3_LN2_RX_CDR_AFC_TOL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG06C4 (0x1B10)
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#define USBDP_TRSV_REG06C4_LN2_RX_CDR_AFC_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06C4_LN2_RX_CDR_AFC_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06C4_LN2_RX_CDR_AFC_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06C4_LN2_RX_CDR_AFC_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06C5 (0x1B14)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_VCO_CNT_WAIT_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_VCO_CNT_WAIT_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_VCO_CNT_WAIT_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_VCO_CNT_WAIT_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_FIX_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_FIX_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_FIX_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06C5_LN2_RX_CDR_AFC_FIX_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06C6 (0x1B18)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_MAN_BSEL_TIME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_MAN_BSEL_TIME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_MAN_BSEL_TIME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06C6_LN2_RX_CDR_AFC_MAN_BSEL_TIME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06C7 (0x1B1C)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_MAN_BSEL_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_MAN_BSEL_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_MAN_BSEL_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_MAN_BSEL_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_BSEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_BSEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06C7_LN2_RX_CDR_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06C8 (0x1B20)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06C8_LN2_RX_CDR_AFC_STEP_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06C9 (0x1B24)
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#define USBDP_TRSV_REG06C9_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06C9_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06C9_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06C9_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06CA (0x1B28)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_MAN_SEL_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_MAN_SEL_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_MAN_SEL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06CA_LN2_RX_CDR_FBB_MAN_SEL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06CB (0x1B2C)
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#define USBDP_TRSV_REG06CB_LN2_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06CB_LN2_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06CB_LN2_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06CB_LN2_RX_CDR_FBB_MAN_CODE_UPDC_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06CC (0x1B30)
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#define USBDP_TRSV_REG06CC_LN2_RX_CDR_FBB_DELTA_CNT_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06CC_LN2_RX_CDR_FBB_DELTA_CNT_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06CC_LN2_RX_CDR_FBB_DELTA_CNT_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06CC_LN2_RX_CDR_FBB_DELTA_CNT_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06CD (0x1B34)
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#define USBDP_TRSV_REG06CD_LN2_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06CD_LN2_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06CD_LN2_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06CD_LN2_RX_CDR_FBB_PLL_MODE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06CE (0x1B38)
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#define USBDP_TRSV_REG06CE_LN2_RX_CDR_FBB_COARSE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06CE_LN2_RX_CDR_FBB_COARSE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06CE_LN2_RX_CDR_FBB_COARSE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06CE_LN2_RX_CDR_FBB_COARSE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06CF (0x1B3C)
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#define USBDP_TRSV_REG06CF_LN2_RX_CDR_FBB_FINE_CTRL_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06CF_LN2_RX_CDR_FBB_FINE_CTRL_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06CF_LN2_RX_CDR_FBB_FINE_CTRL_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06CF_LN2_RX_CDR_FBB_FINE_CTRL_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06D0 (0x1B40)
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#define USBDP_TRSV_REG06D0_LN2_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06D0_LN2_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06D0_LN2_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06D0_LN2_RX_CDR_FBB_PLL_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06D1 (0x1B44)
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#define USBDP_TRSV_REG06D1_LN2_RX_CDR_FBB_HI_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06D1_LN2_RX_CDR_FBB_HI_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06D1_LN2_RX_CDR_FBB_HI_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06D1_LN2_RX_CDR_FBB_HI_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06D2 (0x1B48)
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#define USBDP_TRSV_REG06D2_LN2_RX_CDR_FBB_LO_BW_DIFF_RESERVED_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06D2_LN2_RX_CDR_FBB_LO_BW_DIFF_RESERVED_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06D2_LN2_RX_CDR_FBB_LO_BW_DIFF_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06D2_LN2_RX_CDR_FBB_LO_BW_DIFF_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06D3 (0x1B4C)
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#define USBDP_TRSV_REG06D3_LN2_RX_CDR_PLL_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06D3_LN2_RX_CDR_PLL_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06D3_LN2_RX_CDR_PLL_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06D3_LN2_RX_CDR_PLL_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06D4 (0x1B50)
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#define USBDP_TRSV_REG06D4_LN2_RX_CDR_PLL_VCO_CNT_WAIT_NO_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG06D4_LN2_RX_CDR_PLL_VCO_CNT_WAIT_NO_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG06D4_LN2_RX_CDR_PLL_VCO_CNT_WAIT_NO_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG06D4_LN2_RX_CDR_PLL_VCO_CNT_WAIT_NO_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG06D5 (0x1B54)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_LOCK_PPM_SET_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_LOCK_PPM_SET_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_LOCK_PPM_SET_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_LOCK_PPM_SET_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_ENTRY_SRC_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_ENTRY_SRC_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_ENTRY_SRC_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_ENTRY_SRC_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_RESTART_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_RESTART_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_RESTART_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06D5_LN2_RX_CDR_PLL_MODE_RESTART_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06D6 (0x1B58)
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#define USBDP_TRSV_REG06D6_LN2_RX_CDR_CK_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06D6_LN2_RX_CDR_CK_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06D6_LN2_RX_CDR_CK_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06D6_LN2_RX_CDR_CK_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06D7 (0x1B5C)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_CK_VCO_CNT_WAIT_NO_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_CK_VCO_CNT_WAIT_NO_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_CK_VCO_CNT_WAIT_NO_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_CK_VCO_CNT_WAIT_NO_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_LOCK_SETTLE_NO_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_LOCK_SETTLE_NO_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_LOCK_SETTLE_NO_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06D7_LN2_RX_CDR_LOCK_SETTLE_NO_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06D8 (0x1B60)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CK_LOCK_PPM_SET_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CK_LOCK_PPM_SET_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CK_LOCK_PPM_SET_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CK_LOCK_PPM_SET_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG06D8_LN2_OVRD_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06D8_LN2_OVRD_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06D8_LN2_OVRD_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06D8_LN2_OVRD_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06D8_LN2_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06D9 (0x1B64)
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#define USBDP_TRSV_REG06D9_LN2_OVRD_RX_EFOM_FEEDBACK_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06D9_LN2_OVRD_RX_EFOM_FEEDBACK_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06D9_LN2_OVRD_RX_EFOM_FEEDBACK_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06D9_LN2_OVRD_RX_EFOM_FEEDBACK_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06DA (0x1B68)
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#define USBDP_TRSV_REG06DA_LN2_RX_EFOM_FEEDBACK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06DA_LN2_RX_EFOM_FEEDBACK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06DA_LN2_RX_EFOM_FEEDBACK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06DA_LN2_RX_EFOM_FEEDBACK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06DB (0x1B6C)
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#define USBDP_TRSV_REG06DB_LN2_RX_EFOM_FEEDBACK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06DB_LN2_RX_EFOM_FEEDBACK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06DB_LN2_RX_EFOM_FEEDBACK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06DB_LN2_RX_EFOM_FEEDBACK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06DC (0x1B70)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_DONE_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_DONE_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_MODE_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_MODE_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_MODE_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_MODE_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_START_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_START_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_START_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06DC_LN2_OVRD_RX_EFOM_START_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06DC_LN2_RX_EFOM_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06DD (0x1B74)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_VREF_RESOL_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_VREF_RESOL_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_VREF_RESOL_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_VREF_RESOL_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_START_SSM_DISABLE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_START_SSM_DISABLE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_START_SSM_DISABLE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_START_SSM_DISABLE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_H_WEIGHT_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_H_WEIGHT_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_H_WEIGHT_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_H_WEIGHT_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_V_WEIGHT_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_V_WEIGHT_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_V_WEIGHT_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06DD_LN2_RX_EFOM_V_WEIGHT_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06DE (0x1B78)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_SETTLE_TIME_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_SETTLE_TIME_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_SETTLE_TIME_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_SETTLE_TIME_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_BIT_WIDTH_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_BIT_WIDTH_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_BIT_WIDTH_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_BIT_WIDTH_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06DE_LN2_RX_EFOM_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06DF (0x1B7C)
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#define USBDP_TRSV_REG06DF_LN2_RX_EFOM_NUM_OF_SAMPLE__13_8_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG06DF_LN2_RX_EFOM_NUM_OF_SAMPLE__13_8_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG06DF_LN2_RX_EFOM_NUM_OF_SAMPLE__13_8_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG06DF_LN2_RX_EFOM_NUM_OF_SAMPLE__13_8_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG06E0 (0x1B80)
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#define USBDP_TRSV_REG06E0_LN2_RX_EFOM_NUM_OF_SAMPLE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06E0_LN2_RX_EFOM_NUM_OF_SAMPLE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06E0_LN2_RX_EFOM_NUM_OF_SAMPLE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06E0_LN2_RX_EFOM_NUM_OF_SAMPLE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06E1 (0x1B84)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_TRIAL_NUM_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_TRIAL_NUM_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_TRIAL_NUM_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_TRIAL_NUM_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_OUT_WIDTH_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_OUT_WIDTH_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_OUT_WIDTH_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06E1_LN2_RX_EFOM_OUT_WIDTH_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06E2 (0x1B88)
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#define USBDP_TRSV_REG06E2_LN2_RX_EFOM_DFE_VREF_CTRL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06E2_LN2_RX_EFOM_DFE_VREF_CTRL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06E2_LN2_RX_EFOM_DFE_VREF_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06E2_LN2_RX_EFOM_DFE_VREF_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06E3 (0x1B8C)
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#define USBDP_TRSV_REG06E3_LN2_RX_EFOM_ERROR_TH__9_8_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06E3_LN2_RX_EFOM_ERROR_TH__9_8_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06E3_LN2_RX_EFOM_ERROR_TH__9_8_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06E3_LN2_RX_EFOM_ERROR_TH__9_8_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06E4 (0x1B90)
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#define USBDP_TRSV_REG06E4_LN2_RX_EFOM_ERROR_TH__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06E4_LN2_RX_EFOM_ERROR_TH__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06E4_LN2_RX_EFOM_ERROR_TH__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06E4_LN2_RX_EFOM_ERROR_TH__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06E5 (0x1B94)
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#define USBDP_TRSV_REG06E5_LN2_RX_EFOM_EOM_PH_SEL_MSK USBDP_REG_MSK(1, 7)
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#define USBDP_TRSV_REG06E5_LN2_RX_EFOM_EOM_PH_SEL_CLR USBDP_REG_CLR(1, 7)
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#define USBDP_TRSV_REG06E5_LN2_RX_EFOM_EOM_PH_SEL_SET(_x) USBDP_REG_SET(_x, 1, 7)
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#define USBDP_TRSV_REG06E5_LN2_RX_EFOM_EOM_PH_SEL_GET(_R) USBDP_REG_GET(_R, 1, 7)
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#define USBDP_TRSV_REG06E5_LN2_RXD_ALIGN_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06E5_LN2_RXD_ALIGN_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06E5_LN2_RXD_ALIGN_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06E5_LN2_RXD_ALIGN_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06E6 (0x1B98)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_HOLD_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_HOLD_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_HOLD_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_HOLD_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_WORD_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_WORD_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_WORD_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_ALIGN_WORD_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_LOCK_NUM_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG06E6_LN2_RXD_LOCK_NUM_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG06E6_LN2_RXD_LOCK_NUM_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG06E6_LN2_RXD_LOCK_NUM_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BYTE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BYTE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BYTE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BYTE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BIT_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BIT_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BIT_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06E6_LN2_RXD_FLIP_BIT_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06E7 (0x1B9C)
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#define USBDP_TRSV_REG06E7_LN2_RXD_POLARITY_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06E7_LN2_RXD_POLARITY_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06E7_LN2_RXD_POLARITY_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06E7_LN2_RXD_POLARITY_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06E7_LN2_RX_SIGVAL_LPF_BYPASS_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06E7_LN2_RX_SIGVAL_LPF_BYPASS_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06E7_LN2_RX_SIGVAL_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06E7_LN2_RX_SIGVAL_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06E8 (0x1BA0)
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#define USBDP_TRSV_REG06E8_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06E8_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06E8_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06E8_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06E9 (0x1BA4)
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#define USBDP_TRSV_REG06E9_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06E9_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06E9_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06E9_LN2_RX_SIGVAL_LPF_DELAY_TIME_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06EA (0x1BA8)
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#define USBDP_TRSV_REG06EA_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06EA_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06EA_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06EA_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06EB (0x1BAC)
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#define USBDP_TRSV_REG06EB_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06EB_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06EB_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06EB_LN2_RX_SIGVAL_LPF_DELAY_TIME_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06EC (0x1BB0)
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#define USBDP_TRSV_REG06EC_LN2_RESERVED_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06EC_LN2_RESERVED_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06EC_LN2_RESERVED_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06EC_LN2_RESERVED_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06EC_LN2_OVRD_RX_RCAL_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06EC_LN2_OVRD_RX_RCAL_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06EC_LN2_OVRD_RX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06EC_LN2_OVRD_RX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06EC_LN2_RX_RCAL_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06ED (0x1BB4)
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#define USBDP_TRSV_REG06ED_LN2_RX_RTERM_CTRL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06ED_LN2_RX_RTERM_CTRL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06ED_LN2_RX_RTERM_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06ED_LN2_RX_RTERM_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06ED_LN2_OVRD_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06ED_LN2_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06EE (0x1BB8)
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#define USBDP_TRSV_REG06EE_LN2_OVRD_TX_RCAL_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06EE_LN2_OVRD_TX_RCAL_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06EE_LN2_OVRD_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06EE_LN2_OVRD_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_UP_OPT_CODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_UP_OPT_CODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_UP_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_UP_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_DN_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_DN_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_DN_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06EE_LN2_TX_RCAL_DN_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06EF (0x1BBC)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_UP_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_UP_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_UP_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_UP_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_DN_CODE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_DN_CODE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_DN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG06EF_LN2_TX_RCAL_DN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG06F0 (0x1BC0)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_DONE_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_DONE_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_DONE_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_DONE_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06F0_LN2_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06F0_LN2_LANE_MODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06F0_LN2_LANE_MODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06F0_LN2_LANE_MODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06F0_LN2_LANE_MODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_LANE_RATE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_LANE_RATE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_LANE_RATE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06F0_LN2_OVRD_LANE_RATE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06F0_LN2_LANE_RATE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06F0_LN2_LANE_RATE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06F0_LN2_LANE_RATE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06F0_LN2_LANE_RATE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06F1 (0x1BC4)
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#define USBDP_TRSV_REG06F1_LN2_LANE_TIMER_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06F1_LN2_LANE_TIMER_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06F1_LN2_LANE_TIMER_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06F1_LN2_LANE_TIMER_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_TX_CLK_SRC_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_TX_CLK_SRC_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_TX_CLK_SRC_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_TX_CLK_SRC_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_SRC_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_SRC_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_SRC_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_SRC_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_INV_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_INV_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_INV_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_CLK_INV_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06F1_LN2_OVRD_MISC_RX_SQHS_SIGVAL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06F1_LN2_OVRD_MISC_RX_SQHS_SIGVAL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06F1_LN2_OVRD_MISC_RX_SQHS_SIGVAL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06F1_LN2_OVRD_MISC_RX_SQHS_SIGVAL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_SQHS_SIGVAL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_SQHS_SIGVAL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_SQHS_SIGVAL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_SQHS_SIGVAL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_DATA_CLEAR_SRC_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_DATA_CLEAR_SRC_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_DATA_CLEAR_SRC_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06F1_LN2_MISC_RX_DATA_CLEAR_SRC_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06F2 (0x1BC8)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_LFPS_DET_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_LFPS_DET_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_LFPS_DET_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_LFPS_DET_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_LFPS_DET_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_LFPS_DET_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_TX_RXD_DETECTED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_TX_RXD_DETECTED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_TX_RXD_DETECTED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_TX_RXD_DETECTED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_TX_RXD_DETECTED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_TX_RXD_DETECTED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_TX_RXD_DETECTED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_TX_RXD_DETECTED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_VALID_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_VALID_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06F2_LN2_OVRD_MISC_RX_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_VALID_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_VALID_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_VALID_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06F2_LN2_MISC_RX_VALID_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06F3 (0x1BCC)
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#define USBDP_TRSV_REG06F3_LN2_LANE_RESERVED7_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG06F3_LN2_LANE_RESERVED7_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG06F3_LN2_LANE_RESERVED7_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG06F3_LN2_LANE_RESERVED7_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG06F3_LN2_TG_RCAL_RSTN_DELAY_TIME_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG06F3_LN2_TG_RCAL_RSTN_DELAY_TIME_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG06F3_LN2_TG_RCAL_RSTN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG06F3_LN2_TG_RCAL_RSTN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG06F3_LN2_RX_VALID_RSTN_DELAY_BYPASS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06F3_LN2_RX_VALID_RSTN_DELAY_BYPASS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06F3_LN2_RX_VALID_RSTN_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06F3_LN2_RX_VALID_RSTN_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06F4 (0x1BD0)
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#define USBDP_TRSV_REG06F4_LN2_RX_VALID_RSTN_DELAY_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG06F4_LN2_RX_VALID_RSTN_DELAY_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG06F4_LN2_RX_VALID_RSTN_DELAY_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG06F4_LN2_RX_VALID_RSTN_DELAY_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG06F4_LN2_TG_TX_DCC_EN_DELAY_TIME_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06F4_LN2_TG_TX_DCC_EN_DELAY_TIME_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06F4_LN2_TG_TX_DCC_EN_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06F4_LN2_TG_TX_DCC_EN_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG06F5 (0x1BD4)
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#define USBDP_TRSV_REG06F5_LN2_TG_SER_VREG_FAST_PULSE_TIME_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG06F5_LN2_TG_SER_VREG_FAST_PULSE_TIME_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG06F5_LN2_TG_SER_VREG_FAST_PULSE_TIME_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG06F5_LN2_TG_SER_VREG_FAST_PULSE_TIME_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG06F6 (0x1BD8)
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#define USBDP_TRSV_REG06F6_LN2_TX_LFPS_AFC_PMS_M__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06F6_LN2_TX_LFPS_AFC_PMS_M__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06F6_LN2_TX_LFPS_AFC_PMS_M__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06F6_LN2_TX_LFPS_AFC_PMS_M__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06F7 (0x1BDC)
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#define USBDP_TRSV_REG06F7_LN2_TX_LFPS_AFC_PMS_M__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG06F7_LN2_TX_LFPS_AFC_PMS_M__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG06F7_LN2_TX_LFPS_AFC_PMS_M__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG06F7_LN2_TX_LFPS_AFC_PMS_M__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG06F8 (0x1BE0)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_STB_NUM_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_STB_NUM_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_STB_NUM_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_STB_NUM_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_TOL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_TOL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_TOL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG06F8_LN2_TX_LFPS_AFC_TOL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG06F9 (0x1BE4)
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#define USBDP_TRSV_REG06F9_LN2_TX_LFPS_AFC_VCO_CNT_RUN_NO_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG06F9_LN2_TX_LFPS_AFC_VCO_CNT_RUN_NO_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG06F9_LN2_TX_LFPS_AFC_VCO_CNT_RUN_NO_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG06F9_LN2_TX_LFPS_AFC_VCO_CNT_RUN_NO_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG06FA (0x1BE8)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_VCO_CNT_WAIT_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_VCO_CNT_WAIT_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_VCO_CNT_WAIT_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_VCO_CNT_WAIT_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_FIX_CODE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_FIX_CODE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_FIX_CODE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06FA_LN2_TX_LFPS_AFC_FIX_CODE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06FB (0x1BEC)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_PRESET_VCO_CNT_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_PRESET_VCO_CNT_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_PRESET_VCO_CNT_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_PRESET_VCO_CNT_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_MAN_BSEL_TIME_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_MAN_BSEL_TIME_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_MAN_BSEL_TIME_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06FB_LN2_TX_LFPS_AFC_MAN_BSEL_TIME_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06FC (0x1BF0)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_MAN_BSEL_MSK USBDP_REG_MSK(1, 6)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_MAN_BSEL_CLR USBDP_REG_CLR(1, 6)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_MAN_BSEL_SET(_x) USBDP_REG_SET(_x, 1, 6)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_MAN_BSEL_GET(_R) USBDP_REG_GET(_R, 1, 6)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_BSEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_BSEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_BSEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06FC_LN2_TX_LFPS_AFC_BSEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06FD (0x1BF4)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_MSK USBDP_REG_MSK(5, 3)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_CLR USBDP_REG_CLR(5, 3)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_SET(_x) USBDP_REG_SET(_x, 5, 3)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_GET(_R) USBDP_REG_GET(_R, 5, 3)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG06FD_LN2_TX_LFPS_AFC_STEP_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG06FD_LN2_OVRD_TXD_DESKEW_RSTN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG06FD_LN2_OVRD_TXD_DESKEW_RSTN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG06FD_LN2_OVRD_TXD_DESKEW_RSTN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG06FD_LN2_OVRD_TXD_DESKEW_RSTN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_BYPASS_ERR_CHK_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_BYPASS_ERR_CHK_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_BYPASS_ERR_CHK_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_BYPASS_ERR_CHK_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_FIX_DA_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_FIX_DA_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_FIX_DA_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06FD_LN2_TXD_DESKEW_FIX_DA_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06FE (0x1BF8)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_FIX_DB_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_FIX_DB_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_FIX_DB_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_FIX_DB_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DESKEW_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_CLK_TYPE_MAN_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_CLK_TYPE_MAN_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_CLK_TYPE_MAN_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_CLK_TYPE_MAN_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG06FE_LN2_TXD_CLK_TYPE_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_CLK_TYPE_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_CLK_TYPE_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_CLK_TYPE_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_TYPE_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_TYPE_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_TYPE_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG06FE_LN2_TXD_DATA_TYPE_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG06FE_LN2_RETIMEDLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG06FE_LN2_RETIMEDLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG06FE_LN2_RETIMEDLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG06FE_LN2_RETIMEDLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG06FF (0x1BFC)
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#define USBDP_TRSV_REG06FF_LN2_BIST_AUTO_RUN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG06FF_LN2_BIST_AUTO_RUN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG06FF_LN2_BIST_AUTO_RUN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG06FF_LN2_BIST_AUTO_RUN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG06FF_LN2_BIST_COMDET_NUM_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_COMDET_NUM_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_COMDET_NUM_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_COMDET_NUM_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_SEED_SEL_MSK USBDP_REG_MSK(2, 3)
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#define USBDP_TRSV_REG06FF_LN2_BIST_SEED_SEL_CLR USBDP_REG_CLR(2, 3)
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#define USBDP_TRSV_REG06FF_LN2_BIST_SEED_SEL_SET(_x) USBDP_REG_SET(_x, 2, 3)
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#define USBDP_TRSV_REG06FF_LN2_BIST_SEED_SEL_GET(_R) USBDP_REG_GET(_R, 2, 3)
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#define USBDP_TRSV_REG06FF_LN2_BIST_PRBS_MODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_PRBS_MODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_PRBS_MODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG06FF_LN2_BIST_PRBS_MODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0700 (0x1C00)
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#define USBDP_TRSV_REG0700_LN2_BIST_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_DATA_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_DATA_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_DATA_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_DATA_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_HOLD_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_HOLD_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_HOLD_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_HOLD_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_START_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_START_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_START_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_RX_START_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_ERRINJ_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_ERRINJ_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_ERRINJ_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_ERRINJ_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0700_LN2_BIST_TX_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0701 (0x1C04)
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#define USBDP_TRSV_REG0701_LN2_BIST_USER_PAT_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0701_LN2_BIST_USER_PAT_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0701_LN2_BIST_USER_PAT_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0701_LN2_BIST_USER_PAT_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0702 (0x1C08)
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#define USBDP_TRSV_REG0702_LN2_BIST_USER_PAT__79_72_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0702_LN2_BIST_USER_PAT__79_72_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0702_LN2_BIST_USER_PAT__79_72_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0702_LN2_BIST_USER_PAT__79_72_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0703 (0x1C0C)
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#define USBDP_TRSV_REG0703_LN2_BIST_USER_PAT__71_64_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0703_LN2_BIST_USER_PAT__71_64_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0703_LN2_BIST_USER_PAT__71_64_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0703_LN2_BIST_USER_PAT__71_64_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0704 (0x1C10)
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#define USBDP_TRSV_REG0704_LN2_BIST_USER_PAT__63_56_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0704_LN2_BIST_USER_PAT__63_56_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0704_LN2_BIST_USER_PAT__63_56_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0704_LN2_BIST_USER_PAT__63_56_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0705 (0x1C14)
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#define USBDP_TRSV_REG0705_LN2_BIST_USER_PAT__55_48_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0705_LN2_BIST_USER_PAT__55_48_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0705_LN2_BIST_USER_PAT__55_48_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0705_LN2_BIST_USER_PAT__55_48_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0706 (0x1C18)
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#define USBDP_TRSV_REG0706_LN2_BIST_USER_PAT__47_40_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0706_LN2_BIST_USER_PAT__47_40_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0706_LN2_BIST_USER_PAT__47_40_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0706_LN2_BIST_USER_PAT__47_40_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0707 (0x1C1C)
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#define USBDP_TRSV_REG0707_LN2_BIST_USER_PAT__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0707_LN2_BIST_USER_PAT__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0707_LN2_BIST_USER_PAT__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0707_LN2_BIST_USER_PAT__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0708 (0x1C20)
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#define USBDP_TRSV_REG0708_LN2_BIST_USER_PAT__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0708_LN2_BIST_USER_PAT__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0708_LN2_BIST_USER_PAT__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0708_LN2_BIST_USER_PAT__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0709 (0x1C24)
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#define USBDP_TRSV_REG0709_LN2_BIST_USER_PAT__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0709_LN2_BIST_USER_PAT__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0709_LN2_BIST_USER_PAT__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0709_LN2_BIST_USER_PAT__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG070A (0x1C28)
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#define USBDP_TRSV_REG070A_LN2_BIST_USER_PAT__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG070A_LN2_BIST_USER_PAT__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG070A_LN2_BIST_USER_PAT__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG070A_LN2_BIST_USER_PAT__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG070B (0x1C2C)
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#define USBDP_TRSV_REG070B_LN2_BIST_USER_PAT__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG070B_LN2_BIST_USER_PAT__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG070B_LN2_BIST_USER_PAT__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG070B_LN2_BIST_USER_PAT__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG070C (0x1C30)
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#define USBDP_TRSV_REG070C_LN2_RATE_CHANGE_DELAY_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG070C_LN2_RATE_CHANGE_DELAY_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG070C_LN2_RATE_CHANGE_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG070C_LN2_RATE_CHANGE_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG070D (0x1C34)
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#define USBDP_TRSV_REG070D_LN2_LANE_DTB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG070D_LN2_LANE_DTB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG070D_LN2_LANE_DTB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG070D_LN2_LANE_DTB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG070E (0x1C38)
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#define USBDP_TRSV_REG070E_LN2_RX_SSLMS_DFE_ADAP_DONE_WIDTH_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG070E_LN2_RX_SSLMS_DFE_ADAP_DONE_WIDTH_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG070E_LN2_RX_SSLMS_DFE_ADAP_DONE_WIDTH_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG070E_LN2_RX_SSLMS_DFE_ADAP_DONE_WIDTH_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG070F (0x1C3C)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_TIMEOUT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_DFE_ADAP_DONE_ORG_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_BLOCK_ADAP_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_BLOCK_ADAP_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_BLOCK_ADAP_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG070F_LN2_RX_SSLMS_BLOCK_ADAP_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0710 (0x1C40)
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#define USBDP_TRSV_REG0710_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0710_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0710_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0710_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__9_8_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0711 (0x1C44)
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#define USBDP_TRSV_REG0711_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0711_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0711_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0711_LN2_RX_SSLMS_BLOCK_ADAP_SIZE__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0712 (0x1C48)
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#define USBDP_TRSV_REG0712_LN2_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0712_LN2_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0712_LN2_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0712_LN2_RX_SSLMS_BLOCK_ADAP_UPDATE_TH_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0713 (0x1C4C)
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#define USBDP_TRSV_REG0713_LN2_RX_SSLMS_DFE_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0713_LN2_RX_SSLMS_DFE_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0713_LN2_RX_SSLMS_DFE_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0713_LN2_RX_SSLMS_DFE_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0714 (0x1C50)
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#define USBDP_TRSV_REG0714_LN2_RX_SSLMS_HF_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0714_LN2_RX_SSLMS_HF_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0714_LN2_RX_SSLMS_HF_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0714_LN2_RX_SSLMS_HF_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0715 (0x1C54)
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#define USBDP_TRSV_REG0715_LN2_RX_SSLMS_MF_LOCK_TH_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0715_LN2_RX_SSLMS_MF_LOCK_TH_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0715_LN2_RX_SSLMS_MF_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0715_LN2_RX_SSLMS_MF_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0716 (0x1C58)
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#define USBDP_TRSV_REG0716_LN2_RX_SSLMS_VGA_LOCK_TH_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG0716_LN2_RX_SSLMS_VGA_LOCK_TH_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG0716_LN2_RX_SSLMS_VGA_LOCK_TH_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG0716_LN2_RX_SSLMS_VGA_LOCK_TH_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_EIEN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_EIEN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_EIEN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_EIEN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_LFPS_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_LFPS_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_LFPS_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0716_LN2_TXD_DESKEW_BYPASS_LFPS_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0717 (0x1C5C)
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#define USBDP_TRSV_REG0717_LN2_TXD_DESKEW_BYPASS_DRV_LVL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0717_LN2_TXD_DESKEW_BYPASS_DRV_LVL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0717_LN2_TXD_DESKEW_BYPASS_DRV_LVL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0717_LN2_TXD_DESKEW_BYPASS_DRV_LVL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0717_LN2_ANA_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0717_LN2_ANA_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0717_LN2_ANA_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0717_LN2_ANA_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0718 (0x1C60)
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#define USBDP_TRSV_REG0718_LN2_ANA_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0718_LN2_ANA_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0718_LN2_ANA_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0718_LN2_ANA_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0719 (0x1C64)
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#define USBDP_TRSV_REG0719_LN2_ANA_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0719_LN2_ANA_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0719_LN2_ANA_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0719_LN2_ANA_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG071A (0x1C68)
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#define USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG071B (0x1C6C)
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#define USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG071C (0x1C70)
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#define USBDP_TRSV_REG071C_LN2_TG_RXD_STATUS_DELAY_TIME_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG071C_LN2_TG_RXD_STATUS_DELAY_TIME_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG071C_LN2_TG_RXD_STATUS_DELAY_TIME_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG071C_LN2_TG_RXD_STATUS_DELAY_TIME_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG071C_LN2_RX_SSLMS_ADAP_HOLD_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_SSLMS_ADAP_HOLD_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_SSLMS_ADAP_HOLD_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_SSLMS_ADAP_HOLD_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG071C_LN2_OVRD_RX_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG071C_LN2_OVRD_RX_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG071C_LN2_OVRD_RX_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG071C_LN2_OVRD_RX_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_OC_CAL_DATA_INV_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_OC_CAL_DATA_INV_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_OC_CAL_DATA_INV_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG071C_LN2_RX_OC_CAL_DATA_INV_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG071D (0x1C74)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_NON_DATA_INV_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_NON_DATA_INV_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_NON_DATA_INV_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_NON_DATA_INV_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_DATA_MASK_SEL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_DATA_MASK_SEL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_DATA_MASK_SEL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_CAL_DATA_MASK_SEL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG071D_LN2_CDR_LOCK_DELAY_BYPASS_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG071D_LN2_CDR_LOCK_DELAY_BYPASS_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG071D_LN2_CDR_LOCK_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG071D_LN2_CDR_LOCK_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_DONE_DELAY_BYPASS_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_DONE_DELAY_BYPASS_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_DONE_DELAY_BYPASS_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG071D_LN2_RX_OC_DONE_DELAY_BYPASS_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG071D_LN2_ANA_RX_CDR_EN_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG071D_LN2_ANA_RX_CDR_EN_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG071D_LN2_ANA_RX_CDR_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG071D_LN2_ANA_RX_CDR_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG071E (0x1C78)
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#define USBDP_TRSV_REG071E_LN2_ANA_RX_DES_EN_DELAY_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG071E_LN2_ANA_RX_DES_EN_DELAY_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG071E_LN2_ANA_RX_DES_EN_DELAY_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG071E_LN2_ANA_RX_DES_EN_DELAY_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG071F (0x1C7C)
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#define USBDP_TRSV_REG071F_LN2_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG071F_LN2_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG071F_LN2_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG071F_LN2_RX_SSLMS_DFE_VREF_EVEN_CTRL_OC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0720 (0x1C80)
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#define USBDP_TRSV_REG0720_LN2_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0720_LN2_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0720_LN2_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0720_LN2_RX_SSLMS_DFE_VREF_ODD_CTRL_OC_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0721 (0x1C84)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_MODE_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_MODE_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_MODE_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_MODE_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQHS_OFF_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SQDIG_RSTN_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_SIGVAL_FORCE_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0721_LN2_RX_SIGVAL_DIGITAL_LFPS_DET_MODE_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0722 (0x1C88)
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#define USBDP_TRSV_REG0722_LN2_RX_SIGVAL_DIGITAL_VALID_COUNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0722_LN2_RX_SIGVAL_DIGITAL_VALID_COUNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0722_LN2_RX_SIGVAL_DIGITAL_VALID_COUNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0722_LN2_RX_SIGVAL_DIGITAL_VALID_COUNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0723 (0x1C8C)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_EN_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_EN_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0723_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0724 (0x1C90)
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#define USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0725 (0x1C94)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_EN_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_EN_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0725_LN2_RX_CDR_DATA_MODE_EXIT_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0726 (0x1C98)
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#define USBDP_TRSV_REG0726_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0726_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0726_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0726_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0727 (0x1C9C)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SP_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0727_LN2_RX_CDR_DATA_MODE_EXIT_BW_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0727_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0727_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0727_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0727_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0728 (0x1CA0)
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#define USBDP_TRSV_REG0728_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0728_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0728_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0728_LN2_TG_RX_CDR_BW_CTRL_DELAY_TIME_SSP_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_FBB_CAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_FBB_CAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_FBB_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0728_LN2_OVRD_RX_CDR_FBB_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_FBB_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_FBB_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_FBB_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0728_LN2_RX_CDR_FBB_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0729 (0x1CA4)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_CK_MODE_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_CK_MODE_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_CK_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0729_LN2_OVRD_RX_CDR_FLD_CK_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_CK_MODE_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_CK_MODE_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_CK_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0729_LN2_RX_CDR_FLD_CK_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG072A (0x1CA8)
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#define USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG072B (0x1CAC)
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#define USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG072C (0x1CB0)
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#define USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG072D (0x1CB4)
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#define USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG072E (0x1CB8)
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#define USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG072F (0x1CBC)
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#define USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0730 (0x1CC0)
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#define USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0731 (0x1CC4)
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#define USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0732 (0x1CC8)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_ERR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_ERR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_ERR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_ERR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_EDGE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_EDGE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_EDGE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0732_LN2_RX_OC_DFE_ADAP_EN_EDGE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0733 (0x1CCC)
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#define USBDP_TRSV_REG0733_LN2_RX_SSLMS_C0_E_INIT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0733_LN2_RX_SSLMS_C0_E_INIT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0733_LN2_RX_SSLMS_C0_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0733_LN2_RX_SSLMS_C0_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0734 (0x1CD0)
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#define USBDP_TRSV_REG0734_LN2_RX_SSLMS_C1_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0734_LN2_RX_SSLMS_C1_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0734_LN2_RX_SSLMS_C1_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0734_LN2_RX_SSLMS_C1_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0735 (0x1CD4)
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#define USBDP_TRSV_REG0735_LN2_RX_SSLMS_C2_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0735_LN2_RX_SSLMS_C2_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0735_LN2_RX_SSLMS_C2_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0735_LN2_RX_SSLMS_C2_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0736 (0x1CD8)
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#define USBDP_TRSV_REG0736_LN2_RX_SSLMS_C3_E_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0736_LN2_RX_SSLMS_C3_E_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0736_LN2_RX_SSLMS_C3_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0736_LN2_RX_SSLMS_C3_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0737 (0x1CDC)
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#define USBDP_TRSV_REG0737_LN2_RX_SSLMS_C4_E_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0737_LN2_RX_SSLMS_C4_E_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0737_LN2_RX_SSLMS_C4_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0737_LN2_RX_SSLMS_C4_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0738 (0x1CE0)
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#define USBDP_TRSV_REG0738_LN2_RX_SSLMS_C5_E_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0738_LN2_RX_SSLMS_C5_E_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0738_LN2_RX_SSLMS_C5_E_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0738_LN2_RX_SSLMS_C5_E_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0739 (0x1CE4)
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#define USBDP_TRSV_REG0739_LN2_RX_SSLMS_C0_E_INIT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0739_LN2_RX_SSLMS_C0_E_INIT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0739_LN2_RX_SSLMS_C0_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0739_LN2_RX_SSLMS_C0_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG073A (0x1CE8)
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#define USBDP_TRSV_REG073A_LN2_RX_SSLMS_C1_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG073A_LN2_RX_SSLMS_C1_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG073A_LN2_RX_SSLMS_C1_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG073A_LN2_RX_SSLMS_C1_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG073B (0x1CEC)
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#define USBDP_TRSV_REG073B_LN2_RX_SSLMS_C2_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG073B_LN2_RX_SSLMS_C2_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG073B_LN2_RX_SSLMS_C2_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG073B_LN2_RX_SSLMS_C2_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG073C (0x1CF0)
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#define USBDP_TRSV_REG073C_LN2_RX_SSLMS_C3_E_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG073C_LN2_RX_SSLMS_C3_E_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG073C_LN2_RX_SSLMS_C3_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG073C_LN2_RX_SSLMS_C3_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG073D (0x1CF4)
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#define USBDP_TRSV_REG073D_LN2_RX_SSLMS_C4_E_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG073D_LN2_RX_SSLMS_C4_E_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG073D_LN2_RX_SSLMS_C4_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG073D_LN2_RX_SSLMS_C4_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG073E (0x1CF8)
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#define USBDP_TRSV_REG073E_LN2_RX_SSLMS_C5_E_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG073E_LN2_RX_SSLMS_C5_E_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG073E_LN2_RX_SSLMS_C5_E_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG073E_LN2_RX_SSLMS_C5_E_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG073F (0x1CFC)
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#define USBDP_TRSV_REG073F_LN2_RX_SSLMS_C0_O_INIT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG073F_LN2_RX_SSLMS_C0_O_INIT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG073F_LN2_RX_SSLMS_C0_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG073F_LN2_RX_SSLMS_C0_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0740 (0x1D00)
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#define USBDP_TRSV_REG0740_LN2_RX_SSLMS_C1_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0740_LN2_RX_SSLMS_C1_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0740_LN2_RX_SSLMS_C1_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0740_LN2_RX_SSLMS_C1_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0741 (0x1D04)
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#define USBDP_TRSV_REG0741_LN2_RX_SSLMS_C2_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0741_LN2_RX_SSLMS_C2_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0741_LN2_RX_SSLMS_C2_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0741_LN2_RX_SSLMS_C2_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0742 (0x1D08)
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#define USBDP_TRSV_REG0742_LN2_RX_SSLMS_C3_O_INIT_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0742_LN2_RX_SSLMS_C3_O_INIT_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0742_LN2_RX_SSLMS_C3_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0742_LN2_RX_SSLMS_C3_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0743 (0x1D0C)
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#define USBDP_TRSV_REG0743_LN2_RX_SSLMS_C4_O_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0743_LN2_RX_SSLMS_C4_O_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0743_LN2_RX_SSLMS_C4_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0743_LN2_RX_SSLMS_C4_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0744 (0x1D10)
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#define USBDP_TRSV_REG0744_LN2_RX_SSLMS_C5_O_INIT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0744_LN2_RX_SSLMS_C5_O_INIT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0744_LN2_RX_SSLMS_C5_O_INIT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0744_LN2_RX_SSLMS_C5_O_INIT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0745 (0x1D14)
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#define USBDP_TRSV_REG0745_LN2_RX_SSLMS_C0_O_INIT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0745_LN2_RX_SSLMS_C0_O_INIT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0745_LN2_RX_SSLMS_C0_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0745_LN2_RX_SSLMS_C0_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0746 (0x1D18)
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#define USBDP_TRSV_REG0746_LN2_RX_SSLMS_C1_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0746_LN2_RX_SSLMS_C1_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0746_LN2_RX_SSLMS_C1_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0746_LN2_RX_SSLMS_C1_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0747 (0x1D1C)
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#define USBDP_TRSV_REG0747_LN2_RX_SSLMS_C2_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0747_LN2_RX_SSLMS_C2_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0747_LN2_RX_SSLMS_C2_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0747_LN2_RX_SSLMS_C2_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0748 (0x1D20)
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#define USBDP_TRSV_REG0748_LN2_RX_SSLMS_C3_O_INIT_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0748_LN2_RX_SSLMS_C3_O_INIT_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0748_LN2_RX_SSLMS_C3_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0748_LN2_RX_SSLMS_C3_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0749 (0x1D24)
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#define USBDP_TRSV_REG0749_LN2_RX_SSLMS_C4_O_INIT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0749_LN2_RX_SSLMS_C4_O_INIT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0749_LN2_RX_SSLMS_C4_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0749_LN2_RX_SSLMS_C4_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG074A (0x1D28)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_C5_O_INIT_SSP_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_C5_O_INIT_SSP_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_C5_O_INIT_SSP_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_C5_O_INIT_SSP_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG074A_LN2_OVRD_RX_SSLMS_ADAP_DONE_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG074A_LN2_OVRD_RX_SSLMS_ADAP_DONE_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG074A_LN2_OVRD_RX_SSLMS_ADAP_DONE_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG074A_LN2_OVRD_RX_SSLMS_ADAP_DONE_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_ADAP_DONE_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_ADAP_DONE_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_ADAP_DONE_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG074A_LN2_RX_SSLMS_ADAP_DONE_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG074B (0x1D2C)
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#define USBDP_TRSV_REG074B_LN2_OVRD_RX_SSLMS_TRIG_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG074B_LN2_OVRD_RX_SSLMS_TRIG_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG074B_LN2_OVRD_RX_SSLMS_TRIG_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG074B_LN2_OVRD_RX_SSLMS_TRIG_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG074B_LN2_RX_SSLMS_TRIG_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG074B_LN2_RX_SSLMS_TRIG_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG074B_LN2_RX_SSLMS_TRIG_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG074B_LN2_RX_SSLMS_TRIG_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG074C (0x1D30)
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#define USBDP_TRSV_REG074C_LN2_OVRD_RX_SSLMS_C0_E_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG074C_LN2_OVRD_RX_SSLMS_C0_E_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG074C_LN2_OVRD_RX_SSLMS_C0_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG074C_LN2_OVRD_RX_SSLMS_C0_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG074D (0x1D34)
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#define USBDP_TRSV_REG074D_LN2_RX_SSLMS_C0_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG074D_LN2_RX_SSLMS_C0_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG074D_LN2_RX_SSLMS_C0_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG074D_LN2_RX_SSLMS_C0_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG074E (0x1D38)
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#define USBDP_TRSV_REG074E_LN2_OVRD_RX_SSLMS_C1_E_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG074E_LN2_OVRD_RX_SSLMS_C1_E_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG074E_LN2_OVRD_RX_SSLMS_C1_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG074E_LN2_OVRD_RX_SSLMS_C1_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG074F (0x1D3C)
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#define USBDP_TRSV_REG074F_LN2_RX_SSLMS_C1_E_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG074F_LN2_RX_SSLMS_C1_E_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG074F_LN2_RX_SSLMS_C1_E_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG074F_LN2_RX_SSLMS_C1_E_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0750 (0x1D40)
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#define USBDP_TRSV_REG0750_LN2_RX_SSLMS_C1_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0750_LN2_RX_SSLMS_C1_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0750_LN2_RX_SSLMS_C1_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0750_LN2_RX_SSLMS_C1_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0751 (0x1D44)
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#define USBDP_TRSV_REG0751_LN2_OVRD_RX_SSLMS_C2_E_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0751_LN2_OVRD_RX_SSLMS_C2_E_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0751_LN2_OVRD_RX_SSLMS_C2_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0751_LN2_OVRD_RX_SSLMS_C2_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0751_LN2_RX_SSLMS_C2_E_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0751_LN2_RX_SSLMS_C2_E_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0751_LN2_RX_SSLMS_C2_E_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0751_LN2_RX_SSLMS_C2_E_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0752 (0x1D48)
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#define USBDP_TRSV_REG0752_LN2_RX_SSLMS_C2_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0752_LN2_RX_SSLMS_C2_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0752_LN2_RX_SSLMS_C2_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0752_LN2_RX_SSLMS_C2_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0753 (0x1D4C)
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#define USBDP_TRSV_REG0753_LN2_OVRD_RX_SSLMS_C3_E_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0753_LN2_OVRD_RX_SSLMS_C3_E_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0753_LN2_OVRD_RX_SSLMS_C3_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0753_LN2_OVRD_RX_SSLMS_C3_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0753_LN2_RX_SSLMS_C3_E_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0753_LN2_RX_SSLMS_C3_E_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0753_LN2_RX_SSLMS_C3_E_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0753_LN2_RX_SSLMS_C3_E_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0754 (0x1D50)
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#define USBDP_TRSV_REG0754_LN2_RX_SSLMS_C3_E_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0754_LN2_RX_SSLMS_C3_E_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0754_LN2_RX_SSLMS_C3_E_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0754_LN2_RX_SSLMS_C3_E_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0755 (0x1D54)
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#define USBDP_TRSV_REG0755_LN2_OVRD_RX_SSLMS_C4_E_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0755_LN2_OVRD_RX_SSLMS_C4_E_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0755_LN2_OVRD_RX_SSLMS_C4_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0755_LN2_OVRD_RX_SSLMS_C4_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0755_LN2_RX_SSLMS_C4_E_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0755_LN2_RX_SSLMS_C4_E_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0755_LN2_RX_SSLMS_C4_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0755_LN2_RX_SSLMS_C4_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0756 (0x1D58)
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#define USBDP_TRSV_REG0756_LN2_OVRD_RX_SSLMS_C5_E_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0756_LN2_OVRD_RX_SSLMS_C5_E_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0756_LN2_OVRD_RX_SSLMS_C5_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0756_LN2_OVRD_RX_SSLMS_C5_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0756_LN2_RX_SSLMS_C5_E_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0756_LN2_RX_SSLMS_C5_E_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0756_LN2_RX_SSLMS_C5_E_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0756_LN2_RX_SSLMS_C5_E_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0757 (0x1D5C)
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#define USBDP_TRSV_REG0757_LN2_OVRD_RX_SSLMS_C0_O_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0757_LN2_OVRD_RX_SSLMS_C0_O_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0757_LN2_OVRD_RX_SSLMS_C0_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0757_LN2_OVRD_RX_SSLMS_C0_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0758 (0x1D60)
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#define USBDP_TRSV_REG0758_LN2_RX_SSLMS_C0_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0758_LN2_RX_SSLMS_C0_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0758_LN2_RX_SSLMS_C0_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0758_LN2_RX_SSLMS_C0_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0759 (0x1D64)
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#define USBDP_TRSV_REG0759_LN2_OVRD_RX_SSLMS_C1_O_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0759_LN2_OVRD_RX_SSLMS_C1_O_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0759_LN2_OVRD_RX_SSLMS_C1_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0759_LN2_OVRD_RX_SSLMS_C1_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG075A (0x1D68)
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#define USBDP_TRSV_REG075A_LN2_RX_SSLMS_C1_O_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG075A_LN2_RX_SSLMS_C1_O_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG075A_LN2_RX_SSLMS_C1_O_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG075A_LN2_RX_SSLMS_C1_O_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG075B (0x1D6C)
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#define USBDP_TRSV_REG075B_LN2_RX_SSLMS_C1_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG075B_LN2_RX_SSLMS_C1_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG075B_LN2_RX_SSLMS_C1_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG075B_LN2_RX_SSLMS_C1_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG075C (0x1D70)
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#define USBDP_TRSV_REG075C_LN2_OVRD_RX_SSLMS_C2_O_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG075C_LN2_OVRD_RX_SSLMS_C2_O_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG075C_LN2_OVRD_RX_SSLMS_C2_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG075C_LN2_OVRD_RX_SSLMS_C2_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG075C_LN2_RX_SSLMS_C2_O_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG075C_LN2_RX_SSLMS_C2_O_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG075C_LN2_RX_SSLMS_C2_O_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG075C_LN2_RX_SSLMS_C2_O_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG075D (0x1D74)
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#define USBDP_TRSV_REG075D_LN2_RX_SSLMS_C2_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG075D_LN2_RX_SSLMS_C2_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG075D_LN2_RX_SSLMS_C2_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG075D_LN2_RX_SSLMS_C2_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG075E (0x1D78)
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#define USBDP_TRSV_REG075E_LN2_OVRD_RX_SSLMS_C3_O_BIN_SP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG075E_LN2_OVRD_RX_SSLMS_C3_O_BIN_SP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG075E_LN2_OVRD_RX_SSLMS_C3_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG075E_LN2_OVRD_RX_SSLMS_C3_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG075E_LN2_RX_SSLMS_C3_O_BIN_SP__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG075E_LN2_RX_SSLMS_C3_O_BIN_SP__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG075E_LN2_RX_SSLMS_C3_O_BIN_SP__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG075E_LN2_RX_SSLMS_C3_O_BIN_SP__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG075F (0x1D7C)
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#define USBDP_TRSV_REG075F_LN2_RX_SSLMS_C3_O_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG075F_LN2_RX_SSLMS_C3_O_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG075F_LN2_RX_SSLMS_C3_O_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG075F_LN2_RX_SSLMS_C3_O_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0760 (0x1D80)
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#define USBDP_TRSV_REG0760_LN2_OVRD_RX_SSLMS_C4_O_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0760_LN2_OVRD_RX_SSLMS_C4_O_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0760_LN2_OVRD_RX_SSLMS_C4_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0760_LN2_OVRD_RX_SSLMS_C4_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0760_LN2_RX_SSLMS_C4_O_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0760_LN2_RX_SSLMS_C4_O_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0760_LN2_RX_SSLMS_C4_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0760_LN2_RX_SSLMS_C4_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0761 (0x1D84)
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#define USBDP_TRSV_REG0761_LN2_OVRD_RX_SSLMS_C5_O_BIN_SP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0761_LN2_OVRD_RX_SSLMS_C5_O_BIN_SP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0761_LN2_OVRD_RX_SSLMS_C5_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0761_LN2_OVRD_RX_SSLMS_C5_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0761_LN2_RX_SSLMS_C5_O_BIN_SP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0761_LN2_RX_SSLMS_C5_O_BIN_SP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0761_LN2_RX_SSLMS_C5_O_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0761_LN2_RX_SSLMS_C5_O_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0762 (0x1D88)
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#define USBDP_TRSV_REG0762_LN2_OVRD_RX_SSLMS_HF_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0762_LN2_OVRD_RX_SSLMS_HF_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0762_LN2_OVRD_RX_SSLMS_HF_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0762_LN2_OVRD_RX_SSLMS_HF_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0763 (0x1D8C)
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#define USBDP_TRSV_REG0763_LN2_RX_SSLMS_HF_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0763_LN2_RX_SSLMS_HF_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0763_LN2_RX_SSLMS_HF_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0763_LN2_RX_SSLMS_HF_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0764 (0x1D90)
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#define USBDP_TRSV_REG0764_LN2_RX_SSLMS_HF_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0764_LN2_RX_SSLMS_HF_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0764_LN2_RX_SSLMS_HF_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0764_LN2_RX_SSLMS_HF_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0765 (0x1D94)
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#define USBDP_TRSV_REG0765_LN2_OVRD_RX_SSLMS_MF_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0765_LN2_OVRD_RX_SSLMS_MF_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0765_LN2_OVRD_RX_SSLMS_MF_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0765_LN2_OVRD_RX_SSLMS_MF_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0766 (0x1D98)
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#define USBDP_TRSV_REG0766_LN2_RX_SSLMS_MF_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0766_LN2_RX_SSLMS_MF_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0766_LN2_RX_SSLMS_MF_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0766_LN2_RX_SSLMS_MF_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0767 (0x1D9C)
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#define USBDP_TRSV_REG0767_LN2_RX_SSLMS_MF_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0767_LN2_RX_SSLMS_MF_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0767_LN2_RX_SSLMS_MF_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0767_LN2_RX_SSLMS_MF_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0768 (0x1DA0)
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#define USBDP_TRSV_REG0768_LN2_OVRD_RX_SSLMS_VGA_BIN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0768_LN2_OVRD_RX_SSLMS_VGA_BIN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0768_LN2_OVRD_RX_SSLMS_VGA_BIN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0768_LN2_OVRD_RX_SSLMS_VGA_BIN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0769 (0x1DA4)
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#define USBDP_TRSV_REG0769_LN2_RX_SSLMS_VGA_BIN_SP__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0769_LN2_RX_SSLMS_VGA_BIN_SP__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0769_LN2_RX_SSLMS_VGA_BIN_SP__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0769_LN2_RX_SSLMS_VGA_BIN_SP__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG076A (0x1DA8)
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#define USBDP_TRSV_REG076A_LN2_RX_SSLMS_VGA_BIN_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG076A_LN2_RX_SSLMS_VGA_BIN_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG076A_LN2_RX_SSLMS_VGA_BIN_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG076A_LN2_RX_SSLMS_VGA_BIN_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG076B (0x1DAC)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_DONE_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_DONE_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_DONE_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_DONE_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_DONE_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_DONE_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_DONE_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_DONE_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_TRIG_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_TRIG_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_TRIG_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_TRIG_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_TRIG_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_TRIG_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_TRIG_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_TRIG_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SP_RESERVED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SP_RESERVED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG076B_LN2_OVRD_RX_SSLMS_ADAP_EN_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SSP_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SSP_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG076B_LN2_RX_SSLMS_ADAP_EN_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG076C (0x1DB0)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SP_RESERVED_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SP_RESERVED_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SP_RESERVED_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SP_RESERVED_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG076C_LN2_OVRD_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG076C_LN2_RX_SSLMS_ADAP_HOLD_SSP_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG076D (0x1DB4)
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#define USBDP_TRSV_REG076D_LN2_OVRD_RX_SSLMS_C0_E_BIN_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG076D_LN2_OVRD_RX_SSLMS_C0_E_BIN_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG076D_LN2_OVRD_RX_SSLMS_C0_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG076D_LN2_OVRD_RX_SSLMS_C0_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG076E (0x1DB8)
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#define USBDP_TRSV_REG076E_LN2_RX_SSLMS_C0_E_BIN_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG076E_LN2_RX_SSLMS_C0_E_BIN_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG076E_LN2_RX_SSLMS_C0_E_BIN_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG076E_LN2_RX_SSLMS_C0_E_BIN_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG076F (0x1DBC)
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#define USBDP_TRSV_REG076F_LN2_OVRD_RX_SSLMS_C1_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG076F_LN2_OVRD_RX_SSLMS_C1_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG076F_LN2_OVRD_RX_SSLMS_C1_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG076F_LN2_OVRD_RX_SSLMS_C1_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG076F_LN2_RX_SSLMS_C1_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG076F_LN2_RX_SSLMS_C1_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG076F_LN2_RX_SSLMS_C1_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG076F_LN2_RX_SSLMS_C1_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0770 (0x1DC0)
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#define USBDP_TRSV_REG0770_LN2_OVRD_RX_SSLMS_C2_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0770_LN2_OVRD_RX_SSLMS_C2_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0770_LN2_OVRD_RX_SSLMS_C2_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0770_LN2_OVRD_RX_SSLMS_C2_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0770_LN2_RX_SSLMS_C2_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0770_LN2_RX_SSLMS_C2_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0770_LN2_RX_SSLMS_C2_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0770_LN2_RX_SSLMS_C2_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0771 (0x1DC4)
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#define USBDP_TRSV_REG0771_LN2_OVRD_RX_SSLMS_C3_E_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0771_LN2_OVRD_RX_SSLMS_C3_E_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0771_LN2_OVRD_RX_SSLMS_C3_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0771_LN2_OVRD_RX_SSLMS_C3_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0771_LN2_RX_SSLMS_C3_E_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0771_LN2_RX_SSLMS_C3_E_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0771_LN2_RX_SSLMS_C3_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0771_LN2_RX_SSLMS_C3_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0772 (0x1DC8)
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#define USBDP_TRSV_REG0772_LN2_OVRD_RX_SSLMS_C4_E_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0772_LN2_OVRD_RX_SSLMS_C4_E_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0772_LN2_OVRD_RX_SSLMS_C4_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0772_LN2_OVRD_RX_SSLMS_C4_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0772_LN2_RX_SSLMS_C4_E_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0772_LN2_RX_SSLMS_C4_E_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0772_LN2_RX_SSLMS_C4_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0772_LN2_RX_SSLMS_C4_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0773 (0x1DCC)
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#define USBDP_TRSV_REG0773_LN2_OVRD_RX_SSLMS_C5_E_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0773_LN2_OVRD_RX_SSLMS_C5_E_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0773_LN2_OVRD_RX_SSLMS_C5_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0773_LN2_OVRD_RX_SSLMS_C5_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0773_LN2_RX_SSLMS_C5_E_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0773_LN2_RX_SSLMS_C5_E_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0773_LN2_RX_SSLMS_C5_E_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0773_LN2_RX_SSLMS_C5_E_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG0774 (0x1DD0)
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#define USBDP_TRSV_REG0774_LN2_OVRD_RX_SSLMS_C0_O_BIN_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0774_LN2_OVRD_RX_SSLMS_C0_O_BIN_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0774_LN2_OVRD_RX_SSLMS_C0_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0774_LN2_OVRD_RX_SSLMS_C0_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0775 (0x1DD4)
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#define USBDP_TRSV_REG0775_LN2_RX_SSLMS_C0_O_BIN_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0775_LN2_RX_SSLMS_C0_O_BIN_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0775_LN2_RX_SSLMS_C0_O_BIN_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0775_LN2_RX_SSLMS_C0_O_BIN_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0776 (0x1DD8)
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#define USBDP_TRSV_REG0776_LN2_OVRD_RX_SSLMS_C1_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0776_LN2_OVRD_RX_SSLMS_C1_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0776_LN2_OVRD_RX_SSLMS_C1_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0776_LN2_OVRD_RX_SSLMS_C1_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0776_LN2_RX_SSLMS_C1_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0776_LN2_RX_SSLMS_C1_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0776_LN2_RX_SSLMS_C1_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0776_LN2_RX_SSLMS_C1_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0777 (0x1DDC)
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#define USBDP_TRSV_REG0777_LN2_OVRD_RX_SSLMS_C2_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0777_LN2_OVRD_RX_SSLMS_C2_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0777_LN2_OVRD_RX_SSLMS_C2_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0777_LN2_OVRD_RX_SSLMS_C2_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0777_LN2_RX_SSLMS_C2_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0777_LN2_RX_SSLMS_C2_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0777_LN2_RX_SSLMS_C2_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0777_LN2_RX_SSLMS_C2_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0778 (0x1DE0)
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#define USBDP_TRSV_REG0778_LN2_OVRD_RX_SSLMS_C3_O_BIN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0778_LN2_OVRD_RX_SSLMS_C3_O_BIN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0778_LN2_OVRD_RX_SSLMS_C3_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0778_LN2_OVRD_RX_SSLMS_C3_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0778_LN2_RX_SSLMS_C3_O_BIN_SSP_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG0778_LN2_RX_SSLMS_C3_O_BIN_SSP_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG0778_LN2_RX_SSLMS_C3_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG0778_LN2_RX_SSLMS_C3_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG0779 (0x1DE4)
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#define USBDP_TRSV_REG0779_LN2_OVRD_RX_SSLMS_C4_O_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0779_LN2_OVRD_RX_SSLMS_C4_O_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0779_LN2_OVRD_RX_SSLMS_C4_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0779_LN2_OVRD_RX_SSLMS_C4_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0779_LN2_RX_SSLMS_C4_O_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG0779_LN2_RX_SSLMS_C4_O_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG0779_LN2_RX_SSLMS_C4_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG0779_LN2_RX_SSLMS_C4_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG077A (0x1DE8)
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#define USBDP_TRSV_REG077A_LN2_OVRD_RX_SSLMS_C5_O_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG077A_LN2_OVRD_RX_SSLMS_C5_O_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG077A_LN2_OVRD_RX_SSLMS_C5_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG077A_LN2_OVRD_RX_SSLMS_C5_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG077A_LN2_RX_SSLMS_C5_O_BIN_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG077A_LN2_RX_SSLMS_C5_O_BIN_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG077A_LN2_RX_SSLMS_C5_O_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG077A_LN2_RX_SSLMS_C5_O_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG077B (0x1DEC)
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#define USBDP_TRSV_REG077B_LN2_OVRD_RX_SSLMS_HF_BIN_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG077B_LN2_OVRD_RX_SSLMS_HF_BIN_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG077B_LN2_OVRD_RX_SSLMS_HF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG077B_LN2_OVRD_RX_SSLMS_HF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG077B_LN2_RX_SSLMS_HF_BIN_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG077B_LN2_RX_SSLMS_HF_BIN_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG077B_LN2_RX_SSLMS_HF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG077B_LN2_RX_SSLMS_HF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG077C (0x1DF0)
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#define USBDP_TRSV_REG077C_LN2_OVRD_RX_SSLMS_MF_BIN_SSP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG077C_LN2_OVRD_RX_SSLMS_MF_BIN_SSP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG077C_LN2_OVRD_RX_SSLMS_MF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG077C_LN2_OVRD_RX_SSLMS_MF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG077C_LN2_RX_SSLMS_MF_BIN_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG077C_LN2_RX_SSLMS_MF_BIN_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG077C_LN2_RX_SSLMS_MF_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG077C_LN2_RX_SSLMS_MF_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG077D (0x1DF4)
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#define USBDP_TRSV_REG077D_LN2_OVRD_RX_SSLMS_VGA_BIN_SSP_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG077D_LN2_OVRD_RX_SSLMS_VGA_BIN_SSP_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG077D_LN2_OVRD_RX_SSLMS_VGA_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG077D_LN2_OVRD_RX_SSLMS_VGA_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG077D_LN2_RX_SSLMS_VGA_BIN_SSP_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG077D_LN2_RX_SSLMS_VGA_BIN_SSP_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG077D_LN2_RX_SSLMS_VGA_BIN_SSP_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG077D_LN2_RX_SSLMS_VGA_BIN_SSP_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG077D_LN2_TX_RXD_STATUS_ASYNC_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG077D_LN2_TX_RXD_STATUS_ASYNC_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG077D_LN2_TX_RXD_STATUS_ASYNC_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG077D_LN2_TX_RXD_STATUS_ASYNC_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG077E (0x1DF8)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG077E_LN2_RX_SQHS_TH_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG077F (0x1DFC)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG077F_LN2_RX_SQHS_TH_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0780 (0x1E00)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0780_LN2_RX_SQHS_TH_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0781 (0x1E04)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0781_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0782 (0x1E08)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR2_MSK USBDP_REG_MSK(5, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR2_CLR USBDP_REG_CLR(5, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR3_MSK USBDP_REG_MSK(3, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR3_CLR USBDP_REG_CLR(3, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_DFE_MADD_PBIAS_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 2)
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#define USBDP_TRSV_REG0782_LN2_RX_CDR_CP_CTRL_SP_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0782_LN2_RX_CDR_CP_CTRL_SP_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0782_LN2_RX_CDR_CP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0782_LN2_RX_CDR_CP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0783 (0x1E0C)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_SSP_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_SSP_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_RBR_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_RBR_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0783_LN2_RX_CDR_CP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0784 (0x1E10)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR2_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR2_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0784_LN2_RX_CDR_CP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0785 (0x1E14)
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#define USBDP_TRSV_REG0785_LN2_RX_CDR_CP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0785_LN2_RX_CDR_CP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0785_LN2_RX_CDR_CP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0785_LN2_RX_CDR_CP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0786 (0x1E18)
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#define USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0787 (0x1E1C)
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#define USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0788 (0x1E20)
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#define USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0789 (0x1E24)
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#define USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG078A (0x1E28)
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#define USBDP_TRSV_REG078A_LN2_RX_CDR_AFC_PMS_M_RBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG078A_LN2_RX_CDR_AFC_PMS_M_RBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG078A_LN2_RX_CDR_AFC_PMS_M_RBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG078A_LN2_RX_CDR_AFC_PMS_M_RBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG078B (0x1E2C)
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#define USBDP_TRSV_REG078B_LN2_RX_CDR_AFC_PMS_M_RBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG078B_LN2_RX_CDR_AFC_PMS_M_RBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG078B_LN2_RX_CDR_AFC_PMS_M_RBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG078B_LN2_RX_CDR_AFC_PMS_M_RBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG078C (0x1E30)
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#define USBDP_TRSV_REG078C_LN2_RX_CDR_AFC_PMS_M_HBR__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG078C_LN2_RX_CDR_AFC_PMS_M_HBR__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG078C_LN2_RX_CDR_AFC_PMS_M_HBR__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG078C_LN2_RX_CDR_AFC_PMS_M_HBR__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG078D (0x1E34)
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#define USBDP_TRSV_REG078D_LN2_RX_CDR_AFC_PMS_M_HBR__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG078D_LN2_RX_CDR_AFC_PMS_M_HBR__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG078D_LN2_RX_CDR_AFC_PMS_M_HBR__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG078D_LN2_RX_CDR_AFC_PMS_M_HBR__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG078E (0x1E38)
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#define USBDP_TRSV_REG078E_LN2_RX_CDR_AFC_PMS_M_HBR2__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG078E_LN2_RX_CDR_AFC_PMS_M_HBR2__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG078E_LN2_RX_CDR_AFC_PMS_M_HBR2__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG078E_LN2_RX_CDR_AFC_PMS_M_HBR2__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG078F (0x1E3C)
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#define USBDP_TRSV_REG078F_LN2_RX_CDR_AFC_PMS_M_HBR2__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG078F_LN2_RX_CDR_AFC_PMS_M_HBR2__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG078F_LN2_RX_CDR_AFC_PMS_M_HBR2__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG078F_LN2_RX_CDR_AFC_PMS_M_HBR2__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0790 (0x1E40)
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#define USBDP_TRSV_REG0790_LN2_RX_CDR_AFC_PMS_M_HBR3__8_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0790_LN2_RX_CDR_AFC_PMS_M_HBR3__8_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0790_LN2_RX_CDR_AFC_PMS_M_HBR3__8_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0790_LN2_RX_CDR_AFC_PMS_M_HBR3__8_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0791 (0x1E44)
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#define USBDP_TRSV_REG0791_LN2_RX_CDR_AFC_PMS_M_HBR3__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0791_LN2_RX_CDR_AFC_PMS_M_HBR3__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0791_LN2_RX_CDR_AFC_PMS_M_HBR3__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0791_LN2_RX_CDR_AFC_PMS_M_HBR3__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0792 (0x1E48)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0792_LN2_OVRD_RX_CDR_AFC_PMS_M_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0793 (0x1E4C)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_TARGET_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_TARGET_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_TARGET_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_TARGET_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MAN_MODE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MAN_MODE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MAN_MODE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MAN_MODE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_DAC_CODE_SEL_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_DAC_CODE_SEL_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_DAC_CODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0793_LN2_RX_OC_MON_DAC_CODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0794 (0x1E50)
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#define USBDP_TRSV_REG0794_LN2_RX_OC_MON_CODE_SEL_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0794_LN2_RX_OC_MON_CODE_SEL_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0794_LN2_RX_OC_MON_CODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0794_LN2_RX_OC_MON_CODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0795 (0x1E54)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_MAN_TARGET_SEL_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_MAN_TARGET_SEL_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_MAN_TARGET_SEL_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_MAN_TARGET_SEL_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_RAW_DATA_READ_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_RAW_DATA_READ_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_RAW_DATA_READ_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0795_LN2_RX_OC_RAW_DATA_READ_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0795_LN2_RX_OV_I_OC_DAC_CODE_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG0795_LN2_RX_OV_I_OC_DAC_CODE_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG0795_LN2_RX_OV_I_OC_DAC_CODE_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG0795_LN2_RX_OV_I_OC_DAC_CODE_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG0796 (0x1E58)
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#define USBDP_TRSV_REG0796_LN2_RX_OV_I_OC_CODE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0796_LN2_RX_OV_I_OC_CODE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0796_LN2_RX_OV_I_OC_CODE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0796_LN2_RX_OV_I_OC_CODE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0797 (0x1E5C)
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#define USBDP_TRSV_REG0797_LN2_RX_OC_MODE_SEL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0797_LN2_RX_OC_MODE_SEL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0797_LN2_RX_OC_MODE_SEL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0797_LN2_RX_OC_MODE_SEL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0798 (0x1E60)
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#define USBDP_TRSV_REG0798_LN2_RX_CDR_VCO_STARTUP_DELAY_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0798_LN2_RX_CDR_VCO_STARTUP_DELAY_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0798_LN2_RX_CDR_VCO_STARTUP_DELAY_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0798_LN2_RX_CDR_VCO_STARTUP_DELAY_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0799 (0x1E64)
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#define USBDP_TRSV_REG0799_LN2_RX_CDR_VCO_STARTUP_DELAY_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0799_LN2_RX_CDR_VCO_STARTUP_DELAY_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0799_LN2_RX_CDR_VCO_STARTUP_DELAY_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0799_LN2_RX_CDR_VCO_STARTUP_DELAY_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079A (0x1E68)
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#define USBDP_TRSV_REG079A_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG079A_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG079A_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG079A_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079B (0x1E6C)
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#define USBDP_TRSV_REG079B_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG079B_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG079B_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG079B_LN2_RX_SIGVAL_DIGITAL_CDR_BW_COUNT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079C (0x1E70)
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#define USBDP_TRSV_REG079C_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG079C_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG079C_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG079C_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079D (0x1E74)
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#define USBDP_TRSV_REG079D_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG079D_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG079D_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG079D_LN2_RX_SIGVAL_DIGITAL_HS_EXIT_DELAY_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079E (0x1E78)
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#define USBDP_TRSV_REG079E_LN2_BIST_AUTO_RX_HOLD_COUNT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG079E_LN2_BIST_AUTO_RX_HOLD_COUNT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG079E_LN2_BIST_AUTO_RX_HOLD_COUNT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG079E_LN2_BIST_AUTO_RX_HOLD_COUNT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG079F (0x1E7C)
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#define USBDP_TRSV_REG079F_LN2_LANE_RESERVED8_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG079F_LN2_LANE_RESERVED8_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG079F_LN2_LANE_RESERVED8_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG079F_LN2_LANE_RESERVED8_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_UGAMP_IBOOST_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_VDD_BYPASS_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_VDD_BYPASS_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_VDD_BYPASS_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG079F_LN2_ANA_RX_CDR_FBB_VDD_BYPASS_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07A0 (0x1E80)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED9_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED9_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED9_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED9_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_BIAS_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED10_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED10_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED10_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG07A0_LN2_LANE_RESERVED10_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG07A0_LN2_ANA_RX_DFE_MADD_PBIAS_OC_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG07A1 (0x1E84)
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#define USBDP_TRSV_REG07A1_LN2_LANE_RESERVED11_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG07A1_LN2_LANE_RESERVED11_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG07A1_LN2_LANE_RESERVED11_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG07A1_LN2_LANE_RESERVED11_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG07A1_LN2_ANA_RX_CDR_FBB_POWER_SAVE_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG07A1_LN2_ANA_RX_CDR_FBB_POWER_SAVE_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG07A1_LN2_ANA_RX_CDR_FBB_POWER_SAVE_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG07A1_LN2_ANA_RX_CDR_FBB_POWER_SAVE_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG07A1_LN2_LANE_AUX_DTB_SEL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A1_LN2_LANE_AUX_DTB_SEL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A1_LN2_LANE_AUX_DTB_SEL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A1_LN2_LANE_AUX_DTB_SEL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A2 (0x1E88)
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#define USBDP_TRSV_REG07A2_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A2_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A2_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A2_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A3 (0x1E8C)
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#define USBDP_TRSV_REG07A3_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A3_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A3_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A3_LN2_RX_CDR_FBB_VCO_CNT_RUN_NO_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A4 (0x1E90)
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#define USBDP_TRSV_REG07A4_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A4_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A4_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A4_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A5 (0x1E94)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SSP_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07A5_LN2_RX_CDR_FBB_MAN_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07A6 (0x1E98)
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#define USBDP_TRSV_REG07A6_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A6_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A6_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A6_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A7 (0x1E9C)
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#define USBDP_TRSV_REG07A7_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A7_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A7_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A7_LN2_RX_CDR_FBB_MAN_CODE_UPDC_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A8 (0x1EA0)
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#define USBDP_TRSV_REG07A8_LN2_RX_CDR_FBB_DELTA_CNT_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A8_LN2_RX_CDR_FBB_DELTA_CNT_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A8_LN2_RX_CDR_FBB_DELTA_CNT_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A8_LN2_RX_CDR_FBB_DELTA_CNT_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07A9 (0x1EA4)
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#define USBDP_TRSV_REG07A9_LN2_RX_CDR_FBB_DELTA_CNT_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07A9_LN2_RX_CDR_FBB_DELTA_CNT_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07A9_LN2_RX_CDR_FBB_DELTA_CNT_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07A9_LN2_RX_CDR_FBB_DELTA_CNT_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AA (0x1EA8)
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#define USBDP_TRSV_REG07AA_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AA_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AA_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AA_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AB (0x1EAC)
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#define USBDP_TRSV_REG07AB_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AB_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AB_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AB_LN2_RX_CDR_FBB_PLL_MODE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AC (0x1EB0)
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#define USBDP_TRSV_REG07AC_LN2_RX_CDR_FBB_COARSE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AC_LN2_RX_CDR_FBB_COARSE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AC_LN2_RX_CDR_FBB_COARSE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AC_LN2_RX_CDR_FBB_COARSE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AD (0x1EB4)
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#define USBDP_TRSV_REG07AD_LN2_RX_CDR_FBB_COARSE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AD_LN2_RX_CDR_FBB_COARSE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AD_LN2_RX_CDR_FBB_COARSE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AD_LN2_RX_CDR_FBB_COARSE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AE (0x1EB8)
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#define USBDP_TRSV_REG07AE_LN2_RX_CDR_FBB_FINE_CTRL_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AE_LN2_RX_CDR_FBB_FINE_CTRL_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AE_LN2_RX_CDR_FBB_FINE_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AE_LN2_RX_CDR_FBB_FINE_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07AF (0x1EBC)
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#define USBDP_TRSV_REG07AF_LN2_RX_CDR_FBB_FINE_CTRL_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07AF_LN2_RX_CDR_FBB_FINE_CTRL_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07AF_LN2_RX_CDR_FBB_FINE_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07AF_LN2_RX_CDR_FBB_FINE_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B0 (0x1EC0)
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#define USBDP_TRSV_REG07B0_LN2_RX_CDR_FBB_PLL_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B0_LN2_RX_CDR_FBB_PLL_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B0_LN2_RX_CDR_FBB_PLL_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B0_LN2_RX_CDR_FBB_PLL_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B1 (0x1EC4)
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#define USBDP_TRSV_REG07B1_LN2_RX_CDR_FBB_PLL_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B1_LN2_RX_CDR_FBB_PLL_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B1_LN2_RX_CDR_FBB_PLL_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B1_LN2_RX_CDR_FBB_PLL_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B2 (0x1EC8)
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#define USBDP_TRSV_REG07B2_LN2_RX_CDR_FBB_HI_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B2_LN2_RX_CDR_FBB_HI_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B2_LN2_RX_CDR_FBB_HI_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B2_LN2_RX_CDR_FBB_HI_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B3 (0x1ECC)
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#define USBDP_TRSV_REG07B3_LN2_RX_CDR_FBB_HI_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B3_LN2_RX_CDR_FBB_HI_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B3_LN2_RX_CDR_FBB_HI_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B3_LN2_RX_CDR_FBB_HI_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B4 (0x1ED0)
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#define USBDP_TRSV_REG07B4_LN2_RX_CDR_FBB_LO_BW_DIFF_SP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B4_LN2_RX_CDR_FBB_LO_BW_DIFF_SP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B4_LN2_RX_CDR_FBB_LO_BW_DIFF_SP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B4_LN2_RX_CDR_FBB_LO_BW_DIFF_SP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07B5 (0x1ED4)
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#define USBDP_TRSV_REG07B5_LN2_RX_CDR_FBB_LO_BW_DIFF_SSP_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07B5_LN2_RX_CDR_FBB_LO_BW_DIFF_SSP_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07B5_LN2_RX_CDR_FBB_LO_BW_DIFF_SSP_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07B5_LN2_RX_CDR_FBB_LO_BW_DIFF_SSP_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07C0 (0x1F00)
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#define USBDP_TRSV_REG07C0_LN2_MON_LANE_STATE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_LANE_STATE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_LANE_STATE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_LANE_STATE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_CDR_STATE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_CDR_STATE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_CDR_STATE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07C0_LN2_MON_CDR_STATE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07C1 (0x1F04)
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#define USBDP_TRSV_REG07C1_LN2_MON_LANE_TIME__14_8_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07C1_LN2_MON_LANE_TIME__14_8_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07C1_LN2_MON_LANE_TIME__14_8_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07C1_LN2_MON_LANE_TIME__14_8_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07C2 (0x1F08)
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#define USBDP_TRSV_REG07C2_LN2_MON_LANE_TIME__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07C2_LN2_MON_LANE_TIME__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07C2_LN2_MON_LANE_TIME__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07C2_LN2_MON_LANE_TIME__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07C3 (0x1F0C)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_AFC_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_AFC_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_AFC_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_AFC_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_CAL_DONE_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_CAL_DONE_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_FLD_PLL_MODE_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_FLD_PLL_MODE_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_FLD_PLL_MODE_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_FLD_PLL_MODE_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_LOCK_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_LOCK_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_LOCK_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07C3_LN2_MON_RX_CDR_LOCK_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07C4 (0x1F10)
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#define USBDP_TRSV_REG07C4_LN2_MON_RX_CDR_AFC_SEL_LOGIC_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07C4_LN2_MON_RX_CDR_AFC_SEL_LOGIC_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07C4_LN2_MON_RX_CDR_AFC_SEL_LOGIC_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07C4_LN2_MON_RX_CDR_AFC_SEL_LOGIC_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07C5 (0x1F14)
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#define USBDP_TRSV_REG07C5_LN2_MON_RX_CDR_FBB_FINE_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07C5_LN2_MON_RX_CDR_FBB_FINE_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07C5_LN2_MON_RX_CDR_FBB_FINE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07C5_LN2_MON_RX_CDR_FBB_FINE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07C6 (0x1F18)
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#define USBDP_TRSV_REG07C6_LN2_MON_RX_CDR_FBB_COARSE_CTRL_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07C6_LN2_MON_RX_CDR_FBB_COARSE_CTRL_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07C6_LN2_MON_RX_CDR_FBB_COARSE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07C6_LN2_MON_RX_CDR_FBB_COARSE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07C7 (0x1F1C)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_FBB_PLL_MODE_CTRL_MSK USBDP_REG_MSK(2, 6)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_FBB_PLL_MODE_CTRL_CLR USBDP_REG_CLR(2, 6)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_FBB_PLL_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 6)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_FBB_PLL_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 6)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_MODE_CTRL_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_MODE_CTRL_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_MODE_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG07C7_LN2_MON_RX_CDR_MODE_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG07C8 (0x1F20)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_TEST_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_TEST_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_TEST_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_TEST_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_ERRINJ_TEST_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_ERRINJ_TEST_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_ERRINJ_TEST_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_ERRINJ_TEST_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_START_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_START_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_START_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07C8_LN2_MON_BIST_COMP_START_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07C9 (0x1F24)
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#define USBDP_TRSV_REG07C9_LN2_MON_BIST_EOUT_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07C9_LN2_MON_BIST_EOUT_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07C9_LN2_MON_BIST_EOUT_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07C9_LN2_MON_BIST_EOUT_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07CA (0x1F28)
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#define USBDP_TRSV_REG07CA_LN2_MON_RX_OC_DFE_ADDER_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07CA_LN2_MON_RX_OC_DFE_ADDER_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07CA_LN2_MON_RX_OC_DFE_ADDER_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07CA_LN2_MON_RX_OC_DFE_ADDER_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07CB (0x1F2C)
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#define USBDP_TRSV_REG07CB_LN2_MON_RX_OC_DFE_ADDER_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07CB_LN2_MON_RX_OC_DFE_ADDER_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07CB_LN2_MON_RX_OC_DFE_ADDER_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07CB_LN2_MON_RX_OC_DFE_ADDER_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07CC (0x1F30)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_EVEN_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_EVEN_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_EVEN_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_EVEN_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_ODD_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_ODD_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_ODD_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG07CC_LN2_MON_RX_OC_DFE_DAC_ADDER_ODD_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG07CD (0x1F34)
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#define USBDP_TRSV_REG07CD_LN2_MON_RX_OC_DFE_SA_EDGE_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07CD_LN2_MON_RX_OC_DFE_SA_EDGE_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07CD_LN2_MON_RX_OC_DFE_SA_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07CD_LN2_MON_RX_OC_DFE_SA_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07CE (0x1F38)
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#define USBDP_TRSV_REG07CE_LN2_MON_RX_OC_DFE_SA_EDGE_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07CE_LN2_MON_RX_OC_DFE_SA_EDGE_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07CE_LN2_MON_RX_OC_DFE_SA_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07CE_LN2_MON_RX_OC_DFE_SA_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07CF (0x1F3C)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_ODD_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_ODD_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_ODD_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_ODD_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_EVEN_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_EVEN_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG07CF_LN2_MON_RX_OC_DFE_DAC_EDGE_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG07D0 (0x1F40)
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#define USBDP_TRSV_REG07D0_LN2_MON_RX_OC_DFE_SA_ERR_EVEN_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D0_LN2_MON_RX_OC_DFE_SA_ERR_EVEN_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D0_LN2_MON_RX_OC_DFE_SA_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D0_LN2_MON_RX_OC_DFE_SA_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07D1 (0x1F44)
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#define USBDP_TRSV_REG07D1_LN2_MON_RX_OC_DFE_SA_ERR_ODD_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D1_LN2_MON_RX_OC_DFE_SA_ERR_ODD_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D1_LN2_MON_RX_OC_DFE_SA_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D1_LN2_MON_RX_OC_DFE_SA_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07D2 (0x1F48)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_EVEN_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_EVEN_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_EVEN_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_EVEN_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_ODD_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_ODD_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_ODD_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG07D2_LN2_MON_RX_OC_DFE_DAC_ERR_ODD_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG07D3 (0x1F4C)
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#define USBDP_TRSV_REG07D3_LN2_MON_RX_OC_CTLE_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D3_LN2_MON_RX_OC_CTLE_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D3_LN2_MON_RX_OC_CTLE_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D3_LN2_MON_RX_OC_CTLE_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07D4 (0x1F50)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFN_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFN_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFN_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFN_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07D4_LN2_MON_RX_OC_SQ_DIFP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07D5 (0x1F54)
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#define USBDP_TRSV_REG07D5_LN2_MON_RX_OC_CAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07D5_LN2_MON_RX_OC_CAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07D5_LN2_MON_RX_OC_CAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07D5_LN2_MON_RX_OC_CAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07D6 (0x1F58)
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#define USBDP_TRSV_REG07D6_LN2_MON_RX_OC_FAIL__10_8_MSK USBDP_REG_MSK(0, 3)
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#define USBDP_TRSV_REG07D6_LN2_MON_RX_OC_FAIL__10_8_CLR USBDP_REG_CLR(0, 3)
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#define USBDP_TRSV_REG07D6_LN2_MON_RX_OC_FAIL__10_8_SET(_x) USBDP_REG_SET(_x, 0, 3)
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#define USBDP_TRSV_REG07D6_LN2_MON_RX_OC_FAIL__10_8_GET(_R) USBDP_REG_GET(_R, 0, 3)
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#define EXYNOS_USBDP_TRSV_REG07D7 (0x1F5C)
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#define USBDP_TRSV_REG07D7_LN2_MON_RX_OC_FAIL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D7_LN2_MON_RX_OC_FAIL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D7_LN2_MON_RX_OC_FAIL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D7_LN2_MON_RX_OC_FAIL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07D8 (0x1F60)
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#define USBDP_TRSV_REG07D8_LN2_MON_RX_SSLMS_C0_E_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D8_LN2_MON_RX_SSLMS_C0_E_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D8_LN2_MON_RX_SSLMS_C0_E_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D8_LN2_MON_RX_SSLMS_C0_E_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07D9 (0x1F64)
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#define USBDP_TRSV_REG07D9_LN2_MON_RX_SSLMS_C0_O_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07D9_LN2_MON_RX_SSLMS_C0_O_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07D9_LN2_MON_RX_SSLMS_C0_O_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07D9_LN2_MON_RX_SSLMS_C0_O_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07DA (0x1F68)
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#define USBDP_TRSV_REG07DA_LN2_MON_RX_SSLMS_C1_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DA_LN2_MON_RX_SSLMS_C1_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DA_LN2_MON_RX_SSLMS_C1_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DA_LN2_MON_RX_SSLMS_C1_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07DB (0x1F6C)
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#define USBDP_TRSV_REG07DB_LN2_MON_RX_SSLMS_C1_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DB_LN2_MON_RX_SSLMS_C1_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DB_LN2_MON_RX_SSLMS_C1_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DB_LN2_MON_RX_SSLMS_C1_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07DC (0x1F70)
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#define USBDP_TRSV_REG07DC_LN2_MON_RX_SSLMS_C2_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DC_LN2_MON_RX_SSLMS_C2_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DC_LN2_MON_RX_SSLMS_C2_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DC_LN2_MON_RX_SSLMS_C2_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07DD (0x1F74)
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#define USBDP_TRSV_REG07DD_LN2_MON_RX_SSLMS_C2_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DD_LN2_MON_RX_SSLMS_C2_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DD_LN2_MON_RX_SSLMS_C2_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DD_LN2_MON_RX_SSLMS_C2_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07DE (0x1F78)
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#define USBDP_TRSV_REG07DE_LN2_MON_RX_SSLMS_C3_E_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DE_LN2_MON_RX_SSLMS_C3_E_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DE_LN2_MON_RX_SSLMS_C3_E_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DE_LN2_MON_RX_SSLMS_C3_E_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07DF (0x1F7C)
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#define USBDP_TRSV_REG07DF_LN2_MON_RX_SSLMS_C3_O_MSK USBDP_REG_MSK(0, 7)
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#define USBDP_TRSV_REG07DF_LN2_MON_RX_SSLMS_C3_O_CLR USBDP_REG_CLR(0, 7)
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#define USBDP_TRSV_REG07DF_LN2_MON_RX_SSLMS_C3_O_SET(_x) USBDP_REG_SET(_x, 0, 7)
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#define USBDP_TRSV_REG07DF_LN2_MON_RX_SSLMS_C3_O_GET(_R) USBDP_REG_GET(_R, 0, 7)
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#define EXYNOS_USBDP_TRSV_REG07E0 (0x1F80)
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#define USBDP_TRSV_REG07E0_LN2_MON_RX_SSLMS_C4_E_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07E0_LN2_MON_RX_SSLMS_C4_E_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07E0_LN2_MON_RX_SSLMS_C4_E_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07E0_LN2_MON_RX_SSLMS_C4_E_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07E1 (0x1F84)
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#define USBDP_TRSV_REG07E1_LN2_MON_RX_SSLMS_C4_O_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07E1_LN2_MON_RX_SSLMS_C4_O_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07E1_LN2_MON_RX_SSLMS_C4_O_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07E1_LN2_MON_RX_SSLMS_C4_O_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07E2 (0x1F88)
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#define USBDP_TRSV_REG07E2_LN2_MON_RX_SSLMS_C5_E_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07E2_LN2_MON_RX_SSLMS_C5_E_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07E2_LN2_MON_RX_SSLMS_C5_E_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07E2_LN2_MON_RX_SSLMS_C5_E_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07E3 (0x1F8C)
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#define USBDP_TRSV_REG07E3_LN2_MON_RX_SSLMS_C5_O_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07E3_LN2_MON_RX_SSLMS_C5_O_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07E3_LN2_MON_RX_SSLMS_C5_O_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07E3_LN2_MON_RX_SSLMS_C5_O_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07E4 (0x1F90)
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#define USBDP_TRSV_REG07E4_LN2_MON_RX_SSLMS_HF_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG07E4_LN2_MON_RX_SSLMS_HF_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG07E4_LN2_MON_RX_SSLMS_HF_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG07E4_LN2_MON_RX_SSLMS_HF_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG07E5 (0x1F94)
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#define USBDP_TRSV_REG07E5_LN2_MON_RX_SSLMS_MF_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG07E5_LN2_MON_RX_SSLMS_MF_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG07E5_LN2_MON_RX_SSLMS_MF_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG07E5_LN2_MON_RX_SSLMS_MF_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG07E6 (0x1F98)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_VGA_MSK USBDP_REG_MSK(2, 5)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_VGA_CLR USBDP_REG_CLR(2, 5)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_VGA_SET(_x) USBDP_REG_SET(_x, 2, 5)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_VGA_GET(_R) USBDP_REG_GET(_R, 2, 5)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_ADAP_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_ADAP_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_ADAP_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_SSLMS_ADAP_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_EFOM_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_EFOM_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_EFOM_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07E6_LN2_MON_RX_EFOM_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07E7 (0x1F9C)
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#define USBDP_TRSV_REG07E7_LN2_MON_RX_EFOM_ERR_CNT_OLD__13_8_MSK USBDP_REG_MSK(0, 6)
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#define USBDP_TRSV_REG07E7_LN2_MON_RX_EFOM_ERR_CNT_OLD__13_8_CLR USBDP_REG_CLR(0, 6)
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#define USBDP_TRSV_REG07E7_LN2_MON_RX_EFOM_ERR_CNT_OLD__13_8_SET(_x) USBDP_REG_SET(_x, 0, 6)
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#define USBDP_TRSV_REG07E7_LN2_MON_RX_EFOM_ERR_CNT_OLD__13_8_GET(_R) USBDP_REG_GET(_R, 0, 6)
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#define EXYNOS_USBDP_TRSV_REG07E8 (0x1FA0)
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#define USBDP_TRSV_REG07E8_LN2_MON_RX_EFOM_ERR_CNT_OLD__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07E8_LN2_MON_RX_EFOM_ERR_CNT_OLD__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07E8_LN2_MON_RX_EFOM_ERR_CNT_OLD__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07E8_LN2_MON_RX_EFOM_ERR_CNT_OLD__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07E9 (0x1FA4)
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#define USBDP_TRSV_REG07E9_LN2_MON_RX_EFOM_FEEDBACK__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07E9_LN2_MON_RX_EFOM_FEEDBACK__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07E9_LN2_MON_RX_EFOM_FEEDBACK__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07E9_LN2_MON_RX_EFOM_FEEDBACK__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07EA (0x1FA8)
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#define USBDP_TRSV_REG07EA_LN2_MON_RX_EFOM_FEEDBACK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07EA_LN2_MON_RX_EFOM_FEEDBACK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07EA_LN2_MON_RX_EFOM_FEEDBACK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07EA_LN2_MON_RX_EFOM_FEEDBACK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07EB (0x1FAC)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07EB_LN2_MON_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07EC (0x1FB0)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_DONE_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_DONE_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_RX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_LANE_DTB_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_LANE_DTB_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_LANE_DTB_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_LANE_DTB_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07EC_LN2_MON_TX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07ED (0x1FB4)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_SEL_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_SEL_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_SEL_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_SEL_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG07ED_LN2_MON_RX_CLK_GMUX_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG07EE (0x1FB8)
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#define USBDP_TRSV_REG07EE_LN2_MON_TX_CLK_GMUX_COUNTER__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07EE_LN2_MON_TX_CLK_GMUX_COUNTER__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07EE_LN2_MON_TX_CLK_GMUX_COUNTER__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07EE_LN2_MON_TX_CLK_GMUX_COUNTER__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07EF (0x1FBC)
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#define USBDP_TRSV_REG07EF_LN2_MON_TX_CLK_GMUX_COUNTER__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07EF_LN2_MON_TX_CLK_GMUX_COUNTER__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07EF_LN2_MON_TX_CLK_GMUX_COUNTER__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07EF_LN2_MON_TX_CLK_GMUX_COUNTER__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F0 (0x1FC0)
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#define USBDP_TRSV_REG07F0_LN2_MON_RX_CLK_GMUX_COUNTER__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F0_LN2_MON_RX_CLK_GMUX_COUNTER__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F0_LN2_MON_RX_CLK_GMUX_COUNTER__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F0_LN2_MON_RX_CLK_GMUX_COUNTER__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F1 (0x1FC4)
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#define USBDP_TRSV_REG07F1_LN2_MON_RX_CLK_GMUX_COUNTER__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F1_LN2_MON_RX_CLK_GMUX_COUNTER__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F1_LN2_MON_RX_CLK_GMUX_COUNTER__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F1_LN2_MON_RX_CLK_GMUX_COUNTER__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F2 (0x1FC8)
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#define USBDP_TRSV_REG07F2_LN2_MON_RX_CDR_VCO_CNT_AFC__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07F2_LN2_MON_RX_CDR_VCO_CNT_AFC__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07F2_LN2_MON_RX_CDR_VCO_CNT_AFC__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07F2_LN2_MON_RX_CDR_VCO_CNT_AFC__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07F3 (0x1FCC)
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#define USBDP_TRSV_REG07F3_LN2_MON_RX_CDR_VCO_CNT_AFC__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F3_LN2_MON_RX_CDR_VCO_CNT_AFC__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F3_LN2_MON_RX_CDR_VCO_CNT_AFC__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F3_LN2_MON_RX_CDR_VCO_CNT_AFC__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F4 (0x1FD0)
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#define USBDP_TRSV_REG07F4_LN2_MON_RX_CDR_VCO_CNT_FBB__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07F4_LN2_MON_RX_CDR_VCO_CNT_FBB__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07F4_LN2_MON_RX_CDR_VCO_CNT_FBB__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07F4_LN2_MON_RX_CDR_VCO_CNT_FBB__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07F5 (0x1FD4)
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#define USBDP_TRSV_REG07F5_LN2_MON_RX_CDR_VCO_CNT_FBB__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F5_LN2_MON_RX_CDR_VCO_CNT_FBB__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F5_LN2_MON_RX_CDR_VCO_CNT_FBB__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F5_LN2_MON_RX_CDR_VCO_CNT_FBB__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F6 (0x1FD8)
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#define USBDP_TRSV_REG07F6_LN2_MON_RX_CDR_VCO_CNT_FBB_P__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07F6_LN2_MON_RX_CDR_VCO_CNT_FBB_P__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07F6_LN2_MON_RX_CDR_VCO_CNT_FBB_P__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07F6_LN2_MON_RX_CDR_VCO_CNT_FBB_P__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07F7 (0x1FDC)
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#define USBDP_TRSV_REG07F7_LN2_MON_RX_CDR_VCO_CNT_FBB_P__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F7_LN2_MON_RX_CDR_VCO_CNT_FBB_P__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F7_LN2_MON_RX_CDR_VCO_CNT_FBB_P__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F7_LN2_MON_RX_CDR_VCO_CNT_FBB_P__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07F8 (0x1FE0)
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#define USBDP_TRSV_REG07F8_LN2_MON_RX_CDR_VCO_CNT_PLL__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07F8_LN2_MON_RX_CDR_VCO_CNT_PLL__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07F8_LN2_MON_RX_CDR_VCO_CNT_PLL__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07F8_LN2_MON_RX_CDR_VCO_CNT_PLL__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07F9 (0x1FE4)
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#define USBDP_TRSV_REG07F9_LN2_MON_RX_CDR_VCO_CNT_PLL__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07F9_LN2_MON_RX_CDR_VCO_CNT_PLL__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07F9_LN2_MON_RX_CDR_VCO_CNT_PLL__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07F9_LN2_MON_RX_CDR_VCO_CNT_PLL__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07FA (0x1FE8)
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#define USBDP_TRSV_REG07FA_LN2_MON_RX_CDR_VCO_CNT_CK__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07FA_LN2_MON_RX_CDR_VCO_CNT_CK__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07FA_LN2_MON_RX_CDR_VCO_CNT_CK__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07FA_LN2_MON_RX_CDR_VCO_CNT_CK__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07FB (0x1FEC)
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#define USBDP_TRSV_REG07FB_LN2_MON_RX_CDR_VCO_CNT_CK__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07FB_LN2_MON_RX_CDR_VCO_CNT_CK__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07FB_LN2_MON_RX_CDR_VCO_CNT_CK__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07FB_LN2_MON_RX_CDR_VCO_CNT_CK__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07FC (0x1FF0)
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#define USBDP_TRSV_REG07FC_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07FC_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07FC_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07FC_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07FD (0x1FF4)
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#define USBDP_TRSV_REG07FD_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07FD_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07FD_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07FD_LN2_MON_RX_CDR_VCO_CNT_DATA_LO_BW__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG07FE (0x1FF8)
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#define USBDP_TRSV_REG07FE_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG07FE_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG07FE_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG07FE_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__11_8_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG07FF (0x1FFC)
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#define USBDP_TRSV_REG07FF_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG07FF_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG07FF_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG07FF_LN2_MON_RX_CDR_VCO_CNT_DATA_HI_BW__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0800 (0x2000)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_BEACON_LFPS_OUT_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_BEACON_LFPS_OUT_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_BEACON_LFPS_OUT_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_BEACON_LFPS_OUT_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0800_OVRD_LN3_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_CM_KEEPER_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_CM_KEEPER_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_CM_KEEPER_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0800_LN3_TX_DRV_CM_KEEPER_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0801 (0x2004)
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#define USBDP_TRSV_REG0801_OVRD_LN3_TX_DRV_EI_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0801_OVRD_LN3_TX_DRV_EI_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0801_OVRD_LN3_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0801_OVRD_LN3_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0801_LN3_TX_DRV_EI_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0802 (0x2008)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0802_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0803 (0x200C)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0803_LN3_TX_DRV_EI_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_VREF_SEL_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_VREF_SEL_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_FB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_FB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_FB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_FB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0803_LN3_ANA_TX_DRV_EIEN_ENTRY_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0804 (0x2010)
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#define USBDP_TRSV_REG0804_OVRD_LN3_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0804_OVRD_LN3_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0804_OVRD_LN3_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0804_OVRD_LN3_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0804_LN3_TX_DRV_LVL_CTRL_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG0804_LN3_TX_DRV_LVL_CTRL_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG0804_LN3_TX_DRV_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG0804_LN3_TX_DRV_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG0805 (0x2014)
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#define USBDP_TRSV_REG0805_OVRD_LN3_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0805_OVRD_LN3_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0805_OVRD_LN3_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0805_OVRD_LN3_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0805_LN3_TX_DRV_POST_LVL_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0805_LN3_TX_DRV_POST_LVL_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0805_LN3_TX_DRV_POST_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0805_LN3_TX_DRV_POST_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0806 (0x2018)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_PRE_LVL_CTRL_MSK USBDP_REG_MSK(2, 4)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_PRE_LVL_CTRL_CLR USBDP_REG_CLR(2, 4)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_PRE_LVL_CTRL_SET(_x) USBDP_REG_SET(_x, 2, 4)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_PRE_LVL_CTRL_GET(_R) USBDP_REG_GET(_R, 2, 4)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0806_OVRD_LN3_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_IDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_IDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_IDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0806_LN3_TX_DRV_IDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0807 (0x201C)
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#define USBDP_TRSV_REG0807_OVRD_LN3_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0807_OVRD_LN3_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0807_OVRD_LN3_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0807_OVRD_LN3_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0807_LN3_TX_DRV_IDRV_IUP_CTRL_MSK USBDP_REG_MSK(4, 3)
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#define USBDP_TRSV_REG0807_LN3_TX_DRV_IDRV_IUP_CTRL_CLR USBDP_REG_CLR(4, 3)
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#define USBDP_TRSV_REG0807_LN3_TX_DRV_IDRV_IUP_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 3)
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#define USBDP_TRSV_REG0807_LN3_TX_DRV_IDRV_IUP_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 3)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_SEL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_BEACON_IDRV_DELAY_CTRL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_ACCDRV_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_ACCDRV_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_ACCDRV_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0807_LN3_ANA_TX_DRV_ACCDRV_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0808 (0x2020)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_POL_SEL_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_POL_SEL_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_POL_SEL_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_POL_SEL_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_CTRL_MSK USBDP_REG_MSK(3, 3)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_CTRL_CLR USBDP_REG_CLR(3, 3)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 3)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_ACCDRV_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 3)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_HSCLK_MON_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_HSCLK_MON_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_HSCLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_HSCLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0808_LN3_ANA_TX_DRV_PLL_REF_MON_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0809 (0x2024)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SSP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SSP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0809_LN3_TX_JEQ_CAP_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080A (0x2028)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_RBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_RBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_HBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_HBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080A_LN3_TX_JEQ_CAP_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080B (0x202C)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR2_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR2_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR3_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR3_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080B_LN3_TX_JEQ_CAP_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080C (0x2030)
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#define USBDP_TRSV_REG080C_LN3_ANA_TX_JEQ_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG080C_LN3_ANA_TX_JEQ_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG080C_LN3_ANA_TX_JEQ_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG080C_LN3_ANA_TX_JEQ_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG080C_LN3_TX_JEQ_EVEN_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080C_LN3_TX_JEQ_EVEN_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080C_LN3_TX_JEQ_EVEN_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080C_LN3_TX_JEQ_EVEN_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080D (0x2034)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080D_LN3_TX_JEQ_EVEN_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080E (0x2038)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080E_LN3_TX_JEQ_EVEN_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG080F (0x203C)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_EVEN_CTRL_HBR3_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_EVEN_CTRL_HBR3_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_EVEN_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_EVEN_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_ODD_CTRL_SP_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_ODD_CTRL_SP_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_ODD_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG080F_LN3_TX_JEQ_ODD_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0810 (0x2040)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_SSP_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_SSP_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_RBR_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_RBR_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0810_LN3_TX_JEQ_ODD_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0811 (0x2044)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR2_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR2_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0811_LN3_TX_JEQ_ODD_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG0812 (0x2048)
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#define USBDP_TRSV_REG0812_LN3_TX_JEQ_ODD_CTRL_HBR3_MSK USBDP_REG_MSK(3, 4)
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#define USBDP_TRSV_REG0812_LN3_TX_JEQ_ODD_CTRL_HBR3_CLR USBDP_REG_CLR(3, 4)
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#define USBDP_TRSV_REG0812_LN3_TX_JEQ_ODD_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 4)
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#define USBDP_TRSV_REG0812_LN3_TX_JEQ_ODD_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 4)
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#define USBDP_TRSV_REG0812_OVRD_LN3_TX_RCAL_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0812_OVRD_LN3_TX_RCAL_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0812_OVRD_LN3_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0812_OVRD_LN3_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0812_LN3_TX_RCAL_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0812_LN3_TX_RCAL_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0812_LN3_TX_RCAL_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0812_LN3_TX_RCAL_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0812_LN3_ANA_TX_RTERM_42P5_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0812_LN3_ANA_TX_RTERM_42P5_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0812_LN3_ANA_TX_RTERM_42P5_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0812_LN3_ANA_TX_RTERM_42P5_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0813 (0x204C)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_COMP_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_COMP_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_COMP_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_COMP_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0813_OVRD_LN3_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_RXD_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_COMP_I_CTRL_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_COMP_I_CTRL_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_COMP_I_CTRL_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_COMP_I_CTRL_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_VREF_SEL_MSK USBDP_REG_MSK(1, 2)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_VREF_SEL_CLR USBDP_REG_CLR(1, 2)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_VREF_SEL_SET(_x) USBDP_REG_SET(_x, 1, 2)
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#define USBDP_TRSV_REG0813_LN3_ANA_TX_RXD_VREF_SEL_GET(_R) USBDP_REG_GET(_R, 1, 2)
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#define USBDP_TRSV_REG0813_LN3_TX_SER_40BIT_EN_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_SER_40BIT_EN_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_SER_40BIT_EN_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0813_LN3_TX_SER_40BIT_EN_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0814 (0x2050)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_40BIT_EN_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0814_OVRD_LN3_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0814_OVRD_LN3_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0814_OVRD_LN3_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0814_OVRD_LN3_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_DATA_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_DATA_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_DATA_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_DATA_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_RATE_SEL_SP_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_RATE_SEL_SP_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_RATE_SEL_SP_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0814_LN3_TX_SER_RATE_SEL_SP_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0815 (0x2054)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_SSP_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_SSP_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_RBR_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_RBR_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR2_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR2_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR3_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR3_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_RATE_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0815_OVRD_LN3_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0815_OVRD_LN3_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0815_OVRD_LN3_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0815_OVRD_LN3_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_CLK_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_CLK_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_CLK_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0815_LN3_TX_SER_CLK_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0815_LN3_ANA_TX_CDR_CLK_MON_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0815_LN3_ANA_TX_CDR_CLK_MON_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0815_LN3_ANA_TX_CDR_CLK_MON_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0815_LN3_ANA_TX_CDR_CLK_MON_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0816 (0x2058)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_SER_TXCLK_INV_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_SER_TXCLK_INV_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_SER_TXCLK_INV_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_SER_TXCLK_INV_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_TO_DIG_BYTE_CLK_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_TO_DIG_BYTE_CLK_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_TO_DIG_BYTE_CLK_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0816_LN3_ANA_TX_TO_DIG_BYTE_CLK_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0816_OVRD_LN3_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0816_OVRD_LN3_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0816_OVRD_LN3_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0816_OVRD_LN3_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_RSTN_SEL_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_RSTN_SEL_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_RSTN_SEL_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_RSTN_SEL_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SP_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SP_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SP_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SP_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SSP_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SSP_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_RBR_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_RBR_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_HBR_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_HBR_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0816_LN3_TX_LANE_LC_RO_CLK_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0817 (0x205C)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR2_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR2_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR3_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR3_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_LC_RO_CLK_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_DCC_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_DCC_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_DCC_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_LANE_DCC_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_SEL_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_SEL_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_SEL_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0817_LN3_ANA_TX_LANE_DIV2_SEL_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_SER_VREG_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_SER_VREG_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0817_OVRD_LN3_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_SER_VREG_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_SER_VREG_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_SER_VREG_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0817_LN3_TX_SER_VREG_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0818 (0x2060)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_BYPASS_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_BYPASS_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_BYPASS_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_BYPASS_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0818_OVRD_LN3_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0818_OVRD_LN3_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0818_OVRD_LN3_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0818_OVRD_LN3_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0818_LN3_TX_SER_VREG_LPF_BYPASS_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0818_LN3_TX_SER_VREG_LPF_BYPASS_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0818_LN3_TX_SER_VREG_LPF_BYPASS_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0818_LN3_TX_SER_VREG_LPF_BYPASS_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_LADDER_SEL_MSK USBDP_REG_MSK(1, 3)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_LADDER_SEL_CLR USBDP_REG_CLR(1, 3)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_LADDER_SEL_SET(_x) USBDP_REG_SET(_x, 1, 3)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_LADDER_SEL_GET(_R) USBDP_REG_GET(_R, 1, 3)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_REF_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_REF_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_REF_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0818_LN3_ANA_TX_SER_VREG_REF_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0819 (0x2064)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_I_CTRL_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_I_CTRL_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_I_CTRL_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_I_CTRL_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_GAIN_CTRL_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_GAIN_CTRL_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_GAIN_CTRL_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG0819_LN3_ANA_TX_SER_VREG_GAIN_CTRL_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG081A (0x2068)
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#define USBDP_TRSV_REG081A_LN3_TX_DCC_IN_BUF_STR_SP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG081A_LN3_TX_DCC_IN_BUF_STR_SP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG081A_LN3_TX_DCC_IN_BUF_STR_SP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG081A_LN3_TX_DCC_IN_BUF_STR_SP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG081B (0x206C)
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#define USBDP_TRSV_REG081B_LN3_TX_DCC_IN_BUF_STR_SSP_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG081B_LN3_TX_DCC_IN_BUF_STR_SSP_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG081B_LN3_TX_DCC_IN_BUF_STR_SSP_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG081B_LN3_TX_DCC_IN_BUF_STR_SSP_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG081C (0x2070)
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#define USBDP_TRSV_REG081C_LN3_TX_DCC_IN_BUF_STR_RBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG081C_LN3_TX_DCC_IN_BUF_STR_RBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG081C_LN3_TX_DCC_IN_BUF_STR_RBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG081C_LN3_TX_DCC_IN_BUF_STR_RBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG081D (0x2074)
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#define USBDP_TRSV_REG081D_LN3_TX_DCC_IN_BUF_STR_HBR_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG081D_LN3_TX_DCC_IN_BUF_STR_HBR_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG081D_LN3_TX_DCC_IN_BUF_STR_HBR_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG081D_LN3_TX_DCC_IN_BUF_STR_HBR_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG081E (0x2078)
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#define USBDP_TRSV_REG081E_LN3_TX_DCC_IN_BUF_STR_HBR2_MSK USBDP_REG_MSK(0, 5)
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#define USBDP_TRSV_REG081E_LN3_TX_DCC_IN_BUF_STR_HBR2_CLR USBDP_REG_CLR(0, 5)
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#define USBDP_TRSV_REG081E_LN3_TX_DCC_IN_BUF_STR_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 5)
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#define USBDP_TRSV_REG081E_LN3_TX_DCC_IN_BUF_STR_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 5)
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#define EXYNOS_USBDP_TRSV_REG081F (0x207C)
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#define USBDP_TRSV_REG081F_LN3_TX_DCC_IN_BUF_STR_HBR3_MSK USBDP_REG_MSK(1, 5)
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#define USBDP_TRSV_REG081F_LN3_TX_DCC_IN_BUF_STR_HBR3_CLR USBDP_REG_CLR(1, 5)
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#define USBDP_TRSV_REG081F_LN3_TX_DCC_IN_BUF_STR_HBR3_SET(_x) USBDP_REG_SET(_x, 1, 5)
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#define USBDP_TRSV_REG081F_LN3_TX_DCC_IN_BUF_STR_HBR3_GET(_R) USBDP_REG_GET(_R, 1, 5)
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#define USBDP_TRSV_REG081F_LN3_ANA_TX_TO_RX_CLK_EN_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG081F_LN3_ANA_TX_TO_RX_CLK_EN_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG081F_LN3_ANA_TX_TO_RX_CLK_EN_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG081F_LN3_ANA_TX_TO_RX_CLK_EN_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0820 (0x2080)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_SEL_MSK USBDP_REG_MSK(3, 5)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_SEL_CLR USBDP_REG_CLR(3, 5)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_SEL_SET(_x) USBDP_REG_SET(_x, 3, 5)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_SEL_GET(_R) USBDP_REG_GET(_R, 3, 5)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_ATB_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_SLB_EN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_SLB_EN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_SLB_EN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_SLB_EN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_LLB_EN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_LLB_EN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_LLB_EN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0820_LN3_ANA_TX_LLB_EN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0821 (0x2084)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_SRLB_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_SRLB_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_SRLB_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_SRLB_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_EN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_EN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_EN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_EN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_EN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_EN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0821_OVRD_LN3_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_AFC_CNT_EN_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_AFC_CNT_EN_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_AFC_CNT_EN_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0821_LN3_TX_LFPS_AFC_CNT_EN_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_AFC_FORCE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_AFC_FORCE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_AFC_FORCE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_AFC_FORCE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_CLK_SEL_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_CLK_SEL_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_CLK_SEL_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0821_LN3_ANA_TX_LFPS_CLK_SEL_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0822 (0x2088)
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#define USBDP_TRSV_REG0822_OVRD_LN3_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(7, 1)
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#define USBDP_TRSV_REG0822_OVRD_LN3_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(7, 1)
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#define USBDP_TRSV_REG0822_OVRD_LN3_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 7, 1)
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#define USBDP_TRSV_REG0822_OVRD_LN3_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 7, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_LFPS_CLK_INT_EN_MSK USBDP_REG_MSK(6, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_LFPS_CLK_INT_EN_CLR USBDP_REG_CLR(6, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_LFPS_CLK_INT_EN_SET(_x) USBDP_REG_SET(_x, 6, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_LFPS_CLK_INT_EN_GET(_R) USBDP_REG_GET(_R, 6, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SP_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_RBR_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR2_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0822_LN3_TX_DRV_LFPS_EN_EXIT_DELAY_CTRL_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0823 (0x208C)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SP_MSK USBDP_REG_MSK(6, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SP_CLR USBDP_REG_CLR(6, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SP_SET(_x) USBDP_REG_SET(_x, 6, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SP_GET(_R) USBDP_REG_GET(_R, 6, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SSP_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SSP_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SSP_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_SSP_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_RBR_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_RBR_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_RBR_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_RBR_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG0823_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG0824 (0x2090)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_MSK USBDP_REG_MSK(4, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_CLR USBDP_REG_CLR(4, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_SET(_x) USBDP_REG_SET(_x, 4, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR2_GET(_R) USBDP_REG_GET(_R, 4, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG0824_LN3_TX_DRV_LFPS_EN_DELAY_SEL_HBR3_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG0824_OVRD_LN3_TX_INIT_RSTN_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG0824_OVRD_LN3_TX_INIT_RSTN_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG0824_OVRD_LN3_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG0824_OVRD_LN3_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG0824_LN3_TX_INIT_RSTN_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0824_LN3_TX_INIT_RSTN_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0824_LN3_TX_INIT_RSTN_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0824_LN3_TX_INIT_RSTN_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0825 (0x2094)
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#define USBDP_TRSV_REG0825_LN3_ANA_TX_RESERVED_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0825_LN3_ANA_TX_RESERVED_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0825_LN3_ANA_TX_RESERVED_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0825_LN3_ANA_TX_RESERVED_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0826 (0x2098)
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#define USBDP_TRSV_REG0826_LN3_TX_SR_RESERVED_SP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0826_LN3_TX_SR_RESERVED_SP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0826_LN3_TX_SR_RESERVED_SP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0826_LN3_TX_SR_RESERVED_SP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0827 (0x209C)
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#define USBDP_TRSV_REG0827_LN3_TX_SR_RESERVED_SSP_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0827_LN3_TX_SR_RESERVED_SSP_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0827_LN3_TX_SR_RESERVED_SSP_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0827_LN3_TX_SR_RESERVED_SSP_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0828 (0x20A0)
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#define USBDP_TRSV_REG0828_LN3_TX_SR_RESERVED_RBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0828_LN3_TX_SR_RESERVED_RBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0828_LN3_TX_SR_RESERVED_RBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0828_LN3_TX_SR_RESERVED_RBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0829 (0x20A4)
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#define USBDP_TRSV_REG0829_LN3_TX_SR_RESERVED_HBR_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0829_LN3_TX_SR_RESERVED_HBR_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0829_LN3_TX_SR_RESERVED_HBR_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0829_LN3_TX_SR_RESERVED_HBR_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG082A (0x20A8)
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#define USBDP_TRSV_REG082A_LN3_TX_SR_RESERVED_HBR2_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG082A_LN3_TX_SR_RESERVED_HBR2_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG082A_LN3_TX_SR_RESERVED_HBR2_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG082A_LN3_TX_SR_RESERVED_HBR2_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG082B (0x20AC)
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#define USBDP_TRSV_REG082B_LN3_TX_SR_RESERVED_HBR3_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG082B_LN3_TX_SR_RESERVED_HBR3_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG082B_LN3_TX_SR_RESERVED_HBR3_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG082B_LN3_TX_SR_RESERVED_HBR3_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG082C (0x20B0)
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#define USBDP_TRSV_REG082C_LN3_OVRD_TX_RCAL_RSTN_MSK USBDP_REG_MSK(5, 1)
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#define USBDP_TRSV_REG082C_LN3_OVRD_TX_RCAL_RSTN_CLR USBDP_REG_CLR(5, 1)
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#define USBDP_TRSV_REG082C_LN3_OVRD_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 5, 1)
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#define USBDP_TRSV_REG082C_LN3_OVRD_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 5, 1)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_RSTN_MSK USBDP_REG_MSK(4, 1)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_RSTN_CLR USBDP_REG_CLR(4, 1)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_RSTN_SET(_x) USBDP_REG_SET(_x, 4, 1)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_RSTN_GET(_R) USBDP_REG_GET(_R, 4, 1)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_UP_OPT_CODE_MSK USBDP_REG_MSK(2, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_UP_OPT_CODE_CLR USBDP_REG_CLR(2, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_UP_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 2, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_UP_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 2, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_DN_OPT_CODE_MSK USBDP_REG_MSK(0, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_DN_OPT_CODE_CLR USBDP_REG_CLR(0, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_DN_OPT_CODE_SET(_x) USBDP_REG_SET(_x, 0, 2)
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#define USBDP_TRSV_REG082C_LN3_TX_RCAL_DN_OPT_CODE_GET(_R) USBDP_REG_GET(_R, 0, 2)
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#define EXYNOS_USBDP_TRSV_REG082D (0x20B4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_UP_CODE_MSK USBDP_REG_MSK(4, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_UP_CODE_CLR USBDP_REG_CLR(4, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_UP_CODE_SET(_x) USBDP_REG_SET(_x, 4, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_UP_CODE_GET(_R) USBDP_REG_GET(_R, 4, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_DN_CODE_MSK USBDP_REG_MSK(0, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_DN_CODE_CLR USBDP_REG_CLR(0, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_DN_CODE_SET(_x) USBDP_REG_SET(_x, 0, 4)
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#define USBDP_TRSV_REG082D_LN3_TX_RCAL_DN_CODE_GET(_R) USBDP_REG_GET(_R, 0, 4)
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#define EXYNOS_USBDP_TRSV_REG082E (0x20B8)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(3, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(3, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 3, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 3, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_COMP_OUT_MSK USBDP_REG_MSK(2, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_COMP_OUT_CLR USBDP_REG_CLR(2, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_COMP_OUT_SET(_x) USBDP_REG_SET(_x, 2, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_COMP_OUT_GET(_R) USBDP_REG_GET(_R, 2, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_DONE_MSK USBDP_REG_MSK(1, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_DONE_CLR USBDP_REG_CLR(1, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 1, 1)
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#define USBDP_TRSV_REG082E_LN3_OVRD_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 1, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG082E_LN3_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0900 (0x2400)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_TUNE_CODE_MSK USBDP_REG_MSK(1, 4)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_TUNE_CODE_CLR USBDP_REG_CLR(1, 4)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_TUNE_CODE_SET(_x) USBDP_REG_SET(_x, 1, 4)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_TUNE_CODE_GET(_R) USBDP_REG_GET(_R, 1, 4)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_DONE_MSK USBDP_REG_MSK(0, 1)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_DONE_CLR USBDP_REG_CLR(0, 1)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_DONE_SET(_x) USBDP_REG_SET(_x, 0, 1)
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#define USBDP_TRSV_REG0900_LN3_MON_TX_RCAL_DONE_GET(_R) USBDP_REG_GET(_R, 0, 1)
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#define EXYNOS_USBDP_TRSV_REG0901 (0x2404)
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#define USBDP_TRSV_REG0901_LN3_MON_RXNONDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0901_LN3_MON_RXNONDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0901_LN3_MON_RXNONDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0901_LN3_MON_RXNONDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0902 (0x2408)
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#define USBDP_TRSV_REG0902_LN3_MON_RXNONDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0902_LN3_MON_RXNONDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0902_LN3_MON_RXNONDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0902_LN3_MON_RXNONDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0903 (0x240C)
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#define USBDP_TRSV_REG0903_LN3_MON_RXNONDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0903_LN3_MON_RXNONDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0903_LN3_MON_RXNONDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0903_LN3_MON_RXNONDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0904 (0x2410)
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#define USBDP_TRSV_REG0904_LN3_MON_RXNONDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0904_LN3_MON_RXNONDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0904_LN3_MON_RXNONDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0904_LN3_MON_RXNONDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0905 (0x2414)
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#define USBDP_TRSV_REG0905_LN3_MON_RXNONDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0905_LN3_MON_RXNONDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0905_LN3_MON_RXNONDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0905_LN3_MON_RXNONDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0906 (0x2418)
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#define USBDP_TRSV_REG0906_LN3_MON_TRXDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0906_LN3_MON_TRXDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0906_LN3_MON_TRXDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0906_LN3_MON_TRXDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0907 (0x241C)
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#define USBDP_TRSV_REG0907_LN3_MON_TRXDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0907_LN3_MON_TRXDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0907_LN3_MON_TRXDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0907_LN3_MON_TRXDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0908 (0x2420)
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#define USBDP_TRSV_REG0908_LN3_MON_TRXDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0908_LN3_MON_TRXDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0908_LN3_MON_TRXDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0908_LN3_MON_TRXDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0909 (0x2424)
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#define USBDP_TRSV_REG0909_LN3_MON_TRXDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0909_LN3_MON_TRXDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0909_LN3_MON_TRXDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0909_LN3_MON_TRXDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090A (0x2428)
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#define USBDP_TRSV_REG090A_LN3_MON_TRXDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090A_LN3_MON_TRXDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090A_LN3_MON_TRXDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090A_LN3_MON_TRXDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090B (0x242C)
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#define USBDP_TRSV_REG090B_LN3_MON_TXDATA__39_32_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090B_LN3_MON_TXDATA__39_32_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090B_LN3_MON_TXDATA__39_32_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090B_LN3_MON_TXDATA__39_32_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090C (0x2430)
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#define USBDP_TRSV_REG090C_LN3_MON_TXDATA__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090C_LN3_MON_TXDATA__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090C_LN3_MON_TXDATA__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090C_LN3_MON_TXDATA__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090D (0x2434)
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#define USBDP_TRSV_REG090D_LN3_MON_TXDATA__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090D_LN3_MON_TXDATA__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090D_LN3_MON_TXDATA__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090D_LN3_MON_TXDATA__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090E (0x2438)
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#define USBDP_TRSV_REG090E_LN3_MON_TXDATA__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090E_LN3_MON_TXDATA__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090E_LN3_MON_TXDATA__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090E_LN3_MON_TXDATA__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG090F (0x243C)
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#define USBDP_TRSV_REG090F_LN3_MON_TXDATA__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG090F_LN3_MON_TXDATA__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG090F_LN3_MON_TXDATA__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG090F_LN3_MON_TXDATA__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0910 (0x2440)
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#define USBDP_TRSV_REG0910_LN3_MON_PCS_PORT_LOG_T00__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0910_LN3_MON_PCS_PORT_LOG_T00__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0910_LN3_MON_PCS_PORT_LOG_T00__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0910_LN3_MON_PCS_PORT_LOG_T00__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0911 (0x2444)
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#define USBDP_TRSV_REG0911_LN3_MON_PCS_PORT_LOG_T00__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0911_LN3_MON_PCS_PORT_LOG_T00__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0911_LN3_MON_PCS_PORT_LOG_T00__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0911_LN3_MON_PCS_PORT_LOG_T00__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0912 (0x2448)
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#define USBDP_TRSV_REG0912_LN3_MON_PCS_PORT_LOG_T00__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0912_LN3_MON_PCS_PORT_LOG_T00__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0912_LN3_MON_PCS_PORT_LOG_T00__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0912_LN3_MON_PCS_PORT_LOG_T00__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0913 (0x244C)
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#define USBDP_TRSV_REG0913_LN3_MON_PCS_PORT_LOG_T00__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0913_LN3_MON_PCS_PORT_LOG_T00__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0913_LN3_MON_PCS_PORT_LOG_T00__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0913_LN3_MON_PCS_PORT_LOG_T00__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0914 (0x2450)
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#define USBDP_TRSV_REG0914_LN3_MON_PCS_PORT_LOG_T01__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0914_LN3_MON_PCS_PORT_LOG_T01__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0914_LN3_MON_PCS_PORT_LOG_T01__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0914_LN3_MON_PCS_PORT_LOG_T01__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0915 (0x2454)
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#define USBDP_TRSV_REG0915_LN3_MON_PCS_PORT_LOG_T01__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0915_LN3_MON_PCS_PORT_LOG_T01__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0915_LN3_MON_PCS_PORT_LOG_T01__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0915_LN3_MON_PCS_PORT_LOG_T01__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0916 (0x2458)
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#define USBDP_TRSV_REG0916_LN3_MON_PCS_PORT_LOG_T01__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0916_LN3_MON_PCS_PORT_LOG_T01__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0916_LN3_MON_PCS_PORT_LOG_T01__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0916_LN3_MON_PCS_PORT_LOG_T01__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0917 (0x245C)
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#define USBDP_TRSV_REG0917_LN3_MON_PCS_PORT_LOG_T01__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0917_LN3_MON_PCS_PORT_LOG_T01__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0917_LN3_MON_PCS_PORT_LOG_T01__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0917_LN3_MON_PCS_PORT_LOG_T01__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0918 (0x2460)
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#define USBDP_TRSV_REG0918_LN3_MON_PCS_PORT_LOG_T02__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0918_LN3_MON_PCS_PORT_LOG_T02__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0918_LN3_MON_PCS_PORT_LOG_T02__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0918_LN3_MON_PCS_PORT_LOG_T02__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0919 (0x2464)
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#define USBDP_TRSV_REG0919_LN3_MON_PCS_PORT_LOG_T02__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0919_LN3_MON_PCS_PORT_LOG_T02__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0919_LN3_MON_PCS_PORT_LOG_T02__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0919_LN3_MON_PCS_PORT_LOG_T02__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091A (0x2468)
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#define USBDP_TRSV_REG091A_LN3_MON_PCS_PORT_LOG_T02__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091A_LN3_MON_PCS_PORT_LOG_T02__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091A_LN3_MON_PCS_PORT_LOG_T02__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091A_LN3_MON_PCS_PORT_LOG_T02__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091B (0x246C)
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#define USBDP_TRSV_REG091B_LN3_MON_PCS_PORT_LOG_T02__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091B_LN3_MON_PCS_PORT_LOG_T02__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091B_LN3_MON_PCS_PORT_LOG_T02__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091B_LN3_MON_PCS_PORT_LOG_T02__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091C (0x2470)
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#define USBDP_TRSV_REG091C_LN3_MON_PCS_PORT_LOG_T03__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091C_LN3_MON_PCS_PORT_LOG_T03__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091C_LN3_MON_PCS_PORT_LOG_T03__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091C_LN3_MON_PCS_PORT_LOG_T03__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091D (0x2474)
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#define USBDP_TRSV_REG091D_LN3_MON_PCS_PORT_LOG_T03__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091D_LN3_MON_PCS_PORT_LOG_T03__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091D_LN3_MON_PCS_PORT_LOG_T03__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091D_LN3_MON_PCS_PORT_LOG_T03__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091E (0x2478)
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#define USBDP_TRSV_REG091E_LN3_MON_PCS_PORT_LOG_T03__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091E_LN3_MON_PCS_PORT_LOG_T03__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091E_LN3_MON_PCS_PORT_LOG_T03__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091E_LN3_MON_PCS_PORT_LOG_T03__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG091F (0x247C)
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#define USBDP_TRSV_REG091F_LN3_MON_PCS_PORT_LOG_T03__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG091F_LN3_MON_PCS_PORT_LOG_T03__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG091F_LN3_MON_PCS_PORT_LOG_T03__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG091F_LN3_MON_PCS_PORT_LOG_T03__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0920 (0x2480)
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#define USBDP_TRSV_REG0920_LN3_MON_PCS_PORT_LOG_T04__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0920_LN3_MON_PCS_PORT_LOG_T04__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0920_LN3_MON_PCS_PORT_LOG_T04__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0920_LN3_MON_PCS_PORT_LOG_T04__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0921 (0x2484)
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#define USBDP_TRSV_REG0921_LN3_MON_PCS_PORT_LOG_T04__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0921_LN3_MON_PCS_PORT_LOG_T04__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0921_LN3_MON_PCS_PORT_LOG_T04__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0921_LN3_MON_PCS_PORT_LOG_T04__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0922 (0x2488)
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#define USBDP_TRSV_REG0922_LN3_MON_PCS_PORT_LOG_T04__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0922_LN3_MON_PCS_PORT_LOG_T04__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0922_LN3_MON_PCS_PORT_LOG_T04__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0922_LN3_MON_PCS_PORT_LOG_T04__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0923 (0x248C)
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#define USBDP_TRSV_REG0923_LN3_MON_PCS_PORT_LOG_T04__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0923_LN3_MON_PCS_PORT_LOG_T04__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0923_LN3_MON_PCS_PORT_LOG_T04__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0923_LN3_MON_PCS_PORT_LOG_T04__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0924 (0x2490)
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#define USBDP_TRSV_REG0924_LN3_MON_PCS_PORT_LOG_T05__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0924_LN3_MON_PCS_PORT_LOG_T05__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0924_LN3_MON_PCS_PORT_LOG_T05__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0924_LN3_MON_PCS_PORT_LOG_T05__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0925 (0x2494)
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#define USBDP_TRSV_REG0925_LN3_MON_PCS_PORT_LOG_T05__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0925_LN3_MON_PCS_PORT_LOG_T05__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0925_LN3_MON_PCS_PORT_LOG_T05__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0925_LN3_MON_PCS_PORT_LOG_T05__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0926 (0x2498)
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#define USBDP_TRSV_REG0926_LN3_MON_PCS_PORT_LOG_T05__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0926_LN3_MON_PCS_PORT_LOG_T05__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0926_LN3_MON_PCS_PORT_LOG_T05__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0926_LN3_MON_PCS_PORT_LOG_T05__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0927 (0x249C)
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#define USBDP_TRSV_REG0927_LN3_MON_PCS_PORT_LOG_T05__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0927_LN3_MON_PCS_PORT_LOG_T05__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0927_LN3_MON_PCS_PORT_LOG_T05__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0927_LN3_MON_PCS_PORT_LOG_T05__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0928 (0x24A0)
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#define USBDP_TRSV_REG0928_LN3_MON_PCS_PORT_LOG_T06__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0928_LN3_MON_PCS_PORT_LOG_T06__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0928_LN3_MON_PCS_PORT_LOG_T06__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0928_LN3_MON_PCS_PORT_LOG_T06__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0929 (0x24A4)
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#define USBDP_TRSV_REG0929_LN3_MON_PCS_PORT_LOG_T06__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0929_LN3_MON_PCS_PORT_LOG_T06__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0929_LN3_MON_PCS_PORT_LOG_T06__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0929_LN3_MON_PCS_PORT_LOG_T06__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092A (0x24A8)
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#define USBDP_TRSV_REG092A_LN3_MON_PCS_PORT_LOG_T06__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092A_LN3_MON_PCS_PORT_LOG_T06__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092A_LN3_MON_PCS_PORT_LOG_T06__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092A_LN3_MON_PCS_PORT_LOG_T06__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092B (0x24AC)
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#define USBDP_TRSV_REG092B_LN3_MON_PCS_PORT_LOG_T06__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092B_LN3_MON_PCS_PORT_LOG_T06__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092B_LN3_MON_PCS_PORT_LOG_T06__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092B_LN3_MON_PCS_PORT_LOG_T06__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092C (0x24B0)
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#define USBDP_TRSV_REG092C_LN3_MON_PCS_PORT_LOG_T07__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092C_LN3_MON_PCS_PORT_LOG_T07__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092C_LN3_MON_PCS_PORT_LOG_T07__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092C_LN3_MON_PCS_PORT_LOG_T07__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092D (0x24B4)
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#define USBDP_TRSV_REG092D_LN3_MON_PCS_PORT_LOG_T07__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092D_LN3_MON_PCS_PORT_LOG_T07__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092D_LN3_MON_PCS_PORT_LOG_T07__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092D_LN3_MON_PCS_PORT_LOG_T07__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092E (0x24B8)
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#define USBDP_TRSV_REG092E_LN3_MON_PCS_PORT_LOG_T07__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092E_LN3_MON_PCS_PORT_LOG_T07__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092E_LN3_MON_PCS_PORT_LOG_T07__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092E_LN3_MON_PCS_PORT_LOG_T07__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG092F (0x24BC)
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#define USBDP_TRSV_REG092F_LN3_MON_PCS_PORT_LOG_T07__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG092F_LN3_MON_PCS_PORT_LOG_T07__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG092F_LN3_MON_PCS_PORT_LOG_T07__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG092F_LN3_MON_PCS_PORT_LOG_T07__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0930 (0x24C0)
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#define USBDP_TRSV_REG0930_LN3_MON_PCS_PORT_LOG_T08__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0930_LN3_MON_PCS_PORT_LOG_T08__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0930_LN3_MON_PCS_PORT_LOG_T08__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0930_LN3_MON_PCS_PORT_LOG_T08__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0931 (0x24C4)
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#define USBDP_TRSV_REG0931_LN3_MON_PCS_PORT_LOG_T08__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0931_LN3_MON_PCS_PORT_LOG_T08__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0931_LN3_MON_PCS_PORT_LOG_T08__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0931_LN3_MON_PCS_PORT_LOG_T08__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0932 (0x24C8)
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#define USBDP_TRSV_REG0932_LN3_MON_PCS_PORT_LOG_T08__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0932_LN3_MON_PCS_PORT_LOG_T08__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0932_LN3_MON_PCS_PORT_LOG_T08__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0932_LN3_MON_PCS_PORT_LOG_T08__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0933 (0x24CC)
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#define USBDP_TRSV_REG0933_LN3_MON_PCS_PORT_LOG_T08__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0933_LN3_MON_PCS_PORT_LOG_T08__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0933_LN3_MON_PCS_PORT_LOG_T08__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0933_LN3_MON_PCS_PORT_LOG_T08__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0934 (0x24D0)
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#define USBDP_TRSV_REG0934_LN3_MON_PCS_PORT_LOG_T09__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0934_LN3_MON_PCS_PORT_LOG_T09__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0934_LN3_MON_PCS_PORT_LOG_T09__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0934_LN3_MON_PCS_PORT_LOG_T09__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0935 (0x24D4)
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#define USBDP_TRSV_REG0935_LN3_MON_PCS_PORT_LOG_T09__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0935_LN3_MON_PCS_PORT_LOG_T09__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0935_LN3_MON_PCS_PORT_LOG_T09__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0935_LN3_MON_PCS_PORT_LOG_T09__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0936 (0x24D8)
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#define USBDP_TRSV_REG0936_LN3_MON_PCS_PORT_LOG_T09__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0936_LN3_MON_PCS_PORT_LOG_T09__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0936_LN3_MON_PCS_PORT_LOG_T09__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0936_LN3_MON_PCS_PORT_LOG_T09__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0937 (0x24DC)
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#define USBDP_TRSV_REG0937_LN3_MON_PCS_PORT_LOG_T09__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0937_LN3_MON_PCS_PORT_LOG_T09__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0937_LN3_MON_PCS_PORT_LOG_T09__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0937_LN3_MON_PCS_PORT_LOG_T09__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0938 (0x24E0)
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#define USBDP_TRSV_REG0938_LN3_MON_PCS_PORT_LOG_T10__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0938_LN3_MON_PCS_PORT_LOG_T10__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0938_LN3_MON_PCS_PORT_LOG_T10__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0938_LN3_MON_PCS_PORT_LOG_T10__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0939 (0x24E4)
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#define USBDP_TRSV_REG0939_LN3_MON_PCS_PORT_LOG_T10__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0939_LN3_MON_PCS_PORT_LOG_T10__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0939_LN3_MON_PCS_PORT_LOG_T10__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0939_LN3_MON_PCS_PORT_LOG_T10__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093A (0x24E8)
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#define USBDP_TRSV_REG093A_LN3_MON_PCS_PORT_LOG_T10__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093A_LN3_MON_PCS_PORT_LOG_T10__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093A_LN3_MON_PCS_PORT_LOG_T10__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093A_LN3_MON_PCS_PORT_LOG_T10__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093B (0x24EC)
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#define USBDP_TRSV_REG093B_LN3_MON_PCS_PORT_LOG_T10__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093B_LN3_MON_PCS_PORT_LOG_T10__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093B_LN3_MON_PCS_PORT_LOG_T10__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093B_LN3_MON_PCS_PORT_LOG_T10__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093C (0x24F0)
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#define USBDP_TRSV_REG093C_LN3_MON_PCS_PORT_LOG_T11__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093C_LN3_MON_PCS_PORT_LOG_T11__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093C_LN3_MON_PCS_PORT_LOG_T11__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093C_LN3_MON_PCS_PORT_LOG_T11__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093D (0x24F4)
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#define USBDP_TRSV_REG093D_LN3_MON_PCS_PORT_LOG_T11__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093D_LN3_MON_PCS_PORT_LOG_T11__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093D_LN3_MON_PCS_PORT_LOG_T11__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093D_LN3_MON_PCS_PORT_LOG_T11__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093E (0x24F8)
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#define USBDP_TRSV_REG093E_LN3_MON_PCS_PORT_LOG_T11__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093E_LN3_MON_PCS_PORT_LOG_T11__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093E_LN3_MON_PCS_PORT_LOG_T11__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093E_LN3_MON_PCS_PORT_LOG_T11__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG093F (0x24FC)
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#define USBDP_TRSV_REG093F_LN3_MON_PCS_PORT_LOG_T11__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG093F_LN3_MON_PCS_PORT_LOG_T11__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG093F_LN3_MON_PCS_PORT_LOG_T11__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG093F_LN3_MON_PCS_PORT_LOG_T11__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0940 (0x2500)
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#define USBDP_TRSV_REG0940_LN3_MON_PCS_PORT_LOG_T12__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0940_LN3_MON_PCS_PORT_LOG_T12__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0940_LN3_MON_PCS_PORT_LOG_T12__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0940_LN3_MON_PCS_PORT_LOG_T12__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0941 (0x2504)
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#define USBDP_TRSV_REG0941_LN3_MON_PCS_PORT_LOG_T12__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0941_LN3_MON_PCS_PORT_LOG_T12__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0941_LN3_MON_PCS_PORT_LOG_T12__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0941_LN3_MON_PCS_PORT_LOG_T12__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0942 (0x2508)
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#define USBDP_TRSV_REG0942_LN3_MON_PCS_PORT_LOG_T12__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0942_LN3_MON_PCS_PORT_LOG_T12__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0942_LN3_MON_PCS_PORT_LOG_T12__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0942_LN3_MON_PCS_PORT_LOG_T12__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0943 (0x250C)
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#define USBDP_TRSV_REG0943_LN3_MON_PCS_PORT_LOG_T12__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0943_LN3_MON_PCS_PORT_LOG_T12__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0943_LN3_MON_PCS_PORT_LOG_T12__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0943_LN3_MON_PCS_PORT_LOG_T12__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0944 (0x2510)
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#define USBDP_TRSV_REG0944_LN3_MON_PCS_PORT_LOG_T13__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0944_LN3_MON_PCS_PORT_LOG_T13__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0944_LN3_MON_PCS_PORT_LOG_T13__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0944_LN3_MON_PCS_PORT_LOG_T13__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0945 (0x2514)
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#define USBDP_TRSV_REG0945_LN3_MON_PCS_PORT_LOG_T13__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0945_LN3_MON_PCS_PORT_LOG_T13__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0945_LN3_MON_PCS_PORT_LOG_T13__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0945_LN3_MON_PCS_PORT_LOG_T13__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0946 (0x2518)
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#define USBDP_TRSV_REG0946_LN3_MON_PCS_PORT_LOG_T13__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0946_LN3_MON_PCS_PORT_LOG_T13__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0946_LN3_MON_PCS_PORT_LOG_T13__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0946_LN3_MON_PCS_PORT_LOG_T13__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0947 (0x251C)
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#define USBDP_TRSV_REG0947_LN3_MON_PCS_PORT_LOG_T13__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0947_LN3_MON_PCS_PORT_LOG_T13__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0947_LN3_MON_PCS_PORT_LOG_T13__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0947_LN3_MON_PCS_PORT_LOG_T13__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0948 (0x2520)
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#define USBDP_TRSV_REG0948_LN3_MON_PCS_PORT_LOG_T14__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0948_LN3_MON_PCS_PORT_LOG_T14__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0948_LN3_MON_PCS_PORT_LOG_T14__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0948_LN3_MON_PCS_PORT_LOG_T14__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0949 (0x2524)
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#define USBDP_TRSV_REG0949_LN3_MON_PCS_PORT_LOG_T14__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0949_LN3_MON_PCS_PORT_LOG_T14__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0949_LN3_MON_PCS_PORT_LOG_T14__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0949_LN3_MON_PCS_PORT_LOG_T14__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094A (0x2528)
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#define USBDP_TRSV_REG094A_LN3_MON_PCS_PORT_LOG_T14__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094A_LN3_MON_PCS_PORT_LOG_T14__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094A_LN3_MON_PCS_PORT_LOG_T14__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094A_LN3_MON_PCS_PORT_LOG_T14__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094B (0x252C)
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#define USBDP_TRSV_REG094B_LN3_MON_PCS_PORT_LOG_T14__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094B_LN3_MON_PCS_PORT_LOG_T14__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094B_LN3_MON_PCS_PORT_LOG_T14__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094B_LN3_MON_PCS_PORT_LOG_T14__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094C (0x2530)
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#define USBDP_TRSV_REG094C_LN3_MON_PCS_PORT_LOG_T15__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094C_LN3_MON_PCS_PORT_LOG_T15__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094C_LN3_MON_PCS_PORT_LOG_T15__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094C_LN3_MON_PCS_PORT_LOG_T15__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094D (0x2534)
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#define USBDP_TRSV_REG094D_LN3_MON_PCS_PORT_LOG_T15__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094D_LN3_MON_PCS_PORT_LOG_T15__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094D_LN3_MON_PCS_PORT_LOG_T15__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094D_LN3_MON_PCS_PORT_LOG_T15__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094E (0x2538)
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#define USBDP_TRSV_REG094E_LN3_MON_PCS_PORT_LOG_T15__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094E_LN3_MON_PCS_PORT_LOG_T15__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094E_LN3_MON_PCS_PORT_LOG_T15__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094E_LN3_MON_PCS_PORT_LOG_T15__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG094F (0x253C)
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#define USBDP_TRSV_REG094F_LN3_MON_PCS_PORT_LOG_T15__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG094F_LN3_MON_PCS_PORT_LOG_T15__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG094F_LN3_MON_PCS_PORT_LOG_T15__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG094F_LN3_MON_PCS_PORT_LOG_T15__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0950 (0x2540)
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#define USBDP_TRSV_REG0950_LN3_MON_PCS_PORT_LOG_T16__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0950_LN3_MON_PCS_PORT_LOG_T16__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0950_LN3_MON_PCS_PORT_LOG_T16__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0950_LN3_MON_PCS_PORT_LOG_T16__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0951 (0x2544)
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#define USBDP_TRSV_REG0951_LN3_MON_PCS_PORT_LOG_T16__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0951_LN3_MON_PCS_PORT_LOG_T16__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0951_LN3_MON_PCS_PORT_LOG_T16__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0951_LN3_MON_PCS_PORT_LOG_T16__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0952 (0x2548)
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#define USBDP_TRSV_REG0952_LN3_MON_PCS_PORT_LOG_T16__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0952_LN3_MON_PCS_PORT_LOG_T16__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0952_LN3_MON_PCS_PORT_LOG_T16__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0952_LN3_MON_PCS_PORT_LOG_T16__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0953 (0x254C)
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#define USBDP_TRSV_REG0953_LN3_MON_PCS_PORT_LOG_T16__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0953_LN3_MON_PCS_PORT_LOG_T16__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0953_LN3_MON_PCS_PORT_LOG_T16__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0953_LN3_MON_PCS_PORT_LOG_T16__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0954 (0x2550)
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#define USBDP_TRSV_REG0954_LN3_MON_PCS_PORT_LOG_T17__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0954_LN3_MON_PCS_PORT_LOG_T17__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0954_LN3_MON_PCS_PORT_LOG_T17__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0954_LN3_MON_PCS_PORT_LOG_T17__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0955 (0x2554)
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#define USBDP_TRSV_REG0955_LN3_MON_PCS_PORT_LOG_T17__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0955_LN3_MON_PCS_PORT_LOG_T17__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0955_LN3_MON_PCS_PORT_LOG_T17__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0955_LN3_MON_PCS_PORT_LOG_T17__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0956 (0x2558)
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#define USBDP_TRSV_REG0956_LN3_MON_PCS_PORT_LOG_T17__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0956_LN3_MON_PCS_PORT_LOG_T17__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0956_LN3_MON_PCS_PORT_LOG_T17__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0956_LN3_MON_PCS_PORT_LOG_T17__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0957 (0x255C)
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#define USBDP_TRSV_REG0957_LN3_MON_PCS_PORT_LOG_T17__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0957_LN3_MON_PCS_PORT_LOG_T17__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0957_LN3_MON_PCS_PORT_LOG_T17__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0957_LN3_MON_PCS_PORT_LOG_T17__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0958 (0x2560)
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#define USBDP_TRSV_REG0958_LN3_MON_PCS_PORT_LOG_T18__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0958_LN3_MON_PCS_PORT_LOG_T18__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0958_LN3_MON_PCS_PORT_LOG_T18__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0958_LN3_MON_PCS_PORT_LOG_T18__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0959 (0x2564)
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#define USBDP_TRSV_REG0959_LN3_MON_PCS_PORT_LOG_T18__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0959_LN3_MON_PCS_PORT_LOG_T18__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0959_LN3_MON_PCS_PORT_LOG_T18__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0959_LN3_MON_PCS_PORT_LOG_T18__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095A (0x2568)
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#define USBDP_TRSV_REG095A_LN3_MON_PCS_PORT_LOG_T18__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095A_LN3_MON_PCS_PORT_LOG_T18__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095A_LN3_MON_PCS_PORT_LOG_T18__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095A_LN3_MON_PCS_PORT_LOG_T18__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095B (0x256C)
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#define USBDP_TRSV_REG095B_LN3_MON_PCS_PORT_LOG_T18__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095B_LN3_MON_PCS_PORT_LOG_T18__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095B_LN3_MON_PCS_PORT_LOG_T18__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095B_LN3_MON_PCS_PORT_LOG_T18__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095C (0x2570)
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#define USBDP_TRSV_REG095C_LN3_MON_PCS_PORT_LOG_T19__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095C_LN3_MON_PCS_PORT_LOG_T19__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095C_LN3_MON_PCS_PORT_LOG_T19__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095C_LN3_MON_PCS_PORT_LOG_T19__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095D (0x2574)
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#define USBDP_TRSV_REG095D_LN3_MON_PCS_PORT_LOG_T19__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095D_LN3_MON_PCS_PORT_LOG_T19__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095D_LN3_MON_PCS_PORT_LOG_T19__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095D_LN3_MON_PCS_PORT_LOG_T19__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095E (0x2578)
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#define USBDP_TRSV_REG095E_LN3_MON_PCS_PORT_LOG_T19__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095E_LN3_MON_PCS_PORT_LOG_T19__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095E_LN3_MON_PCS_PORT_LOG_T19__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095E_LN3_MON_PCS_PORT_LOG_T19__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG095F (0x257C)
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#define USBDP_TRSV_REG095F_LN3_MON_PCS_PORT_LOG_T19__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG095F_LN3_MON_PCS_PORT_LOG_T19__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG095F_LN3_MON_PCS_PORT_LOG_T19__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG095F_LN3_MON_PCS_PORT_LOG_T19__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0960 (0x2580)
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#define USBDP_TRSV_REG0960_LN3_MON_PCS_PORT_LOG_T20__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0960_LN3_MON_PCS_PORT_LOG_T20__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0960_LN3_MON_PCS_PORT_LOG_T20__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0960_LN3_MON_PCS_PORT_LOG_T20__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0961 (0x2584)
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#define USBDP_TRSV_REG0961_LN3_MON_PCS_PORT_LOG_T20__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0961_LN3_MON_PCS_PORT_LOG_T20__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0961_LN3_MON_PCS_PORT_LOG_T20__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0961_LN3_MON_PCS_PORT_LOG_T20__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0962 (0x2588)
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#define USBDP_TRSV_REG0962_LN3_MON_PCS_PORT_LOG_T20__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0962_LN3_MON_PCS_PORT_LOG_T20__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0962_LN3_MON_PCS_PORT_LOG_T20__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0962_LN3_MON_PCS_PORT_LOG_T20__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0963 (0x258C)
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#define USBDP_TRSV_REG0963_LN3_MON_PCS_PORT_LOG_T20__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0963_LN3_MON_PCS_PORT_LOG_T20__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0963_LN3_MON_PCS_PORT_LOG_T20__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0963_LN3_MON_PCS_PORT_LOG_T20__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0964 (0x2590)
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#define USBDP_TRSV_REG0964_LN3_MON_PCS_PORT_LOG_T21__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0964_LN3_MON_PCS_PORT_LOG_T21__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0964_LN3_MON_PCS_PORT_LOG_T21__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0964_LN3_MON_PCS_PORT_LOG_T21__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0965 (0x2594)
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#define USBDP_TRSV_REG0965_LN3_MON_PCS_PORT_LOG_T21__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0965_LN3_MON_PCS_PORT_LOG_T21__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0965_LN3_MON_PCS_PORT_LOG_T21__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0965_LN3_MON_PCS_PORT_LOG_T21__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0966 (0x2598)
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#define USBDP_TRSV_REG0966_LN3_MON_PCS_PORT_LOG_T21__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0966_LN3_MON_PCS_PORT_LOG_T21__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0966_LN3_MON_PCS_PORT_LOG_T21__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0966_LN3_MON_PCS_PORT_LOG_T21__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0967 (0x259C)
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#define USBDP_TRSV_REG0967_LN3_MON_PCS_PORT_LOG_T21__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0967_LN3_MON_PCS_PORT_LOG_T21__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0967_LN3_MON_PCS_PORT_LOG_T21__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0967_LN3_MON_PCS_PORT_LOG_T21__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0968 (0x25A0)
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#define USBDP_TRSV_REG0968_LN3_MON_PCS_PORT_LOG_T22__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0968_LN3_MON_PCS_PORT_LOG_T22__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0968_LN3_MON_PCS_PORT_LOG_T22__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0968_LN3_MON_PCS_PORT_LOG_T22__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0969 (0x25A4)
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#define USBDP_TRSV_REG0969_LN3_MON_PCS_PORT_LOG_T22__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0969_LN3_MON_PCS_PORT_LOG_T22__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0969_LN3_MON_PCS_PORT_LOG_T22__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0969_LN3_MON_PCS_PORT_LOG_T22__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096A (0x25A8)
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#define USBDP_TRSV_REG096A_LN3_MON_PCS_PORT_LOG_T22__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096A_LN3_MON_PCS_PORT_LOG_T22__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096A_LN3_MON_PCS_PORT_LOG_T22__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096A_LN3_MON_PCS_PORT_LOG_T22__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096B (0x25AC)
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#define USBDP_TRSV_REG096B_LN3_MON_PCS_PORT_LOG_T22__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096B_LN3_MON_PCS_PORT_LOG_T22__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096B_LN3_MON_PCS_PORT_LOG_T22__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096B_LN3_MON_PCS_PORT_LOG_T22__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096C (0x25B0)
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#define USBDP_TRSV_REG096C_LN3_MON_PCS_PORT_LOG_T23__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096C_LN3_MON_PCS_PORT_LOG_T23__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096C_LN3_MON_PCS_PORT_LOG_T23__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096C_LN3_MON_PCS_PORT_LOG_T23__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096D (0x25B4)
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#define USBDP_TRSV_REG096D_LN3_MON_PCS_PORT_LOG_T23__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096D_LN3_MON_PCS_PORT_LOG_T23__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096D_LN3_MON_PCS_PORT_LOG_T23__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096D_LN3_MON_PCS_PORT_LOG_T23__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096E (0x25B8)
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#define USBDP_TRSV_REG096E_LN3_MON_PCS_PORT_LOG_T23__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096E_LN3_MON_PCS_PORT_LOG_T23__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096E_LN3_MON_PCS_PORT_LOG_T23__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096E_LN3_MON_PCS_PORT_LOG_T23__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG096F (0x25BC)
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#define USBDP_TRSV_REG096F_LN3_MON_PCS_PORT_LOG_T23__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG096F_LN3_MON_PCS_PORT_LOG_T23__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG096F_LN3_MON_PCS_PORT_LOG_T23__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG096F_LN3_MON_PCS_PORT_LOG_T23__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0970 (0x25C0)
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#define USBDP_TRSV_REG0970_LN3_MON_PCS_PORT_LOG_T24__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0970_LN3_MON_PCS_PORT_LOG_T24__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0970_LN3_MON_PCS_PORT_LOG_T24__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0970_LN3_MON_PCS_PORT_LOG_T24__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0971 (0x25C4)
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#define USBDP_TRSV_REG0971_LN3_MON_PCS_PORT_LOG_T24__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0971_LN3_MON_PCS_PORT_LOG_T24__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0971_LN3_MON_PCS_PORT_LOG_T24__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0971_LN3_MON_PCS_PORT_LOG_T24__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0972 (0x25C8)
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#define USBDP_TRSV_REG0972_LN3_MON_PCS_PORT_LOG_T24__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0972_LN3_MON_PCS_PORT_LOG_T24__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0972_LN3_MON_PCS_PORT_LOG_T24__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0972_LN3_MON_PCS_PORT_LOG_T24__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0973 (0x25CC)
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#define USBDP_TRSV_REG0973_LN3_MON_PCS_PORT_LOG_T24__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0973_LN3_MON_PCS_PORT_LOG_T24__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0973_LN3_MON_PCS_PORT_LOG_T24__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0973_LN3_MON_PCS_PORT_LOG_T24__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0974 (0x25D0)
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#define USBDP_TRSV_REG0974_LN3_MON_PCS_PORT_LOG_T25__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0974_LN3_MON_PCS_PORT_LOG_T25__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0974_LN3_MON_PCS_PORT_LOG_T25__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0974_LN3_MON_PCS_PORT_LOG_T25__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0975 (0x25D4)
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#define USBDP_TRSV_REG0975_LN3_MON_PCS_PORT_LOG_T25__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0975_LN3_MON_PCS_PORT_LOG_T25__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0975_LN3_MON_PCS_PORT_LOG_T25__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0975_LN3_MON_PCS_PORT_LOG_T25__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0976 (0x25D8)
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#define USBDP_TRSV_REG0976_LN3_MON_PCS_PORT_LOG_T25__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0976_LN3_MON_PCS_PORT_LOG_T25__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0976_LN3_MON_PCS_PORT_LOG_T25__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0976_LN3_MON_PCS_PORT_LOG_T25__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0977 (0x25DC)
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#define USBDP_TRSV_REG0977_LN3_MON_PCS_PORT_LOG_T25__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0977_LN3_MON_PCS_PORT_LOG_T25__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0977_LN3_MON_PCS_PORT_LOG_T25__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0977_LN3_MON_PCS_PORT_LOG_T25__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0978 (0x25E0)
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#define USBDP_TRSV_REG0978_LN3_MON_PCS_PORT_LOG_T26__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0978_LN3_MON_PCS_PORT_LOG_T26__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0978_LN3_MON_PCS_PORT_LOG_T26__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0978_LN3_MON_PCS_PORT_LOG_T26__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0979 (0x25E4)
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#define USBDP_TRSV_REG0979_LN3_MON_PCS_PORT_LOG_T26__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0979_LN3_MON_PCS_PORT_LOG_T26__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0979_LN3_MON_PCS_PORT_LOG_T26__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0979_LN3_MON_PCS_PORT_LOG_T26__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097A (0x25E8)
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#define USBDP_TRSV_REG097A_LN3_MON_PCS_PORT_LOG_T26__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097A_LN3_MON_PCS_PORT_LOG_T26__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097A_LN3_MON_PCS_PORT_LOG_T26__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097A_LN3_MON_PCS_PORT_LOG_T26__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097B (0x25EC)
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#define USBDP_TRSV_REG097B_LN3_MON_PCS_PORT_LOG_T26__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097B_LN3_MON_PCS_PORT_LOG_T26__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097B_LN3_MON_PCS_PORT_LOG_T26__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097B_LN3_MON_PCS_PORT_LOG_T26__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097C (0x25F0)
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#define USBDP_TRSV_REG097C_LN3_MON_PCS_PORT_LOG_T27__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097C_LN3_MON_PCS_PORT_LOG_T27__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097C_LN3_MON_PCS_PORT_LOG_T27__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097C_LN3_MON_PCS_PORT_LOG_T27__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097D (0x25F4)
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#define USBDP_TRSV_REG097D_LN3_MON_PCS_PORT_LOG_T27__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097D_LN3_MON_PCS_PORT_LOG_T27__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097D_LN3_MON_PCS_PORT_LOG_T27__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097D_LN3_MON_PCS_PORT_LOG_T27__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097E (0x25F8)
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#define USBDP_TRSV_REG097E_LN3_MON_PCS_PORT_LOG_T27__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097E_LN3_MON_PCS_PORT_LOG_T27__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097E_LN3_MON_PCS_PORT_LOG_T27__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097E_LN3_MON_PCS_PORT_LOG_T27__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG097F (0x25FC)
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#define USBDP_TRSV_REG097F_LN3_MON_PCS_PORT_LOG_T27__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG097F_LN3_MON_PCS_PORT_LOG_T27__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG097F_LN3_MON_PCS_PORT_LOG_T27__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG097F_LN3_MON_PCS_PORT_LOG_T27__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0980 (0x2600)
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#define USBDP_TRSV_REG0980_LN3_MON_PCS_PORT_LOG_T28__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0980_LN3_MON_PCS_PORT_LOG_T28__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0980_LN3_MON_PCS_PORT_LOG_T28__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0980_LN3_MON_PCS_PORT_LOG_T28__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0981 (0x2604)
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#define USBDP_TRSV_REG0981_LN3_MON_PCS_PORT_LOG_T28__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0981_LN3_MON_PCS_PORT_LOG_T28__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0981_LN3_MON_PCS_PORT_LOG_T28__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0981_LN3_MON_PCS_PORT_LOG_T28__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0982 (0x2608)
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#define USBDP_TRSV_REG0982_LN3_MON_PCS_PORT_LOG_T28__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0982_LN3_MON_PCS_PORT_LOG_T28__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0982_LN3_MON_PCS_PORT_LOG_T28__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0982_LN3_MON_PCS_PORT_LOG_T28__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0983 (0x260C)
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#define USBDP_TRSV_REG0983_LN3_MON_PCS_PORT_LOG_T28__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0983_LN3_MON_PCS_PORT_LOG_T28__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0983_LN3_MON_PCS_PORT_LOG_T28__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0983_LN3_MON_PCS_PORT_LOG_T28__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0984 (0x2610)
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#define USBDP_TRSV_REG0984_LN3_MON_PCS_PORT_LOG_T29__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0984_LN3_MON_PCS_PORT_LOG_T29__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0984_LN3_MON_PCS_PORT_LOG_T29__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0984_LN3_MON_PCS_PORT_LOG_T29__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0985 (0x2614)
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#define USBDP_TRSV_REG0985_LN3_MON_PCS_PORT_LOG_T29__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0985_LN3_MON_PCS_PORT_LOG_T29__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0985_LN3_MON_PCS_PORT_LOG_T29__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0985_LN3_MON_PCS_PORT_LOG_T29__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0986 (0x2618)
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#define USBDP_TRSV_REG0986_LN3_MON_PCS_PORT_LOG_T29__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0986_LN3_MON_PCS_PORT_LOG_T29__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0986_LN3_MON_PCS_PORT_LOG_T29__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0986_LN3_MON_PCS_PORT_LOG_T29__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0987 (0x261C)
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#define USBDP_TRSV_REG0987_LN3_MON_PCS_PORT_LOG_T29__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0987_LN3_MON_PCS_PORT_LOG_T29__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0987_LN3_MON_PCS_PORT_LOG_T29__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0987_LN3_MON_PCS_PORT_LOG_T29__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0988 (0x2620)
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#define USBDP_TRSV_REG0988_LN3_MON_PCS_PORT_LOG_T30__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0988_LN3_MON_PCS_PORT_LOG_T30__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0988_LN3_MON_PCS_PORT_LOG_T30__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0988_LN3_MON_PCS_PORT_LOG_T30__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG0989 (0x2624)
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#define USBDP_TRSV_REG0989_LN3_MON_PCS_PORT_LOG_T30__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG0989_LN3_MON_PCS_PORT_LOG_T30__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG0989_LN3_MON_PCS_PORT_LOG_T30__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG0989_LN3_MON_PCS_PORT_LOG_T30__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098A (0x2628)
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#define USBDP_TRSV_REG098A_LN3_MON_PCS_PORT_LOG_T30__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098A_LN3_MON_PCS_PORT_LOG_T30__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098A_LN3_MON_PCS_PORT_LOG_T30__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098A_LN3_MON_PCS_PORT_LOG_T30__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098B (0x262C)
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#define USBDP_TRSV_REG098B_LN3_MON_PCS_PORT_LOG_T30__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098B_LN3_MON_PCS_PORT_LOG_T30__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098B_LN3_MON_PCS_PORT_LOG_T30__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098B_LN3_MON_PCS_PORT_LOG_T30__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098C (0x2630)
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#define USBDP_TRSV_REG098C_LN3_MON_PCS_PORT_LOG_T31__31_24_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098C_LN3_MON_PCS_PORT_LOG_T31__31_24_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098C_LN3_MON_PCS_PORT_LOG_T31__31_24_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098C_LN3_MON_PCS_PORT_LOG_T31__31_24_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098D (0x2634)
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#define USBDP_TRSV_REG098D_LN3_MON_PCS_PORT_LOG_T31__23_16_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098D_LN3_MON_PCS_PORT_LOG_T31__23_16_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098D_LN3_MON_PCS_PORT_LOG_T31__23_16_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098D_LN3_MON_PCS_PORT_LOG_T31__23_16_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098E (0x2638)
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#define USBDP_TRSV_REG098E_LN3_MON_PCS_PORT_LOG_T31__15_8_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098E_LN3_MON_PCS_PORT_LOG_T31__15_8_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098E_LN3_MON_PCS_PORT_LOG_T31__15_8_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098E_LN3_MON_PCS_PORT_LOG_T31__15_8_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define EXYNOS_USBDP_TRSV_REG098F (0x263C)
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#define USBDP_TRSV_REG098F_LN3_MON_PCS_PORT_LOG_T31__7_0_MSK USBDP_REG_MSK(0, 8)
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#define USBDP_TRSV_REG098F_LN3_MON_PCS_PORT_LOG_T31__7_0_CLR USBDP_REG_CLR(0, 8)
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#define USBDP_TRSV_REG098F_LN3_MON_PCS_PORT_LOG_T31__7_0_SET(_x) USBDP_REG_SET(_x, 0, 8)
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#define USBDP_TRSV_REG098F_LN3_MON_PCS_PORT_LOG_T31__7_0_GET(_R) USBDP_REG_GET(_R, 0, 8)
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#define USB31DRD_LINK_LCSR_TX_DEEMPH (0xD060)
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#define USB31DRD_LINK_LCSR_TX_DEEMPH_1 (0xD064)
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#define USB31DRD_LINK_LCSR_TX_DEEMPH_2 (0xD068)
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typedef union {
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unsigned char data;
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struct {
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/* BGR output voltage selection */
|
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unsigned ana_dbg_ladder_en :1;
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/* BGR chopper clock enable */
|
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unsigned ana_bgr_clk_en :1;
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/* BGR 820mV selection ( for current bias ) */
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unsigned ana_bgr_820m_sel :2;
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/* BGR LPF bypass to reduce BGR settle time */
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unsigned bgr_lpf_bypass :1;
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/* override enable flag for bgr_lpf_bypass */
|
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unsigned ovrd_bgr_lpf_bypass :1;
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/* BGR enable */
|
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unsigned bgr_en :1;
|
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/* override enable flag for bgr_en */
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unsigned ovrd_bgr_en :1;
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} b;
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} __attribute__((__packed__)) usbdp_pma_reg0000;
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typedef union {
|
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unsigned char data;
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struct {
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|
/* RX RCAL bias current enable, or BIAS ICAL current enable */
|
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unsigned bias_rcal_en :1;
|
|
/* override enable flag for bias_rcal_en */
|
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unsigned ovrd_bias_rcal_en :1;
|
|
/* Bias current enable */
|
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unsigned bias_en :2;
|
|
/* override enable flag for bias_en */
|
|
unsigned ovrd_bias_en :1;
|
|
/* override enable flag for bgr_lpf_bypass */
|
|
unsigned ovrd_bgr_lpf_bypass :1;
|
|
/* BGR enable */
|
|
unsigned bgr_en :1;
|
|
/* override enable flag for bgr_en */
|
|
unsigned ovrd_bgr_en :1;
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|
} b;
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|
} __attribute__((__packed__)) usbdp_pma_reg0001;
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typedef struct {
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usbdp_pma_reg0000 reg0000;
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usbdp_pma_reg0001 reg0001;
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} __attribute__((aligned(4))) reg_set;
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#define PMA_REG(_REG, _DATA) ((usbdp_pma_##_REG *)(&_DATA)) |