3ad9a4e4db
[ Upstream commit 22e0eb04837a63af111fae35a92f7577676b9bc8 ]
This is a backport of a fix that was done in OpenSBI: ec0559eb315b
("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP").
Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.
Additionally, the previous check was incorrect since it was checking
the immediate field of the instruction instead of the rs2 field.
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231103090223.702340-1-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| .. | ||
| vdso | ||
| asm-offsets.c | ||
| cacheinfo.c | ||
| cpu-hotplug.c | ||
| cpu.c | ||
| cpu_ops.c | ||
| cpu_ops_sbi.c | ||
| cpu_ops_spinwait.c | ||
| cpufeature.c | ||
| efi-header.S | ||
| efi.c | ||
| entry.S | ||
| fpu.S | ||
| ftrace.c | ||
| head.h | ||
| head.S | ||
| image-vars.h | ||
| irq.c | ||
| jump_label.c | ||
| kgdb.c | ||
| Makefile | ||
| mcount-dyn.S | ||
| mcount.S | ||
| module-sections.c | ||
| module.c | ||
| patch.c | ||
| perf_callchain.c | ||
| perf_event.c | ||
| perf_regs.c | ||
| process.c | ||
| ptrace.c | ||
| reset.c | ||
| riscv_ksyms.c | ||
| sbi.c | ||
| setup.c | ||
| signal.c | ||
| smp.c | ||
| smpboot.c | ||
| soc.c | ||
| stacktrace.c | ||
| sys_riscv.c | ||
| syscall_table.c | ||
| time.c | ||
| trace_irq.c | ||
| trace_irq.h | ||
| traps.c | ||
| traps_misaligned.c | ||
| vdso.c | ||
| vmlinux.lds.S | ||