535 lines
18 KiB
C
Executable file
535 lines
18 KiB
C
Executable file
/* sound/soc/samsung/slif/slif.h
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*
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* ALSA SoC - Samsung VTS Serial Local Interface driver
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*
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* Copyright (c) 2019 Samsung Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SND_SOC_SLIF_H
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#define __SND_SOC_SLIF_H
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#include <sound/memalloc.h>
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#define GENMASK32(h, l) \
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(((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
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#define SLIF_SOC_VERSION(m, n, r) (((m) << 16) | ((n) << 8) | (r))
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#define SLIF_FLD(name) (GENMASK32(SLIF_##name##_H, \
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SLIF_##name##_L))
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#define SLIF_SFR(name, o, x) (SLIF_##name##_BASE + \
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((x) * SLIF_##name##_ITV) + (o))
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#define SLIF_BMASK(name, x) (SLIF_##name##_MASK_BIT << \
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((x) * SLIF_##name##_ITV))
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#define SLIF_MAX_CHANNEL (8)
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/* removed address fields */
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#define SLIF_MAX_REGISTER (0x300)
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#define SLIF_DMIC_AUD_MAX_REGISTER (0x10)
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/* 1. SERIAL LIF register base */
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#define SLIF_SFR_APB_BASE (0x30)
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#define SLIF_INT_EN_SET_BASE (0x40)
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#define SLIF_INT_EN_CLR_BASE (0x44)
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#define SLIF_INT_PEND_BASE (0x48)
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#define SLIF_INT_CLR_BASE (0x4C)
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#define SLIF_CTRL_BASE (0x100)
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#define SLIF_CONFIG_MASTER_BASE (0x104)
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#define SLIF_CONFIG_SLAVE_BASE (0x108)
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#define SLIF_CONFIG_DONE_BASE (0x10C)
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#define SLIF_SAMPLE_PCNT_BASE (0x110)
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#define SLIF_INPUT_EN_BASE (0x114)
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#define SLIF_VOL_SET_BASE (0x118)
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#define SLIF_VOL_SET_ITV (0x4)
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#define SLIF_VOL_SET(x) SLIF_SFR(VOL_SET, 0x0, x)
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#define SLIF_VOL_CHANGE_BASE (0x128)
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#define SLIF_VOL_CHANGE_ITV (0x4)
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#define SLIF_VOL_CHANGE(x) SLIF_SFR(VOL_CHANGE, 0x0, x)
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#define SLIF_CHANNEL_MAP_BASE (0x138)
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#define SLIF_CHANNEL_MAP_ITV (0x4)
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#define SLIF_DBG_INFO0_BASE (0x150)
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#define SLIF_DBG_INOF1_BASE (0x154)
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#define SLIF_MSIF_FIFO00_BASE (0x200)
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#define SLIF_MSIF_FIFO01_BASE (0x204)
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#define SLIF_MSIF_FIFO10_BASE (0x208)
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#define SLIF_MSIF_FIFO11_BASE (0x20C)
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#define SLIF_MSIF_FIFO20_BASE (0x210)
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#define SLIF_MSIF_FIFO21_BASE (0x214)
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#define SLIF_MSIF_FIFO30_BASE (0x218)
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#define SLIF_MSIF_FIFO31_BASE (0x21C)
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#define SLIF_SSIF_FIFO00_BASE (0x220)
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#define SLIF_SSIF_FIFO01_BASE (0x224)
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#define SLIF_SSIF_FIFO10_BASE (0x228)
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#define SLIF_SSIF_FIFO11_BASE (0x22C)
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#define SLIF_SSIF_FIFO20_BASE (0x230)
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#define SLIF_SSIF_FIFO21_BASE (0x234)
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#define SLIF_SSIF_FIFO30_BASE (0x238)
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#define SLIF_SSIF_FIFO31_BASE (0x23C)
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#define SLIF_CONTROL_AHB_WMASTER_BASE (0x300)
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#define SLIF_STARTADDR_SET0_BASE (0x304)
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#define SLIF_ENDADDR_SET0_BASE (0x308)
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#define SLIF_FILLED_SIZE_SET0_BASE (0x30C)
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#define SLIF_WRITE_POINTER_SET0_BASE (0x310)
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#define SLIF_READ_POINTER_SET0_BASE (0x314)
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#define SLIF_STARTADDR_SET1_BASE (0x318)
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#define SLIF_ENDADDR_SET1_BASE (0x31C)
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#define SLIF_FILLED_SIZE_SET1_BASE (0x320)
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#define SLIF_WRITE_POINTER_SET1_BASE (0x324)
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#define SLIF_READ_POINTER_SET1_BASE (0x328)
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/* SYS REG : 0x15510000 + 1010 */
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#define SLIF_SEL_PAD_AUD_BASE (0x0) /* 0x15511010 */
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#define SLIF_SEL_DIV2_CLK_BASE (0x4) /* 0x15511014 */
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/* INT_EN_SET */
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/* INT_EN_CLR */
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/* INT_PEND */
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/* INT_CLR */
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/* SLIF_CTRL_BASE */
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#define SLIF_CTRL_MASTER_IF_EN_H (0)
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#define SLIF_CTRL_MASTER_IF_EN_L (0)
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#define SLIF_CTRL_MASTER_IF_EN_MASK SLIF_FLD(CTRL_MASTER_IF_EN)
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#define SLIF_CTRL_SLAVE_IF_EN_H (4)
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#define SLIF_CTRL_SLAVE_IF_EN_L (4)
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#define SLIF_CTRL_SLAVE_IF_EN_MASK SLIF_FLD(CTRL_SLAVE_IF_EN)
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#define SLIF_CTRL_SPU_EN_H (8)
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#define SLIF_CTRL_SPU_EN_L (8)
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#define SLIF_CTRL_SPU_EN_MASK SLIF_FLD(CTRL_SPU_EN)
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#define SLIF_CTRL_LOOPBACK_EN_H (12)
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#define SLIF_CTRL_LOOPBACK_EN_L (12)
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#define SLIF_CTRL_LOOPBACK_EN_MASK SLIF_FLD(CTRL_LOOPBACK_EN)
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/* CONFIG_MASTER */
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#if (SLIF_SOC_VERSION(1, 0, 0) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_MASTER_OPMODE_H (3)
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#define SLIF_CONFIG_MASTER_OPMODE_L (0)
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#define SLIF_CONFIG_MASTER_OPMODE_MASK SLIF_FLD(CONFIG_MASTER_OPMODE)
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#define SLIF_CONFIG_MASTER_WS_MODE_H (4)
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#define SLIF_CONFIG_MASTER_WS_MODE_L (4)
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#define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE)
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#define SLIF_CONFIG_MASTER_WS_POLAR_H (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_L (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_H (15)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_L (12)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_MASTER_DIFF_MSIF_STR)
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#elif (SLIF_SOC_VERSION(1, 1, 1) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_MASTER_OP_D_H (3)
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#define SLIF_CONFIG_MASTER_OP_D_L (3)
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#define SLIF_CONFIG_MASTER_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D)
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#define SLIF_CONFIG_MASTER_OP_C_H (2)
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#define SLIF_CONFIG_MASTER_OP_C_L (0)
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#define SLIF_CONFIG_MASTER_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C)
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#define SLIF_CONFIG_MASTER_WS_MODE_H (4)
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#define SLIF_CONFIG_MASTER_WS_MODE_L (4)
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#define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE)
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#define SLIF_CONFIG_MASTER_WS_POLAR_H (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_L (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_H (15)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_L (12)
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#define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_MASTER_DIFF_MSIF_STR)
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#elif (SLIF_SOC_VERSION(1, 1, 2) >= CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_MASTER_BCLK_POLAR_H (24)
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#define SLIF_CONFIG_MASTER_BCLK_POLAR_L (24)
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#define SLIF_CONFIG_MASTER_BCLK_POLAR_MASK SLIF_FLD(CONFIG_MASTER_BCLK_POLAR)
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#define SLIF_CONFIG_MASTER_WS_MODE_H (20)
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#define SLIF_CONFIG_MASTER_WS_MODE_L (20)
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#define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE)
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#define SLIF_CONFIG_MASTER_BCLK_SEL_H (16)
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#define SLIF_CONFIG_MASTER_BCLK_SEL_L (16)
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#define SLIF_CONFIG_MASTER_BCLK_SEL_MASK SLIF_FLD(CONFIG_MASTER_BCLK_SEL)
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#define SLIF_CONFIG_MASTER_WS_POLAR_H (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_L (8)
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#define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR)
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#define SLIF_CONFIG_MASTER_OP_D_H (4)
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#define SLIF_CONFIG_MASTER_OP_D_L (3)
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#define SLIF_CONFIG_MASTER_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D)
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#define SLIF_CONFIG_MASTER_OP_C_H (2)
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#define SLIF_CONFIG_MASTER_OP_C_L (0)
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#define SLIF_CONFIG_MASTER_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C)
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#else
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#error "SLIF_SOC_VERSION is not defined"
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#endif
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/* CONFIG_SLAVE */
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#if (SLIF_SOC_VERSION(1, 0, 0) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_SLAVE_OPMODE_H (3)
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#define SLIF_CONFIG_SLAVE_OPMODE_L (0)
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#define SLIF_CONFIG_SLAVE_OPMODE_MASK SLIF_FLD(CONFIG_SLAVE_OPMODE)
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#define SLIF_CONFIG_SLAVE_WS_MODE_H (4)
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#define SLIF_CONFIG_SLAVE_WS_MODE_L (4)
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#define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_SLAVE_WS_MODE)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_H (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_L (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_SLAVE_WS_POLAR)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_H (15)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_L (12)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_SLAVE_DIFF_MSIF_STR)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_SLAVE_BCLK_SEL)
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#elif (SLIF_SOC_VERSION(1, 1, 1) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_SLAVE_OP_D_H (3)
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#define SLIF_CONFIG_SLAVE_OP_D_L (3)
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#define SLIF_CONFIG_SLAVE_OP_D_MASK SLIF_FLD(CONFIG_SLAVE_OP_D)
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#define SLIF_CONFIG_SLAVE_OP_C_H (2)
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#define SLIF_CONFIG_SLAVE_OP_C_L (0)
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#define SLIF_CONFIG_SLAVE_OP_C_MASK SLIF_FLD(CONFIG_SLAVE_OP_C)
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#define SLIF_CONFIG_SLAVE_WS_MODE_H (4)
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#define SLIF_CONFIG_SLAVE_WS_MODE_L (4)
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#define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_SLAVE_WS_MODE)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_H (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_L (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_SLAVE_WS_POLAR)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_H (15)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_L (12)
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#define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_SLAVE_DIFF_MSIF_STR)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_SLAVE_BCLK_SEL)
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#elif (SLIF_SOC_VERSION(1, 1, 2) >= CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION)
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#define SLIF_CONFIG_SLAVE_BCLK_POLAR_H (24)
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#define SLIF_CONFIG_SLAVE_BCLK_POLAR_L (24)
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#define SLIF_CONFIG_SLAVE_BCLK_POLAR_MASK SLIF_FLD(CONFIG_MASTER_BCLK_POLAR)
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#define SLIF_CONFIG_SLAVE_WS_MODE_H (20)
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#define SLIF_CONFIG_SLAVE_WS_MODE_L (20)
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#define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16)
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#define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_MASTER_BCLK_SEL)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_H (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_L (8)
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#define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR)
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#define SLIF_CONFIG_SLAVE_OP_D_H (4)
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#define SLIF_CONFIG_SLAVE_OP_D_L (3)
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#define SLIF_CONFIG_SLAVE_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D)
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#define SLIF_CONFIG_SLAVE_OP_C_H (2)
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#define SLIF_CONFIG_SLAVE_OP_C_L (0)
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#define SLIF_CONFIG_SLAVE_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C)
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#else
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#error "SLIF_SOC_VERSION is not defined"
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#endif
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/* CONFIG_DONE */
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#define SLIF_CONFIG_DONE_ALL_CONFIG_H (0)
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#define SLIF_CONFIG_DONE_ALL_CONFIG_L (0)
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#define SLIF_CONFIG_DONE_ALL_CONFIG_MASK SLIF_FLD(CONFIG_DONE_ALL_CONFIG)
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#define SLIF_CONFIG_DONE_MASTER_CONFIG_H (4)
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#define SLIF_CONFIG_DONE_MASTER_CONFIG_L (4)
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#define SLIF_CONFIG_DONE_MASTER_CONFIG_MASK SLIF_FLD(CONFIG_DONE_MASTER_CONFIG)
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#define SLIF_CONFIG_DONE_SLAVE_CONFIG_H (8)
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#define SLIF_CONFIG_DONE_SLAVE_CONFIG_L (8)
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#define SLIF_CONFIG_DONE_SLAVE_CONFIG_MASK SLIF_FLD(CONFIG_DONE_SLAVE_CONFIG)
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/* SAMPLE_PCNT */
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/* INPUT_EN */
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#define SLIF_INPUT_EN_EN0_H (0)
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#define SLIF_INPUT_EN_EN0_L (0)
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#define SLIF_INPUT_EN_EN0_MASK SLIF_FLD(INPUT_EN_EN0)
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#define SLIF_INPUT_EN_EN1_H (1)
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#define SLIF_INPUT_EN_EN1_L (1)
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#define SLIF_INPUT_EN_EN1_MASK SLIF_FLD(INPUT_EN_EN1)
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#define SLIF_INPUT_EN_EN2_H (2)
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#define SLIF_INPUT_EN_EN2_L (2)
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#define SLIF_INPUT_EN_EN2_MASK SLIF_FLD(INPUT_EN_EN2)
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#define SLIF_INPUT_EN_EN3_H (3)
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#define SLIF_INPUT_EN_EN3_L (3)
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#define SLIF_INPUT_EN_EN3_MASK SLIF_FLD(INPUT_EN_EN3)
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#define SLIF_INPUT_EN_FADE_IN_EN0_H (4)
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#define SLIF_INPUT_EN_FADE_IN_EN0_L (4)
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#define SLIF_INPUT_EN_FADE_IN_EN0_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN0)
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#define SLIF_INPUT_EN_FADE_IN_EN1_H (5)
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#define SLIF_INPUT_EN_FADE_IN_EN1_L (5)
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#define SLIF_INPUT_EN_FADE_IN_EN1_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN1)
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#define SLIF_INPUT_EN_FADE_IN_EN2_H (6)
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#define SLIF_INPUT_EN_FADE_IN_EN2_L (6)
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#define SLIF_INPUT_EN_FADE_IN_EN2_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN2)
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#define SLIF_INPUT_EN_FADE_IN_EN3_H (7)
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#define SLIF_INPUT_EN_FADE_IN_EN3_L (7)
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#define SLIF_INPUT_EN_FADE_IN_EN3_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN3)
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#define SLIF_INPUT_EN_FADE_OUT_EN0_H (8)
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#define SLIF_INPUT_EN_FADE_OUT_EN0_L (8)
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#define SLIF_INPUT_EN_FADE_OUT_EN0_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN0)
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#define SLIF_INPUT_EN_FADE_OUT_EN1_H (9)
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#define SLIF_INPUT_EN_FADE_OUT_EN1_L (9)
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#define SLIF_INPUT_EN_FADE_OUT_EN1_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN1)
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#define SLIF_INPUT_EN_FADE_OUT_EN2_H (10)
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#define SLIF_INPUT_EN_FADE_OUT_EN2_L (10)
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#define SLIF_INPUT_EN_FADE_OUT_EN2_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN2)
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#define SLIF_INPUT_EN_FADE_OUT_EN3_H (11)
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#define SLIF_INPUT_EN_FADE_OUT_EN3_L (11)
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#define SLIF_INPUT_EN_FADE_OUT_EN3_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN3)
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/* VOL_SET */
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#define SLIF_VOL_SET_H (23)
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#define SLIF_VOL_SET_L (0)
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#define SLIF_VOL_SET_MASK SLIF_FLD(VOL_SET)
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/* VOL_change */
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#define SLIF_VOL_CHANGE_H (23)
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#define SLIF_VOL_CHANGE_L (0)
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#define SLIF_VOL_CHANGE_MASK SLIF_FLD(VOL_CHANGE)
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/* CHANNEL_MAP */
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#define SLIF_CHANNEL_MAP_MASK_BIT (0xF)
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#define SLIF_CHANNEL_MAP_MASK(x) SLIF_BMASK(CHANNEL_MAP, x)
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/* DBG_INFO0 */
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/* DBG_INFO1 */
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/* MSIF_FIFO00 */
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/* MSIF_FIFO01 */
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/* MSIF_FIFO10 */
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/* MSIF_FIFO11 */
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/* MSIF_FIFO20 */
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/* MSIF_FIFO21 */
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/* MSIF_FIFO30 */
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/* MSIF_FIFO31 */
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/* SSIF_FIFO00 */
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/* SSIF_FIFO01 */
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/* SSIF_FIFO10 */
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/* SSIF_FIFO11 */
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/* SSIF_FIFO20 */
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/* SSIF_FIFO21 */
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/* SSIF_FIFO30 */
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/* SSIF_FIFO31 */
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/* CONTROL_AHB_WMASTER */
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#define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_H (0)
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#define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_L (0)
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#define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_MASK \
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SLIF_FLD(CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER)
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#define SLIF_CONTROL_AHB_WMASTER_SETINFO_H (4)
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#define SLIF_CONTROL_AHB_WMASTER_SETINFO_L (4)
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#define SLIF_CONTROL_AHB_WMASTER_SETINFO_MASK \
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SLIF_FLD(CONTROL_AHB_WMASTER_SETINFO)
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#define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_H (8)
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#define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_L (8)
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#define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_MASK \
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SLIF_FLD(CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER)
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/* STARTADDR_SET0 */
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#define SLIF_STARTADDR_SET0_H (31)
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#define SLIF_STARTADDR_SET0_L (2)
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#define SLIF_STARTADDR_SET0_MASK SLIF_FLD(STARTADDR_SET0)
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/* ENDADDR_SET0 */
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#define SLIF_ENDADDR_SET0_H (31)
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#define SLIF_ENDADDR_SET0_L (2)
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#define SLIF_ENDADDR_SET0_MASK SLIF_FLD(ENDADDR_SET0)
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/* FILLED_SIZE_SET0 */
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#define SLIF_FILLED_SIZE_SET0_H (31)
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#define SLIF_FILLED_SIZE_SET0_L (2)
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#define SLIF_FILLED_SIZE_SET0_MASK SLIF_FLD(FILLED_SIZE_SET0)
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/* WRITE_POINTER_SET0 */
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#define SLIF_WRITE_POINTER_SET0_H (31)
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#define SLIF_WRITE_POINTER_SET0_L (2)
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#define SLIF_WRITE_POINTER_SET0_MASK SLIF_FLD(WRITE_POINTER_SET0)
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/* READ_POINTER_SET0 */
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#define SLIF_READ_POINTER_SET0_H (31)
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#define SLIF_READ_POINTER_SET0_L (2)
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#define SLIF_READ_POINTER_SET0_MASK SLIF_FLD(READ_POINTER_SET0)
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/* STARTADDR_SET1 */
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#define SLIF_STARTADDR_SET1_H (31)
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#define SLIF_STARTADDR_SET1_L (2)
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#define SLIF_STARTADDR_SET1_MASK SLIF_FLD(STARTADDR_SET1)
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/* ENDADDR_SET1 */
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#define SLIF_ENDADDR_SET1_H (31)
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#define SLIF_ENDADDR_SET1_L (2)
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#define SLIF_ENDADDR_SET1_MASK SLIF_FLD(ENDADDR_SET1)
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/* FILLED_SIZE_SET1 */
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#define SLIF_FILLED_SIZE_SET1_H (31)
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#define SLIF_FILLED_SIZE_SET1_L (2)
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#define SLIF_FILLED_SIZE_SET1_MASK SLIF_FLD(FILLED_SIZE_SET1)
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/* WRITE_POINTER_SET1 */
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#define SLIF_WRITE_POINTER_SET1_H (31)
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#define SLIF_WRITE_POINTER_SET1_L (2)
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#define SLIF_WRITE_POINTER_SET1_MASK SLIF_FLD(WRITE_POINTER_SET1)
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/* READ_POINTER_SET1 */
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#define SLIF_READ_POINTER_SET1_H (31)
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#define SLIF_READ_POINTER_SET1_L (2)
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#define SLIF_READ_POINTER_SET1_MASK SLIF_FLD(READ_POINTER_SET1)
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/* 2. DMIC AUD register base */
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#define SLIF_SFR_ENABLE_DMIC_AUD_BASE (0x0)
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#define SLIF_SFR_CONTROL_DMIC_AUD_BASE (0x4)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_H (6)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_L (1)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_MASK \
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SLIF_FLD(SFR_CONTROL_DMIC_AUD_HPF_SEL)
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#define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_H (14)
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#define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_L (12)
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#define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_MASK \
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SLIF_FLD(SFR_CONTROL_DMIC_AUD_SYS_SEL)
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#define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_H (26)
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#define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_L (21)
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#define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_MASK \
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SLIF_FLD(SFR_CONTROL_DMIC_AUD_GAIN)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_H (31)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_L (31)
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#define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_MASK \
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SLIF_FLD(SFR_CONTROL_DMIC_AUD_HPF_EN)
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#define SLIF_SFR_GAIN_MODE_BASE (0x8)
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#define SLIF_SFR_MAX_SCALE_MODE_BASE (0xC)
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#define SLIF_SFR_MAX_SCALE_GAIN_BASE (0x10)
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#define SLIF_DMIC_AUD_NUM_MAX (3)
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/* 3. DMIC AUD value */
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#if (IS_ENABLED(CONFIG_SOC_S5E9925))
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#define SLIF_DMIC_AUD_NUM (3)
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#elif (IS_ENABLED(CONFIG_SOC_S5E8825))
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#define SLIF_DMIC_AUD_NUM (2)
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#endif
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#define SLIF_DEFAULT_GAIN_MODE (0x1717)
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#define SLIF_DEFAULT_MAX_SCALE_GAIN (0x85)
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#define SLIF_DEFAULT_CONTROL_DMIC_AUD (0x8C6300CC)
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enum slif_mode {
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SLIF_MODE_SLAVE,
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SLIF_MODE_MASTER,
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SLIF_MODE_BOTH,
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};
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enum slif_state {
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SLIF_STATE_CLOSED,
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SLIF_STATE_OPENED,
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SLIF_STATE_SET_PARAM,
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SLIF_STATE_DMA_ENBLED,
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SLIF_STATE_DMA_DISABLED,
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};
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enum slif_gain_mode {
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GAIN_MODE0,
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GAIN_MODE1,
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GAIN_MODE2,
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};
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enum slif_max_scale_gain {
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MAX_SCALE_GAIN0,
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MAX_SCALE_GAIN1,
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MAX_SCALE_GAIN2,
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};
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enum slif_control_dmic_aud {
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CONTROL_DMIC_AUD0,
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CONTROL_DMIC_AUD1,
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CONTROL_DMIC_AUD2,
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};
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enum slif_vol_set {
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VOL_SET0,
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VOL_SET1,
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VOL_SET2,
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VOL_SET3,
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};
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enum s_lif_channel_map {
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MAP_CH0,
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MAP_CH1,
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MAP_CH2,
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MAP_CH3,
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MAP_CH4,
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MAP_CH5,
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MAP_CH6,
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MAP_CH7,
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};
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enum slif_clk_input_path {
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SLIF_CLK_PLL_AUD0, /* 294.912MHz */
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SLIF_CLK_PLL_AUD1,
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SLIF_CLK_OSCCLK_RCO, /* 24.576MHz */
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SLIF_CLK_RCO_PMU, /* 49.152MHz */
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};
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struct slif_data {
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/* id */
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struct platform_device *pdev;
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struct device *dev;
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|
struct device *dev_vts;
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struct vts_data *vts_data;
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|
int id;
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char name[64];
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/* resouece */
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void __iomem *sfr_base;
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void __iomem *sfr_sys_base;
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void __iomem *sram_base;
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void __iomem *dmic_aud[SLIF_DMIC_AUD_NUM_MAX];
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struct regmap *regmap_sfr;
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struct regmap *regmap_dmic_aud[SLIF_DMIC_AUD_NUM_MAX];
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struct clk *clk_mux_dmic_aud_user;
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struct clk *clk_mux_dmic_aud;
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struct clk *clk_mux_serial_lif;
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|
struct clk *clk_dmic_aud_pad;
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|
struct clk *clk_dmic_aud_div2;
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|
struct clk *clk_dmic_aud;
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|
struct clk *clk_mux_dmic_aud0;
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|
struct clk *clk_mux_dmic_aud1;
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|
struct clk *clk_serial_lif;
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|
struct clk *clk_slif_src;
|
|
struct pinctrl *pinctrl;
|
|
struct delayed_work mute_work;
|
|
unsigned int mute_ms;
|
|
bool mute_enable;
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|
bool clk_enable;
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|
|
|
/* data */
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|
unsigned int gain_mode[SLIF_DMIC_AUD_NUM_MAX];
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|
unsigned int max_scale_gain[SLIF_DMIC_AUD_NUM_MAX];
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|
unsigned int control_dmic_aud[SLIF_DMIC_AUD_NUM_MAX];
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|
unsigned int dmic_en[SLIF_DMIC_AUD_NUM_MAX];
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|
unsigned int channel_map;
|
|
unsigned int channels;
|
|
unsigned int rate;
|
|
unsigned int width;
|
|
unsigned int clk_input_path;
|
|
unsigned int clk_table_id;
|
|
unsigned int slif_dump_enabled;
|
|
|
|
/* sync */
|
|
wait_queue_head_t ipc_wait_queue;
|
|
spinlock_t ipc_spinlock;
|
|
struct mutex ipc_mutex;
|
|
spinlock_t state_spinlock;
|
|
struct wakeup_source *wake_lock;
|
|
|
|
/* status */
|
|
volatile bool enabled;
|
|
volatile bool running;
|
|
unsigned long state;
|
|
unsigned long mode;
|
|
unsigned int fmt;
|
|
|
|
/* alsa data */
|
|
struct snd_soc_component *cmpnt;
|
|
struct snd_soc_card *card;
|
|
|
|
/* ETC. */
|
|
unsigned int last_array[10];
|
|
};
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#endif /* __SND_SOC_SLIF_H */
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